A method for preparing a CMOS device and a CMOS device

Abstract

The present application discloses a method for preparing a CMOS device and a CMOS device, belonging to the field of semiconductor process technology. The method sequentially deposits a first transition metal layer of a first thickness, a first nickel metal layer of a second thickness, and a titanium nitride protective layer of a third thickness on the upper surfaces of a first gate and a second gate and a high-doped N-type diffusion region, a low-doped N-type diffusion region, a high-doped P-type diffusion region, and a low-doped P-type diffusion region to form a first nickel silicide alloy layer; and sequentially deposits a second transition metal layer of a fourth thickness, a second nickel metal layer of a fifth thickness, and a titanium nitride protective layer of a sixth thickness on the first nickel silicide alloy layer corresponding to the first gate, the second gate, and the high-doped N-type diffusion region and the high-doped P-type diffusion region to form a second nickel silicide alloy layer, wherein the thickness of the second nickel silicide alloy layer is greater than the thickness of the first nickel silicide alloy layer. The present application can significantly reduce the contact resistivity of the contact layer of the transistor gate and the source-drain electrode of the CMOS device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor process technology, and in particular to a method for preparing a CMOS device and a CMOS device. Background Art

[0002] As CMOS (complementary metal oxide semiconductor) devices continue to expand towards smaller nano-devices, higher requirements are placed on the contact process of transistor gates and source-drain electrodes, namely, the contact resistivity of transistor gates and source-drain electrodes is lower, and the long-term stability is high, and the process is easy to implement. In order to meet the contact process requirements of micro-CMOS devices, the prior art usually uses a self-aligned silicide process (Salicide) based on rapid thermal processing (RTP) to form a metal silicide contact layer film, such as nickel silicide (NiSi) film, in the transistor gate and source-drain electrode region through a solid-phase reaction of metal and silicon. However, nickel silicide has low thermal stability, which will cause the interface between the nickel silicide film formed by the metal silicide process and the silicon substrate to be rough, and the interface leakage current will increase, which will in turn cause the contact resistivity of the transistor gate and source-drain electrodes to increase, making it difficult to meet the process requirements of the contact resistivity of micro-CMOS devices. Therefore, an improved process is urgently needed to solve the above technical problems. Summary of the invention

[0003] In view of this, the present application proposes a method for preparing a CMOS device and a CMOS device, which can significantly reduce the contact resistivity of the contact layer of the transistor gate and source / drain electrodes of the CMOS device, and meet the process requirements of the contact resistivity of the micro-CMOS device.

[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a CMOS device, the method comprising:

[0005] An NMOS region and a PMOS region isolated by an isolation region are formed on a silicon substrate, a first gate is grown in the NMOS region, and a second gate is grown in the PMOS region;

[0006] Forming a high-doped N-type diffusion region and a low-doped N-type diffusion region on both sides of the first gate, and forming a high-doped P-type diffusion region and a low-doped P-type diffusion region on both sides of the second gate by ion implantation;

[0007] A first transition metal layer of a first thickness, a first nickel metal layer of a second thickness, and a titanium nitride protective layer of a third thickness are sequentially deposited on the upper surfaces of the first gate and the second gate and the upper surfaces of the highly doped N-type diffusion region, the low doped N-type diffusion region, the highly doped P-type diffusion region, and the low doped P-type diffusion region, and a first nickel silicide alloy layer is formed by a first rapid thermal treatment process;

[0008] A second transition metal layer of a fourth thickness, a second nickel metal layer of a fifth thickness, and a titanium nitride protective layer of a sixth thickness are sequentially deposited on the upper surfaces of the first gate, the second gate and the first nickel silicide alloy layer corresponding to the highly doped N-type diffusion region and the highly doped P-type diffusion region, and a second nickel silicide alloy layer is formed by a second rapid thermal treatment process, wherein the thickness of the second nickel silicide alloy layer is greater than the thickness of the first nickel silicide alloy layer.

[0009] In some embodiments, the doping concentration of the highly doped N-type diffusion region is greater than the doping concentration of the low doped N-type diffusion region, and the doping concentration of the highly doped P-type diffusion region is greater than the doping concentration of the low doped P-type diffusion region.

[0010] In some embodiments, the first transition metal and the second transition metal are selected from terbium (Tb) metal and holmium (Ho) metal.

[0011] In some embodiments, the first thickness, the second thickness, and the fourth thickness, and the fifth thickness satisfy a ratio of 1:3 to 1:5; the first thickness, the third thickness, and the fourth thickness, and the sixth thickness satisfy a ratio of 1:2 to 1:3.

[0012] In some embodiments, the forming of the first nickel silicide alloy layer by the first rapid thermal processing process includes: performing rapid annealing at a temperature of 450-500°C for 30-40 seconds in a rapid thermal processing reaction chamber, so that the first transition metal layer, the first nickel metal layer and the silicon elements in the first gate, the second gate, the highly doped N-type diffusion region, the low-doped N-type diffusion region, the highly doped P-type diffusion region, and the low-doped P-type diffusion region undergo silicidation reaction to form the first nickel silicide alloy layer.

[0013] In some embodiments, the forming of the second nickel silicide alloy layer by the second rapid thermal processing process includes: performing rapid annealing at a temperature of 500-600°C in a rapid thermal processing reaction chamber for 40-60 seconds, so that the second transition metal layer, the second nickel metal layer and the silicon element in the first gate, the second gate, the highly doped N-type diffusion region, and the highly doped P-type diffusion region undergo silicidation reaction to form the second nickel silicide alloy layer.

[0014] In some embodiments, the junction depth of the highly doped N-type diffusion region is greater than the junction depth of the low doped N-type diffusion region, and the junction depth of the highly doped P-type diffusion region is greater than the junction depth of the low doped P-type diffusion region.

[0015] In some embodiments, the ratio of the thickness of the second nickel silicide alloy layer to the thickness of the first nickel silicide alloy layer satisfies: ,in represents the thickness of the first nickel silicide alloy layer, represents the thickness of the second nickel silicide alloy layer, represents the junction depth of the highly doped N-type diffusion region or the junction depth of the highly doped P-type diffusion region, represents the junction depth of the low-doped N-type diffusion region or the junction depth of the low-doped P-type diffusion region, represents the proportionality coefficient, The value is in the interval [1,2].

[0016] In a second aspect, an embodiment of the present application provides a CMOS device, wherein the CMOS device comprises:

[0017] An NMOS region and a PMOS region isolated by an isolation region are formed on a silicon substrate, wherein the NMOS region includes a first gate and the PMOS region includes a second gate;

[0018] The NMOS region includes a high-doped N-type diffusion region and a low-doped N-type diffusion region on both sides of the first gate, and the PMOS region includes a high-doped P-type diffusion region and a low-doped P-type diffusion region on both sides of the second gate;

[0019] The NMOS region and the PMOS region respectively include a first nickel silicide alloy layer covering the upper surfaces of the low-doped N-type diffusion region and the low-doped P-type diffusion region, and a second nickel silicide alloy layer covering the upper surfaces of the first gate and the second gate, the upper surfaces of the highly doped N-type diffusion region and the highly doped P-type diffusion region, wherein the thickness of the second nickel silicide alloy layer is greater than the thickness of the first nickel silicide alloy layer.

[0020] In some embodiments, the ratio of the thickness of the second nickel silicide alloy layer to the thickness of the first nickel silicide alloy layer satisfies: ,in represents the thickness of the first nickel silicide alloy layer, represents the thickness of the second nickel silicide alloy layer, represents the junction depth of the highly doped N-type diffusion region or the junction depth of the highly doped P-type diffusion region, represents the junction depth of the low-doped N-type diffusion region or the junction depth of the low-doped P-type diffusion region, represents the proportionality coefficient, The value is in the interval [1,2].

[0021] This application can at least achieve the following beneficial effects:

[0022] The preparation method of the CMOS device and the CMOS device of the embodiment of the present application, on the one hand, by forming a second nickel silicide alloy layer with a larger thickness on the upper surfaces of the high-doped N-type diffusion region and the high-doped P-type diffusion region of the CMOS device, and forming a first nickel silicide alloy layer with a smaller thickness on the upper surfaces of the low-doped N-type diffusion region and the low-doped P-type diffusion region, the first nickel silicide alloy layer and the second nickel silicide alloy layer are nickel silicide alloy phases doped with transition metals in the metal silicidation reaction of nickel silicide, and the junctions with the upper surfaces of the first gate and the second gate and the upper surfaces of the high-doped N-type diffusion region, the low-doped N-type diffusion region, the high-doped P-type diffusion region, and the low-doped P-type diffusion region are smoother, which greatly reduces the junction leakage current of the contact layer, thereby significantly reducing the contact resistivity of the contact layer. On the other hand, the first nickel silicide alloy layer with a smaller thickness can reduce the contact resistivity of the source and drain electrodes without damaging the conduction performance of the shallow channel composed of the low-doped N-type diffusion region and the low-doped P-type diffusion region, while the second nickel silicide alloy layer with a larger thickness can also more significantly reduce the contact resistivity of the gate and source and drain electrodes, and will not affect the conduction performance of the deep channel composed of the highly doped N-type diffusion region and the highly doped P-type diffusion region. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope of the present application.

[0024] Figure 1 It is a schematic flow chart of a method for preparing a CMOS device according to an embodiment of the present application;

[0025] Figure 2 A cross-sectional view of a first process stage of a CMOS device prepared by a preparation method according to an embodiment of the present application is shown;

[0026] Figure 3 A cross-sectional view of a second process stage of a CMOS device prepared by a preparation method according to an embodiment of the present application is shown;

[0027] Figure 4 A cross-sectional view of a CMOS device at a third process stage prepared by a preparation method according to an embodiment of the present application is shown;

[0028] Figure 5 A cross-sectional view of a CMOS device manufactured by a manufacturing method according to an embodiment of the present application at a fourth process stage is shown;

[0029] Figure 6A cross-sectional view of a CMOS device manufactured by a manufacturing method according to an embodiment of the present application at a fifth process stage is shown;

[0030] Figure 7 A cross-sectional view of a CMOS device at a sixth process stage prepared by a preparation method according to an embodiment of the present application is shown;

[0031] Figure 8 yes Figure 7 A partial enlarged view of the dotted circle portion of the cross-sectional view of the CMOS device at the sixth process stage is shown. DETAILED DESCRIPTION

[0032] To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. However, it should be understood that the described embodiments are only some exemplary embodiments of the present application, rather than all embodiments, and therefore the following detailed description of the embodiments of the present application is not intended to limit the scope of protection claimed in the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of this application are only used to distinguish and describe similar objects, rather than to describe a specific order or sequence, and cannot be understood as indicating or implying relative importance.

[0034] As mentioned above, the prior art uses a self-aligned silicide process (Salicide) based on rapid thermal processing (RTP) to form a contact layer film of metal silicide nickel silicide (NiSi) in the transistor gate and source-drain electrode regions through a solid-phase reaction of metal and silicon. However, nickel silicide has low thermal stability, which will cause the interface between the nickel silicide film formed by the metal silicide process and the silicon substrate to be rough, increase the junction leakage current, and further increase the contact resistivity of the transistor gate and source-drain electrodes, making it difficult to meet the process requirements of micro-CMOS devices for contact resistivity. To this end, the embodiment of the present application proposes a method for preparing a CMOS device and a CMOS device, which can significantly reduce the contact resistivity of the contact layer of the transistor gate and source-drain electrodes of the CMOS device, and meet the process requirements of the micro-CMOS device for contact resistivity.

[0035] Figure 1 FIG. 1 is a flow chart of a method for preparing a CMOS device according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0036] Step S1, forming an NMOS region and a PMOS region isolated by an isolation region on a silicon substrate, growing a first gate in the NMOS region and growing a second gate in the PMOS region;

[0037] Step S2, forming a highly doped N-type diffusion region and a low doped N-type diffusion region on both sides of the first gate, and forming a highly doped P-type diffusion region and a low doped P-type diffusion region on both sides of the second gate by ion implantation;

[0038] Step S3, depositing a first transition metal layer of a first thickness, a first nickel metal layer of a second thickness, and a titanium nitride protective layer of a third thickness in sequence on the upper surfaces of the first gate and the second gate and the upper surfaces of the highly doped N-type diffusion region, the low doped N-type diffusion region, the highly doped P-type diffusion region, and the low doped P-type diffusion region, and forming a first nickel silicide alloy layer by a first rapid thermal treatment process;

[0039] Step S4, depositing a second transition metal layer of a fourth thickness, a second nickel metal layer of a fifth thickness, and a titanium nitride protective layer of a sixth thickness in sequence on the upper surfaces of the first gate, the second gate and the first nickel silicide alloy layer corresponding to the highly doped N-type diffusion region and the highly doped P-type diffusion region, and forming a second nickel silicide alloy layer through a second rapid thermal treatment process, wherein the thickness of the second nickel silicide alloy layer is greater than the thickness of the first nickel silicide alloy layer.

[0040] Figure 2-8 The cross-sectional view of each process stage of the CMOS device prepared by the preparation method according to the embodiment of the present application is shown. Figure 2-8 The method for preparing the CMOS device according to the embodiment of the present application is described in detail.

[0041] In this embodiment, Figure 2 As shown, in step S1, an NMOS region 100 and a PMOS region 200 isolated by an isolation region 300 are formed on a silicon substrate 10, a first gate 101 composed of a first insulating layer 101a and a first polysilicon layer 101b is grown in the NMOS region 100, and a second gate 201 composed of a second insulating layer 201a and a second polysilicon layer 201b is grown in the PMOS region. The isolation region 300 is formed in a predetermined region of the silicon substrate 10 by a shallow trench isolation (STI) process. The first insulating layer 101a and the first polysilicon layer 101b, the second insulating layer 201a and the second polysilicon layer 201b are formed on the silicon substrate 10 by a physical or chemical vapor deposition process, respectively.

[0042] like Figure 3 and Figure 4As shown, in step S2, a highly doped N-type diffusion region 103 and a low doped N-type diffusion region 104 are formed on both sides of the first gate 101 by ion implantation, and a highly doped P-type diffusion region 203 and a low doped P-type diffusion region 204 are formed on both sides of the second gate 201.

[0043] Specifically, if Figure 3 As shown, first, a first spacer component 102 can be formed on both sides of the first gate 101, and a second spacer component 202 can be formed on both sides of the second gate 201, and a highly doped N-type diffusion region 103 can be formed on both sides of the first gate 101 and a highly doped P-type diffusion region 203 can be formed on both sides of the second gate 201 by ion implantation. The first spacer component 102 and the second spacer component 202 can be formed by depositing an insulating material such as silicon oxide and undergoing an etching process. The highly doped N-type diffusion region 103 can be formed by implanting N-type impurity ions with a high doping concentration into a silicon substrate 10 based on the first spacer component 102 as an ion implantation mask. The highly doped P-type diffusion region 203 can be formed by implanting P-type impurity ions with a high doping concentration into a silicon substrate 10 based on the second spacer component 202 as an ion implantation mask.

[0044] like Figure 4 As shown, the first spacer component 102 and the second spacer component 202 are subsequently removed to form a low-doped N-type diffusion region 104 between the first gate 101 and the high-doped N-type diffusion region 103, and a low-doped P-type diffusion region 204 between the second gate 201 and the high-doped P-type diffusion region 203 by ion implantation.

[0045] The first spacer component 102 and the second spacer component 202 can be removed by a wet etching process. The low-doped N-type diffusion region 104 can be formed by implanting N-type impurities with low doping concentration into the silicon substrate 10 by an ion implantation process. The low-doped P-type diffusion region 204 can be formed by implanting P-type impurities with low doping concentration into the silicon substrate 10 by an ion implantation process. That is, the doping concentration of the high-doped N-type diffusion region 103 is greater than the doping concentration of the low-doped N-type diffusion region 104, and the doping concentration of the high-doped P-type diffusion region 203 is greater than the doping concentration of the low-doped P-type diffusion region 204. The high-doped N-type diffusion region 103 and the low-doped N-type diffusion region 104 are used to form the source and drain of the NMOS region 100. The high-doped P-type diffusion region 203 and the low-doped P-type diffusion region 204 are used to form the source and drain of the PMOS region 200.

[0046] like Figure 5As shown, in step S3, a first transition metal layer of a first thickness, a first nickel metal layer of a second thickness, and a titanium nitride protective layer of a third thickness are sequentially deposited on the upper surfaces of the first gate 101 and the second gate 201 and the upper surfaces of the highly doped N-type diffusion region 103, the low doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low doped P-type diffusion region 204, and a first nickel silicide alloy layer 105 is formed by a first rapid thermal processing (RTP) process.

[0047] In some embodiments, the first transition metal is selected from terbium (Tb) metal and holmium (Ho) metal. Since the nickel silicide (NiSi) contact layer formed by the metal silicidation reaction between the nickel (Ni) metal layer and the first polysilicon layer 101b of the first gate 101, the second polysilicon layer 201b of the second gate 201 and the silicon elements of the highly doped N-type diffusion region 103, the low-doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low-doped P-type diffusion region 204 through the self-aligned silicide process usually has a low thermal stability, which will cause the junction between the nickel silicide film formed by the self-aligned silicide process and the first gate 101, the second gate 201, the highly doped N-type diffusion region 103, the low-doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low-doped P-type diffusion region 204 to be rough, thereby increasing the junction leakage current, thereby increasing the contact resistivity of the gate and the source and drain electrodes. In the embodiment of the present application, a first transition metal layer composed of terbium (Tb) metal or holmium (Ho) metal is first deposited on the upper surfaces of the first gate 101, the second gate 201 and the upper surfaces of the highly doped N-type diffusion region 103, the low doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low doped P-type diffusion region 204, and then a first nickel metal layer of a second thickness is deposited. Due to the high thermal stability of terbium (Tb) metal or holmium (Ho) metal, a nickel silicide alloy phase doped with terbium (Tb) metal or holmium (Ho) metal is formed in the metal silicide reaction of nickel silicide. This terbium (Tb)-doped nickel silicide alloy phase is The first nickel silicide alloy layer 105 of the nickel silicide alloy phase of metal or holmium (Ho) metal serves as a contact layer, and the junction between the first gate 101, the second gate 201, the highly doped N-type diffusion region 103, the low-doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low-doped P-type diffusion region 204 is smoother, which greatly reduces the junction leakage current between the contact layer and the first gate 101, the second gate 201, the highly doped N-type diffusion region 103, the low-doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low-doped P-type diffusion region 204, thereby significantly reducing the contact resistivity of the contact layer.

[0048] In this embodiment, by depositing a titanium nitride protective layer of a third thickness on the first nickel metal layer, the first nickel metal layer can be prevented from being oxidized during the rapid thermal processing. The titanium nitride protective layer can be removed through a process after the metal silicidation reaction is completed.

[0049] In one embodiment, the first thickness and the second thickness satisfy a ratio of 1:3 to 1:5. For example, when the first thickness of the first transition metal layer is 4 nm, the second thickness of the first nickel metal layer may be 12-20 nm, and so on, when the first thickness of the first transition metal layer is 5 nm, the second thickness of the first nickel metal layer may be 15-25 nm.

[0050] In one embodiment, the first thickness and the third thickness satisfy a ratio of 1:2 to 1:3. For example, when the first thickness of the first transition metal layer is 4 nm, the third thickness of the titanium nitride protective layer may be 8-12 nm, and by analogy, when the first thickness of the first transition metal layer is 5 nm, the third thickness of the titanium nitride protective layer may be 10-15 nm.

[0051] In some embodiments, the forming of the first nickel silicide alloy layer 105 by the first rapid thermal processing process may include: performing rapid annealing at a temperature of 450-500°C for 30-40 seconds in a rapid thermal processing reaction chamber, so that the first transition metal layer, the first nickel metal layer and the silicon element in the first gate 101, the second gate 201, the highly doped N-type diffusion region 103, the low-doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low-doped P-type diffusion region 204 undergo a silicidation reaction to form the first nickel silicide alloy layer 105.

[0052] like Figure 6 and 7 As shown, in step S4, a second transition metal layer of a fourth thickness, a second nickel metal layer of a fifth thickness, and a titanium nitride protective layer of a sixth thickness are sequentially deposited on the upper surfaces of the first gate 101, the second gate 201 and the first nickel silicide alloy layer 105 corresponding to the highly doped N-type diffusion region 103 and the highly doped P-type diffusion region 203, and a second nickel silicide alloy layer 106 is formed by a second rapid thermal processing (RTP) process, wherein the thickness of the second nickel silicide alloy layer 106 is greater than the thickness of the first nickel silicide alloy layer 105.

[0053] Specifically, if Figure 6As shown, first, the first spacer component 102 and the second spacer component 202 are re-formed on both sides of the first gate 101 and the second gate 201, and the first spacer component 102 and the second spacer component 202 respectively cover the upper surface of the first nickel silicide alloy layer 105 corresponding to the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204.

[0054] like Figure 7 As shown, subsequently, using the first spacer component 102 and the second spacer component 202 as masks, a second transition metal layer of a fourth thickness, a second nickel metal layer of a fifth thickness, and a titanium nitride protective layer of a sixth thickness are sequentially deposited on the upper surfaces of the first gate 101, the second gate 201 and the first nickel silicide alloy layer 105 corresponding to the highly doped N-type diffusion region 103 and the highly doped P-type diffusion region 203, and a second nickel silicide alloy layer 106 is formed by a second rapid thermal processing (RTP) process.

[0055] In this embodiment, the first spacer component 102 and the second spacer component 202 respectively cover the upper surfaces of the first nickel silicide alloy layer 105 corresponding to the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204, but do not cover the upper surfaces of the first nickel silicide alloy layer 105 corresponding to the high-doped N-type diffusion region 103 and the high-doped P-type diffusion region 203.

[0056] In some embodiments, the second transition metal is selected from terbium (Tb) metal and holmium (Ho) metal. In the embodiment of the present application, a second transition metal layer composed of terbium (Tb) metal or holmium (Ho) metal with a fourth thickness is further deposited on the first nickel silicide alloy layer 105 corresponding to the first gate 101, the second gate 201 and the highly doped N-type diffusion region 103 and the highly doped P-type diffusion region 203, and then a second nickel metal layer with a fifth thickness is deposited, and a second rapid thermal processing (RTP) process is continued to perform further metal silicide reaction, so that a nickel silicide alloy phase with a greater thickness can be further formed on the basis of the first nickel silicide alloy layer 105, and the nickel silicide alloy phase with a greater thickness covers the upper surface of the highly doped N-type diffusion region 103 and the highly doped P-type diffusion region 203.

[0057] On the one hand, due to the high thermal stability of terbium (Tb) metal or holmium (Ho) metal, a nickel silicide alloy phase doped with terbium (Tb) metal or holmium (Ho) metal will be formed in the metal silicide reaction of nickel silicide. The second nickel silicide alloy layer 106 of the nickel silicide alloy phase doped with terbium (Tb) metal or holmium (Ho) metal serves as a contact layer, and the interface between the second nickel silicide alloy layer 106 and the silicon substrate 10 is smoother, which greatly reduces the interface leakage current between the contact layer and the upper surface of the first gate 101, the second gate 201 and the highly doped N-type diffusion region 103, the highly doped P-type diffusion region 203, thereby significantly reducing the contact resistivity of the contact layer. On the other hand, the thickness of the second nickel silicide alloy layer 106 covering the upper surface of the highly doped N-type diffusion region 103, the highly doped P-type diffusion region 203 is greater than the thickness of the first nickel silicide alloy layer 105 covering the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204. Since the first nickel silicide alloy layer 105 finally only retains the portion covering the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204, the junction depth of the high-doped N-type diffusion region 103 is greater than the junction depth of the low-doped N-type diffusion region 104, and the junction depth of the high-doped P-type diffusion region 203 is greater than the junction depth of the low-doped P-type diffusion region 204. Therefore, the first nickel silicide alloy layer 105 with a smaller thickness can reduce the contact resistivity of the source and drain electrodes without damaging the conduction performance of the shallow channel formed by the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204. At the same time, the second nickel silicide alloy layer 106 covering the upper surface of the high-doped N-type diffusion region 103 and the high-doped P-type diffusion region 203 has a larger thickness, which can more significantly reduce the contact resistivity of the gate and the source and drain electrodes, and will not affect the conduction performance of the deep channel formed by the high-doped N-type diffusion region 103 and the high-doped P-type diffusion region 203.

[0058] In this embodiment, by depositing a titanium nitride protective layer of the sixth thickness on the second nickel metal layer, the second nickel metal layer can be prevented from being oxidized during the rapid thermal processing. The titanium nitride protective layer can be removed through a process after the metal silicidation reaction is completed.

[0059] In one embodiment, the fourth thickness and the fifth thickness satisfy a ratio of 1:3 to 1:5. For example, when the fourth thickness of the second transition metal layer is 5 nm, the fifth thickness of the second nickel metal layer may be 15-25 nm, and so on. When the fourth thickness of the second transition metal layer is 6 nm, the fifth thickness of the second nickel metal layer may be 18-30 nm.

[0060] In one embodiment, the fourth thickness and the sixth thickness satisfy a ratio of 1:2 to 1:3. For example, when the fourth thickness of the second transition metal layer is 5 nm, the sixth thickness of the titanium nitride protective layer may be 10-15 nm, and so on, when the fourth thickness of the second transition metal layer is 6 nm, the sixth thickness of the titanium nitride protective layer may be 12-18 nm.

[0061] In some embodiments, the forming of the second nickel silicide alloy layer 106 by the second rapid thermal processing process may include: performing rapid annealing at a temperature of 500-600°C in a rapid thermal processing reaction chamber for 40-60 seconds, so that the second transition metal layer, the second nickel metal layer and the silicon element in the first gate 101, the second gate 201, the highly doped N-type diffusion region 103, and the highly doped P-type diffusion region 203 undergo silicidation reaction to form the second nickel silicide alloy layer 106.

[0062] In one embodiment, Figure 8 yes Figure 7 The partial enlarged view of the dotted circle frame portion of the cross-sectional view of the sixth process stage of the CMOS device shown, as shown in FIG. Figure 8 As shown, the ratio of the thickness of the second nickel silicide alloy layer 106 to the thickness of the first nickel silicide alloy layer 105 satisfies: ， in represents the thickness of the first nickel silicide alloy layer 105, represents the thickness of the second nickel silicide alloy layer 106, represents the junction depth of the highly doped N-type diffusion region 103 or the junction depth of the highly doped P-type diffusion region 203, represents the junction depth of the low-doped N-type diffusion region 104 or the junction depth of the low-doped P-type diffusion region 204, represents the proportionality coefficient, The value is in the interval [1,2].

[0063] In this embodiment, the junction depth of the highly doped N-type diffusion region 103 is consistent with the junction depth of the highly doped P-type diffusion region 203, and the junction depth of the low doped N-type diffusion region 104 is consistent with the junction depth of the low doped P-type diffusion region 204. The above formula represents the ratio of the thickness of the first nickel silicide alloy layer 105 and the second nickel silicide alloy layer 106 to the ratio of the junction depth of the highly doped N-type diffusion region 103 and the low doped N-type diffusion region 104 or the highly doped P-type diffusion region 2 The ratio of the junction depth of the high-doped N-type diffusion region 103 to the low-doped N-type diffusion region 104 is proportional to the ratio of the junction depth of the high-doped P-type diffusion region 203 to the low-doped P-type diffusion region 204, and the thickness ratio of the first nickel silicide alloy layer 105 and the second nickel silicide alloy layer 106 is adjusted by adjusting the junction depth ratio of the high-doped N-type diffusion region 103 to the low-doped N-type diffusion region 104, or the junction depth ratio of the high-doped P-type diffusion region 203 to the low-doped P-type diffusion region 204, so that the upper surface of the high-doped N-type diffusion region 103 and the high-doped P-type diffusion region 203 is covered. The thickness of the second nickel silicide alloy layer 106 on the surface is greater than the thickness of the first nickel silicide alloy layer 105 covering the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204, and the thickness ratio of the second nickel silicide alloy layer 106 to the first nickel silicide alloy layer 105 is proportional to the ratio of the junction depth of the highly doped N-type diffusion region 103, the highly doped P-type diffusion region 203 to the low-doped N-type diffusion region 104, the low-doped P-type diffusion region 204. For example, the first nickel silicide alloy layer 105 can reduce the contact resistivity of the source and drain electrodes without damaging the conduction performance of the shallow channel composed of the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204. At the same time, the second nickel silicide alloy layer 106 can more significantly reduce the contact resistivity of the gate and the source and drain electrodes, and will not affect the conduction performance of the deep channel composed of the highly doped N-type diffusion region 103 and the highly doped P-type diffusion region 203.

[0064] like Figure 7 As shown, the present application also proposes a CMOS device, which can be prepared by the above-mentioned embodiment, and the CMOS device includes:

[0065] An NMOS region 100 and a PMOS region 200 isolated by an isolation region 300 are formed on a silicon substrate 10, wherein the NMOS region 100 includes a first gate 101, and the PMOS region 200 includes a second gate 201;

[0066] The NMOS region 100 includes a high-doped N-type diffusion region 103 and a low-doped N-type diffusion region 104 on both sides of the first gate 101, and the PMOS region 200 includes a high-doped P-type diffusion region 203 and a low-doped P-type diffusion region 204 on both sides of the second gate 201;

[0067] The NMOS region 100 and the PMOS region 200 respectively include a first nickel silicide alloy layer 105 covering the upper surfaces of the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204, and a second nickel silicide alloy layer 106 covering the upper surfaces of the first gate 101 and the second gate 201, the high-doped N-type diffusion region 103, and the high-doped P-type diffusion region 203, wherein the thickness of the second nickel silicide alloy layer 106 is greater than the thickness of the first nickel silicide alloy layer 105.

[0068] In one embodiment, the ratio of the thickness of the second nickel silicide alloy layer 106 to the thickness of the first nickel silicide alloy layer 105 satisfies: ， in represents the thickness of the first nickel silicide alloy layer 105, represents the thickness of the second nickel silicide alloy layer 106, represents the junction depth of the highly doped N-type diffusion region 103 or the junction depth of the highly doped P-type diffusion region 203, represents the junction depth of the low-doped N-type diffusion region 104 or the junction depth of the low-doped P-type diffusion region 204, represents the proportionality coefficient, The value is in the interval [1,2].

[0069] In summary, a method for preparing a CMOS device and a CMOS device in an embodiment of the present application form a second nickel silicide alloy layer 106 with a larger thickness on the upper surfaces of the highly doped N-type diffusion region 103 and the highly doped P-type diffusion region 203, and form a first nickel silicide alloy layer 105 with a smaller thickness on the upper surfaces of the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204. The first nickel silicide alloy layer 105 and the second nickel silicide alloy layer 106 are nickel silicide alloy phases doped with transition metals in the metal silicidation reaction of nickel silicide, and the junctions between the upper surfaces of the first gate 101 and the second gate 201 and the upper surfaces of the highly doped N-type diffusion region 103, the low-doped N-type diffusion region 104, the highly doped P-type diffusion region 203, and the low-doped P-type diffusion region 204 are smoother, which greatly reduces the junction leakage current of the contact layer, thereby significantly reducing the contact resistivity of the contact layer. On the other hand, the first nickel silicide alloy layer 105 with a smaller thickness can reduce the contact resistivity of the source and drain electrodes without damaging the conduction performance of the shallow channel formed by the low-doped N-type diffusion region 104 and the low-doped P-type diffusion region 204, while the second nickel silicide alloy layer 106 with a larger thickness can also more significantly reduce the contact resistivity of the gate and source and drain electrodes, and will not affect the conduction performance of the deep channel formed by the highly doped N-type diffusion region 103 and the highly doped P-type diffusion region 203.

[0070] It should be noted that those skilled in the art can understand that the different implementation methods described in the method embodiments of the present application and their explanations and technical effects achieved are also applicable to the device embodiments of the present application and will not be repeated here.

[0071] The above describes the exemplary embodiments of the present application. It should be understood that the above exemplary embodiments are not restrictive but illustrative, and the protection scope of the present application is not limited thereto. It should be understood that those skilled in the art can modify and vary the embodiments of the present application without departing from the spirit and scope of the present application, and these modifications and variations should be within the protection scope of the present application.

Claims

1. A method for preparing a CMOS device, characterized in that: The method comprises: An NMOS region and a PMOS region isolated by an isolation region are formed on a silicon substrate, a first gate is grown in the NMOS region, and a second gate is grown in the PMOS region; Forming a high-doped N-type diffusion region and a low-doped N-type diffusion region on both sides of the first gate, and forming a high-doped P-type diffusion region and a low-doped P-type diffusion region on both sides of the second gate by ion implantation; A first transition metal layer of a first thickness, a first nickel metal layer of a second thickness, and a titanium nitride protective layer of a third thickness are sequentially deposited on the upper surfaces of the first gate and the second gate and the upper surfaces of the highly doped N-type diffusion region, the low doped N-type diffusion region, the highly doped P-type diffusion region, and the low doped P-type diffusion region, and a first nickel silicide alloy layer is formed by a first rapid thermal treatment process; A second transition metal layer of a fourth thickness, a second nickel metal layer of a fifth thickness, and a titanium nitride protective layer of a sixth thickness are sequentially deposited on the upper surfaces of the first gate and the second gate and the first nickel silicide alloy layer corresponding to the highly doped N-type diffusion region and the highly doped P-type diffusion region, and a second nickel silicide alloy layer is formed by a second rapid thermal treatment process, wherein the first transition metal layer and the second transition metal layer are selected from one of terbium (Tb) metal and holmium (Ho) metal, the thickness of the second nickel silicide alloy layer is greater than the thickness of the first nickel silicide alloy layer, and the ratio of the thickness of the second nickel silicide alloy layer to the thickness of the first nickel silicide alloy layer satisfies: ,in represents the thickness of the first nickel silicide alloy layer, represents the thickness of the second nickel silicide alloy layer, represents the junction depth of the highly doped N-type diffusion region or the junction depth of the highly doped P-type diffusion region, represents the junction depth of the low-doped N-type diffusion region or the junction depth of the low-doped P-type diffusion region, represents the proportionality coefficient, The value is in the interval [1,2].

2. The method for preparing a CMOS device according to claim 1, characterized in that: The doping concentration of the highly doped N-type diffusion region is greater than the doping concentration of the low doped N-type diffusion region, and the doping concentration of the highly doped P-type diffusion region is greater than the doping concentration of the low doped P-type diffusion region.

3. The method for preparing a CMOS device according to claim 2, characterized in that: The first thickness and the second thickness, as well as the fourth thickness and the fifth thickness, satisfy a ratio relationship of 1:3 to 1:5; the first thickness and the third thickness, as well as the fourth thickness and the sixth thickness, satisfy a ratio relationship of 1:2 to 1:

3.

4. The method for preparing a CMOS device according to claim 3, characterized in that: The forming of the first nickel silicide alloy layer by the first rapid thermal processing process includes: performing rapid annealing for 30-40 seconds at a temperature of 450-500°C in a rapid thermal processing reaction chamber, so that the first transition metal layer, the first nickel metal layer and the silicon elements in the first gate, the second gate, the highly doped N-type diffusion region, the low-doped N-type diffusion region, the highly doped P-type diffusion region, and the low-doped P-type diffusion region undergo silicidation reaction to form the first nickel silicide alloy layer.

5. The method for preparing a CMOS device according to claim 4, characterized in that: The forming of the second nickel silicide alloy layer by the second rapid thermal processing process includes: performing rapid annealing at a temperature of 500-600°C for 40-60 seconds in a rapid thermal processing reaction chamber, so that the second transition metal layer, the second nickel metal layer and the silicon elements in the first gate, the second gate, the highly doped N-type diffusion region, and the highly doped P-type diffusion region undergo silicidation reaction to form the second nickel silicide alloy layer.

6. The method for preparing a CMOS device according to claim 2, characterized in that: The junction depth of the highly doped N-type diffusion region is greater than the junction depth of the low doped N-type diffusion region, and the junction depth of the highly doped P-type diffusion region is greater than the junction depth of the low doped P-type diffusion region.

7. A CMOS device, characterized in that: The CMOS device comprises: An NMOS region and a PMOS region isolated by an isolation region are formed on a silicon substrate, wherein the NMOS region includes a first gate and the PMOS region includes a second gate; The NMOS region includes a high-doped N-type diffusion region and a low-doped N-type diffusion region on both sides of the first gate, and the PMOS region includes a high-doped P-type diffusion region and a low-doped P-type diffusion region on both sides of the second gate; The NMOS region and the PMOS region respectively include a first nickel silicide alloy layer covering the upper surfaces of the low-doped N-type diffusion region and the low-doped P-type diffusion region, and a second nickel silicide alloy layer covering the upper surfaces of the first gate and the second gate, the upper surfaces of the highly doped N-type diffusion region and the highly doped P-type diffusion region, the first nickel silicide alloy layer includes a first transition metal layer of a first thickness, a first nickel metal layer of a second thickness, and a titanium nitride protective layer of a third thickness deposited in sequence, the second nickel silicide alloy layer includes a second transition metal layer of a fourth thickness, a second nickel metal layer of a fifth thickness, and a titanium nitride protective layer of a sixth thickness deposited in sequence, wherein the first transition metal layer and the second transition metal layer are selected from one of terbium (Tb) metal and holmium (Ho) metal, the thickness of the second nickel silicide alloy layer is greater than the thickness of the first nickel silicide alloy layer, and the ratio of the thickness of the second nickel silicide alloy layer to the thickness of the first nickel silicide alloy layer satisfies: ,in represents the thickness of the first nickel silicide alloy layer, represents the thickness of the second nickel silicide alloy layer, represents the junction depth of the highly doped N-type diffusion region or the junction depth of the highly doped P-type diffusion region, represents the junction depth of the low-doped N-type diffusion region or the junction depth of the low-doped P-type diffusion region, represents the proportionality coefficient, The value is in the interval [1,2].

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