Memory and operating method thereof, memory system

Abstract

The embodiment of the present application provides a memory and an operation method thereof and a memory system, wherein the memory comprises a first storage surface, a second storage surface and a surface data bus connected with the first storage surface and the second storage surface; wherein the surface data bus is used for receiving input data; the first storage surface is used for storing first data in the input data; the second storage surface is used for storing second data in the input data; and the second data is used for representing whether the first data is subjected to an inversion operation before transmission.

Description

Memory and its operation methods, memory system

[0001] This application is a divisional application of the patent filed on March 16, 2022, with application number 2022102583377, entitled "Method for Programming a Memory and a Memory". Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a memory and its operation method, and a memory system. Background Technology

[0003] Data Bus Inversion (DBI) is a low-power transmission technology that requires the transmission of both the actual data and DBI data (indicating whether the actual data has been inverted during transmission) when storing data.

[0004] In related technologies, when using DBI technology to transmit data, the memory is not compatible with the transmission and / or storage of DBI data. For example, additional storage space is required, and the memory manufacturing cost is high. Summary of the Invention

[0005] To address the related technical problems, embodiments of the present invention propose a memory, its operation method, and a memory system.

[0006] This invention provides a memory, including: a first storage surface, a second storage surface, and a surface data bus connected to both the first storage surface and the second storage surface; wherein,

[0007] The surface data bus is used to receive input data;

[0008] The first storage surface is used to store the first data in the input data; the second storage surface is used to store the second data in the input data; the second data is used to characterize whether the first data was reversed before transmission.

[0009] In the above scheme, the first data includes M data bits; the second data includes 1 data bit; the input data is M+1 data bits; and M is an integer multiple of 8.

[0010] In the above scheme, the memory further includes: a first surface storage bus transmission control module disposed between the first storage surface and the surface data bus, and a second surface storage bus transmission control module disposed between the second storage surface and the surface data bus; wherein,

[0011] In response to the first instruction, the first data is written to the first storage surface through the first surface storage bus transmission control module, and the second data is written to the second storage surface through the second surface storage bus transmission control module;

[0012] In response to the second instruction, the first data is read from the first storage surface via the first storage bus transmission control module, and the second data is read from the second storage surface via the second storage bus transmission control module.

[0013] In the above scheme, the second-side storage bus transmission control module includes: a first write data interface, a second write data interface, a first selector, a first read data interface, a second read data interface, and a second selector; wherein,

[0014] The input terminal of the first selector is connected to the first write data interface and the second write data interface, and the output terminal is connected to the second storage surface.

[0015] The input of the second selector is connected to the second storage surface, and the output is connected to the first data read interface and the second data read interface.

[0016] In the above scheme, the second-side storage bus transmission control module is specifically used for:

[0017] In response to the first instruction, N second data are written to the second storage surface through the first selector and the second write data interface; the N data on the N data bits specified in the M*N data bits output by the first selector output terminal correspond to the N second data; where N is a positive integer;

[0018] In response to the second instruction, N second data are read from the second storage surface through the second selector and the second data read interface; the N data on the N data bits output by the output of the second selector correspond to the N second data.

[0019] In the above scheme, the second-side storage bus transmission control module further includes: a first interface data bus, a second interface data bus, and a third interface data bus; wherein,

[0020] The first write data interface is connected to the input terminal of the first selector through the first interface data bus;

[0021] The second write data interface is connected to the input terminal of the first selector through the second interface data bus;

[0022] The second storage surface is connected to the output of the first selector via the third interface data bus.

[0023] In the above scheme, the first-side storage bus transmission control module includes: a third write data interface, a fourth write data interface, a third selector, a third read data interface, a fourth read data interface, and a fourth selector; wherein,

[0024] The input of the third selector is connected to the third write data interface and the fourth write data interface, and the output is connected to the first storage surface.

[0025] The input of the fourth selector is connected to the first storage surface, and the output is connected to the third and fourth read data interfaces.

[0026] In the above scheme, the first-side storage bus transmission control module is specifically used for:

[0027] In response to the first instruction, N first data are written into the first storage surface through the third selector and the third write data interface; the M*N data on the M*N data bits output by the third selector output terminal correspond to the N first data; N is a positive integer;

[0028] In response to the second instruction, N first data are read from the storage in the first storage plane through the fourth selector and the third data reading interface; the M*N data on the M*N data bits output by the fourth selector output terminal correspond to the N first data.

[0029] In the above scheme, the power supply voltage of the first write data interface, the second write data interface, the first read data interface, the second read data interface, the third write data interface, the fourth write data interface, the third read data interface, and the fourth read data interface is approximately 1.2V.

[0030] In the above scheme, the first-side storage bus transmission control module further includes a first data buffer, and the second-side storage bus transmission control module further includes a second data buffer; wherein,

[0031] The first data buffer is located between the output of the fourth selector and the third and fourth data read interfaces, and is used to temporarily store the first data read from the first storage surface;

[0032] The second data buffer is located between the output of the second selector and the first and second data read interfaces, and is used to temporarily store the second data read from the second storage surface;

[0033] The surface data bus is also used to merge the temporarily stored first data and the temporarily stored second data into output data before outputting it.

[0034] In the above scheme, the memory further includes a serial-to-parallel conversion circuit;

[0035] The serial-to-parallel conversion circuit has one end connected to the data input interface and the other end connected to the surface data bus, and is used to convert the input data from serial to parallel.

[0036] In the above scheme, the first data is transmitted in an unencoded format.

[0037] In the above scheme, the first storage surface and the second storage surface have basically the same structural features and share the surface data bus;

[0038] The memory further includes peripheral circuitry configured to perform write and read operations on the first and second storage surfaces.

[0039] In the above scheme, the memory includes a three-dimensional NAND memory.

[0040] This invention also provides a memory system, comprising:

[0041] One or more memories as described in the above embodiments of the present invention; and

[0042] A storage controller coupled to the memory.

[0043] This invention also provides a method for operating a memory, used in the memory described in the above embodiments of this invention; the method for operating the memory includes:

[0044] Received the first instruction;

[0045] In response to the first instruction, both the first storage plane and the second storage plane are activated simultaneously; and

[0046] Write the first data from the input data into the first storage surface, and write the second data from the input data into the second storage surface.

[0047] The method in the above scheme further includes:

[0048] Received the second instruction;

[0049] In response to the second instruction, both the first storage plane and the second storage plane are activated simultaneously;

[0050] Read the first data from the first storage surface and temporarily store the read first data; and read the second data from the second storage surface and temporarily store the read second data; and

[0051] The first and second temporarily stored data are merged and then output.

[0052] This invention also provides another method for operating a memory, used in the memory described in the above embodiments of this invention; the method for operating the memory includes:

[0053] Received the second instruction;

[0054] In response to the second instruction, both the first storage plane and the second storage plane are activated simultaneously;

[0055] Read the first data from the first storage surface and temporarily store the read first data; and read the second data from the second storage surface and temporarily store the read second data; and

[0056] The first and second temporarily stored data are merged and then output.

[0057] This invention provides a memory and its operating method, as well as a memory system. The memory includes a first storage surface, a second storage surface, and a surface data bus connected to both the first and second storage surfaces. The surface data bus is used to receive input data. The first storage surface stores first data from the input data. The second storage surface stores second data from the input data. The second data is used to characterize whether the first data underwent a reversal operation before transmission. In this invention, by storing the first data to be transmitted in the first storage surface and storing the second data characterizing whether the first data underwent a reversal operation before transmission in the second storage surface connected to the same surface data bus as the first storage surface, the existing memory architecture can be used without adding extra storage space for transmitting the second data, thereby reducing the manufacturing cost of the memory. Attached Figure Description

[0058] Figure 1 is a schematic diagram of the structure of a memory in the related technology;

[0059] Figure 2 is a schematic diagram of the composition structure of a memory provided in an embodiment of the present invention;

[0060] Figures 3a-3c are schematic diagrams of several example structures of a memory provided in an embodiment of the present invention;

[0061] Figure 4 is a schematic diagram of the implementation flow of a memory operation method provided in an embodiment of the present invention;

[0062] Figure 5 is a schematic diagram of the implementation flow of another memory operation method provided in an embodiment of the present invention. Detailed Implementation

[0063] To make the technical solutions and advantages of the embodiments of the present invention clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of the present invention. The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0064] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0065] The DBI technology involved in this embodiment of the invention is a low-power transmission technology. The DBI mechanism is used to limit the number of data bits that can be switched across the interface width (e.g., half or less). Under the DBI mechanism, if the logic level of most bits of the current data differs from the previous data transmitted in the previous data transmission cycle without inversion, then all bits of the current data to be transmitted are inverted before transmitting the current data. However, if the previous data with inversion is transmitted, then the current data is transmitted in the same way, even if the logic level of most bits of the current data differs from the previous data. The DBI mechanism is executed to detect whether the logic level of most bits of the current data differs from the previous data. DBI data can be used to indicate whether to perform an inversion on the transmitted current data. That is, the purpose of setting DBI data is to reduce power consumption in systems where power consumption between Alternate Signaled States is asymmetrical by selectively inverting the system's data bus.

[0066] The following example illustrates DBI technology. For instance, suppose the memory's data interface includes eight DQ (DataQueue) interfaces and one DBI interface. The eight DQ interfaces transmit eight-bit data signals, i.e., DQ data (stored data), while the one DBI interface transmits a one-bit signal indicating whether the data has been inverted, i.e., DBI data. In some embodiments, transmitting a high-level data signal is more power-efficient. When more than half (five) of the eight data bits to be transmitted are at a low level, these five data bits are inverted to a high level, while the remaining three data bits are inverted from a high level to a low level. Simultaneously, the DBI is set to indicate that the data has been inverted, such as when the DBI interface is set to a high level. Conversely, when less than half (three) of the eight data bits to be transmitted are at a high level, the data is transmitted directly, and the DBI is set to indicate that the data has not been inverted, such as when the DBI interface is set to a low level. In this way, during the synchronous transmission of data, more than half of the data bits in the multiple data interfaces of the memory interface are kept in a power-saving potential state at the same time, so as to save power during data transmission.

[0067] DBI technology can also be used to transfer data in memory, such as NAND flash memory.

[0068] In some specific examples, the Joint Electron Device Engineering Council (JEDEC) protocol specifies requirements for the data transfer speed and method of NAND flash memory. During data transfer, to reduce power consumption, each storage surface stores multiple data items with corresponding DBI (Data Inversion Buffer) data supporting the DBI mechanism. Here, the DBI data and the stored data are stored on the same storage surface, and the DBI data indicates whether the corresponding stored data underwent a reversal operation before transmission. In some embodiments, as shown in FIG1, the memory 10 includes a first storage surface 101 and a second storage surface 102. Data is written or read from the memory and transmitted to other devices via the surface data bus 103.

[0069] In some specific examples, read operations can be performed on data stored in the first storage surface 101 or the second storage surface 102 according to the received instructions; write data can also be stored in the first storage surface 101 or the second storage surface 102 according to the received instructions. Here, the second storage surface 102 and the first storage surface 101 may have the same structural features and have basically the same data bus structure. For example, as shown in Figure 1, the data transmission bus corresponding to the first storage surface 101 (the data bus between the first storage surface 101 and the surface data bus 103) and the data transmission bus corresponding to the second storage surface 102 (the data transmission bus between the second storage surface 102 and the surface data bus 103) are basically the same, and can even be arranged symmetrically on the left and right. The surface storage bus transmission control module corresponding to the first storage surface 101 and the surface storage bus transmission control module corresponding to the second storage surface 102 are basically the same. The data transmission bus and the surface storage bus transmission control module corresponding to the first storage surface 101 / second storage surface 102 are not compatible with the transmission of DBI data. Therefore, additional storage elements and desired additional data transmission buses (i.e., fourth data buses 1014 and 1024) can be set for the first storage surface 101 and the second storage surface 102 respectively to transmit and store DBI data.

[0070] For ease of understanding, this embodiment of the invention will be described using the example of writing the data to be operated on into the first storage surface or reading the data stored in the first storage surface.

[0071] In some specific examples, stored data with multiple data bits, such as 8 data bits, is input from 8 data interfaces, while DBI data with 1 data bit is input from 1 data interface, which is DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 and DBI shown in Figure 1. This data is transmitted to the surface data bus after passing through a serial-to-parallel conversion circuit.

[0072] In some specific examples, during a write operation, the data corresponding to the DQ0-DQ7 interfaces is transmitted via the third data bus 1013 and stored in the first storage surface 101; simultaneously, the data corresponding to the DBI interface is transmitted via the fourth data bus 1014 and stored in an additional storage element. Here, the additional storage element is a storage element independent of the storage surface, and the fourth data bus is a data transmission line connected to the additional storage element.

[0073] It should be noted that the data corresponding to the DBI interface corresponds to the data in the DQ0-DQ7 interfaces. That is, the data corresponding to 1 DBI interface can indicate whether the data corresponding to 8 (DQ0-DQ7) interfaces has been reversed.

[0074] In some specific examples, when performing a read operation, the data to be operated on is read from the first storage surface 101 via the first data bus 1011, and the read data is transferred to the surface data bus 103. At the same time, the DBI data corresponding to the read data is transferred to the surface data bus 103 via the second data bus 1012.

[0075] In some specific embodiments, referring to FIG1, when the data for performing the write or read operation includes 8 data, the data occupies 64 bits, i.e., gwd_l_vlo<63:0> in FIG1; the corresponding DBI data also includes 8 data, which occupies 8 bits, i.e., gwd_dbi_l_vlo<7:0> in FIG1. ​​Therefore, the data transmitted by the surface data bus 103 includes the data for performing the write or read operation and the DBI data, i.e., 72 data bits.

[0076] In the above embodiments, when using DBI technology, it is impossible to realize the transmission and storage of DBI data under a memory architecture that only includes the storage plane and the corresponding data transmission bus. It is necessary to provide an additional, longer data bus (fourth data bus 1014) and additional storage space (additional storage element) to transmit and store dedicated DBI data, which increases the manufacturing cost of the memory.

[0077] This invention also provides a memory that is improved in at least some aspects compared to the memory shown in FIG1. ​​FIG2 is a schematic diagram of the main components of the memory 20 provided in this invention. As shown in FIG2, the memory 20 includes: a first storage surface 201, a second storage surface 202, and a surface data bus 203 connected to both the first storage surface 201 and the second storage surface 202; wherein,

[0078] The surface data bus 203 is used to receive input data;

[0079] The first storage surface 201 is used to store the first data in the input data; the second storage surface is used to store the second data in the input data; the second data is used to characterize whether the first data was reversed before transmission.

[0080] The memory in the embodiments of this application includes, but is not limited to, three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is used as an example for explanation. However, it should be understood that the embodiments conceived in this application are not limited to this configuration, but can also be applied to, for example, two-dimensional NAND memory. In addition, without departing from the scope of this application, this application can be applied to other non-volatile memory devices, such as electrically erasable programmable read-only memory (EEPROM), NOR flash memory, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0081] In some specific examples, the three-dimensional NAND type memory may include a stacked array of memory cells and peripheral circuitry; wherein the memory cell array has multiple memory planes, each memory plane includes multiple memory blocks, each memory block includes multiple memory pages, a memory page is the smallest unit for reading and writing (i.e., programming), and a memory block is the smallest unit for erasing.

[0082] The peripheral circuitry may include any suitable digital, analog, and / or mixed-signal circuitry configured to facilitate various operations such as read, write, and erase operations of the memory. For example, the peripheral circuitry may include control logic (e.g., control circuitry or controller), data buffers, decoders (also called decoders), drivers, and read / write circuitry. When the control logic receives read / write operation commands and address data, under the control of the control logic, the decoder can, based on the decoded address, apply the corresponding voltage from the driver to the corresponding bit line and word line to realize data read / write and interact with the outside world through the data buffer.

[0083] Here, the memory 20 includes at least a first storage surface 201 and a second storage surface 202. In some specific embodiments, the first storage surface 201 and the second storage surface 202 may have essentially the same structural features, and they are physically isolated in terms of device structure, so that no signal interference will occur during data transmission. Here, the surface data bus 203 connects the first storage surface 201 and the second storage surface 202 respectively. After the host or memory system issues a write command, the write data (i.e., input data) can be stored in the first storage surface 201 or the second storage surface 202 through the surface data bus 203. Similarly, after the host or memory system receives a read command, it can also read the data stored in the first storage surface 201 or the second storage surface 202 and transmit it through the surface data bus 203.

[0084] It should be noted that both the first storage surface 201 and the second storage surface 202 can perform data writing and data reading operations, and the first storage surface 201 and the second storage surface 202 share a surface data bus 203.

[0085] In this embodiment of the invention, the first storage surface and the second storage surface in the memory with the above-mentioned hardware conditions are utilized simultaneously. That is, the input data transmitted to the surface data bus is divided into two. The actual data to be transmitted (first data) in the input data that supports the DBI mechanism is stored in the first storage surface, while the data in the input data used to characterize whether a reversal operation was performed during actual data transmission (second data) is stored in the second storage surface.

[0086] In other words, in the previous embodiments, when performing write or read operations on input data, only one of the storage surface and the spare storage surface is activated and used. In order to store DBI data, additional storage elements and data transmission buses need to be added under the current memory architecture. However, in the embodiments of the present invention, DBI data is stored in the second storage surface, and the current memory architecture can be used during the transmission process, thus eliminating the need to change the existing storage architecture, saving memory manufacturing costs, and improving the utilization rate of the spare storage surface.

[0087] Here, the input data supports the DBI mechanism. The first data is the actual data to be transmitted during the data transmission process, i.e., the actual data to be transmitted in the input data; the second data is the data used to characterize whether the actual data to be transmitted underwent a reversal operation during transmission. In some specific examples, the second data corresponds to the first data in real time. The DBI mechanism has been introduced previously and will not be repeated here.

[0088] Here, the surface data bus 203 can receive input data and also send output data. The input data may include first data and second data; the output data may also include first data and second data.

[0089] In some specific examples, the first data in the input data can be stored in a second storage surface, while the second data in the input data can be stored in a first storage surface. That is, the first data in the input data is stored in a storage surface connected to a certain data bus, and the second data in the input data is stored in another storage surface connected to that data bus.

[0090] In some embodiments, the first storage surface 201 and the second storage surface 202 have substantially the same structural features and share the surface data bus;

[0091] The memory further includes peripheral circuitry configured to perform write and read operations on the first storage surface 201 and the second storage surface 202.

[0092] Here, the fact that the first storage surface 201 and the second storage surface 202 have basically the same structural features can be understood as the first storage surface 201 and the second storage surface 202 having the same architecture, the number of storage blocks they contain, the number of storage pages, and the connection relationship between each component, except for minor differences caused by factors such as manufacturing errors.

[0093] How the peripheral circuitry specifically implements the operations of writing and reading data to the first storage surface 201 and the second storage surface 202 will be described in detail later.

[0094] In some embodiments, the first data includes M data bits; the second data includes 1 data bit; the input data is M+1 data bits; and M is an integer multiple of 8.

[0095] Here, the first data may include multiple data bits, and the number of data bits in the first data is an integer multiple of 8, such as 8 bits, 16 bits, etc.; the second data may include 1 data bit. In some specific embodiments, the first data may include 8 data bits, and the second data may include 1 data bit, which can indicate whether the 8 data bits of the first data have been inverted.

[0096] Here, the data bits of the input data or the data bits of the output data transmitted in the surface data bus 203 are the sum of the first data and the second data, that is, the surface data bus 203 includes M+1 data bits.

[0097] Figures 3a-3c are schematic diagrams of a memory provided in an embodiment of the present invention. The memory of the embodiment of the present invention will be described in detail below with reference to Figures 3a-3c.

[0098] In some embodiments, as shown in FIG3a, the memory further includes: a first surface storage bus transmission control module 206 disposed between the first storage surface 201 and the surface data bus 203, and a second surface storage bus transmission control module 207 disposed between the second storage surface 202 and the surface data bus 203; wherein,

[0099] In response to the first instruction, the first data is written to the first storage surface 201 through the first surface storage bus transmission control module 206, and the second data is written to the second storage surface 202 through the second surface storage bus transmission control module 207.

[0100] In response to the second instruction, the first data is read from the first storage surface 201 through the first surface storage bus transmission control module 206, and the second data is read from the second storage surface 202 through the second surface storage bus transmission control module 207.

[0101] In some specific examples, the first instruction includes a write instruction; the second instruction includes a read instruction.

[0102] As shown in Figure 3a, the control logic of the peripheral circuit can issue corresponding write commands based on the instructions of the host or storage controller. Based on the write commands, the allocation of, for example, M+1 data bits transmitted by the control plane data bus 203 can be controlled. The first data bit of M data bits can be written to the first storage plane 201 by controlling the first storage bus transmission control module 206. At the same time, the second data bit of 1 data bit (i.e., DBI data) can be written to the second storage plane 202 by controlling the second storage bus transmission control module 207.

[0103] The control logic of the peripheral circuit can issue corresponding read commands based on instructions from the host or storage controller. Based on these read commands, it controls, for example, M+1 data bits to be read from the first storage surface 201 and the second storage surface 202 respectively. First data can be read from the first storage surface 201 by controlling the first storage bus transmission control module 206. Simultaneously, second data can be read from the second storage surface 202 by controlling the second storage bus transmission control module 207.

[0104] The specific components (structural features) included in the first-side storage bus transmission control module 206 and the second-side storage bus transmission control module 207 may be the same or different. It is understood that the first-side storage bus transmission control module 206 and the second-side storage bus transmission control module 207 can realize the writing and reading of first and second data containing different data bits.

[0105] In some embodiments, as shown in FIG3b or 3c, the second-side storage bus transmission control module 207 includes: a first write data interface 2021, a second write data interface 2022, a first selector 2023, a first read data interface 2024, a second read data interface 2025, and a second selector 2026; wherein,

[0106] The input terminal of the first selector 2023 is connected to the first write data interface 2021 and the second write data interface 2022, and the output terminal is connected to the second storage surface 202.

[0107] The input of the second selector 2026 is connected to the second storage surface 202, and the output is connected to the first read data interface 2024 and the second read data interface 2025.

[0108] Here, both the first selector 2023 and the second selector 2026 are used to select a certain data transmission mode. In some specific examples, both the first selector 2023 and the second selector 2026 can be coupled to the control logic of the peripheral circuit and controlled by the control logic. The control logic can issue a corresponding write instruction according to the instruction of the host or storage controller, and send a first selection signal such as "1" to the first selector, thereby controlling the first selector 2023 to select the bus for transmitting DBI; similarly, the control logic can issue a corresponding read instruction according to the instruction of the host or storage controller, and send a second selection signal (cmd_wr_train shown in Figure 3b) such as "1" to the second selector 2026, thereby controlling the second selector 2026 to select the bus for transmitting DBI.

[0109] In some embodiments, as shown in FIG3b or 3c, the second-side storage bus transmission control module 207 is specifically used for:

[0110] In response to the first instruction, N second data are written to the second storage surface 202 through the first selector 2023 and the second write data interface 2022; the N data on the N data bits specified in the M*N data bits output by the first selector 2023 correspond to the N second data; N is a positive integer.

[0111] In response to the second instruction, N second data are read from the second storage surface 202 through the second selector 2026 and the second read data interface 2025; the N data on the N data bits output by the output terminal of the second selector 2026 correspond to the N second data.

[0112] Here, when writing N second data bits, the M*N data bits output by the first selector 2023 are mapped to N specified data bits out of the M*N data bits when the first selector 2023 selects the bus for transmitting DBI. The specified N data bits can be one bit taken from every M data bits. For example, when M=N=8, the specified 8 data bits can be the first one shown in Figure 3b. <0> Position, No. <8> Position, No. <16> Position, No. <24> Position, No. <32> Position, No. <40> Position, No. <48> Position, No. <56> Bit.

[0113] When reading N pieces of second data, the output of the second selector 2026 outputs N data bits, which constitute the N pieces of second data. When the second selector 2026 reads data from the second storage surface 202, it maps N data bits specified from the M*N data bits to the second read data interface 2025. The N data bits specified during reading are the same as the N data bits specified during writing.

[0114] In some embodiments, as shown in FIG3b or 3c, the second-side storage bus transmission control module 207 further includes: a first interface data bus 2027, a second interface data bus 2028, and a third interface data bus 2029; wherein,

[0115] The first write data interface 2021 is connected to the input terminal of the first selector 2023 through the first interface data bus 2027;

[0116] The second write data interface 2022 is connected to the input terminal of the first selector 2023 through the second interface data bus 2028;

[0117] The second storage surface 202 is connected to the output of the first selector 2023 through the third interface data bus 2029.

[0118] Here, both the first interface data bus 2027 and the second interface data bus 2028 are shorter than the third interface data bus 2029. It can be understood that the lengths of the first interface data bus 2027 and the third interface data bus 2029 are equivalent to the length of 1023 in the scheme of Figure 1, while the newly added second interface data bus 2028 is much shorter than the length of 1024 in the scheme of Figure 1. Therefore, the scheme of this embodiment can save data buses.

[0119] In some embodiments, the specific devices (structural features) included in the first surface storage bus transmission control module 206 and the second surface storage bus transmission control module 207 may be the same.

[0120] In some specific embodiments, as shown in FIG3b, the first-side storage bus transmission control module 206 includes: a third write data interface 2011, a fourth write data interface 2012, a third selector 2013, a third read data interface 2014, a fourth read data interface 2015, and a fourth selector 2016; wherein,

[0121] The input terminal of the third selector 2013 is connected to the third write data interface 2011 and the fourth write data interface 2012, and the output terminal is connected to the first storage surface 201.

[0122] The input of the fourth selector 2016 is connected to the first storage surface 201, and the output is connected to the third read data interface 2014 and the fourth read data interface 2015.

[0123] Here, both the third selector 2013 and the fourth selector 2016 are used to select a certain data transmission mode. In some specific examples, both the third selector 2013 and the fourth selector 2016 can be coupled to the control logic of the peripheral circuit and controlled by the control logic. The control logic can issue a corresponding write instruction according to the instruction of the host or storage controller, and send a third selection signal such as "0" to the third selector, thereby controlling the third selector 2013 to select the bus for transmitting write data; similarly, the control logic can issue a corresponding read instruction according to the instruction of the host or storage controller, and send a fourth selection signal such as "0" to the fourth selector, thereby controlling the fourth selector 2016 to select the bus for transmitting read data.

[0124] In some specific embodiments, as shown in FIG3b, the first surface storage bus transmission control module 206 is specifically used for:

[0125] In response to the first instruction, N first data are written into the first storage surface 201 through the third selector 2013 and the third write data interface 2011; the M*N data on the M*N data bits output by the third selector output terminal correspond to the N first data; N is a positive integer.

[0126] In response to the second instruction, N first data are read from the storage in the first storage surface 201 through the fourth selector 2016 and the third data reading interface 2014; the M*N data on the M*N data bits output by the output terminal of the fourth selector 2016 correspond to the N first data.

[0127] Here, when writing N first data, the M*N data bits output by the third selector 2013 are directly mapped to the M*N data bits when the third selector 2013 selects the bus for transmitting the written data.

[0128] When reading N first data points, the fourth selector 2016 outputs M*N data bits, which constitute N M-bit second data points. When the fourth selector 2016 reads data from the first storage surface 201, it directly maps the data in the M*N data bits to the third data read interface 2014.

[0129] In some embodiments, as shown in FIG3b, the first-side storage bus transmission control module 206 further includes: a fourth interface data bus 2017, a fifth interface data bus 2018, and a sixth interface data bus 2019; wherein,

[0130] The third write data interface 2011 is connected to the input terminal of the third selector 2013 through the fourth interface data bus 2017;

[0131] The fourth write data interface 2012 is connected to the input terminal of the fourth selector 2016 through the fourth interface data bus 2018;

[0132] The first storage surface 201 is connected to the output of the third selector 2013 through the sixth interface data bus 2019.

[0133] It is understandable that when the specific devices included in the first-side storage bus transmission control module 206 and the second-side storage bus transmission control module 207 are the same, both the first-side storage bus transmission control module 206 and the second-side storage bus transmission control module 207 can be compatible with the data transmission of different data bits between the surface data bus and the storage surface. Thus, by controlling and sending corresponding selection signals to each selector, the first data or the second data can be stored in one of the first storage surface and the second storage surface respectively, and this storage relationship can be interchanged.

[0134] Meanwhile, when the specific components included in the first-side storage bus transmission control module 206 and the second-side storage bus transmission control module 207 are the same, the first-side storage bus transmission control module 206 and the second-side storage bus transmission control module 207 can support the use of the same set of programs, thus reducing the workload of program development. In addition, when the structural features of the first-side storage bus transmission control module 206 and the second-side storage bus transmission control module 207 are consistent, the manufacturing process can also be simplified.

[0135] In some embodiments, the specific devices (structural features) included in the first surface storage bus transmission control module 206 and the second surface storage bus transmission control module 207 may be different.

[0136] In some specific embodiments, as shown in FIG3c, the first-side storage bus transmission control module 206 does not include the third selector 2013 shown in FIG3b and the related data bus; and the fourth selector 2016 in the first-side storage bus transmission control module 206 is always fixed to select the bus used for transmitting read data, or even the fourth selector 2016 can be omitted.

[0137] It is understandable that when the specific devices contained in the first storage bus transmission control module 206 and the second storage bus transmission control module 207 are different, and the first storage bus transmission control module 206 cannot realize the data transmission of different data bits between the surface data bus and the storage surface, it is necessary to store the first data in the first storage surface and store the second data in the second storage surface, and this storage relationship cannot be changed.

[0138] For example, referring to FIG3b, the input data in the surface data bus 203 includes 72 data bits (vlo<71:0>), which includes eight 8-bit first data bits (vlo<63:0>) and eight 1-bit second data bits (vlo<7:0>).

[0139] In response to the first instruction, eight 8-bit first data (vlo<63:0>) from the input data are stored in the first storage surface 201; and eight 1-bit second data (vlo<7:0>) from the input data are stored in the second storage surface 202. These eight second data correspond one-to-one with the eight first data.

[0140] In response to the second instruction, read eight 8-bit first data (vlo<63:0>) stored in the first storage surface 201; read eight 1-bit second data (vlo<7:0>) stored in the second storage surface 202.

[0141] Next, the eight 8-bit first data (vlo<63:0>) and the eight 1-bit second data (vlo<7:0>) are merged to form the output data.

[0142] Next, the output data will be transferred to the data buffer (DQ FIFO).

[0143] In some embodiments, the power supply voltage (VCCQ) of the first write data interface 2021, the second write data interface 2022, the first read data interface 2024, the second read data interface 2025, and the third write data interface 2011, the fourth write data interface 2012, the third read data interface 2014, and the fourth read data interface 2015 is a low-level voltage, for example, about 1.2V.

[0144] It is understandable that the lower the power supply voltage of the input or output data interface, the less power is consumed in data transmission; the higher the power supply voltage, the easier it is to distinguish the logic high or low level of the transmitted data.

[0145] In related technologies, the power supply voltage for input or output data interfaces is typically around 1.8V, resulting in high power consumption during data transmission. In this embodiment of the invention, the power supply voltage for both input and output data interfaces is approximately 1.2V, thereby reducing power consumption during data transmission while still being able to distinguish between high and low data levels.

[0146] It should be noted that the "approximately" in the above-mentioned approximately 1.8V or approximately 1.2V can be understood as the target voltage value designed for the power supply voltage during circuit design. However, in actual use, the voltage value will be distributed within a certain range around the target voltage value. This certain range is usually relatively small, such as ±0.1V. This certain range is related to the accuracy of the power supply device and the load conditions.

[0147] In some embodiments, as shown in FIG3b, the first-side storage bus transmission control module 206 further includes a first data buffer 2020 and a second-side storage bus transmission control module 207; the memory further includes a second data buffer 2030; wherein...

[0148] The first data buffer 2020 is located between the output of the fourth selector 2016 and the third data read interface 2014 and the fourth data read interface 2015, and is used to temporarily store the first data read from the first storage surface 201;

[0149] The second data buffer 2030 is located between the output of the second selector 2026 and the first data read interface 2024 and the second data read interface 2025, and is used to temporarily store the second data read from the second storage surface 202;

[0150] The surface data bus 203 is also used to merge the temporarily stored first data and the temporarily stored second data into output data and then output it.

[0151] A data buffer is a memory used to temporarily store data when it passes between components with different transmission capabilities, thereby balancing the transmission speeds of different components. In some specific examples, the first data buffer 2020 and the second data buffer 2030 can be latches.

[0152] Understandably, the first storage surface 201 and the second storage surface 202 store different data bits, resulting in a difference in their data transmission speeds. Here, a first data buffer is set in the first storage surface to temporarily store the first data read from the first storage surface; a second data buffer is set in the second storage surface to temporarily store the second data read from the second storage surface. Then, the temporarily stored first data and the temporarily stored second data are merged into output data via the surface data bus 203 and output.

[0153] For example, as shown in Figure 3b, after reading the first data (grd_l_int_vlo<63:0>) from the first storage surface 201, the first data is temporarily stored in the first data buffer 2020; simultaneously, the second data (grd_r_vlo) read from the second storage surface 202... <0> , <8> , <16> , <24> , <32> , <40> , <48> , <56> After that, the second data is temporarily stored in the second data buffer 2030. The temporarily stored first data and the temporarily stored second data are then merged into output data via the surface data bus 203 and output.

[0154] In some embodiments, as shown in FIG3b, the memory further includes a serial-to-parallel conversion circuit 205;

[0155] The serial-to-parallel conversion circuit 205 is connected at one end to the data input interface 204 and at the other end to the surface data bus 203, and is used to convert the input data into serial-to-parallel data.

[0156] In some specific examples, serial-to-parallel conversion is a technique that converts between serial and parallel transmission methods. These are typically configured as "serial input, parallel output (SIPO)" or "parallel input, serial output (PISO)".

[0157] Serial data output transmits data and characters bit by bit in a time sequence, while parallel data transmission transmits a fixed number of bits (usually 8 or 16 bits) of data and characters to the receiving end simultaneously. Serial-to-parallel conversion is a technology that converts between these two transmission methods.

[0158] In some specific examples, the serial-to-parallel conversion circuit may include two. The input data interface may include nine data interfaces, of which eight data interfaces (DQ0-DQ7) are used to transmit actual data, and one data interface (DBI) is used to transmit DBI data. In some specific examples, each data may correspond to an input data pin and a reference voltage (VrefQ) pin, which can be used to determine the level of the input data on its corresponding input data pin. In this embodiment of the invention, a serial-to-parallel conversion circuit 205 is provided between the data input interface 204 and the surface data bus 203, which can save the number of transmission buses.

[0159] In some embodiments, the first data is transmitted in an unencoded format.

[0160] In some specific examples, during the data transmission process, the first data can be transmitted in an encoded format or in an unencoded format.

[0161] Understandably, transmitting the first data in an unencoded format can reduce the chance of data errors when reading the first data.

[0162] This invention also provides a memory system, comprising:

[0163] One or more memories as described in any of the above embodiments of the present invention; and

[0164] A storage controller coupled to the memory.

[0165] In some specific examples, the memory controller can be used to control the memory to perform erase, read or write operations, and to decode, parse or perform operations on instructions issued or received in the memory.

[0166] This invention also provides a method for operating a memory, used in any of the above embodiments of the invention. Figure 4 is a schematic flowchart illustrating the implementation of the method for operating the memory according to an embodiment of the invention. As shown in Figure 4, the method includes the following steps:

[0167] Step 401: Receive the first instruction;

[0168] Step 402: In response to the first instruction, simultaneously activate the first storage plane and the second storage plane; and

[0169] Step 403: Write the first data in the input data into the first storage surface, and write the second data in the input data into the second storage surface.

[0170] It should be understood that the operations shown in Figure 4 are not exclusive, and other operations can be performed before, after, or between any of the operations shown. The operation method of the memory in this embodiment will be described in detail below with reference to Figures 3b and 4.

[0171] In some specific examples, in step 401, a first instruction is received.

[0172] It is understandable that the first instruction can be an instruction issued by other devices in the memory to instruct the memory to perform operations such as writing.

[0173] Here, the first instruction is used to instruct the input data to be written.

[0174] It should be noted that 63h shown in Figure 3b can be understood as the first instruction in the embodiment of the present invention, namely the write instruction.

[0175] In step 402, according to the received first instruction, the memory system simultaneously activates the first storage surface and the second storage surface, so that the storage space in the first storage surface and the second storage surface that can be used to store data is in a ready-to-write state; and puts the first storage bus transmission control module 206 and the second storage bus transmission control module 207 in a standby state that can be used to transmit data.

[0176] Next, in step 403, the transmitted data is allocated and stored.

[0177] In some specific examples, the storage address of the transmitted data is determined based on the received instruction content. It should be noted that in the first instruction, the transmitted data in the surface data bus 203 is input data.

[0178] It is understandable that here, the first data in the input data can be written into the first storage surface 201 through the first storage bus transmission control module 206, and at the same time, the first data in the input data can be written into the second storage surface 202 through the second storage bus transmission control module 207.

[0179] Specifically, according to the first instruction, the surface data bus 203 transmits the first data in the input data to the third write data interface 2011; the third write data interface 2011 transmits the first data in the input data to the first target address in the first storage surface 201 via the third selector 2013.

[0180] At the same time, the surface data bus 203 transmits the second data in the input data to the second write data interface 2022; the second write data interface 2022 transmits the second data in the input data to the second target address in the second storage surface after the first selector 2023 performs the corresponding 8-bit to 64-bit conversion.

[0181] For example, referring to FIG3b, the input data in the surface data bus 203 includes 72 data bits (pdio_vlo<71:0>), which includes eight 8-bit first data bits (vlo<63:0>) and eight 1-bit second data bits (pdio_vlo<7:0>).

[0182] According to the first instruction, the first eight 8-bit data (grd_l_vlo<63:0>) in the input data are transmitted to the third write data interface 2011; the first eight 8-bit data (grd_l_vlo<63:0>) in the input data are written to the first target address in the first storage surface 201 through the third write data interface 2011 and the third selector 2013.

[0183] Simultaneously, the eight 1-bit second data bits (gwd_dbi_l_vlo<7:0>) from the input data are transmitted to the second write data interface 2022; the eight 1-bit second data bits (vlo<7:0>) are then processed by the first selector 2023 through the second write data interface 2022 to be converted from 8 bits to 64 bits, and then written to the second target address in the second storage plane. In some embodiments, the eight 1-bit second data bits (gwd_dbi_l_vlo<7:0>) from the input data occupy the corresponding eight data positions (grd_r_vlo) in the second storage plane. <0> , <8> , <16> , <24> , <32> , <40> , <48> , <56> ).

[0184] It is understandable that the second data in the input data is stored in the second storage plane, without the need to add extra storage space for storing the second data. Therefore, it saves the need to add storage space in the memory.

[0185] In some embodiments, the method further includes:

[0186] Step 501: Received the second instruction;

[0187] Step 502: In response to the second instruction, simultaneously activate the first storage plane and the second storage plane;

[0188] Step 503: Read the first data from the first storage surface and temporarily store the read first data; and read the second data from the second storage surface and temporarily store the read second data; and

[0189] Step 504: Merge the temporarily stored first data and the temporarily stored second data and output them.

[0190] It should be understood that the operations shown in Figure 5 are not exclusive, and other operations can be performed before, after, or between any of the operations shown. The operation method of the memory in this embodiment will be described in detail below with reference to Figures 3b and 5.

[0191] In step 501, a second instruction is received.

[0192] Here, the second instruction is used to instruct the execution of a read operation on the data stored in the first storage surface 201 and the second storage surface 202.

[0193] It should be noted that 64h shown in Figure 3b can be understood as the second instruction in the embodiment of the present invention, namely the read instruction.

[0194] In step 502, according to the received second instruction, the memory system simultaneously activates the first storage surface and the second storage surface, so that the storage space in the first storage surface and the second storage surface that can be used to store data is in a ready-to-read state; and the first storage bus transmission control module 206 and the second storage bus transmission control module 207 are in a standby state that can be used to transmit data.

[0195] Next, in step 503, the target address for the transmitted data is determined, and the transmitted data is temporarily stored.

[0196] Here, the memory determines the first target address of the first data in the first storage plane based on the content of the read instruction.

[0197] Next, the first data is read from the first target address of the first storage surface, and the read first data is temporarily stored in the first data cache 2020.

[0198] At the same time, the memory determines the second target address of the second data in the second storage surface based on the content of the read instruction. Next, the second data is read from the second target address of the second storage surface and temporarily stored in the second data buffer 2030.

[0199] Next, the first data temporarily stored in the first data buffer 2020 is output to the surface data bus 203 through the third data read interface 2014; at the same time, the second data temporarily stored in the second data buffer 2030 is transmitted to the surface data bus 203 through the second data read interface 2025.

[0200] Next, in step 504, the surface data bus 203 merges the received data and outputs it.

[0201] Here, the transmitted data in the surface data bus 203, i.e. the output data, includes the first data and the second data.

[0202] For example, referring to Figures 3b and 5, a second instruction is received, and according to the second instruction, the first target address of the eight 8-bit first data (grd_l_int_vlo<63:0>) stored in the first storage surface 201 is determined, the eight 8-bit first data (grd_l_int_vlo<63:0>) at that address is read, and temporarily stored in the first data buffer 2020; simultaneously, the eight 1-bit second data (gwd_r_vlo) stored in the eight data bits of the 64 bits in the second storage surface 202 is determined. <0> , <8> , <16> , <24> , <32> , <40> , <48> , <56> The second target address is used to read the eight 1-bit second data (gwd_r_vlo) at that address. <0> , <8> , <16> , <24> , <32> , <40> , <48> , <56> ), and temporarily stored in the second data cache 2030.

[0203] Next, the eight 8-bit first data (grd_l_vlo<63:0>) temporarily stored in the first data buffer 2020 are output to the surface data bus 203 through the third read data interface 2014; at the same time, the eight 1-bit second data (gwd_dbi_r_vlo<7:0>) temporarily stored in the second data buffer 2030 are transmitted to the surface data bus 203.

[0204] Next, the 84 8-bit first data (grd_l_vlo<63:0>) and 8 1-bit second data (gwd_dbi_r_vlo<7:0>) are combined into output data via the surface data bus 203 and then transmitted to the data buffer (DQ FIFO), and then output from the data buffer to external devices.

[0205] In this embodiment of the invention, by storing the second data, which indicates whether the first data has been reversed before transmission, in a spare storage surface of the storage surface to which the first data belongs, the manufacturing cost of the memory can be reduced without adding an extra data bus and storage space for transmitting the second data within the existing storage architecture of the memory.

[0206] It should be noted that the solutions in this application embodiment can be applied to data training scenarios. Here, data training can be understood as the testing of data storage operations performed during the development phase of the memory to verify the timing of data storage on the storage surface. Of course, the solutions in this application embodiment can also be applied to actual data transmission.

[0207] It should be noted that terms such as "first" and "second" are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0208] Furthermore, the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.

[0209] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A memory, characterized in that, include: First storage surface; The first storage bus transmission control module is coupled to the first storage surface; Second storage surface; The second storage bus transmission control module is coupled to the second storage surface; A surface data bus is coupled to the first surface storage bus transmission control module and the second surface storage bus transmission control module; The control logic is coupled to the first-side storage bus transmission control module and the second-side storage bus transmission control module, and is configured to: receive a first instruction; In response to the first instruction, the first M bits of the M+1 bits of data received in the surface data bus are transmitted to the first storage surface via the first surface storage bus transmission control module, and the second 1 bit of the M+1 bits of data received in the surface data bus is transmitted to the second storage surface via the second surface storage bus transmission control module; wherein, the first data is the actual data to be transmitted; and the second data is used to characterize whether the first data was reversed before transmission.

2. The memory according to claim 1, characterized in that, The second-side storage bus transmission control module includes: a first write data interface, a second write data interface, and a first selector; wherein, the input terminal of the first selector is coupled to the first write data interface and the second write data interface, and the output terminal of the first selector is coupled to the second storage surface.

3. The memory according to claim 1, characterized in that, M is an integer multiple of 8.

4. The memory according to claim 1 or 3, characterized in that, The control logic is further configured to: in response to a second instruction, read the first data from the first storage surface via the first storage bus transmission control module, and read the second data from the second storage surface via the second storage bus transmission control module.

5. The memory according to claim 2, characterized in that, The second-side storage bus transmission control module further includes: a first read data interface, a second read data interface, and a second selector; wherein, the input end of the second selector is coupled to the second storage surface, and the output end is coupled to the first read data interface and the second read data interface.

6. The memory according to claim 5, characterized in that, The control logic is configured to: in response to the first instruction, write N second data to the second storage surface through the first selector and the second write data interface; In response to the second instruction, N second data items are read from the second storage surface through the second selector and the second data read interface.

7. The memory according to claim 5, characterized in that, The second-side storage bus transmission control module further includes: a first interface data bus, a second interface data bus, and a third interface data bus; wherein, the first write data interface is coupled to the input terminal of the first selector through the first interface data bus; the second write data interface is coupled to the input terminal of the first selector through the second interface data bus; and the second storage surface is coupled to the output terminal of the first selector through the third interface data bus.

8. The memory according to claim 5, characterized in that, The first storage bus transmission control module includes: a third write data interface, a fourth write data interface, a third selector, a third read data interface, a fourth read data interface, and a fourth selector; wherein, the input end of the third selector is coupled to the third write data interface and the fourth write data interface, and the output end is coupled to the first storage surface; the input end of the fourth selector is connected to the first storage surface, and the output end is coupled to the third read data interface and the fourth read data interface.

9. The memory according to claim 8, characterized in that, The control logic is configured to: in response to the first instruction, write N first data into the first storage surface through the third selector and the third write data interface; the M*N data on the M*N data bits output by the third selector output terminal correspond to the N first data; where N is a positive integer; In response to the second instruction, N first data items are read from the storage in the first storage plane through the fourth selector and the third data reading interface; the M*N data items on the M*N data bits output by the fourth selector output terminal correspond to the N first data items.

10. The memory according to claim 8, characterized in that, The power supply voltage for the first write data interface, the second write data interface, the first read data interface, the second read data interface, the third write data interface, the fourth write data interface, the third read data interface, and the fourth read data interface is approximately 1.2V.

11. The memory according to claim 8, characterized in that, The first-side storage bus transmission control module further includes a first data buffer, and the second-side storage bus transmission control module memory further includes a second data buffer; wherein, the first data buffer is located between the output terminal of the fourth selector and the third and fourth read data interfaces, and is used to temporarily store the first data read from the first storage surface; the second data buffer is located between the output terminal of the second selector and the first and second read data interfaces, and is used to temporarily store the data read from the second storage surface; the surface data bus is used to merge the temporarily stored first data and the temporarily stored second data into output data and then output it.

12. The memory according to claim 1, characterized in that, The memory also includes a serial-to-parallel conversion circuit; one end of the serial-to-parallel conversion circuit is connected to the data input interface, and the other end is connected to the surface data bus, used to convert the input data into serial-to-parallel data.

13. The memory according to claim 1, characterized in that, The first data was transmitted in an unencoded format.

14. The memory according to claim 1, characterized in that, The first storage surface and the second storage surface have basically the same structural features.

15. The memory according to claim 1, characterized in that, The memory includes a three-dimensional NAND memory.

16. A memory system, characterized in that, include: One or more memories as described in any one of claims 1 to 15; And a memory controller coupled to the memory.

17. A method for operating a memory, characterized in that, The memory includes a first storage surface and a second storage surface. The operation method of the memory includes: receiving a first instruction and M+1 bits of input data; in response to the first instruction, writing M bits of first data from the M+1 bits of input data into the first storage surface, and writing 1 bit of second data from the M+1 bits of input data into the second storage surface; wherein, the first data is the actual data to be transmitted; and the second data indicates whether the first data was reversed before being written into the first storage surface.

18. The operating method according to claim 17, characterized in that, The method further includes: receiving a second instruction; in response to the second instruction, reading the first data from the first storage surface, temporarily storing the read first data, and reading the second data from the second storage surface, temporarily storing the read second data; and merging the temporarily stored first data and the temporarily stored second data and outputting them.

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