Semiconductor device and method for manufacturing the same

Abstract

The present disclosure embodiment discloses a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device may include: providing a silicon carbide body; forming a silicon carbide groove extending from a first surface of the silicon carbide body into the silicon carbide body; forming a body region, wherein the body region extends from a bottom of the silicon carbide groove into the silicon carbide body; forming a gate oxide layer, wherein the gate oxide layer is located inside the silicon carbide trench and on the first surface; and forming polycrystalline silicon in a first silicon carbide trench in the silicon carbide trench, wherein the polycrystalline silicon is located on a side of the gate oxide layer away from the silicon carbide body.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the field of modern power electronics, the optimization of terminal structure is crucial to improving the performance of semiconductor devices. Especially in high-voltage applications such as electric vehicles, renewable energy conversion systems and high-voltage transmission networks, the design of the terminal structure is directly related to the breakdown voltage, leakage current control and long-term reliability of the device. Traditional silicon (Si)-based semiconductor devices face performance bottlenecks in these high-voltage environments, while silicon carbide (SiC), as a wide-bandgap semiconductor material, offers the potential to break through these limitations due to its excellent electrical properties and thermal stability. The terminal structure design of SiC devices can significantly improve the breakdown voltage of the device and reduce leakage current by precisely controlling the electric field distribution and optimizing the dielectric layer inside the device, thereby showing excellent performance in high-voltage, high-temperature and high-power density applications.

[0003] With the continuous advancement of power electronics technology, higher requirements are placed on the reliability and stability of semiconductor devices. The reliability of the terminal structure of existing SiC devices is low, which may cause technical problems such as device leakage. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure are intended to provide a semiconductor device and a method for manufacturing the same, which can solve the technical problem that the terminal structure of SiC devices in the prior art has low reliability and is prone to device leakage.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] Providing a silicon carbide body;

[0008] forming a silicon carbide groove extending from a first surface of the silicon carbide body into the silicon carbide body;

[0009] forming a body region, wherein the body region extends from the bottom of the silicon carbide trench into the silicon carbide body;

[0010] forming a gate oxide layer, wherein the gate oxide layer is located inside the silicon carbide trench and on the first surface;

[0011] Polysilicon is formed in a first silicon carbide trench among the silicon carbide trenches, and the polysilicon is located on a side of the gate oxide layer away from the silicon carbide body.

[0012] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0013] Silicon carbide body;

[0014] a silicon carbide groove extending from a first surface of the silicon carbide body into the silicon carbide body;

[0015] a body region extending from the bottom of the silicon carbide trench into the silicon carbide body;

[0016] A gate oxide layer, disposed inside the silicon carbide trench and on the first surface;

[0017] Polycrystalline silicon is disposed in a first silicon carbide trench among the silicon carbide trenches, and the polycrystalline silicon is located on a side of the gate oxide layer away from the silicon carbide body.

[0018] The disclosed embodiments provide a semiconductor device and a method for manufacturing the same; by forming a gate oxide layer and polysilicon inside a silicon carbide trench, the electric field distribution in the terminal region can be more effectively controlled, the electric field concentration can be reduced, and the risk of device breakdown under high voltage can be reduced. The combination of the gate oxide layer and polysilicon provides good electrical isolation, which helps prevent electrical interference between the terminal structure and other device parts. Filling polysilicon can also reduce leakage current and improve the energy efficiency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.

[0020] Figure 2 A schematic diagram of a silicon carbide body provided in accordance with an embodiment of the present disclosure.

[0021] Figure 3 A vertical cross-sectional schematic diagram of a semiconductor device after a silicon carbide trench is formed, provided in an embodiment of the present disclosure.

[0022] Figure 4 A vertical cross-sectional schematic diagram of a semiconductor device after a body region is formed according to an embodiment of the present disclosure.

[0023] Figure 5 A vertical cross-sectional schematic diagram of a semiconductor device after a gate oxide layer is formed according to an embodiment of the present disclosure.

[0024] Figure 6 A vertical cross-sectional schematic diagram of a semiconductor device after polysilicon is formed provided in an embodiment of the present disclosure.

[0025] Figure 7 A vertical cross-sectional schematic diagram of a semiconductor device after an interlayer dielectric layer is formed according to an embodiment of the present disclosure.

[0026] Figure 8 A vertical cross-sectional schematic diagram of a semiconductor device after a first dielectric layer trench is formed according to an embodiment of the present disclosure.

[0027] Fig. 9 A vertical cross-sectional schematic diagram of a semiconductor device after a second silicon carbide trench is formed, provided in an embodiment of the present disclosure.

[0028] Fig.10 A vertical cross-sectional schematic diagram of a semiconductor device behind a fourth dielectric layer trench provided in an embodiment of the present disclosure.

[0029] Fig.11 A vertical cross-sectional schematic diagram of a semiconductor device after a lightly doped region is formed according to an embodiment of the present disclosure.

[0030] Fig.12 A vertical cross-sectional schematic diagram of a semiconductor device after a third silicon carbide trench is formed according to an embodiment of the present disclosure.

[0031] Fig.13 A vertical cross-sectional schematic diagram of a semiconductor device after a silicon carbide trench is formed, provided in an embodiment of the present disclosure.

[0032] Fig.14 A vertical cross-sectional schematic diagram of another semiconductor device after forming a lightly doped region provided by an embodiment of the present disclosure.

[0033] Fig.15 A vertical cross-sectional schematic diagram of another semiconductor device after forming a body region provided by an embodiment of the present disclosure.

[0034] Fig.16 A vertical cross-sectional schematic diagram of another semiconductor device after a cut-off region is formed according to an embodiment of the present disclosure.

[0035] Fig.17 A vertical cross-sectional schematic diagram of another semiconductor device after forming a gate oxide layer provided by an embodiment of the present disclosure.

[0036] Fig.18 A vertical cross-sectional schematic diagram of another semiconductor device after polysilicon is formed provided in an embodiment of the present disclosure.

[0037] Fig.19 A vertical cross-sectional schematic diagram of another semiconductor device after forming an interlayer dielectric layer provided in an embodiment of the present disclosure.

[0038] Fig. 20 A vertical cross-sectional schematic diagram of a semiconductor device after a dielectric layer trench is formed according to an embodiment of the present disclosure.

[0039] Fig.21A vertical cross-sectional schematic diagram of a semiconductor device after a passivation layer is formed according to an embodiment of the present disclosure.

[0040] Fig. 22 A vertical cross-sectional schematic diagram of a semiconductor device with a silicon carbide substrate added provided in an embodiment of the present disclosure.

[0041] Fig.23 A vertical cross-sectional schematic diagram of a semiconductor device after a polyimide structure is formed according to an embodiment of the present disclosure.

[0042] Description of reference numerals:

[0043] 1. Silicon carbide body; 11. First silicon carbide trench; 12. Body region; 13. Second silicon carbide trench; 14. Cut-off region; 15. Lightly doped region; 16. Third silicon carbide trench; 2. Gate oxide layer; 3. Polysilicon; 4. Interlayer dielectric layer; 41. First dielectric layer trench; 42. Second dielectric layer trench; 43 Third dielectric layer trench; 44. Fourth dielectric layer trench; 51. First metal contact layer; 52. Second metal contact layer; 53. Third metal contact layer; 6. Passivation layer; 7. Silicon carbide substrate; 8. Polyimide structure.

[0044] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0045] In the detailed description that follows, reference is made to the accompanying drawings, which form a part hereof, and in which specific embodiments in which silicon carbide devices may be implemented are illustrated by way of illustration. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used on other embodiments or used in combination with other embodiments to produce yet another embodiment. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. If not otherwise stated, corresponding elements in different drawings are represented by the same reference symbols.

[0046] The terms "having", "comprising", "including", and "comprising" and the like are open ended, and the terms indicate the presence of stated structures, elements, or features but do not exclude the presence of additional elements or features. The quantifiers and pronouns "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0047] Ohmic contact is a non-rectifying electrical junction with linear or almost linear current-voltage characteristics. Schottky junction, i.e., Schottky contact is a metal-semiconductor junction with rectifying characteristics, in which the work function of the metal and the dopant concentration in the semiconductor material are selected so that a depletion zone is formed in the semiconductor material along the metal-semiconductor junction in the absence of an externally applied electric field. In the case of Schottky contact, the term "metal-semiconductor junction" can also refer to a junction between a metalloid semiconductor and a semiconductor, wherein the junction has the same characteristics as a metal-semiconductor junction. For example, a Schottky contact can be formed between polysilicon and silicon carbide. If two components (e.g., two zones) form an ohmic contact or a Schottky contact respectively, this may mean that there is an ohmic contact or a Schottky contact between the two components. In both cases, it can be directly adjacent to each other for the two zones. However, it can also be that a further component is located between the two components.

[0048] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations. Two adjacent doping regions of the same conductivity type and having different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doping regions. At a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa.

[0049] The main components of a layer or structure from a chemical composition or alloy are the elements whose atoms form the chemical composition or alloy. For example, nickel and silicon are the main components of a nickel silicide layer, and copper and aluminum are the main components of a copper-aluminum alloy.

[0050] Power devices play a vital role in power supply, power processing and other systems. Compared with Si materials, wide bandgap semiconductors have a wider bandgap width, so they usually have advantages such as high frequency, high power density, high breakdown voltage, and strong radiation resistance. Among them, SiC materials have the characteristics of high critical breakdown electric field, high thermal conductivity and high saturation electron drift velocity. Compared with the current mainstream switching device Si IGBT, the unipolar conductive characteristics and high saturation electron drift velocity of SiC MOSFET make it have lower switching losses and higher operating frequencies.

[0051] However, the terminal structure in the SiC MOSFET in the related art will have a large leakage current, resulting in low reliability of the semiconductor device.

[0052] Based on this, the present disclosure first provides a method for manufacturing a semiconductor device, referring to Figure 1 , the method for manufacturing a semiconductor device may include steps S110 to S150.

[0053] In step S110 , a silicon carbide body is provided.

[0054] In some of the disclosed examples, reference Figure 2 First, a silicon carbide body 1 may be provided. By way of example, the silicon carbide body 1 may be of the polytype 15R-SiC, 2H-SiC, 4H-SiC or 6H-SiC. In addition to the main components silicon and carbon, the silicon carbide body 1 may also include dopant atoms, such as nitrogen N, phosphorus P, beryllium Be, boron B, aluminum Al and / or gallium Ga. Further, the silicon carbide body 1 may include unwanted impurities, such as hydrogen and / or oxygen. The silicon carbide body 1 may include a first surface 1A at the front side and an opposite second surface 1B at the back side.

[0055] It should be noted that the conductivity type of the silicon carbide body 1 may be a first conductivity type, and the first conductivity type may be an n-type or a p-type. Here and below, the conductivity type of the silicon carbide body 1 is named as the first conductivity type.

[0056] It should be noted that the first conductivity type and the second conductivity type in the present disclosure are used to distinguish between n-type and p-type. When the first conductivity type is n-type, the second conductivity type is p-type. When the first conductivity type is p-type, the second conductivity type is n-type.

[0057] The following description will be made by taking the case where the conductivity type of the silicon carbide body 1 is the first conductivity type and the first conductivity type is n-type as an example.

[0058] In step S120 , a silicon carbide trench extending from the first surface of the silicon carbide body into the silicon carbide body is formed.

[0059] In an exemplary embodiment of the present disclosure, referring to Figure 3 A groove extending from the first surface 1A into the silicon carbide body 1 may be formed on the silicon carbide body 1. Since the groove is generated on the silicon carbide body 1, the groove is named as a silicon carbide groove to distinguish it from other groove structures. The silicon carbide groove may be a first silicon carbide groove 11, Figure 3 The structure of the semiconductor device is shown when the silicon carbide trench includes only the first silicon carbide trench 11 .

[0060] Specifically, when forming the silicon carbide groove, a mask etching process can be used to etch the silicon carbide groove on the silicon carbide body 1, and the formed silicon carbide groove has sidewalls and a bottom. The specific location of the silicon carbide groove area can be customized based on user needs and will not be repeated in this example implementation.

[0061] In step S130 , a body region is formed, where the body region extends from the bottom of the silicon carbide trench into the silicon carbide body.

[0062] In some examples, the silicon carbide trench may be a first silicon carbide trench 11. After forming the silicon carbide trench, refer to Figure 4 , a body region 12 may be formed at the bottom of the silicon carbide trench by ion implantation, and the conductivity type of the silicon carbide body 1 is different from that of the silicon carbide body 1 , that is, the conductivity type of the body region 12 is the second conductivity type.

[0063] In some examples, the body region 12 is formed by injecting elemental aluminum into the bottom of the trench. The doping concentration of the body region 12 can be between 10^17 atoms / cm^3 and 10^20 atoms / cm^3, and can also be customized based on demand, which is not described in detail in this example.

[0064] In step S140 , a gate oxide layer is formed, where the gate oxide layer is located inside the silicon carbide trench and on the first surface.

[0065] In some example embodiments of the present disclosure, reference is made to Figure 5 After forming the above-mentioned body region 12, a gate oxide layer 2 is formed. The gate oxide layer 2 can be arranged inside the above-mentioned silicon carbide trench and the above-mentioned first surface 1A. Specifically, the above-mentioned gate oxide layer 2 can be formed on the sidewall and inside of the above-mentioned silicon carbide trench and cover the above-mentioned first surface 1A.

[0066] Optionally, the gate oxide layer 2 may be grown by high temperature oxidation or low temperature atomic layer deposition (ALD) process, and the material may be an oxide such as silicon dioxide. In some examples, the thickness of the gate oxide layer 2 at the bottom of the silicon carbide trench is greater than the thickness of the sidewall of the silicon carbide trench, and the thickness of the gate oxide layer 2 at the bottom of the silicon carbide trench may also be greater than the thickness of the gate oxide layer 2 on the first surface 1A. The specific thickness may be customized based on demand and will not be elaborated in this example implementation.

[0067] In step S150 , polysilicon is formed in a first silicon carbide trench among the silicon carbide trenches, and the polysilicon is located on a side of the gate oxide layer away from the silicon carbide body.

[0068] After the gate oxide layer 2 is formed, refer to Figure 5 and Figure 6 , polysilicon 3 can be formed in the first silicon carbide groove 11 in the silicon carbide groove. The number of the silicon carbide grooves can be multiple, all of the silicon carbide grooves can be used as the first silicon carbide grooves 11, or some of the silicon carbide grooves can be selected as the first silicon carbide grooves 11. For example, the silicon carbide grooves not arranged at the edge of the silicon carbide body 1 can be used as the first silicon carbide grooves 11.

[0069] The method for manufacturing a semiconductor device in the embodiment of the present disclosure can more effectively control the electric field distribution in the terminal region and reduce the electric field concentration, thereby reducing the breakdown risk of the device under high voltage by forming a gate oxide layer 2 and polysilicon 3 inside the silicon carbide trench. The combination of the gate oxide layer 2 and the polysilicon 3 provides good electrical isolation, which helps prevent electrical interference between the terminal structure and other device parts. And filling the polysilicon 3 can reduce leakage current and improve the energy efficiency of the device.

[0070] In some examples, reference Figure 7 After the polysilicon 3 is formed, an interlayer dielectric layer 4 can be formed. The interlayer dielectric layer 4 is arranged on a side of the gate oxide layer 2 away from the silicon carbide body 1 and can cover the polysilicon 3 .

[0071] The semiconductor device may include an active region and a terminal structure, referring to Figure 8 , a first dielectric layer trench 41 penetrating the interlayer dielectric layer 4 and the gate oxide layer 2 and having its bottom in contact with the body region 12 can be formed in the transition region (the region selected by the dotted line frame) between the active region (not shown) and the terminal structure. A first metal contact layer 51 is formed in the first dielectric layer trench 41, and the first metal contact layer 51 is in contact with the body region 12, the gate oxide layer 2 and the interlayer dielectric layer 4. Optionally, the first metal contact layer 51 can fill the first dielectric layer trench 41, extend out of the first dielectric layer trench 41, and contact the surface of the interlayer dielectric layer 4 away from the gate oxide layer 2.

[0072] It should be noted that the active area is not shown in the figure, and the transition area is Figure 8 and Fig. 9 The dotted box selects the area, the right side of the transition area is the terminal structure, and the left side of the transition area is the active area. In the specific implementation process, the transition area can be divided into the terminal structure part. The purpose of defining the transition area is to more clearly define the positional relationship between the structures.

[0073] In some examples, reference Fig. 9The interlayer dielectric layer 4 may include a gate isolation layer and an insulating layer, wherein the gate isolation layer is disposed between the insulating layer and the gate oxide layer 2. A second silicon carbide trench 13 extending from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1 may also be formed in the transition region, wherein the gate oxide layer 2 covers the bottom and sidewalls of the second silicon carbide trench 13, that is, the interlayer dielectric layer 4 is also formed in the second silicon carbide trench 13.

[0074] Optionally, the first dielectric layer trench 41 may also be formed in the interlayer dielectric layer 4 within the second silicon carbide trench 13 .

[0075] In some examples, a second dielectric layer groove 42 penetrating the insulating layer and contacting the gate isolation layer at the bottom can be formed in the interlayer dielectric layer 4 within the above-mentioned second silicon carbide groove 13, and a third dielectric layer groove 43 penetrating the insulating layer and contacting the gate isolation layer at the bottom can be formed on the interlayer dielectric layer 4 on the first surface 1A of the above-mentioned transition region.

[0076] After forming the second dielectric layer trench 42 and the third dielectric layer trench 43, a second metal contact layer 52 may be formed, the second metal contact layer 52 fills the second dielectric layer trench 42 and the third dielectric layer trench 43, and the second metal contact layer 52 covers the insulating layer between the second dielectric layer trench 42 and the third dielectric layer trench 43. A stepped metal contact layer is formed, which can better control the electric field.

[0077] The materials of the gate isolation layer and the insulating layer can both be silicon dioxide. Optionally, the gate isolation layer can be arranged in the active area (not shown) and the terminal structure area, and the insulating layer is only arranged in the terminal area. The specific materials of the gate isolation layer and the insulating layer can also be customized according to user needs, which will not be described in detail in this example implementation. The interlayer dielectric layer 4 can be formed by chemical vapor deposition, physical vapor deposition, thermal oxidation, etc., which will not be described in detail in this example implementation.

[0078] In some examples, reference Fig.10 A cut-off region 14 is formed on a side of the first silicon carbide trench 11 farthest from the active region and away from the active region (not shown). The cut-off region 14 has the same conductivity type as the silicon carbide body 1, that is, both are the first conductivity type, and the doping concentration of the cut-off region 14 is greater than the doping concentration of the silicon carbide body 1.

[0079] Optionally, after forming the interlayer dielectric layer 4, a fourth dielectric layer trench 44 may be formed, the fourth dielectric layer trench 44 penetrates the interlayer dielectric layer 4, and the bottom of the fourth dielectric layer trench 44 contacts the cut-off region 14. After forming the fourth dielectric layer trench 44, a third metal contact layer 53 may be formed, wherein the third metal contact layer 53 may completely fill the fourth dielectric layer trench 44, so that the third metal contact layer 53 contacts the cut-off region 14, and the cut-off region 14 is set as a heavily doped region, which can form a good ohmic contact with the third metal contact layer 53.

[0080] In some examples, reference Fig.11 A lightly doped region 15 extending into the silicon carbide body 1 is formed from the bottom of the silicon carbide trench and the first surface 1A between the silicon carbide trenches, wherein the conductivity type of the lightly doped region 15 is the second conductivity type.

[0081] In some examples, reference Fig.12 There are multiple first silicon carbide trenches 11, and a third silicon carbide trench 16 extending from the first surface 1A of the silicon carbide body 1 to the silicon carbide body 1 can be formed between the multiple first silicon carbide trenches 11; the gate oxide layer 2 covers the bottom and sidewalls of the third silicon carbide trench 16; and a body region 12 penetrating the lightly doped region 15 and extending into the silicon carbide body 1 is formed in a partial area of ​​the bottom of the third silicon carbide trench 16.

[0082] The above is described below in conjunction with a specific embodiment. Fig.12 The formation process of the semiconductor device shown in FIG. is described in detail. In the specific implementation process, Fig.12 The specific formation logic in the structure can be referred to Figures 13 to 20 .

[0083] Specifically, refer to Fig.13 , the first silicon carbide groove 11, the second silicon carbide groove 13 and the third silicon carbide groove 16 can be formed in the silicon carbide body 1 by a single process, wherein the number of the first silicon carbide groove 11 can be multiple, and after the silicon carbide groove is formed, refer to Fig.14 A lightly doped region 15 may be formed at the bottom of the plurality of silicon carbide trenches and on the first surface 1A between the plurality of silicon carbide trenches. The formation of the lightly doped region 15 may enhance the voltage dividing capability of the terminal structure.

[0084] After forming the lightly doped region 15, Fig.15, a body region 12 extending from the bottom of the silicon carbide trench to the inside of the silicon carbide body 1 can be formed, wherein the body region 12 formed in the first silicon carbide trench 11 and the second silicon carbide trench 13 completely covers the bottom of the first silicon carbide trench 11 and the bottom of the second silicon carbide trench 13, and the body region 12 formed at the bottom of the third silicon carbide trench 16 covers part of the bottom of the third silicon carbide trench 16, which can enable the semiconductor device to have better voltage division capability.

[0085] In some examples, reference Fig.16 After the body region 12 is formed, a cut-off region 14 extending from the first surface 1A into the silicon carbide body 1 is formed on the side of the first silicon carbide trench 11 farthest from the active area away from the active area, wherein the conductivity type of the cut-off region 14 is the first conductivity type, and the doping concentration of the cut-off region 14 is greater than the doping concentration of the above-mentioned silicon carbide body 1.

[0086] Reference Fig.17 After forming the above-mentioned cut-off region 14, a gate oxide layer 2 may be formed at the bottom of the silicon carbide trench and the first surface 1A. The specific material of the gate oxide layer 2 has been described in detail above, and therefore, will not be repeated here.

[0087] Reference Fig.18 After forming the cut-off region 14, polysilicon 3 may be formed in the first silicon carbide trench 11. The polysilicon 3 has a high dielectric constant and can reduce the leakage current of the semiconductor device.

[0088] In some examples, reference Fig.19 After the formation of the gate oxide layer 2 is completed, an interlayer dielectric layer 4 can be formed on the side of the gate oxide layer 2 away from the silicon carbide body 1. The interlayer dielectric layer 4 can include a gate isolation layer and an insulating layer. The specific materials and formation methods of the gate isolation layer and the insulating layer have been described above, so they will not be repeated here.

[0089] Reference Fig. 20 After the formation of the interlayer dielectric layer 4 is completed, a dielectric layer groove can be formed in the above-mentioned interlayer dielectric layer 4, wherein the dielectric layer groove can include a first dielectric layer groove 41, a second dielectric layer groove 42, a third dielectric layer groove 43 and a fourth dielectric layer groove 44, wherein the first dielectric layer groove 41 is arranged in the above-mentioned transition area, penetrates the interlayer dielectric layer 4 and the bottom of the first dielectric layer groove 41 is in contact with the above-mentioned body region 12, and the first dielectric layer groove 41 is opened in the interlayer dielectric layer 4 located in the second silicon carbide groove 13.

[0090] The second dielectric layer trench 42 is opened in the interlayer dielectric layer 4 located in the second silicon carbide trench 13 , and is located on the side of the first dielectric layer trench 41 away from the active area. The second dielectric layer trench 42 penetrates the insulating layer, and the bottom contacts the gate isolation layer.

[0091] The third dielectric layer groove 43 is opened in the interlayer dielectric layer 4 of the first plane located in the transition area, and is located on the side of the second dielectric layer groove 42 away from the first dielectric layer groove 41. The third dielectric layer groove 43 penetrates the above insulating layer, and the bottom is in contact with the above gate isolation layer.

[0092] The fourth dielectric layer trench 44 penetrates the interlayer dielectric layer 4 , and the bottom thereof contacts the cut-off region 14 .

[0093] Reference Fig.12 After the first dielectric layer groove 41, the second dielectric layer groove 42 and the third dielectric layer groove 43 are formed, a first metal contact layer 51 can be formed in the first dielectric layer groove 41 by deposition, and a second metal contact layer 52 can be formed in the second dielectric layer groove 42 and the third dielectric layer groove 43. The second metal contact layer 52 fills the second dielectric layer groove 42 and the third dielectric layer groove 43 and covers the insulating layer between the second dielectric layer groove 42 and the third dielectric layer groove 43.

[0094] Continue to refer to Fig.12 A third metal contact layer 53 may be formed in the fourth dielectric layer trench 44 , wherein the third metal contact layer 53 completely fills the fourth dielectric layer trench 44 and extends out of the fourth dielectric layer trench 44 , and the extended portion contacts the insulating layer of the interlayer dielectric layer 4 .

[0095] In some examples, reference Fig.21 After forming the first metal contact layer 51, the second metal contact layer 52 and the third metal contact layer 53, that is, after forming the Fig.12 After the semiconductor device is shown, the above method may further include forming a passivation layer 6. The material of the passivation layer 6 may be SiO2 or Si3N4, and may also be customized according to the device function and user needs, which will not be described in detail in this exemplary embodiment. The passivation layer 6 completely covers the first metal contact layer 51, the second metal contact layer 52, the third metal contact layer 53 and the interlayer dielectric layer 4, and flattens the side of the semiconductor device away from the second surface 1B.

[0096] In some examples, reference Figure 1 and Fig. 22Before providing the silicon carbide body 1, a silicon carbide substrate 7 may be provided first. The conductivity type of the silicon carbide substrate 7 is the same as that of the silicon carbide body 1, but the doping concentration of the silicon carbide substrate 7 is higher than that of the silicon carbide body 1. The silicon carbide body 1 is formed on one side of the silicon carbide substrate 7, that is, the second surface 1B of the silicon carbide body 1 is in contact with the silicon carbide substrate 7.

[0097] It should be noted that when the silicon carbide body 1 is formed, the silicon carbide body 1 is formed on the silicon carbide substrate 7 by depositing a silicon carbide epitaxial layer.

[0098] In some examples, reference Fig.23 A polyimide structure 8 may also be formed on the side of the passivation layer 6 away from the interlayer dielectric layer 4. The polyimide structure 8 has good moisture and mechanical stress resistance, and can improve the service life of the semiconductor device.

[0099] The manufacturing method of the semiconductor device provided in this embodiment, on the one hand, by forming the gate oxide layer 2 and the polysilicon 3 inside the silicon carbide groove, the electric field distribution in the terminal area can be more effectively controlled, the electric field concentration can be reduced, and the breakdown risk of the device under high voltage can be reduced. On the second hand, the combination of the gate oxide layer 2 and the polysilicon 3 provides good electrical isolation, which helps to prevent electrical interference between the terminal structure and other device parts. On the third hand, filling the polysilicon 3 can reduce leakage current and improve the energy efficiency of the device. On the fourth hand, by forming the interlayer dielectric layer 4, the dielectric layer groove and the metal contact layer, the structure of the device is optimized, and the stability and performance of the device are enhanced. On the fifth hand, the polyimide structure 8 is formed on the side of the passivation layer 6 away from the interlayer dielectric layer 4, which can enhance the moisture resistance and mechanical stress resistance of the semiconductor device and extend the service life. On the sixth hand, the manufacturing method allows the formation of various types of grooves on the silicon carbide body 1, and the formation of layers with different functions in the grooves, providing a high degree of manufacturing flexibility to meet the needs of different applications. Seventhly, during the manufacturing process, different materials can be selected to form the gate oxide layer 2, the interlayer dielectric layer 4, the passivation layer 6, etc., to meet different performance requirements and user needs.

[0100] Furthermore, the present disclosure also provides a semiconductor device, referring to Figures 1 to 6 , the semiconductor device may include a silicon carbide body 1, a silicon carbide trench, a body region 12, a gate oxide layer 2, and polysilicon 3. The silicon carbide trench extends from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1; the body region 12 extends from the bottom of the silicon carbide trench into the silicon carbide body 1. The gate oxide layer 2 is arranged inside the silicon carbide trench and on the first surface 1A; the polysilicon 3 is arranged in the first silicon carbide trench 11 in the silicon carbide trench, and the polysilicon 3 is located on the side of the gate oxide layer 2 away from the silicon carbide body 1.

[0101] In some examples, reference Figure 8 The semiconductor device includes an active area and a terminal structure, and the semiconductor device also includes an interlayer dielectric layer 4, a first dielectric layer groove 41 and a first metal contact layer 51, wherein the interlayer dielectric layer 4 is located on the side of the gate oxide layer 2 away from the silicon carbide body 1 and covers the polysilicon 3; the first dielectric layer groove 41 is located in the transition area between the active area and the terminal structure, penetrates the interlayer dielectric layer 4 and the gate oxide layer 2, and the bottom is in contact with the body area 12; the first metal contact layer 51 is arranged in the first dielectric layer groove 41 and extends out of the first dielectric layer groove 41, and is in contact with the body area 12, the gate oxide layer 2 and the interlayer dielectric layer 4.

[0102] In some examples, reference Fig. 9 The silicon carbide groove further includes a second silicon carbide groove 13, a second dielectric layer groove 42, a third dielectric layer groove 43 and a second metal contact layer 52, wherein the second silicon carbide groove 13 is located in the transition region and extends from the first surface 1A of the silicon carbide body 1 to the silicon carbide body 1, wherein the gate oxide layer 2 covers the bottom and sidewalls of the second silicon carbide groove 13; the interlayer dielectric layer 4 includes a gate isolation layer and an insulating layer, the insulating layer is located on the side of the gate isolation layer away from the gate oxide layer 2, the second dielectric layer groove 42 is located in the interlayer dielectric layer 4 in the second silicon carbide groove 13, penetrates the insulating layer, and the bottom is in contact with the gate isolation layer; the third dielectric layer groove 43 is located in the interlayer dielectric layer 4 on the first surface 1A of the transition region, penetrates the insulating layer, and the bottom is in contact with the gate isolation layer; the second metal contact layer 52 fills the second dielectric layer groove 42 and the third dielectric layer groove 43, and covers the insulating layer between the second dielectric layer groove 42 and the third dielectric layer groove 43.

[0103] In some examples, reference Fig.10 The semiconductor device further includes a cut-off region 14, a fourth dielectric layer trench 44, and a third metal contact layer 53. The cut-off region 14 is arranged on a side of the first silicon carbide trench 11 farthest from the active region and away from the active region, and the cut-off region 14 extends from the first surface 1A to the silicon carbide body 1; the fourth dielectric layer trench 44 penetrates the interlayer dielectric layer 4, and the bottom of the fourth dielectric layer trench 44 contacts the cut-off region 14; and the third metal contact layer 53 completely fills the fourth dielectric layer trench 44.

[0104] In some examples, reference Fig.12 The semiconductor device also includes a lightly doped region 15, which extends from the bottom of the silicon carbide trench and the first surface 1A between the silicon carbide trenches to the silicon carbide body 1, wherein the conductivity type of the lightly doped region 15 is the same as that of the body region 12, and different from the conductivity type of the silicon carbide body 1.

[0105] In some examples, reference Fig.12, there are multiple first silicon carbide trenches 11, and the silicon carbide trenches further include a third silicon carbide trench 16. The third silicon carbide trench 16 is disposed between the multiple first silicon carbide trenches 11, extending from the first surface 1A of the silicon carbide body 1 into the silicon carbide body 1, and the gate oxide layer 2 covers the bottom and sidewalls of the third silicon carbide trench 16; the body region 12 extends from a portion of the bottom of the third silicon carbide trench 16 into the silicon carbide body 1, and runs through the lightly doped region 15.

[0106] It should be noted that the specific details of each part of the above-mentioned semiconductor device have been described in detail when describing the manufacturing method of the semiconductor device, and therefore, they will not be repeated here.

[0107] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the inventions claimed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not claimed in the present disclosure.

[0109] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a silicon carbide body (1); forming a silicon carbide groove extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1); forming a body region (12), wherein the body region (12) extends from the bottom of the silicon carbide trench into the silicon carbide body (1); forming a gate oxide layer (2), wherein the gate oxide layer (2) is located inside the silicon carbide trench and on the first surface (1A); Forming polysilicon (3) in a first silicon carbide trench (11) in the silicon carbide trench, the polysilicon (3) being located on a side of the gate oxide layer (2) away from the silicon carbide body (1); Wherein, the semiconductor device comprises an active region and a terminal structure, and the method further comprises: forming an interlayer dielectric layer (4), wherein the interlayer dielectric layer (4) is located on a side of the gate oxide layer (2) away from the silicon carbide body (1) and covers the polysilicon (3); Forming a first dielectric layer trench (41) in a transition region between the active region and the terminal structure, the trench penetrating the interlayer dielectric layer (4) and the gate oxide layer (2) and having a bottom in contact with the body region (12); A first metal contact layer (51) is formed, wherein the first metal contact layer (51) is arranged in the first dielectric layer trench (41) and is in contact with the body region (12), the gate oxide layer (2) and the interlayer dielectric layer (4).

2. The method according to claim 1, characterized in that The interlayer dielectric layer (4) comprises a gate isolation layer and an insulating layer, wherein the insulating layer is located on a side of the gate isolation layer away from the gate oxide layer (2); The forming of a silicon carbide groove extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1) comprises: forming a second silicon carbide trench (13) in the transition region extending from the first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1), wherein the gate oxide layer (2) covers the bottom and sidewalls of the second silicon carbide trench (13); The method further comprises: Forming a second dielectric layer trench (42) in the interlayer dielectric layer (4) within the second silicon carbide trench (13), the trench penetrating the insulating layer and having a bottom in contact with the gate isolation layer; Forming a third dielectric layer trench (43) in the interlayer dielectric layer (4) on the first surface (1A) of the transition region, the trench penetrating the insulating layer and having a bottom in contact with the gate isolation layer; A second metal contact layer (52) is formed in the second dielectric layer groove (42) and the third dielectric layer groove (43), wherein the second metal contact layer (52) fills the second dielectric layer groove (42) and the third dielectric layer groove (43), and covers the insulating layer between the second dielectric layer groove (42) and the third dielectric layer groove (43).

3. The method according to claim 1, characterized in that Before forming the gate oxide layer (2), the method further comprises: A cut-off region (14) extending from the first surface (1A) into the silicon carbide body (1) is formed on a side of the first silicon carbide trench (11) farthest from the active region away from the active region; After forming the interlayer dielectric layer (4), the method further comprises: forming a fourth dielectric layer trench (44), wherein the fourth dielectric layer trench (44) penetrates the interlayer dielectric layer (4), and the bottom of the fourth dielectric layer trench (44) contacts the cut-off region (14); A third metal contact layer (53) is formed to completely fill the fourth dielectric layer trench (44).

4. The method according to claim 1, characterized in that: Before forming the body region (12), the method further comprises: forming a lightly doped region (15), wherein the lightly doped region (15) extends from the bottom of the silicon carbide trench and the first surface (1A) between the silicon carbide trenches into the silicon carbide body (1); The conductivity type of the lightly doped region (15) is the same as that of the main region (12), and different from that of the silicon carbide main body (1).

5. The method according to claim 4, characterized in that The number of the first silicon carbide grooves (11) is plural, and the step of forming the silicon carbide grooves extending from the first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1) comprises: A third silicon carbide trench (16) is formed between the plurality of first silicon carbide trenches (11), extending from the first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1); the gate oxide layer (2) covers the bottom and sidewalls of the third silicon carbide trench (16); Forming the body region (12) includes: A body region (12) is formed in a partial area of ​​the bottom of the third silicon carbide trench (16), penetrating the lightly doped region (15) and extending into the silicon carbide body (1).

6. A semiconductor device, characterized in that: The semiconductor device comprises: Silicon carbide body (1); A silicon carbide groove extending from a first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1); A body region (12) extending from the bottom of the silicon carbide trench into the silicon carbide body (1); A gate oxide layer (2), arranged inside the silicon carbide trench and on the first surface (1A); Polycrystalline silicon (3) is arranged in a first silicon carbide groove (11) in the silicon carbide grooves, and the polycrystalline silicon (3) is located on a side of the gate oxide layer (2) away from the silicon carbide body (1); Wherein, the semiconductor device comprises an active region and a terminal structure, and the semiconductor device further comprises: An interlayer dielectric layer (4), located on a side of the gate oxide layer (2) away from the silicon carbide body (1), and covering the polysilicon (3); A first dielectric layer trench (41), located in a transition region between the active region and the terminal structure, penetrating the interlayer dielectric layer (4) and the gate oxide layer (2), and having a bottom in contact with the body region (12); A first metal contact layer (51) is disposed in the first dielectric layer trench (41) and extends out of the first dielectric layer trench (41), and is in contact with the body region (12), the gate oxide layer (2) and the interlayer dielectric layer (4).

7. The semiconductor device according to claim 6, characterized in that The silicon carbide trench further comprises: a second silicon carbide trench (13), located in the transition region, extending from the first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1), wherein the gate oxide layer (2) covers the bottom and sidewalls of the second silicon carbide trench (13); The interlayer dielectric layer (4) comprises a gate isolation layer and an insulating layer, wherein the insulating layer is located on a side of the gate isolation layer away from the gate oxide layer (2), and the semiconductor device further comprises: A second dielectric layer trench (42) is located in the interlayer dielectric layer (4) in the second silicon carbide trench (13), penetrates the insulating layer, and has a bottom in contact with the gate isolation layer; A third dielectric layer trench (43) is located in the interlayer dielectric layer (4) on the first surface (1A) of the transition region, penetrates the insulating layer, and has a bottom in contact with the gate isolation layer; The second metal contact layer (52) fills the second dielectric layer trench (42) and the third dielectric layer trench (43), and covers the insulating layer between the second dielectric layer trench (42) and the third dielectric layer trench (43).

8. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises: A cut-off region (14) is arranged on a side of the first silicon carbide trench (11) farthest from the active region and away from the active region, the cut-off region (14) extending from the first surface (1A) into the silicon carbide body (1); A fourth dielectric layer groove (44) penetrates the interlayer dielectric layer (4), and the bottom of the fourth dielectric layer groove (44) contacts the cut-off region (14); The third metal contact layer (53) completely fills the fourth dielectric layer groove (44).

9. The semiconductor device according to claim 6, characterized in that The semiconductor device further comprises: A lightly doped region (15) extends from the bottom of the silicon carbide trench and the first surface (1A) between the silicon carbide trenches into the silicon carbide body (1), wherein the conductivity type of the lightly doped region (15) is the same as that of the body region (12) and different from that of the silicon carbide body (1).

10. The semiconductor device according to claim 9, characterized in that The number of the first silicon carbide grooves (11) is multiple, and the silicon carbide grooves further include: A third silicon carbide trench (16) is arranged between the plurality of first silicon carbide trenches (11), extending from the first surface (1A) of the silicon carbide body (1) into the silicon carbide body (1), the gate oxide layer (2) covering the bottom and sidewalls of the third silicon carbide trench (16); The body region (12) extends from a partial area at the bottom of the third silicon carbide trench (16) into the silicon carbide body (1) and penetrates the lightly doped region (15).

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