Test structure and method of manufacturing and testing thereof

Abstract

The present disclosure provides a test structure and a manufacturing method and a test method thereof, which are used to solve the technical problem that the sensitivity of the test structure is low, it is difficult to dynamically monitor, and it is not easy to compare the early development. The test structure is arranged on a shutter, and comprises a substrate, a first dielectric layer arranged on the substrate, a first conductive part spaced apart from the substrate in the first dielectric layer, a second dielectric layer covering the first conductive part and the first dielectric layer, and a wire structure penetrating through the second dielectric layer and the first dielectric layer, the wire structure is arranged spaced apart from the first conductive part and in contact with the substrate, the first conductive part, the first dielectric layer and the substrate form a test capacitor, and the capacitance voltage characteristic curve of the test capacitor is used to monitor the content information of metal ions in the first dielectric layer. The test structure is on the shutter, which is beneficial to early development comparison process, and the capacitance voltage characteristic curve is used for monitoring, which has high sensitivity and can be dynamically monitored.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test structure and a manufacturing method and a testing method thereof. Background Art

[0002] With the development of semiconductor manufacturing process technology, the dielectric layers in the advanced processes of semiconductor devices such as logic chips and memory chips, such as intermetallic dielectric layers (IMD), are often provided with interconnects to connect the conductive layers on both sides of the dielectric layer. The dielectric layer, especially the low dielectric constant material layer, is usually a loose porous structure that easily absorbs water vapor. Under high temperature and high voltage conditions, the metal ions in the interconnects are easily migrated into the dielectric layer under the catalysis of water vapor, and may even diffuse into other film layers, causing the semiconductor device to fail and causing serious reliability problems. Therefore, a test structure is needed to detect the diffusion of metal ions in the dielectric layer. However, the sensitivity of the existing test structure is low, making it difficult to dynamically monitor the migration of metal ions, and is not conducive to early research and development comparison processes. Summary of the Invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a test structure and a manufacturing method and a testing method thereof, which can dynamically monitor the migration of metal ions and are conducive to early research and development of comparative processes.

[0004] According to some embodiments, a first aspect of the present disclosure provides a test structure, the test structure being disposed on a baffle and comprising: a substrate, a first dielectric layer disposed on the substrate, a first conductive member located within the first dielectric layer and spaced apart from the substrate, a second dielectric layer covering the first conductive member and the first dielectric layer, and a conductive wire structure penetrating the second dielectric layer and the first dielectric layer, the conductive wire structure being spaced apart from the first conductive member and in contact with the substrate;

[0005] In which, the first conductive member, the first dielectric layer and the substrate form a test capacitor, one of the wire structure and the first conductive member is used to connect to the positive pole of the power supply, and the other of the wire structure and the first conductive member is used to connect to the negative pole of the power supply, and the capacitance-voltage characteristic curve of the test capacitor is used to monitor the metal ion content information of the first conductive member in the first dielectric layer.

[0006] In some possible embodiments, the first conductive member includes a first conductive layer and a first diffusion barrier layer disposed between the first conductive layer and the first dielectric layer, and the metal ions include metal ions from the first conductive layer and the first diffusion barrier layer.

[0007] In some possible embodiments, the first conductive layer includes:

[0008] a conductive connecting portion extending along a first direction;

[0009] A plurality of conductive branches are connected to the same side of the conductive connection portion, the plurality of conductive branches are spaced apart and extend along a second direction, and the second direction intersects the first direction.

[0010] In some possible embodiments, the conductive line structure includes a contact plug and a second conductive member, the contact plug is located in the first dielectric layer and contacts the substrate, and the second conductive member penetrates the second dielectric layer and contacts the contact plug.

[0011] In some possible embodiments, the second conductive member includes:

[0012] a first section disposed close to a side of the conductive branch away from the conductive connection portion, the first section extending along the first direction;

[0013] Two second segments are respectively connected to both ends of the first segment and are arranged on a side close to the conductive connection portion. The two second segments extend along the second direction and are respectively located on both sides of the conductive branch portion.

[0014] In some possible embodiments, an orthographic projection of the second conductive member on the substrate covers an orthographic projection of the contact plug on the substrate.

[0015] In some possible embodiments, the conductive line structure includes a third conductive member, wherein the third conductive member passes through the first dielectric layer and the second dielectric layer and contacts the substrate;

[0016] The third conductive member includes a first conductive column, and a second diffusion barrier layer disposed between the first conductive column and the first dielectric layer, and between the first conductive column and the second dielectric layer.

[0017] In some possible embodiments, a distance between a bottom surface of the first conductive element and a top surface of the substrate is 5-5000 nm.

[0018] The test structure provided by the embodiments of the present disclosure has at least the following advantages:

[0019] The test structure provided by the embodiment of the present disclosure is arranged on the baffle, which is conducive to the early research and development of the comparison process, and can also be used for production line monitoring. The test structure includes a substrate, a first dielectric layer arranged on the substrate, a first conductive member located in the first dielectric layer and spaced apart from the substrate, a second dielectric layer covering the first conductive member and the first dielectric layer, and a wire structure running through the second dielectric layer and the first dielectric layer, the wire structure being spaced apart from the first conductive member and in contact with the substrate. The first conductive member, the first dielectric layer and the substrate form a test capacitor, and the capacitance-voltage characteristic curve of the test capacitor is used to monitor the content information of the metal ions of the first conductive member in the first dielectric layer, thereby obtaining the diffusion of the metal ions of the first conductive member in the first dielectric layer, and the test capacitor has high sensitivity. The substrate in the test capacitor (such as a silicon substrate) is highly sensitive to metal ion contamination, so the dynamic process of metal ion migration and failure can also be monitored based on the capacitance-voltage characteristic curve of the test capacitor, so that the failure mechanism of the test capacitor can be analyzed.

[0020] According to some embodiments, a second aspect of the present disclosure provides a method for manufacturing a test structure, comprising:

[0021] forming a first dielectric layer on the substrate of the control plate;

[0022] forming a first conductive member in the first dielectric layer, wherein the first conductive member is spaced apart from the substrate;

[0023] forming a second dielectric layer covering the first conductive member and the first dielectric layer;

[0024] A conductive line structure is formed that penetrates the second dielectric layer and the first dielectric layer. The conductive line structure is spaced apart from the first conductive member and contacts the substrate.

[0025] The method for manufacturing the test structure provided by the embodiment of the present disclosure has at least the following advantages:

[0026] In the manufacturing method of the test structure provided by the embodiment of the present disclosure, a first dielectric layer, a first conductive member, a second dielectric layer, and a wire structure are formed on the substrate of the baffle plate, so that the test structure is arranged on the baffle plate, which is convenient for early research and development comparison and can also be used for production line monitoring. A first dielectric layer is formed on the substrate, a first conductive member spaced apart from the substrate is formed in the first dielectric layer, and a wire structure is formed in the second dielectric layer covering the first conductive member and the first dielectric layer. The wire structure is spaced apart from the first conductive member and is in contact with the substrate, thereby leading out the substrate so that the first conductive member and the substrate form two plates of the test capacitor. The capacitance-voltage characteristic curve of the test capacitor is used to monitor the content information of the metal ions of the first conductive member in the first dielectric layer, thereby obtaining the diffusion of the metal ions of the first conductive member in the first dielectric layer, and the test capacitor has high sensitivity. The substrate in the test capacitor (such as a silicon substrate) is highly sensitive to metal ion contamination, so the dynamic process of metal ion migration and failure can also be monitored based on the capacitance-voltage characteristic curve of the test capacitor, so that the failure mechanism of the test capacitor can be analyzed.

[0027] According to some embodiments, a second aspect of the present disclosure provides a testing method for the test structure described above, the testing method comprising:

[0028] Turning on a power supply, connecting the positive electrode of the power supply to one of the wire structure and the first conductive member, and connecting the negative electrode of the power supply to the other of the wire structure and the first conductive member;

[0029] Obtaining a capacitance-voltage characteristic curve of the test capacitor;

[0030] According to the capacitance-voltage characteristic curve, the metal ion content information of the first conductive member in the first dielectric layer is monitored.

[0031] The testing method provided by the embodiment of the present disclosure has at least the following advantages:

[0032] In the test method provided by the embodiment of the present disclosure, one of the first conductive member and the wire structure is connected to one pole of the power supply, and the other of the first conductive member and the wire structure is connected to the other pole of the power supply, so that the substrate and the first conductive member serve as two plates of the test capacitor respectively. The capacitance-voltage characteristic curve of the test structure is used to monitor the content information of the metal ions of the first conductive member in the first dielectric layer, so as to obtain the diffusion of the metal ions of the first conductive member in the first dielectric layer, and the sensitivity of the test capacitor is high. The substrate (such as a silicon substrate) in the test capacitor is highly sensitive to metal ion contamination, so the dynamic process of metal ion migration and failure can also be monitored based on the capacitance-voltage characteristic curve of the test capacitor, so that the failure mechanism of the test capacitor can be analyzed. In addition, the test method can also be applied to the test structure set on the baffle plate, which is convenient for early research and comparison process. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a test structure in related art;

[0034] Figure 2 for Figure 1 Schematic diagram of the cross section at point A;

[0035] Figure 3 A breakdown life diagram of a test structure in the related art;

[0036] Figure 4 is a schematic structural diagram of a test structure in an embodiment of the present disclosure;

[0037] Figure 5 for Figure 4 Schematic diagram of the cross section at point B;

[0038] Figure 6 This is a schematic structural diagram of a first conductive member in an embodiment of the present disclosure;

[0039] Figure 7 This is a schematic structural diagram of a second conductive member in an embodiment of the present disclosure;

[0040] Figure 8 Schematic diagram of the structure of the third conductive member in one embodiment of the present disclosure;

[0041] Figure 9 Schematic diagram of the structure after the second filling space is formed in one embodiment of the present disclosure;

[0042] Figure 10 Schematic diagram of the structure after forming the first filling groove in one embodiment of the present disclosure;

[0043] Figure 11 Schematic diagram of the structure after forming the second filling groove in one embodiment of the present disclosure;

[0044] Figure 12 Schematic diagram of the structure after forming the first conductive layer in one embodiment of the present disclosure;

[0045] Figure 13 Schematic diagram of the structure after forming the first conductive member in one embodiment of the present disclosure;

[0046] Figure 14 Schematic diagram of the structure after forming contact holes in one embodiment of the present disclosure;

[0047] Figure 15 Schematic diagram of the structure after forming a contact plug in one embodiment of the present disclosure;

[0048] Figure 16 Schematic diagram of the structure after forming the second dielectric layer in one embodiment of the present disclosure;

[0049] Figure 17 This is a schematic diagram of the structure after the filling groove is formed in one embodiment of the present disclosure;

[0050] Figure 18 Schematic diagram of the structure after forming the second conductive member in one embodiment of the present disclosure;

[0051] Figure 19 is a schematic structural diagram after forming a second contact hole in one embodiment of the present disclosure;

[0052] Figure 20 Schematic diagram of the structure after forming the third contact hole in one embodiment of the present disclosure.

[0053] Description of reference numerals:

[0054] 10-substrate; 20-first dielectric layer;

[0055] 21-first filling groove; 22-second filling groove;

[0056] 23-first contact hole; 30-first conductive member;

[0057] 31-conductive connecting portion; 32-conductive branch portion;

[0058] 33-first diffusion barrier layer; 34-first conductive layer;

[0059] 40-second dielectric layer; 41-first layer;

[0060] 42-second layer; 43-filling groove;

[0061] 50- conductor structure; 51- contact plug;

[0062] 52-second conductive member; 53-first section;

[0063] 54-second segment; 55-second conductive layer;

[0064] 56-third diffusion barrier layer; 57-second conductive column;

[0065] 58-fourth diffusion barrier layer; 60-third conductive element;

[0066] 61-first conductive column; 62-second diffusion barrier layer;

[0067] 63-second contact hole; 64-third contact hole;

[0068] 70-comb tooth conductive member; 71-tooth portion. DETAILED DESCRIPTION

[0069] The problem in the related art is that the sensitivity of the test structure is low, it is difficult to dynamically monitor the migration process of metal ions, and it is difficult to conduct research and development comparisons in the early stage. The inventors have found that the reason is: Figure 1 and Figure 2 The test structure generally includes a first dielectric layer 20 and two comb-tooth conductive members 70 disposed in the first dielectric layer 20 and spaced apart from each other. The multiple teeth 71 of the two comb-tooth conductive members 70 intersect. Figure 3 The test structure is usually directly tested for the breakdown life of the first dielectric layer 20 at high temperature and high voltage. During the test, the test structure often undergoes hard breakdown, resulting in low test sensitivity and difficulty in analyzing the failure mechanism of the breakdown point.

[0070] The two comb-tooth conductive members 70 and the first dielectric layer 20 located between them form a parallel-plate metal capacitor structure, making it difficult to electrically reflect metal ion diffusion and, consequently, to dynamically monitor metal ion migration. Furthermore, test structures are typically fabricated on wafers, which often undergo other semiconductor processes to form semiconductor devices or structures, hindering early R&D comparisons.

[0071] To this end, the embodiment of the present disclosure provides a test structure, which is beneficial for early research and development of comparative processes by manufacturing the test structure on the substrate of the baffle plate, and can also be used for monitoring the production line. A first dielectric layer is provided on the substrate in the test structure, and a first conductive member is provided in the first dielectric layer, and the first conductive member is spaced apart from the substrate. The substrate, the first dielectric layer and the first conductive member form a test capacitor, and the substrate is externally connected using a wire structure. By using the capacitance-voltage characteristic curve of the test capacitor, the diffusion of the metal ions of the first conductive member in the first dielectric layer can be obtained, and the dynamic process of metal ion migration and failure can be monitored. The test capacitor has high sensitivity, which facilitates the analysis of the failure mechanism of the test capacitor.

[0072] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0073] See Figure 4 and Figure 5 The embodiment of the present disclosure provides a test structure, which is arranged on a non-pattern wafer (NPW). The test structure undergoes fewer semiconductor process steps, which is beneficial for early research and development comparison processes and can also be used for production line monitoring.

[0074] like Figure 4 and Figure 5 As shown, the test structure includes a substrate 10, a first dielectric layer 20, a first conductive member 30, a second dielectric layer 40, and a conductive wire structure 50. The substrate 10 can be made of single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, etc. The first dielectric layer 20 is disposed on the substrate 10, the first conductive member 30 is located within the first dielectric layer 20 and spaced apart from the substrate 10, the second dielectric layer 40 covers the first conductive member 30 and the first dielectric layer 20, and the conductive wire structure 50 penetrates the second dielectric layer 40 and the first dielectric layer 20. The conductive wire structure 50 is spaced apart from the first conductive member 30 and contacts the substrate 10.

[0075] The first conductive member 30, the first dielectric layer 20 and the substrate 10 form a test capacitor. One of the conductive structure 50 and the first conductive member 30 is used to connect to the positive electrode of the power supply, and the other of the conductive structure 50 and the first conductive member 30 is used to connect to the negative electrode of the power supply. Exemplarily, the conductive structure 50 is connected to the negative electrode of the power supply, and the first conductive member 30 is connected to the positive electrode of the power supply. The conductive structure 50 is used to connect the substrate 10 to the power supply, so that the substrate 10 and the first conductive member 30 are respectively the two plates of the test capacitor, and the two plates are connected through the pad to perform a CV test to obtain a capacitance-voltage characteristic curve. For example, the substrate 10 is the negative plate of the test capacitor, and the first conductive member 30 is the positive plate of the test capacitor.

[0076] The capacitance-voltage characteristic curve of the test capacitor is used to monitor the metal ion content information of the first conductive member 30 in the first dielectric layer 20. Using the capacitance-voltage characteristic curve, that is, the CV curve, the metal ion content information in the first dielectric layer 20 can be monitored. The metal ions come from the first conductive member 30, thereby obtaining the diffusion of the metal ions in the first conductive member 30. The substrate 10 (especially the silicon substrate) is highly sensitive to metal ion contamination. When the first dielectric layer 20 contains metal ions, the sensitivity of the test capacitor is high. In addition, the capacitance-voltage characteristic curve, combined with the test voltage (10-50V) and test temperature (25-150°C), can also monitor the dynamic process of metal ion migration and failure, thereby analyzing the failure mechanism of the test capacitor.

[0077] In some examples, the first dielectric layer 20 may be made of a low-k material with a dielectric constant less than or equal to 2.8 to reduce parasitic capacitance. For example, the first dielectric layer 20 may be made of hafnium oxide, zirconium oxide, or the like.

[0078] like Figure 5 As shown, the distance between the bottom surface of the first conductive member 30 and the top surface of the substrate 10 is 5-5000 nm. Figure 5 and Figure 6 The first conductive member 30 includes a first conductive layer 34 and a first diffusion barrier layer 33 disposed between the first conductive layer 34 and the first dielectric layer 20 . The metal ions include metal ions from the first conductive layer 34 and the first diffusion barrier layer 33 .

[0079] In some examples, first conductive layer 34 faces away from the surface of substrate 10 ( Figure 5 The top surface shown in FIG3 is flush with the surface of the first dielectric layer 20 facing away from the substrate 10, the first diffusion barrier layer 33 covers the side of the first conductive layer 34, and the surface of the first conductive layer 34 facing the substrate 10 ( FIG3 is a top surface shown in FIG3 Figure 5 The first diffusion barrier layer 33 contacts the first dielectric layer 20 and is spaced apart from the substrate 10.

[0080] Among them, the material of the first conductive layer 34 can be a diffusible material, that is, a material that can diffuse into the first dielectric layer 20. For example, the material of the first conductive layer 34 includes at least one of copper, aluminum, nickel, and molybdenum, and the material of the first diffusion barrier layer 33 includes at least one of cobalt, platinum, tantalum, tantalum nitride, titanium, and titanium nitride.

[0081] The material of the first conductive layer 34 and the material of the first diffusion barrier layer 33 both contain metal. For example, the material of the first conductive layer 34 is a single metal or a metal compound, and the material of the first diffusion barrier layer 33 is a single metal or a metal compound. The metal in the first conductive layer 34 and the first diffusion barrier layer 33 may diffuse into the first dielectric layer 20 in the form of ions, causing failure of the test capacitor. Therefore, the metal ions monitored by the test capacitor include the aforementioned two metal ions, that is, the metal ions monitored by the test capacitor include metal ions from the first conductive layer 34 and the first diffusion barrier layer 33.

[0082] Continue reading Figure 6 The first conductive member 30 includes a conductive connecting portion 31 (such as Figure 6 The conductive connection portion 31 is used as a connector of the first conductive layer 34 and is connected to the power supply. The conductive connection portion 31 extends along the first direction. The first conductive layer 34 also includes a plurality of conductive branches 32 ( Figure 6 The area indicated by the dotted line is shown).

[0083] In some examples, the number of the conductive branches 32 is greater than or equal to 20. The plurality of conductive branches 32 are connected to the same side of the conductive connection portion 31. The plurality of conductive branches 32 are spaced apart and extend along the second direction, that is, the conductive connection portion 31 and the plurality of conductive branches 32 are in a comb-like shape. The second direction intersects with the first direction, for example, is perpendicular to the first direction. Figure 4 The horizontal direction (X direction) shown in FIG. Figure 4 The vertical direction (Y direction) shown.

[0084] The plurality of conductive branches 32 and the conductive connection portion 31 may be an integral structure, and each conductive branch 32 and conductive connection portion 31 may include a first conductive layer 34 and a first diffusion barrier layer 33. The plurality of conductive branches 32 and the first conductive layer 34 of the conductive connection portion 31 are connected to form an integral structure, and the first diffusion barrier layer 33 of each conductive branch 32 is located on the side of the first conductive layer 34 of the conductive branch 32 and on the end surface away from the conductive connection portion 31.

[0085] The distance between the bottom of the conductive branch 32 and the top surface of the substrate 10 is 5-5000 nm. In some examples, the depth of the conductive connection portion 31 and the depth of the multiple conductive branches 32 are the same, so that the multiple conductive branches 32 and the conductive connection portion 31 are in contact on the sides facing each other. This arrangement maximizes the contact area between each conductive branch 32 and the conductive connection portion 31 and also facilitates the fabrication of the conductive connection portion 31 and the multiple conductive branches 32.

[0086] Continue reading Figure 5The second dielectric layer 40 covers the first conductive member 30 and the first dielectric layer 20 and is insulated from the first conductive member 30. In some examples, the second dielectric layer 40 can be a single material layer. For example, the second dielectric layer 40 can be made of a low-k material, which can be the same as or different from the material of the first dielectric layer 20.

[0087] In other examples, such as Figure 5 As shown, the second dielectric layer 40 can be a multi-layer material layer, wherein the second dielectric layer 40 has a stacked structure. For example, the second dielectric layer 40 includes a first layer 41 located on the first conductive member 30 and the first dielectric layer 20, and a second layer 42 located on the first layer 41, wherein the thickness of the second layer 42 is greater than that of the first layer 41. The material of the first layer 41 can be a nitride, such as silicon nitride or silicon oxynitride, and the material of the second layer 42 can be a low dielectric constant material.

[0088] Continue reading Figure 4 and Figure 5 The conductive line structure 50 includes a contact plug 51 and a second conductive member 52. The contact plug 51 is located in the first dielectric layer 20 and contacts the substrate 10. The second conductive member 52 penetrates the second dielectric layer 40 and contacts the contact plug 51. The contact plug 51 contacts the substrate 10 and is spaced apart from the first conductive member 30. There can be multiple contact plugs 51, and the multiple contact plugs 51 are spaced apart.

[0089] like Figure 4 As shown, the orthographic projection of the second conductive member 52 on the substrate 10 covers the orthographic projection of the contact plug 51 on the substrate 10, so that the surfaces of the second conductive member 52 and the contact plug 51 facing each other are completely in contact, thereby increasing the contact area between the second conductive member 52 and the contact plug 51 and reducing the contact resistance between the second conductive member 52 and the contact plug 51.

[0090] See Figure 4 、 Figure 5 and Figure 7 The second conductive member 52 includes a second conductive layer 55 and a third diffusion barrier layer 56 disposed between the second conductive layer 55 and the second dielectric layer 40. The second conductive layer 55 is made of at least one of copper, aluminum, nickel, and molybdenum, and the third diffusion barrier layer 56 is made of at least one of cobalt, platinum, tantalum, tantalum nitride, titanium, and titanium nitride.

[0091] The contact plug 51 includes a second conductive pillar 57 and a fourth diffusion barrier layer 58 covering the side surfaces of the second conductive pillar 57 and the surface facing the substrate 10. The second conductive pillar 57 can be made of a material that does not react with the substrate 10, such as tungsten. The fourth diffusion barrier layer 58 prevents the second conductive pillar 57 from diffusing into the first dielectric layer 20. The material of the fourth diffusion barrier layer 58 can include at least one of cobalt, platinum, tantalum, tantalum nitride, titanium, and titanium nitride.

[0092] Continue reading Figure 4 、 Figure 5 and Figure 7 In some examples, the second conductive member 52 includes a first segment 53 and two second segments 54. The first segment 53 (e.g. Figure 7 The area indicated by the double-dotted line in the middle) extends along the first direction, and the two second sections 54 (as shown in FIG. Figure 7 The areas indicated by the dotted lines are respectively connected to the two ends of the first section 53, and the first section 53 or the second section 54 is used to connect to a power source.

[0093] The first section 53 is close to the side of the conductive branch 32 away from the conductive connection part 31 , that is, one side of the conductive branch 32 is connected to the conductive connection part 31 , and the other side of the conductive branch 32 is close to the first section 53 of the second conductive member 52 .

[0094] The two second segments 54 are both located on the side of the first segment 53 close to the conductive connection portion 31 and extend along the second direction. The two second segments 54 are respectively located on both sides of the conductive branch portion 32, and the two second segments 54 are respectively located on the side of the conductive branch portion 32 that is away from each other (i.e., the outer side). Figure 1 As shown, one second segment 54 is located on the left side of the conductive branch 32 , and the other second segment 54 is located on the right side of the conductive branch 32 .

[0095] It can be understood that the first segment 53 and the two second segments 54 each include a second conductive layer 55 and a third diffusion barrier layer 56. The second conductive layer 55 of the first segment 53 is integrally connected to the second conductive layers 55 of the two second segments 54, and no third diffusion barrier layer 56 is disposed between the second conductive layer 55 of the first segment 53 and the second conductive layers 55 of the two second segments 54. The third diffusion barrier layer 56 of the first segment 53 is integrally connected to the third diffusion barrier layer 56 of the second segment 54.

[0096] In an embodiment where there are multiple contact plugs 51, the first segment 53 and each second segment 54 are in contact with at least one contact plug 51, that is, multiple contact plugs 51 semi-surround the conductive branch 32, and both the first segment 53 and the second segment 54 are in contact with the contact plug 51. Figure 4As shown, the first segment 53 contacts five contact plugs 51 , and each second segment 54 contacts three contact plugs 51 , so as to improve the uniformity of the current between the first conductive member 30 and the substrate 10 .

[0097] For other examples, see Figure 8 The conductive line structure 50 includes a third conductive member 60, which penetrates the first dielectric layer 20 and the second dielectric layer 40 and contacts the substrate 10. The third conductive member 60 can be a column to facilitate the fabrication of the third conductive member 60.

[0098] The third conductive member 60 includes a first conductive pillar 61 and a second diffusion barrier layer 62 disposed between the first conductive pillar 61 and the first dielectric layer 20, and between the first conductive pillar 61 and the second dielectric layer 40. Specifically, the second diffusion barrier layer 62 covers the side surfaces of the first conductive pillar 61 and the surface facing the substrate 10. The material of the first conductive pillar 61 may include tungsten or an alloy thereof. The second diffusion barrier layer 62 prevents the first conductive pillar 61 from diffusing into the first dielectric layer 20 and the second dielectric layer 40. The material of the second diffusion barrier layer 62 may include at least one of cobalt, platinum, tantalum, tantalum nitride, titanium, and titanium nitride.

[0099] In summary, the test structure in the embodiment of the present disclosure is arranged on the baffle, which is conducive to the early development of the comparison process and can also be used for production line monitoring. The test structure includes a substrate 10, a first dielectric layer 20 arranged on the substrate 10, a first conductive member 30 located in the first dielectric layer 20 and spaced apart from the substrate 10, a second dielectric layer 40 covering the first conductive member 30 and the first dielectric layer 20, and a wire structure 50 running through the second dielectric layer 40 and the first dielectric layer 20, the wire structure 50 is spaced apart from the first conductive member 30 and in contact with the substrate 10. The first conductive member 30, the first dielectric layer 20 and the substrate 10 form a test capacitor, and the capacitance-voltage characteristic curve of the test structure is used to monitor the content information of the metal ions of the first conductive member 30 in the first dielectric layer 20, thereby obtaining the diffusion of the metal ions of the first conductive member 30 in the first dielectric layer 20, and the sensitivity of the test capacitor is high. The substrate 10 (such as a silicon substrate) in the test capacitor is highly sensitive to metal ion contamination. Therefore, the dynamic process of metal ion migration and failure can be monitored based on the capacitance-voltage characteristic curve of the test structure, thereby analyzing the failure mechanism of the test capacitor.

[0100] See Figure 9 The present disclosure also provides a method for manufacturing a test structure, which specifically includes the following steps:

[0101] Step S100: forming a first dielectric layer on the substrate of the control plate.

[0102] The test structure is formed on the substrate 10 of the barrier plate. No other semiconductor devices or structures are formed on the substrate 10 of the barrier plate, which facilitates early R&D comparison process of the test structure and can also be used for production line monitoring.

[0103] See Figure 10 The substrate 10 may be a silicon substrate, a silicon germanium substrate, or the like. The first dielectric layer 20 may be formed on the substrate by a deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The first dielectric layer 20 may be made of a low-k material.

[0104] Step S200: forming a first conductive member in the first dielectric layer, wherein the first conductive member is spaced apart from the substrate.

[0105] See Figures 11 to 13 The first conductive member 30 is spaced apart from the substrate 10, serving as the two plates of the test capacitor. The first dielectric layer 20 between the first conductive member 30 and the substrate 10 serves as the dielectric layer of the test capacitor. The distance between the bottom surface of the first conductive member 30 and the top surface of the substrate 10 is 5-5000 nm. The first conductive member 30 includes a first conductive layer 34 and a first diffusion barrier layer 33 disposed between the first conductive layer 34 and the first dielectric layer 20.

[0106] In some possible implementations, such as Figures 11 to 13 As shown, a first conductive member 30 is formed in the first dielectric layer 20, and the first conductive member 30 is spaced apart from the substrate 10, including:

[0107] A portion of the first dielectric layer 20 is removed to form a first filling groove 21, which is spaced apart from the substrate 10. Figure 10 As shown, the first filling groove 21 is located in the first dielectric layer 20 and does not expose the substrate 10 , that is, the bottom of the first filling groove 21 is located in the first dielectric layer 20 .

[0108] A first diffusion barrier layer 33 is formed on the first dielectric layer 20, and the first diffusion barrier layer 33 located in the first filling groove 21 encloses the second filling groove 22. Figure 10 and Figure 11As shown, the first diffusion barrier layer 33 covers the first dielectric layer 20 located on the sidewalls and bottom of the first filling groove 21, as well as the first dielectric layer 20 located outside the first filling groove 21. The first diffusion barrier layer 33 located within the first filling groove 21 does not completely fill the first filling groove 21, and encloses the second filling groove 22.

[0109] A first conductive layer 34 is formed on the first diffusion barrier layer 33, and the first conductive layer 34 completely fills the second filling groove 22. Figure 11 and Figure 12 As shown, the first conductive layer 34 covers the first diffusion barrier layer 33 located on the sidewalls and bottom of the second filling groove 22 and the first diffusion barrier layer 33 located outside the second filling groove 22 , and the first conductive layer 34 completely fills the second filling groove 22 .

[0110] See Figure 10 and Figure 13 , part of the first diffusion barrier layer 33 and part of the first conductive layer 34 on the first dielectric layer 20 are removed, and the remaining first diffusion barrier layer 33 and the first conductive layer 34 form a first conductive member 30, and the surface of the first conductive member 30 facing away from the substrate 10 is flush with the surface of the first dielectric layer 20 facing away from the substrate 10.

[0111] Step S300: forming a second dielectric layer covering the first conductive member and the first dielectric layer.

[0112] See Figures 14 to 16 A second dielectric layer 40 is deposited on the first conductive member 30 and the first dielectric layer 20, covering the first conductive member 30 and the first dielectric layer 20. The second dielectric layer 40 may be a single layer or a stacked layer. The second dielectric layer 40 or at least one layer of the second dielectric layer 40 may be made of a low-k material.

[0113] It can be understood that, in the example where the contact plug 51 is formed in the first dielectric layer 20, as shown in FIG. Figure 16 As shown, the second dielectric layer 40 is formed on the first dielectric layer 20 , the contact plug 51 and the first conductive member 30 , and covers the surfaces of the first dielectric layer 20 , the contact plug 51 and the first conductive member 30 facing away from the substrate 10 .

[0114] Step S400: forming a conductive line structure penetrating the second dielectric layer and the first dielectric layer, wherein the conductive line structure is spaced apart from the first conductive element and contacts the substrate.

[0115] Conductor structure 50 (see Figure 5) penetrates the first dielectric layer 20 and the second dielectric layer 40 to contact the substrate 10. The wire structure 50 is spaced apart from the first conductive member 30 to prevent interconnection between the wire structure 50 and the first conductive member 30, thereby preventing interconnection between the first conductive member 30 and the substrate 10. The first conductive member 30 and the substrate 10 respectively form two plates of the test capacitor.

[0116] In summary, in the method for manufacturing the test structure in the embodiment of the present disclosure, a first dielectric layer 20, a first conductive member 30, a second dielectric layer 40, a wire structure 50, etc. are formed on the substrate 10 of the baffle plate, so that the test structure is set on the baffle plate, which is convenient for early research and development of the comparison process and can also be used for production line monitoring. A first dielectric layer 20 is formed on the substrate 10, a first conductive member 30 spaced apart from the substrate 10 is formed in the first dielectric layer 20, and a wire structure 50 is formed in the second dielectric layer 40 covering the first conductive member 30 and the first dielectric layer 20. The wire structure 50 is spaced apart from the first conductive member 30 and contacts the substrate 10, thereby leading out the substrate 10 so that the first conductive member 30 and the substrate 10 form two plates of the test capacitor. The capacitance-voltage characteristic curve of the test capacitor is used to monitor the content information of the metal ions of the first conductive member 30 in the first dielectric layer 20, thereby obtaining the diffusion of the metal ions of the first conductive member 30 in the first dielectric layer 20, and the sensitivity of the test capacitor is high. The substrate 10 (such as a silicon substrate) in the test capacitor is highly sensitive to metal ion contamination, so the dynamic process of metal ion migration and failure can also be monitored based on the capacitance-voltage characteristic curve of the test capacitor, thereby analyzing the failure mechanism of the test capacitor.

[0117] For some examples, see Figure 14 and Figure 15 After forming a first conductive member 30 in the first dielectric layer 20 and the first conductive member 30 being spaced apart from the substrate 10, the method further includes: removing a portion of the first dielectric layer 20 to form a first contact hole 23, wherein the first contact hole 23 exposes the substrate 10 and is spaced apart from the first conductive member 30; and forming a contact plug 51 in the first contact hole 23, wherein the contact plug 51 fills the first contact hole 23 and contacts the substrate 10.

[0118] The first dielectric layer 20 is etched to form a first contact hole 23. Figure 14 As shown, the first contact hole 23 penetrates the first dielectric layer 20 and exposes the substrate 10, that is, the first contact hole 23 extends to the substrate 10. The first contact hole 23 is spaced apart from the first conductive member 30, that is, the first contact hole 23 only exposes the substrate 10 and does not expose the first conductive member 30, so as to prevent the conductive line structure 50 subsequently formed in the first contact hole 23 from being interconnected with the first conductive member 30. There can be multiple first contact holes 23, and the multiple first contact holes 23 surround or semi-surround the first conductive member 30.

[0119] A contact plug 51 is formed in the first contact hole 23 and on the first dielectric layer 20 , and the contact plug 51 completely fills the first contact hole 23 . The surface of the contact plug 51 facing away from the substrate 10 is flush with the surface of the first dielectric layer 20 facing away from the substrate 10 .

[0120] The contact plug 51 includes a second conductive pillar 57 and a fourth diffusion barrier layer 58 covering the side surfaces of the second conductive pillar 57 and the surface facing the substrate 10. The second conductive pillar 57 can be made of a material that does not react with the substrate 10, such as tungsten. The fourth diffusion barrier layer 58 prevents the second conductive pillar 57 from diffusing into the first dielectric layer 20. The material of the fourth diffusion barrier layer 58 can include at least one of cobalt, platinum, tantalum, tantalum nitride, titanium, and titanium nitride.

[0121] Accordingly, see Figures 16 to 18 , forming a wire structure 50 penetrating the second dielectric layer 40 and the first dielectric layer 20, wherein the wire structure 50 is spaced apart from the first conductive member 30 and in contact with the substrate 10, including:

[0122] A portion of the second dielectric layer 40 is removed to form a filling groove 43 , which exposes the contact plug 51 ; a second conductive member 52 is formed in the filling groove 43 , which contacts the contact plug 51 , and the second conductive member 52 and the contact plug 51 form a wire structure 50 .

[0123] Among them, such as Figure 16 and Figure 17 As shown, the second dielectric layer 40 is etched to form a filled through-groove 43. Filled through-groove 43 penetrates the second dielectric layer 40 to expose the contact plug 51. Filled through-groove 43 is spaced apart from the first conductive member 30 to prevent the first conductive member 30 from being exposed within filled through-groove 43. Filled through-groove 43 also exposes a portion of the first dielectric layer 20. That is, filled through-groove 43 exposes at least the portion of the first dielectric layer 20 adjacent to the contact plug 51, making filled through-groove 43 larger and easier to manufacture. If there are multiple contact plugs 51, all of them are exposed within filled through-groove 43.

[0124] It can be understood that the conductive line structure 50 includes a contact plug 51 formed in the first dielectric layer 20 and a second conductive member 52 formed in the second dielectric layer 40, and the contact plug 51 and the second conductive member 52 are formed separately, rather than through a single deposition process, so that the materials of the contact plug 51 and the second conductive member 52 can be selected as needed.

[0125] In some possible implementations, a second conductive member 52 is formed in the filled through-slot 43 , the second conductive member 52 contacts the contact plug 51 , and the second conductive member 52 and the contact plug 51 form a conductive line structure 50 , including:

[0126] A third diffusion barrier layer 56 is deposited on the second dielectric layer 40. The third diffusion barrier layer 56 within the filling trench 43 forms a third filling groove. The third diffusion barrier layer 56 covers the second dielectric layer 40 located on the sidewalls and bottom of the filling trench 43, as well as the second dielectric layer 40 located outside the filling trench 43. The third diffusion barrier layer 56 within the filling trench 43 does not completely fill the filling trench 43, and forms a third filling groove.

[0127] A second conductive layer 55 is deposited on the third diffusion barrier layer 56, and the second conductive layer 55 completely fills the third filling groove. The second conductive layer 55 covers the third diffusion barrier layer 56 located on the sidewalls and bottom of the third filling groove, as well as the third diffusion barrier layer 56 located outside the third filling groove, and completely fills the third filling groove. That is, the surface of the second conductive layer 55 facing away from the substrate 10 is higher than the surface of the second dielectric layer 40 facing away from the substrate 10.

[0128] A portion of the second conductive layer 55 and a portion of the third diffusion barrier layer 56 on the second dielectric layer 40 are removed, and the remaining second conductive layer 55 and the third diffusion barrier layer 56 form a second conductive member 52. The second conductive member 52 completely fills the filling groove 43, and the surface of the second conductive layer facing away from the substrate 10 is flush with the surface of the second dielectric layer 40 facing away from the substrate 10.

[0129] For other examples, see Figure 8 、 Figure 19 and Figure 20 , forming a wire structure 50 penetrating the second dielectric layer 40 and the first dielectric layer 20, wherein the wire structure 50 is spaced apart from the first conductive member 30 and in contact with the substrate 10, including:

[0130] A portion of the first dielectric layer 20 and a portion of the second dielectric layer 40 are removed to form a second contact hole 63 , which exposes the substrate 10 and is spaced apart from the first conductive member 30 ; a third conductive member 60 is formed in the second contact hole 63 , which fills the second contact hole 63 and contacts the substrate 10 .

[0131] like Figure 19 As shown, the second dielectric layer 40 and the first dielectric layer 20 are etched to form a second contact hole 63. The second contact hole 63 penetrates the second dielectric layer 40 and the first dielectric layer 20, exposing the substrate 10, but does not expose the first conductive member 30, so as to prevent the third conductive member 60 subsequently formed in the second contact hole 63 from being interconnected with the first conductive member 30.

[0132] In some possible implementations, such as Figure 19 and Figure 20As shown, a third conductive member 60 is formed in the second contact hole 63. The third conductive member 60 fills the second contact hole 63 and contacts the substrate 10, including:

[0133] A second diffusion barrier layer 62 is deposited on the sidewalls and bottom of the second contact hole 63 and the second dielectric layer 40 . The second diffusion barrier layer 62 in the second contact hole 63 encloses a third contact hole 64 .

[0134] A third conductive layer is deposited on the second diffusion barrier layer 62, and the third conductive layer completely fills the third contact hole 64. The third conductive layer covers the second diffusion barrier layer 62 located on the sidewalls and bottom of the third contact hole 64, as well as the second diffusion barrier layer 62 located outside the third contact hole 64, and completely fills the third contact hole 64. That is, the surface of the third conductive layer facing away from the substrate 10 is higher than the surface of the second dielectric layer 40 facing away from the substrate 10.

[0135] A portion of the third conductive layer and a portion of the second diffusion barrier layer 62 on the second dielectric layer 40 are removed, and the remaining third conductive layer forms a first conductive column 61. The first conductive column 61 and the remaining second diffusion barrier layer 62 form a third conductive member 60. The third conductive member 60 completely fills the second contact hole 63, and the surface of the third conductive member 60 facing away from the substrate 10 is flush with the surface of the second dielectric layer 40 facing away from the substrate 10.

[0136] The present disclosure also provides a test method for the test structure in the above embodiment (see Figure 4 and Figure 5 ), the test method includes:

[0137] Turn on the power supply, connect the positive electrode of the power supply to one of the wire structure 50 and the first conductive member 30, and connect the negative electrode of the power supply to the other of the wire structure 50 and the first conductive member 30;

[0138] Obtaining a capacitance-voltage characteristic curve of the test structure;

[0139] According to the capacitance-voltage characteristic curve, the metal ion content information of the first conductive member 30 in the first dielectric layer 20 is monitored.

[0140] The test voltage of the power supply is 10-50V, and the test temperature is 25-150°C. Compared to directly testing the breakdown life of the first dielectric layer 20 between two conductive parts at high temperature and high voltage, the testing method in the embodiment of the present disclosure uses the capacitance-voltage characteristic curve for monitoring, which has high sensitivity and can also monitor the dynamic process of metal ion migration and failure, thereby analyzing the failure mechanism of the test capacitor.

[0141] In summary, in the test method in the embodiment of the present disclosure, by connecting one of the first conductive part 30 and the wire structure 50 to one pole of the power supply, and connecting the other of the first conductive part 30 and the wire structure 50 to the other pole of the power supply, the substrate 10 and the first conductive part 30 are respectively used as two plates of the test capacitor. The capacitance-voltage characteristic curve of the test structure is used to monitor the content information of the metal ions of the first conductive part 30 in the first dielectric layer 20, so as to obtain the diffusion of the metal ions of the first conductive part 30 in the first dielectric layer 20, and the sensitivity of the test capacitor is high. The substrate 10 (such as a silicon substrate) in the test capacitor is highly sensitive to metal ion contamination, so the dynamic process of metal ion migration and failure can also be monitored based on the capacitance-voltage characteristic curve of the test capacitor, so that the failure mechanism of the test capacitor can be analyzed. In addition, the test method can also be applied to the test structure set on the baffle, which is convenient for early research and comparison process.

[0142] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A test structure, characterized in that: The test structure is provided on the baffle plate, and includes: a substrate, a first dielectric layer provided on the substrate, a first conductive member located within the first dielectric layer and spaced apart from the substrate, a second dielectric layer covering the first conductive member and the first dielectric layer, and a conductive wire structure penetrating the second dielectric layer and the first dielectric layer, the conductive wire structure being spaced apart from the first conductive member and in contact with the substrate; In which, the first conductive member, the first dielectric layer and the substrate form a test capacitor, one of the wire structure and the first conductive member is used to connect to the positive pole of the power supply, and the other of the wire structure and the first conductive member is used to connect to the negative pole of the power supply, and the capacitance-voltage characteristic curve of the test capacitor is used to monitor the metal ion content information of the first conductive member in the first dielectric layer.

2. The test structure according to claim 1, characterized in that The first conductive member includes a first conductive layer and a first diffusion barrier layer disposed between the first conductive layer and the first dielectric layer. The metal ions include metal ions from the first conductive layer and the first diffusion barrier layer.

3. The test structure according to claim 2, characterized in that The first conductive layer includes: a conductive connecting portion extending along a first direction; A plurality of conductive branches are connected to the same side of the conductive connection portion, the plurality of conductive branches are spaced apart and extend along a second direction, and the second direction intersects the first direction.

4. The test structure according to claim 3, characterized in that The conductive line structure includes a contact plug and a second conductive member. The contact plug is located in the first dielectric layer and contacts the substrate. The second conductive member penetrates the second dielectric layer and contacts the contact plug.

5. The test structure according to claim 4, characterized in that The second conductive member includes: a first section disposed close to a side of the conductive branch away from the conductive connection portion, the first section extending along the first direction; Two second segments are respectively connected to both ends of the first segment and are arranged on a side close to the conductive connection portion. The two second segments extend along the second direction and are respectively located on both sides of the conductive branch portion.

6. The test structure according to claim 4, characterized in that An orthographic projection of the second conductive member on the substrate covers an orthographic projection of the contact plug on the substrate.

7. The test structure according to claim 3, characterized in that The conductive line structure includes a third conductive member, wherein the third conductive member passes through the first dielectric layer and the second dielectric layer and contacts the substrate; The third conductive member includes a first conductive column, and a second diffusion barrier layer provided between the first conductive column and the first dielectric layer, and between the first conductive column and the second dielectric layer.

8. The test structure according to any one of claims 1 to 7, characterized in that: The distance between the bottom surface of the first conductive member and the top surface of the substrate is 5-5000 nm.

9. A method for manufacturing a test structure, characterized in that: include: forming a first dielectric layer on the substrate of the control plate; forming a first conductive member in the first dielectric layer, wherein the first conductive member is spaced apart from the substrate; forming a second dielectric layer covering the first conductive member and the first dielectric layer; A conductive line structure is formed that penetrates the second dielectric layer and the first dielectric layer. The conductive line structure is spaced apart from the first conductive member and contacts the substrate.

10. A testing method, characterized in that: For the test structure according to any one of claims 1 to 8, the test method comprises: Turning on a power supply, connecting the positive electrode of the power supply to one of the wire structure and the first conductive member, and connecting the negative electrode of the power supply to the other of the wire structure and the first conductive member; Obtaining a capacitance-voltage characteristic curve of the test capacitor; According to the capacitance-voltage characteristic curve, the metal ion content information of the first conductive member in the first dielectric layer is monitored.

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