Silicon-based three-dimensional stacked phased array receiving microsystem, processing method and phased array system

Abstract

The invention discloses a silicon-based three-dimensional stacked phased array receiving microsystem, a processing method and a phased array system. The invention comprises the following steps: an upper cover plate is stacked on an upper silicon substrate, a lower cover plate is stacked on a lower silicon substrate, and the upper silicon substrate is stacked on the lower cover plate. An amplitude-phase multifunctional chip is arranged on the top of the upper silicon substrate, a low-noise amplifier is arranged on the top of the lower silicon substrate, a first accommodating groove for accommodating the amplitude-phase multifunctional chip is arranged in the upper cover plate, a second accommodating groove for accommodating the low-noise amplifier is arranged in the lower cover plate, a rewiring layer and a through-hole group are respectively arranged on the upper cover plate, the upper silicon substrate, the lower cover plate and the lower silicon substrate, and a through-hole metal is arranged in the through-hole group, so that the upper cover plate, the upper silicon substrate, the amplitude-phase multifunctional chip, the lower cover plate, the lower silicon substrate and the low-noise amplifier are interconnected, so as to realize three-dimensional heterogeneous and high-density integrated integration of the multifunctional chip, realize miniaturization of the phased array receiving microsystem and reduce the cost.

Description

Technical Field

[0001] The present invention relates to the field of radar antenna technology, and in particular to a silicon-based three-dimensional stacked phased array receiving microsystem, a processing method and a phased array system. Background Art

[0002] Currently, phased arrays integrate dual-frequency, multi-polarization antennas with multiple RF functional modules. The RF system is relatively complex and has a high operating frequency. All materials, such as the connection / coupling materials between the chip and the substrate, must have low-loss characteristics. The traditional two-dimensional mounting process has long microwave lines and excessive insertion loss, which leads to system noise deterioration and gain loss.

[0003] The chips used in the phased array receiving system are all analog chips, which cannot be reduced exponentially with "Moore's Law". Therefore, the phased array receiving system-in-a-package (SIP) must have multi-functional integration such as multi-channel amplification and amplitude and phase control, and must also have low noise characteristics. However, the area of ​​the phased array receiving SIP is relatively large. For the increasingly smaller phased array front end, the space left for the RF system is getting smaller and smaller, and there is a problem of limited layout of phased array receiving components. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art phased array receiving components, such as large size, low integration, limited layout and high cost, and to provide a silicon-based three-dimensional stacked phased array receiving microsystem, a processing method and a phased array system.

[0005] The technical solution of the present invention provides a silicon-based three-dimensional stacked phased array receiving microsystem, comprising an upper silicon substrate and a lower silicon substrate, wherein the top cover of the upper silicon substrate is provided with an upper cover plate, and the upper cover plate is sealed with the upper silicon substrate, the top cover of the lower silicon substrate is provided with a lower cover plate, and the lower cover plate is sealed with the lower silicon substrate, and the upper silicon substrate is superimposed on the lower cover plate,

[0006] A first rewiring layer is provided on the top of the upper silicon substrate, a second rewiring layer is provided on the bottom of the upper silicon substrate, a first through-hole group penetrating the upper silicon substrate is provided in the upper silicon substrate, a first through-hole metal is provided in the first through-hole group, the first rewiring layer is electrically connected to the second rewiring layer through the first through-hole metal, and an amplitude-phase multifunctional chip electrically connected to the first rewiring layer is provided on the top of the first rewiring layer;

[0007] The upper cover plate is provided with a first receiving groove for accommodating the amplitude-phase multifunctional chip, the top of the upper cover plate is provided with a third rewiring layer, the bottom of the upper cover plate is provided with a fourth rewiring layer electrically connected to the first rewiring layer, the upper cover plate is provided with a second through-hole group penetrating the upper cover plate, the second through-hole group is provided with a second through-hole metal, and the third rewiring layer is electrically connected to the fourth rewiring layer through the second through-hole metal;

[0008] A fifth rewiring layer is provided on the top of the lower silicon substrate, a sixth rewiring layer is provided on the bottom of the lower silicon substrate, a third through-hole group penetrating the lower silicon substrate is provided in the lower silicon substrate, a third through-hole metal is provided in the third through-hole group, the fifth rewiring layer is electrically connected to the sixth rewiring layer through the third through-hole metal, and at least one low-noise amplifier electrically connected to the fifth rewiring layer is provided on the top of the fifth rewiring layer;

[0009] At least one second accommodating groove for accommodating the low-noise amplifier is provided in the lower cover plate, a seventh redistribution layer electrically connected to the second redistribution layer is provided on the top of the lower cover plate, an eighth redistribution layer electrically connected to the fifth redistribution layer is provided on the bottom of the lower cover plate, a fourth through hole group penetrating the lower cover plate is provided in the lower cover plate, a fourth through hole metal is provided in the fourth through hole group, and the seventh redistribution layer is electrically connected to the eighth redistribution layer through the fourth through hole metal.

[0010] In one of the optional technical solutions, a window is provided on the third redistribution layer.

[0011] In one of the optional technical solutions, a first solder ball array ball is disposed between the second rewiring layer and the seventh rewiring layer, and a second solder ball array ball is disposed at the bottom of the sixth rewiring layer.

[0012] In one of the optional technical solutions, at least one amplifier input port and an amplifier output port electrically connected to the antenna feed point are provided on the lower silicon substrate, the input end of the low-noise amplifier is electrically connected to the amplifier input port through a first bonding gold wire, and the output end of the low-noise amplifier is electrically connected to the amplifier output port through a second bonding gold wire.

[0013] In one of the optional technical solutions, an amplitude-phase input port corresponding to the amplifier output port is provided on the upper silicon substrate, and the amplitude-phase multifunctional chip is electrically connected to the amplitude-phase input port via a third bonding gold wire.

[0014] In one of the optional technical solutions, a first matching branch is provided between the amplifier output port and the second bonding gold wire, and a second matching branch is provided between the amplitude and phase input port and the third bonding gold wire.

[0015] In one of the optional technical solutions, there are multiple low-noise amplifiers, there are multiple second accommodating grooves, a shielding column is provided between two adjacent second accommodating grooves, and each of the shielding columns is provided with the fourth through hole group.

[0016] The technical solution of the present invention also provides a method for processing the aforementioned silicon-based three-dimensional stacked phased array receiving microsystem, comprising:

[0017] Disposing a first rewiring layer and a second rewiring layer on the top and bottom of the upper silicon substrate, respectively;

[0018] A first through hole group penetrating the upper silicon substrate is provided in the upper silicon substrate, and a first through hole metal is provided in the first through hole group, and the first rewiring layer is electrically connected to the second rewiring layer through the first through hole metal;

[0019] Disposing an amplitude-phase multifunctional chip electrically connected to the first rewiring layer on top of the first rewiring layer;

[0020] A first receiving groove for receiving the amplitude-phase multifunctional chip is provided in the upper cover plate;

[0021] A third redistribution layer is disposed on the top of the upper cover plate, and a fourth redistribution layer electrically connected to the first redistribution layer is disposed on the bottom of the upper cover plate;

[0022] A second through hole group penetrating the upper cover plate is provided in the upper cover plate, and a second through hole metal is provided in the second through hole group, and the third rewiring layer is electrically connected to the fourth rewiring layer through the second through hole metal;

[0023] Covering the upper cover plate on the top of the upper silicon substrate to form an upper assembly;

[0024] Disposing a fifth rewiring layer and a sixth rewiring layer on the top and bottom of the lower silicon substrate respectively;

[0025] A third through hole group penetrating the lower silicon substrate is provided in the lower silicon substrate, and a third through hole metal is provided in the third through hole group, and the fifth rewiring layer is electrically connected to the sixth rewiring layer through the third through hole metal;

[0026] Disposing at least one low noise amplifier electrically connected to the fifth rewiring layer on top of the fifth rewiring layer;

[0027] At least one second receiving groove for receiving the low noise amplifier is provided in the lower cover plate;

[0028] A seventh redistribution layer is disposed on the top of the lower cover plate, and an eighth redistribution layer electrically connected to the fifth redistribution layer is disposed on the bottom of the lower cover plate;

[0029] A fourth through hole group penetrating the lower cover plate is provided in the lower cover plate, and a fourth through hole metal is provided in the fourth through hole group, and the seventh rewiring layer is electrically connected to the eighth rewiring layer through the fourth through hole metal;

[0030] Covering the lower cover plate on the top of the lower silicon substrate to form a lower assembly;

[0031] The upper layer component is stacked on the lower layer component, and the second redistribution layer is electrically connected to the seventh redistribution layer to form the silicon-based three-dimensional stacked phased array receiving microsystem.

[0032] In one of the optional technical solutions, the upper layer component is superimposed on the lower layer component, and the method also includes:

[0033] disposing a first solder ball array ball between the second redistribution layer and the seventh redistribution layer;

[0034] A second solder ball array ball is disposed at the bottom of the sixth redistribution layer.

[0035] The technical solution of the present invention also provides a phased array system, including the silicon-based three-dimensional stacked phased array receiving microsystem as described above.

[0036] After adopting the above technical scheme, the following beneficial effects are achieved: by stacking an upper cover plate on an upper silicon substrate, stacking a lower cover plate on a lower silicon substrate, and stacking the upper silicon substrate on the lower cover plate, and arranging an amplitude-phase multifunctional chip on the top of the upper silicon substrate, and arranging a low-noise amplifier on the top of the lower silicon substrate, a first accommodating groove for accommodating the amplitude-phase multifunctional chip is arranged in the upper cover plate, and a second accommodating groove for accommodating the low-noise amplifier is arranged in the lower cover plate, and a rewiring layer and a through-hole group are respectively arranged on the upper cover plate, the upper silicon substrate, the lower cover plate and the lower silicon substrate, and a through-hole metal is arranged in the through-hole group, so that the upper cover plate, the upper silicon substrate, the amplitude-phase multifunctional chip, the lower cover plate, the lower silicon substrate and the low-noise amplifier are interconnected, so as to realize three-dimensional heterogeneous and high-density integrated integration of the multifunctional chip, improve the overall integration, realize the miniaturization of the phased array receiving microsystem, reduce the volume, and reduce the design complexity and production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. It should be understood that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In the drawings:

[0038] Figure 1A schematic diagram of the structure of a silicon-based three-dimensional stacked phased array receiving microsystem provided in one embodiment of the present invention;

[0039] Figure 2 for Figure 1 The schematic diagram of the circuit principle structure of the silicon-based three-dimensional stacked phased array receiving microsystem shown;

[0040] Figure 3 for Figure 1 A schematic diagram of the structure of the lower silicon substrate shown;

[0041] Figure 4 for Figure 1 A schematic diagram of the structure of the upper silicon substrate shown;

[0042] Figure 5 This is a comparison chart of the reflection coefficient analysis results with and without windows on the upper cover;

[0043] Figure 6 A flowchart of a method for processing a silicon-based three-dimensional stacked phased array receiving microsystem provided in one embodiment of the present invention.

[0044] Reference numerals:

[0045] 11-upper silicon substrate; 111-first rewiring layer; 112-second rewiring layer; 113-first through hole group; 114-amplitude and phase input port; 12-lower silicon substrate; 121-fifth rewiring layer; 122-sixth rewiring layer; 123-third through hole group; 124-amplifier input port; 125-amplifier output port; 13-upper cover plate; 131-first receiving groove; 132-third rewiring layer; 1321-opening window; 133- Fourth redistribution layer; 134-second through hole group; 14-lower cover plate; 141-second accommodating groove; 142-seventh redistribution layer; 143-eighth redistribution layer; 144-fourth through hole group; 145-shielding column; 15-first solder ball array ball; 16-second solder ball array ball; 17-first bonding gold wire; 18-first matching branch; 19-third bonding gold wire; 191-second matching branch; 20-amplitude and phase multifunctional chip; 30-low noise amplifier. DETAILED DESCRIPTION

[0046] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0047] It is easy to understand that according to the technical solution of the present invention, without changing the essential spirit of the present invention, a variety of structural modes and implementation modes that can be replaced by those skilled in the art can be replaced with each other. Therefore, the following specific implementation modes and drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as the whole of the present invention or as a limitation or restriction to the technical solution of the invention.

[0048] The directional terms such as up, down, left, right, front, back, front, back, top, bottom, etc. mentioned or may be mentioned in this specification are defined relative to the structures shown in the drawings. They are relative concepts and may change accordingly according to different positions and different usage conditions. Therefore, these or other directional terms should not be interpreted as restrictive terms.

[0049] like Figure 1 As shown, a silicon-based three-dimensional stacked phased array receiving microsystem provided by an embodiment of the present invention comprises an upper silicon substrate 11 and a lower silicon substrate 12, wherein an upper cover plate 13 is provided on the top cover of the upper silicon substrate 11, and the upper cover plate 13 and the upper silicon substrate 11 are sealed, and a lower cover plate 14 is provided on the top cover of the lower silicon substrate 12, and the lower cover plate 14 and the lower silicon substrate 12 are sealed, and the upper silicon substrate 11 is superimposed on the lower cover plate 14,

[0050] A first rewiring layer 111 is provided on the top of the upper silicon substrate 11, a second rewiring layer 112 is provided on the bottom of the upper silicon substrate 11, a first through hole group 113 penetrating the upper silicon substrate 11 is provided in the upper silicon substrate 11, a first through hole metal is provided in the first through hole group 113, the first rewiring layer 111 is electrically connected to the second rewiring layer 112 through the first through hole metal, and an amplitude-phase multifunctional chip 20 electrically connected to the first rewiring layer 111 is provided on the top of the first rewiring layer 111;

[0051] The upper cover plate 13 is provided with a first accommodating groove 131 for accommodating the amplitude-phase multifunctional chip 20, the top of the upper cover plate 13 is provided with a third rewiring layer 132, the bottom of the upper cover plate 13 is provided with a fourth rewiring layer 133 electrically connected to the first rewiring layer 111, the upper cover plate 13 is provided with a second through hole group 134 penetrating the upper cover plate 13, the second through hole group 134 is provided with a second through hole metal, and the third rewiring layer 132 is electrically connected to the fourth rewiring layer 133 through the second through hole metal;

[0052] A fifth rewiring layer 121 is provided on the top of the lower silicon substrate 12, a sixth rewiring layer 122 is provided on the bottom of the lower silicon substrate 12, a third through hole group 123 penetrating the lower silicon substrate 12 is provided in the lower silicon substrate 12, a third through hole metal is provided in the third through hole group 123, the fifth rewiring layer 121 is electrically connected to the sixth rewiring layer 122 through the third through hole metal, and at least one low noise amplifier 30 electrically connected to the fifth rewiring layer 121 is provided on the top of the fifth rewiring layer 121;

[0053] At least one second accommodating groove 141 for accommodating the low noise amplifier 30 is provided in the lower cover plate 14, a seventh redistribution layer 142 electrically connected to the second redistribution layer 112 is provided on the top of the lower cover plate 14, an eighth redistribution layer 143 electrically connected to the fifth redistribution layer 121 is provided on the bottom of the lower cover plate 14, a fourth through hole group 144 penetrating the lower cover plate 14 is provided in the lower cover plate 14, a fourth through hole metal is provided in the fourth through hole group 144, and the seventh redistribution layer 142 is electrically connected to the eighth redistribution layer 143 through the fourth through hole metal.

[0054] The silicon-based three-dimensional stacked phased array receiving microsystem provided by the present invention is used for amplifying, amplitude and phase control, and combining antenna receiving signals. The operating frequency is 32-38 GHz. The circuit principle is as follows: Figure 2 As shown, it is mainly composed of an amplitude-phase multifunctional chip 20 and a low-noise amplifier 30. The amplitude-phase multifunctional chip 20 is used for beamforming, and the low-noise amplifier 30 is used to amplify very weak antenna signals.

[0055] The silicon-based three-dimensional stacked phased array receiving microsystem provided in this embodiment mainly includes an upper silicon substrate 11, a lower silicon substrate 12, an upper cover plate 13, a lower cover plate 14, an amplitude and phase multifunctional chip 20 and a low-noise amplifier 30. The upper cover plate 13, the upper silicon substrate 11, the lower cover plate 14 and the lower silicon substrate 12 are stacked in sequence from top to bottom to form a three-dimensional stacked integration.

[0056] The top and bottom of the upper silicon substrate 11 are respectively provided with a first redistribution layer 111 and a second redistribution layer 112 using redistribution layer (RDL) technology. Then, the upper silicon substrate 11 is etched with a uniform and smooth first through hole group 113 using etching technology to improve high-frequency characteristics and reduce noise loss caused by connection insertion loss, and metal is plated in the first through hole group 113 to interconnect the first redistribution layer 111 and the second redistribution layer 112. The amplitude-phase multifunctional chip 20 is assembled on the top of the first redistribution layer 111 in a flat manner, and is electrically connected to the first redistribution layer 111 through bonding wires, so that the amplitude-phase multifunctional chip 20 is embedded in the large-sized first receiving groove 131. The amplitude-phase multifunctional chip 20 is a four-channel multifunctional amplitude chip, and each channel has low-noise amplification, phase shifting, amplification, and attenuation functions. Among them, the number of through holes in the first through hole group 113 corresponds to at least the number of bare chips.

[0057] The upper cover plate 13 is stacked on the upper silicon substrate 11 by wafer-level bonding. The top and bottom of the upper cover plate 13 are provided with a third rewiring layer 132 and a fourth rewiring layer 133 respectively by using RDL technology, and a uniform and smooth second through-hole group 134 is etched by using etching technology. The second through-hole group 134 is filled with metal plating, so that the fourth rewiring layer 133 is interconnected with the third rewiring layer 132 and the first rewiring layer 111 respectively. A fully covered metal shielding structure is formed between the upper cover plate 13 and the upper silicon substrate 11 by the third rewiring layer 132, the second through-hole group 134, the second through-hole metal, the fourth rewiring layer 133, the first through-hole group 113, the first through-hole metal and the second rewiring layer, so as to realize electromagnetic compatibility and airtight packaging of the system and avoid signal crosstalk between multiple chips and multiple channels.

[0058] The top and bottom of the lower silicon substrate 12 are provided with a fifth rewiring layer 121 and a sixth rewiring layer 122 respectively by using RDL technology, and a uniform and smooth third through hole group 123 is etched by using etching technology, and the third through hole group 123 is filled with metal plating to interconnect the fifth rewiring layer 121 and the sixth rewiring layer 122. The low noise amplifier 30 is mounted on the top of the fifth rewiring layer 121 in a flat manner, and is electrically connected to the fifth rewiring layer 121 by gold wire bonding, so that the low noise amplifier 30 is embedded in the large-sized second receiving groove 141.

[0059] The lower cover plate 14 is stacked on the lower silicon substrate 12 by wafer-level bonding. The top and bottom of the lower cover plate 14 are provided with a seventh rewiring layer 142 and an eighth rewiring layer 143 respectively by using RDL technology, and a uniform and smooth fourth through-hole group 144 is etched by using etching technology. The fourth through-hole group 144 is filled with metal plating, so that the seventh rewiring layer 142 is electrically connected to the second rewiring layer 112 and the eighth rewiring layer 143 respectively. A fully covered metal shielding structure is formed between the lower cover plate 14 and the lower silicon substrate 12 by the seventh rewiring layer 142, the fourth through-hole group 144, the fourth through-hole metal, the eighth rewiring layer 143, the fifth rewiring layer 121, the third through-hole group 123, the third through-hole metal and the sixth rewiring layer 122, so as to realize the electromagnetic compatibility and airtight packaging of the system and avoid signal crosstalk between multiple chips and multiple channels.

[0060] Optionally, the upper silicon substrate 11, the lower silicon substrate 12, the upper cover plate 13 and the lower cover plate 14 are made of high-resistance silicon to reduce tolerance and improve accuracy, thereby forming a silicon-based three-dimensional stacked phased array receiving component.

[0061] In this embodiment, an upper cover plate is superimposed on an upper silicon substrate, a lower cover plate is superimposed on a lower silicon substrate, and the upper silicon substrate is stacked on the lower cover plate, and an amplitude-phase multifunctional chip is arranged on the top of the upper silicon substrate, a low-noise amplifier is arranged on the top of the lower silicon substrate, a first accommodating groove for accommodating the amplitude-phase multifunctional chip is arranged in the upper cover plate, and a second accommodating groove for accommodating the low-noise amplifier is arranged in the lower cover plate, and a rewiring layer and a through-hole group are respectively arranged on the upper cover plate, the upper silicon substrate, the lower cover plate and the lower silicon substrate, and a through-hole metal is arranged in the through-hole group, so that the upper cover plate, the upper silicon substrate, the amplitude-phase multifunctional chip, the lower cover plate, the lower silicon substrate and the low-noise amplifier are interconnected, so as to realize three-dimensional heterogeneous and high-density integrated integration of the multifunctional chip, improve the overall integration, realize the miniaturization of the phased array receiving microsystem, reduce the volume, and reduce the design complexity and production cost.

[0062] In one embodiment, if Figure 1 As shown, a window 1321 is provided on the third redistribution layer 132 .

[0063] Since the upper cover plate 13 and the upper silicon substrate 11 are stacked and integrated with the lower cover plate 14 and the lower silicon substrate 12 to form an upper and lower two-layer structure, the second receiving groove 141 may have cavity eigenmode resonance interference, so it is necessary to optimize the eigenmode of the cavity of the second receiving groove 141 to ensure that the eigenmode of the cavity is outside the operating frequency band of the microsystem to prevent the cavity effect from generating spurious. The eigenmode calculation results are shown in Table 1 below:

[0064] Table 1 Eigenmode calculation results of the cavity of the second receiving groove

[0065] model frequency Q Value Mode 1 41.72 358.4 Mode 2 41.86 360.0 Mode 3 42.78 395.2 Mode 4 42.94 395.4 Mode 5 45.27 444.8 Mode 6 45.73 463.9 Mode 7 46.48 471.7

[0066] From the results in Table 1, it can be seen that the eigenmodes of the cavity of the second containing groove 141 are all outside the working frequency band.

[0067] When no window is provided on the third redistribution layer 132, the calculation results of the eigenmode of the cavity of the first receiving groove 131 are shown in Table 2 below:

[0068] Table 2 Calculation results of the eigenmode of the cavity of the first receiving groove

[0069] model Frequency / GHz Q Value Mode 1 32.46 226.5 Mode 2 33.16 13.7 Mode 3 34.78 329.0 Mode 4 35.77 249.1 Mode 5 35.87 245.3 Mode 6 36.00 265.4 Mode 7 36.9 252.6 Mode 8 37.15 271.3 Mode 9 38.22 277.6

[0070] From the results in Table 2, it can be seen that the first receiving slot 131 has resonance in the working frequency band, and the Q value of the in-band mode is relatively large, with a maximum value of 329, resulting in a resonance point near 33 GHz in the S parameter simulation results, such as Figure 5 The curve of "cover plate without window" is shown.

[0071] When the third redistribution layer 132 is provided with a window 1321, the size of the window is 2.8*6.2 mm, which destroys the boundary condition of the resonant cavity, suppresses the in-band resonant mode, and also optimizes the reflection coefficient of the RF transmission structure in the cavity. Figure 5 In order to further verify its effect of suppressing the in-band resonant mode, as shown in Figure 3 and Figure 4 As shown, two ports are set at both ends of any transmission line of the first rewiring layer 111 to analyze the port reflection coefficient (S11). The S11 analysis results of the third rewiring layer 132 with and without the window 1321 are shown as follows: Figure 5 As shown, from Figure 5 It can be seen that when the window 1321 is not set, its S11 resonates near 33 GHz in the band; when the window 1321 is set, its S11 does not resonate, thereby suppressing the in-band resonance.

[0072] Optionally, in order to further achieve better suppression of in-band resonant modes, the size of the window 1321 is 2.8*6.2 mm.

[0073] In one embodiment, if Figure 1 As shown, a first solder ball array ball 15 is disposed between the second re-wiring layer 112 and the seventh re-wiring layer 142 , and a second solder ball array ball 16 is disposed at the bottom of the sixth re-wiring layer 122 .

[0074] A first solder ball array ball 15 is provided between the second redistribution layer 112 and the seventh redistribution layer 142. The first solder ball array ball 15 is used for structural support and electrical vertical interconnection. A second solder ball array ball 16 is provided at the bottom of the sixth redistribution layer 122. The second solder ball array ball 16 is used for electrical vertical interconnection with other silicon substrates.

[0075] In one embodiment, if Figure 3 As shown, at least one amplifier input port 124 and an amplifier output port 125 electrically connected to the antenna feed point are provided on the lower silicon substrate 12, the input end of the low noise amplifier 30 is electrically connected to the amplifier input port 124 through the first bonding gold wire 17, and the output end of the low noise amplifier 30 is electrically connected to the amplifier output port 125 through the second bonding gold wire.

[0076] The input end of the low noise amplifier 30 is communicatively connected to the antenna feed point through the first gold bonding wire 17 and the amplifier input port 124 , and the output end of the low noise amplifier 30 is communicatively connected to the amplitude and phase multifunctional chip 20 through the second gold bonding wire and the amplifier output port 125 .

[0077] In one embodiment, if Figure 4As shown, an amplitude-phase input port 114 corresponding to the amplifier output port 125 is provided on the upper silicon substrate 11, and the amplitude-phase multifunctional chip 20 is electrically connected to the amplitude-phase input port 114 through a third bonding gold wire 19, thereby facilitating interconnection between the amplitude-phase multifunctional chip 20 and the low-noise amplifier 30.

[0078] In one embodiment, if Figure 3 and Figure 4 As shown, a first matching branch 18 is provided between the amplifier output port 125 and the second bonding gold wire, and a second matching branch 191 is provided between the amplitude and phase input port 114 and the third bonding gold wire 19, thereby achieving matching of different transmission line conversions of upper and lower chips.

[0079] In one embodiment, if Figure 1 and Figure 3 As shown, there are multiple low noise amplifiers 30 , multiple second receiving grooves 141 , shielding columns 145 are provided between two adjacent second receiving grooves 141 , and each shielding column 145 is provided with a fourth through hole group 144 .

[0080] A shielding column 145 is provided between two adjacent second accommodating grooves 141 to form a plurality of chambers. The shielding column 145 is used to change the eigenmode (or resonant frequency) of the chamber so that the eigenmode of the chamber is outside the operating frequency band of the receiving component to prevent the chamber from generating stray signals (or in-band resonance). The shielding column 145 can also play an isolating role to prevent interference between circuit elements in adjacent chambers.

[0081] In one embodiment, if Figure 1 and Figure 4 As shown, at least one first filter capacitor electrically connected to the first rewiring layer 111 is provided on the top of the first rewiring layer 111, and at least one second filter capacitor electrically connected to the fifth rewiring layer 121 is provided in each second receiving groove 141, thereby playing a filtering role.

[0082] Optionally, the amplitude and phase multifunctional chip 20 is a silicon-based CMOS chip, the low-noise amplifier 30 is a gallium arsenide chip, the first filter capacitor 40 and the second filter capacitor 50 are ceramic devices, and the chips and devices made of different materials and different processes are collaboratively designed through the upper silicon substrate 11, the upper cover plate 13, the lower silicon substrate 12 and the lower cover plate 14 to achieve modular heterogeneous and heterogeneous integration of phased array receiving components.

[0083] like Figure 6 As shown, an embodiment of the present invention provides a method for processing a silicon-based three-dimensional stacked phased array receiving microsystem, comprising:

[0084] Step S601: Disposing a first rewiring layer and a second rewiring layer on the top and bottom of the upper silicon substrate respectively;

[0085] Step S602: a first through hole group penetrating the upper silicon substrate is provided in the upper silicon substrate, and a first through hole metal is provided in the first through hole group, and the first rewiring layer is electrically connected to the second rewiring layer through the first through hole metal;

[0086] Step S603: Arranging an amplitude-phase multifunctional chip electrically connected to the first rewiring layer on top of the first rewiring layer;

[0087] Step S604: a first receiving slot for receiving the amplitude-phase multifunctional chip is provided in the upper cover plate;

[0088] Step S605: disposing a third redistribution layer on the top of the upper cover plate, and disposing a fourth redistribution layer electrically connected to the first redistribution layer on the bottom of the upper cover plate;

[0089] Step S606: a second through hole group penetrating the upper cover plate is provided in the upper cover plate, and a second through hole metal is provided in the second through hole group, and the third rewiring layer is electrically connected to the fourth rewiring layer through the second through hole metal;

[0090] Step S607: Covering the upper cover plate on the top of the upper silicon substrate to form an upper assembly;

[0091] Step S608: Disposing a fifth rewiring layer and a sixth rewiring layer on the top and bottom of the lower silicon substrate respectively;

[0092] Step S609: a third through hole group penetrating the lower silicon substrate is provided in the lower silicon substrate, and a third through hole metal is provided in the third through hole group, and the fifth rewiring layer is electrically connected to the sixth rewiring layer through the third through hole metal;

[0093] Step S610: disposing at least one low noise amplifier electrically connected to the fifth rewiring layer on top of the fifth rewiring layer;

[0094] Step S611: providing at least one second receiving groove for receiving a low noise amplifier in the lower cover plate;

[0095] Step S612: disposing a seventh redistribution layer on the top of the lower cover plate, and disposing an eighth redistribution layer electrically connected to the fifth redistribution layer on the bottom of the lower cover plate;

[0096] Step S613: a fourth through hole group penetrating the lower cover plate is provided in the lower cover plate, and a fourth through hole metal is provided in the fourth through hole group, and the seventh rewiring layer is electrically connected to the eighth rewiring layer through the fourth through hole metal;

[0097] Step S614: Covering the lower cover plate on the top of the lower silicon substrate to form a lower assembly;

[0098] Step S615: stacking the upper layer component on the lower layer component, and electrically connecting the second redistribution layer to the seventh redistribution layer to form a silicon-based three-dimensional stacked phased array receiving microsystem.

[0099] Specifically:

[0100] Step S601, step S605, step S608 and step S612: by making a seed layer, electroplating, exposing, developing, etching and other process steps, a first RDL, a second RDL, a third RDL, a fourth RDL, a fifth RDL, a sixth RDL, a seventh RDL and an eighth RDL are respectively made on the top and bottom of the upper silicon substrate, the upper cover plate, the lower silicon substrate and the lower cover plate;

[0101] Step S602, step S606, step S609 and step S613: using etching technology to form a first through hole group, a second through hole group, a third through hole group and a fourth through hole group respectively penetrating the upper silicon substrate, the upper cover plate, the lower cover plate and the lower silicon substrate, and filling and plating metal in the first through hole group, the second through hole group, the third through hole group and the fourth through hole group;

[0102] Step S603 and step S610: mounting the amplitude-phase multifunctional chip and the low noise amplifier on the top of the first RDL and the fifth RDL respectively by bonding glue or the like;

[0103] Step S604 and step S611: using etching technology to make a first receiving groove and a second receiving groove in the upper cover plate and the lower cover plate respectively;

[0104] Step S607, step S614 and step S615: respectively cover the upper cover plate on the upper silicon substrate to form an upper component, cover the lower cover plate on the lower silicon substrate to form a lower component, and finally stack the upper component on the lower component to form a silicon-based three-dimensional stacked phased array receiving microsystem.

[0105] Among them, the execution order of steps S601-S603 and steps S604-S606, steps S608-S610 and steps S611-S613, steps S601-S607 and steps S608-S614 can be interchanged or performed simultaneously, and their execution order is not limited to this embodiment.

[0106] In this embodiment, an upper cover plate is superimposed on an upper silicon substrate, a lower cover plate is superimposed on a lower silicon substrate, and the upper silicon substrate is stacked on the lower cover plate, and an amplitude-phase multifunctional chip is arranged on the top of the upper silicon substrate, a low-noise amplifier is arranged on the top of the lower silicon substrate, a first accommodating groove for accommodating the amplitude-phase multifunctional chip is arranged in the upper cover plate, and a second accommodating groove for accommodating the low-noise amplifier is arranged in the lower cover plate, and a rewiring layer and a through-hole group are respectively arranged on the upper cover plate, the upper silicon substrate, the lower cover plate and the lower silicon substrate, and a through-hole metal is arranged in the through-hole group, so that the upper cover plate, the upper silicon substrate, the amplitude-phase multifunctional chip, the lower cover plate, the lower silicon substrate and the low-noise amplifier are interconnected, so as to realize three-dimensional heterogeneous and high-density integrated integration of the multifunctional chip, improve the overall integration, realize the miniaturization of the phased array receiving microsystem, reduce the volume, and reduce the design complexity and production cost.

[0107] In one embodiment, the step of stacking the upper layer component on the lower layer component also includes:

[0108] disposing a first solder ball array ball between the second redistribution layer and the seventh redistribution layer;

[0109] A second solder ball array ball is disposed at the bottom of the sixth redistribution layer.

[0110] Specifically, ball grid array (BGA) balls are soldered between the second RDL and the seventh RDL and at the bottom of the sixth RDL, thereby completing a direct connection port with the outside world.

[0111] The technical solution of the present invention also provides a phased array system, including the silicon-based three-dimensional stacked phased array receiving microsystem as described above.

[0112] In this embodiment, an upper cover plate is superimposed on an upper silicon substrate, a lower cover plate is superimposed on a lower silicon substrate, and the upper silicon substrate is stacked on the lower cover plate, and an amplitude-phase multifunctional chip is arranged on the top of the upper silicon substrate, a low-noise amplifier is arranged on the top of the lower silicon substrate, a first accommodating groove for accommodating the amplitude-phase multifunctional chip is arranged in the upper cover plate, and a second accommodating groove for accommodating the low-noise amplifier is arranged in the lower cover plate, and a rewiring layer and a through-hole group are respectively arranged on the upper cover plate, the upper silicon substrate, the lower cover plate and the lower silicon substrate, and a through-hole metal is arranged in the through-hole group, so that the upper cover plate, the upper silicon substrate, the amplitude-phase multifunctional chip, the lower cover plate, the lower silicon substrate and the low-noise amplifier are interconnected, so as to realize three-dimensional heterogeneous and high-density integrated integration of the multifunctional chip, improve the overall integration, realize the miniaturization of the phased array receiving microsystem, reduce the volume, and reduce the design complexity and production cost.

[0113] The above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon-based three-dimensional stacked phased array receiving microsystem, characterized in that: The invention comprises an upper silicon substrate and a lower silicon substrate, wherein the upper silicon substrate is provided with an upper cover plate on the top cover thereof, and the upper cover plate is sealed with the upper silicon substrate, the lower silicon substrate is provided with a lower cover plate on the top cover thereof, and the lower cover plate is sealed with the lower silicon substrate, and the upper silicon substrate is superimposed on the lower cover plate, A first rewiring layer is provided on the top of the upper silicon substrate, a second rewiring layer is provided on the bottom of the upper silicon substrate, a first through-hole group penetrating the upper silicon substrate is provided in the upper silicon substrate, a first through-hole metal is provided in the first through-hole group, the first rewiring layer is electrically connected to the second rewiring layer through the first through-hole metal, and an amplitude-phase multifunctional chip electrically connected to the first rewiring layer is provided on the top of the first rewiring layer; The upper cover plate is provided with a first accommodating groove for accommodating the amplitude-phase multifunctional chip, the top of the upper cover plate is provided with a third rewiring layer, the third rewiring layer is provided with a window, the bottom of the upper cover plate is provided with a fourth rewiring layer electrically connected to the first rewiring layer, the upper cover plate is provided with a second through-hole group penetrating the upper cover plate, the second through-hole group is provided with a second through-hole metal, and the third rewiring layer is electrically connected to the fourth rewiring layer through the second through-hole metal; A fifth rewiring layer is provided on the top of the lower silicon substrate, a sixth rewiring layer is provided on the bottom of the lower silicon substrate, a third through-hole group penetrating the lower silicon substrate is provided in the lower silicon substrate, a third through-hole metal is provided in the third through-hole group, the fifth rewiring layer is electrically connected to the sixth rewiring layer through the third through-hole metal, and at least one low-noise amplifier electrically connected to the fifth rewiring layer is provided on the top of the fifth rewiring layer; At least one second accommodating groove for accommodating the low-noise amplifier is provided in the lower cover plate, a seventh redistribution layer electrically connected to the second redistribution layer is provided on the top of the lower cover plate, an eighth redistribution layer electrically connected to the fifth redistribution layer is provided on the bottom of the lower cover plate, a fourth through hole group penetrating the lower cover plate is provided in the lower cover plate, a fourth through hole metal is provided in the fourth through hole group, and the seventh redistribution layer is electrically connected to the eighth redistribution layer through the fourth through hole metal.

2. The silicon-based three-dimensional stacked phased array receiving microsystem according to claim 1, characterized in that: A first solder ball array ball is disposed between the second rewiring layer and the seventh rewiring layer, and a second solder ball array ball is disposed at the bottom of the sixth rewiring layer.

3. The silicon-based three-dimensional stacked phased array receiving microsystem according to claim 2, characterized in that: The lower silicon substrate is provided with at least one amplifier input port and an amplifier output port electrically connected to the antenna feed point. The input end of the low-noise amplifier is electrically connected to the amplifier input port through a first bonding gold wire, and the output end of the low-noise amplifier is electrically connected to the amplifier output port through a second bonding gold wire.

4. The silicon-based three-dimensional stacked phased array receiving microsystem according to claim 3, characterized in that: An amplitude and phase input port corresponding to the amplifier output port is arranged on the upper silicon substrate, and the amplitude and phase multifunctional chip is electrically connected to the amplitude and phase input port through a third bonding gold wire.

5. The silicon-based three-dimensional stacked phased array receiving microsystem according to claim 4, characterized in that: A first matching branch is provided between the amplifier output port and the second bonding gold wire, and a second matching branch is provided between the amplitude and phase input port and the third bonding gold wire.

6. The silicon-based three-dimensional stacked phased array receiving microsystem according to claim 1, characterized in that: There are a plurality of low-noise amplifiers, there are a plurality of second accommodating grooves, a shielding column is provided between two adjacent second accommodating grooves, and each of the shielding columns is provided with the fourth through hole group.

7. A method for processing a silicon-based three-dimensional stacked phased array receiving microsystem according to any one of claims 1 to 6, characterized in that: include: Disposing a first rewiring layer and a second rewiring layer on the top and bottom of the upper silicon substrate, respectively; A first through hole group penetrating the upper silicon substrate is provided in the upper silicon substrate, and a first through hole metal is provided in the first through hole group, and the first rewiring layer is electrically connected to the second rewiring layer through the first through hole metal; Disposing an amplitude-phase multifunctional chip electrically connected to the first rewiring layer on top of the first rewiring layer; A first receiving groove for receiving the amplitude-phase multifunctional chip is provided in the upper cover plate; A third rewiring layer is arranged on the top of the upper cover plate, wherein a window is arranged on the third rewiring layer, and a fourth rewiring layer electrically connected to the first rewiring layer is arranged on the bottom of the upper cover plate; A second through hole group penetrating the upper cover plate is provided in the upper cover plate, and a second through hole metal is provided in the second through hole group, and the third rewiring layer is electrically connected to the fourth rewiring layer through the second through hole metal; Covering the upper cover plate on the top of the upper silicon substrate to form an upper assembly; Disposing a fifth rewiring layer and a sixth rewiring layer on the top and bottom of the lower silicon substrate, respectively; A third through hole group penetrating the lower silicon substrate is provided in the lower silicon substrate, and a third through hole metal is provided in the third through hole group, and the fifth rewiring layer is electrically connected to the sixth rewiring layer through the third through hole metal; Disposing at least one low noise amplifier electrically connected to the fifth rewiring layer on top of the fifth rewiring layer; At least one second receiving groove for receiving the low noise amplifier is provided in the lower cover plate; A seventh redistribution layer is disposed on the top of the lower cover plate, and an eighth redistribution layer electrically connected to the fifth redistribution layer is disposed on the bottom of the lower cover plate; A fourth through hole group penetrating the lower cover plate is provided in the lower cover plate, and a fourth through hole metal is provided in the fourth through hole group, and the seventh rewiring layer is electrically connected to the eighth rewiring layer through the fourth through hole metal; Covering the lower cover plate on the top of the lower silicon substrate to form a lower assembly; The upper layer component is stacked on the lower layer component, and the second redistribution layer is electrically connected to the seventh redistribution layer to form the silicon-based three-dimensional stacked phased array receiving microsystem.

8. The processing method according to claim 7, characterized in that: The upper layer component is superimposed on the lower layer component, and the method further comprises: disposing a first solder ball array ball between the second redistribution layer and the seventh redistribution layer; A second solder ball array ball is disposed at the bottom of the sixth redistribution layer.

9. A phased array system, characterized in that: It comprises the silicon-based three-dimensional stacked phased array receiving microsystem as described in any one of claims 1-6.

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