An adaptive precise zero-crossing adjustment circuit

Abstract

This invention discloses an adaptive precise zero-crossing regulation circuit, applied to the zero-crossing detection of the output power transistor in a single-inductor dual-output DC / DC switching power supply; the zero-crossing regulation circuit includes: a DCM mode determination circuit used to determine the voltage V at the connection node between the drain of the output power transistor and the inductor. X And the output voltage V of a single-inductor dual-output DC / DC switching power supply OP It determines and outputs the DCM mode entry signal; the body diode monitoring circuit is used to detect the voltage V. X and output voltage V OP The system monitors sudden voltage changes at the connection node in real time, compares these changes with a reference voltage, and outputs a logic pulse signal based on the comparison result. An adjustment circuit, controlled by the DCM mode entry signal and the logic pulse signal, generates an initial ramp voltage, adjusts it to a target ramp voltage, and calculates the adjustment time required to reach the target ramp voltage from 0V. This invention achieves accurate zero-crossing detection.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an adaptive precise zero-crossing adjustment circuit. Background Technology

[0002] Switching power supplies operate in two modes depending on the load current: CCM (Continuous Conduction Mode) and DCM (Discontinuous Conduction Mode). The difference between the two modes lies in whether the inductor current crosses zero. When the inductor current crosses zero, if the output power transistor is not turned off in time to cut off the current transmission path, the inductor current will flow in reverse, causing significant power loss to the switching power supply. Therefore, it is necessary to monitor the moment when the inductor current reaches zero and turn off the output power transistor in time to prevent inductor current reverse flow. The accuracy of the zero-crossing point has a significant impact on the efficiency of a single-inductor dual-output DC / DC switching power supply in DCM mode.

[0003] Currently, zero-crossing issues are addressed in DCM mode by introducing zero-crossing comparators. However, for integrated circuits, device mismatch and ambient temperature differences often introduce mismatch voltages into individual zero-crossing comparators, affecting the determination of zero-crossing points. Furthermore, zero-crossing comparators themselves have a certain propagation delay, and there is also a delay effect from the drive signal to the output of the drive circuit. Therefore, zero-crossing control achieved by relying solely on a single zero-crossing comparator has too many uncontrollable factors. It lacks its own adjustment circuit and cannot optimize the error value it generates. If the output power transistor turns off too early, the inductor current will freewheel through the parasitic diode of the output power transistor, causing conduction losses. If the output power transistor turns off too late, the inductor current reverse flow will also lead to power loss.

[0004] Therefore, precise adjustable zero-crossing detection is essential. The output power transistor needs to be turned off precisely when the inductor current is 0, in order to reduce losses and improve the efficiency of the switching power supply. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an adaptive precise zero-crossing adjustment circuit. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides an adaptive precise zero-crossing adjustment circuit for detecting the zero-crossing point of the output power transistor in a single-inductor dual-output DC / DC switching power supply. The drain of the output power transistor is connected to an inductor, the gate of the output power transistor is connected to the input terminal of a drive control signal DR, and the source of the output power transistor serves as the output terminal of the single-inductor dual-output DC / DC switching power supply. The zero-crossing adjustment circuit includes:

[0007] The DCM mode determination circuit, connected to the gate, source, and drain of the output power transistor, is used, under the control of the drive control signal DR, to determine the mode based on the voltage V at the connection node between the drain and the inductor of the output power transistor. X And the output voltage V of a single-inductor dual-output DC / DC switching power supply OP Determine and output the DCM mode entry signal;

[0008] A body diode monitoring circuit, connected to the source and drain of the output power transistor, is used to monitor the voltage V. X and the output voltage V OP Real-time monitoring of sudden voltage changes at connection nodes, comparison of the sudden voltage change with a reference voltage, and output of a logic pulse signal based on the comparison result;

[0009] An adjustment circuit, connected to the gate of the output power transistor, the DCM mode judgment circuit, and the body diode monitoring circuit, is used to generate an initial ramp voltage under the control of the drive control signal DR, the DCM mode entry signal, and the logic pulse signal, adjust the initial ramp voltage to a target ramp voltage, and calculate the adjustment time required to adjust from 0V to the target ramp voltage. This adjustment time is then used as the control time of the drive control signal DR for the gate of the output power transistor, thereby adjusting the zero-crossing point of the output power transistor.

[0010] In one embodiment of the present invention, the zero-crossing adjustment circuit further includes:

[0011] A counting circuit, connected to the gate of the output power transistor and the DCM mode determination circuit, is used to count the rising edges of the drive control signal DR under the control of the DCM mode entry signal. If the number of rising edges reaches a preset number, a counting control signal is generated. The counting circuit has a built-in rising edge detector for detecting the rising edge of the drive control signal DR.

[0012] The adjustment circuit, connected to the counting circuit, is also used to adjust the initial ramp voltage to the target ramp voltage under the control of the drive control signal DR, the DCM mode entry signal, the logic pulse signal and the counting control signal, and to count the adjustment time required to adjust to the target ramp voltage.

[0013] In one embodiment of the present invention, the DCM mode determination circuit includes a comparator COMP1 and a flip-flop DFF; wherein,

[0014] The positive input terminal of comparator COMP1 is connected to the drain of the output power transistor, the negative input terminal of comparator COMP1 is connected to the source of the output power transistor, the output terminal of comparator COMP1 is connected to the input terminal D of flip-flop DFF, the clock terminal CLK of flip-flop DFF is connected to the gate of the output power transistor, and the output terminal Q of flip-flop DFF serves as the output terminal of the DCM mode determination circuit.

[0015] In one embodiment of the present invention, the body diode monitoring circuit includes a crystal M1 to a transistor M13, a Schmitt trigger, inverters INV1 to INV3, a current source IB1, a current source IB2, and a capacitor C1; wherein,

[0016] The drain of transistor M1 is connected to the gate of transistor M1, the gate of transistor M2, the gate of transistor M7, and the negative terminal of current source IB1. The sources of transistors M1, M2, M7, M10, and M14, and the negative terminal of current source IB2 are all grounded to GND. The drain of transistor M2 is connected to the source of transistor M3. The gate of transistor M3 is connected to the drain of transistor M3, the gate of transistor M4, the drain of transistor M4, the drain of transistor M6, the gate of transistor M8, and the drain of the output power transistor. The source of transistor M4 is connected to the drain and gate of transistor M5. The source of transistor M5 is connected to the gate of transistor M6, the source of transistor M9, the source of transistor M12, and the source of transistor M13. The positive terminal of current source IB1 is connected to the source of the output power transistor. The source of transistor M6 is connected to the drain of transistor M8, the drain of transistor M9, the gate of transistor M9, and one end of capacitor C1. The drain of transistor M7 is connected to the source of transistor M8. The gate of transistor M10 is connected to the drain of transistor M10 and the source of transistor M11. The gate of transistor M11 is connected to the drain of transistor M11, the drain of transistor M12, the other end of capacitor C1, and the input of Schmitt trigger. The gate of transistor M12 is connected to the gate of transistor M13, the drain of transistor M13, and the positive terminal of current source IB2. The output of Schmitt trigger is connected in sequence to inverters INV1 to INV3. The output of inverter INV3 serves as the output of the body diode monitoring circuit.

[0017] In one embodiment of the present invention, the Schmitt trigger includes transistors M14 to M19; wherein,

[0018] The gate of transistor M14 is connected to the gates of transistors M15, M16, M17, and M11. The sources of transistors M14 and M19 are grounded to GND. The drain of transistor M14 is connected to the sources of transistors M15 and M18. The drain of transistor M15 is connected to the drain of transistor M16, the gate of transistor M18, the gate of transistor M19, and the input of inverter INV1. The source of transistor M16 is connected to the drain of transistors M17 and M19. The source of transistor M17 and the drain of transistor M18 are both connected to the power supply VDD.

[0019] In one embodiment of the present invention, the adjustment circuit includes:

[0020] A preset circuit, connected to the gate of the output power transistor and the counting circuit, is used to generate an initial ramp voltage under the control of the drive control signal DR and the counting control signal;

[0021] A reference signal adjustment circuit, connected to the gate of the output power transistor, the preset position circuit, the counting circuit, the body diode monitoring circuit, and the DCM mode judgment circuit, is used to adjust the initial ramp voltage to the target ramp voltage under the control of the counting control signal, the logic pulse signal, and the DCM mode entry signal.

[0022] The adjustment signal output circuit is connected to the reference signal adjustment circuit, the DCM mode judgment circuit, and the gate of the output power transistor. It is used to calculate the adjustment time required to adjust from 0V to the target ramp voltage under the control of the DCM mode entry signal and the drive control signal DR.

[0023] In one embodiment of the present invention, the preset bit circuit includes transistors M20 to M23, a current source IB3, a sample-and-hold circuit SH, a capacitor C2, and an OR gate; wherein,

[0024] The sources of transistors M20 and M21 are both connected to power supply VDD. The gate of transistor M20 is connected to the gate of transistor M21, the drain of transistor M20, and the positive terminal of current source IB3. The drain of transistor M21 is connected to the source of transistor M22. The gate of transistor M22 is connected to the output terminal of OR gate and the gate of transistor M23. The drain of transistor M22 is connected to the drain of transistor M23, one end of capacitor C2, and the data input terminal of sample-and-hold circuit SH. The clock input terminal of sample-and-hold circuit SH is connected to the gate of the output power transistor. The output terminal of sample-and-hold circuit SH is connected to the reference signal adjustment circuit. The source of transistor M23, one end of capacitor C2, and the negative terminal of current source IB3 are all grounded to GND. The two input terminals of OR gate are connected to the gate of the output power transistor and the counting circuit, respectively.

[0025] In one embodiment of the present invention, the reference signal adjustment circuit includes NAND gates NAND1 to NAND gates NAND4, rising edge detectors PG1 to PG3, a delay unit Delay, an RS flip-flop, an inverter INV4, transistors M24 to M30, current source IB4, current source IB5, and capacitor C3; wherein,

[0026] The two inputs of NAND gate NAND1 are connected to the counting circuit and the gate of the output power transistor, respectively. The output of NAND gate NAND1 is connected to the input of rising edge detector PG1. The two inputs of NAND gate NAND2 are connected to the counting circuit and the output of delay unit Delay, respectively. The output of NAND gate NAND2 is connected to the input S of RS flip-flop. The input of delay unit Delay is connected to the gate of the output power transistor. The input of rising edge detector PG2 is connected to the body diode monitoring circuit. The output of rising edge detector PG2 is connected to the input R of RS flip-flop. The three inputs of NAND gate NAND3 are connected to the DCM mode determination circuit, the output of rising edge detector PG1, and the output NQ of RS flip-flop, respectively. The output of NAND gate NAND3 is connected to the input of inverter INV4. The three inputs of NAND gate NAND4 are connected to the DCM mode determination circuit, the output of rising edge detector PG1, and the output Q of RS flip-flop, respectively. The output of NAND gate NAND4 is connected to the crystal. The gate of transistor M26 is connected to the ground. The sources of transistors M26, M25, M24, and M30, one end of capacitor C3, and the negative terminal of current source IB4 are all grounded to GND. The drain of transistor M26 is connected to the gate of transistor M24, the drain of transistor M24, the gate of transistor M25, and the negative terminal of current source IB5. The positive terminal of current source IB5, the source of transistor M27, M28, and M29 are all connected to the power supply VDD. The drain of transistor M25 is connected to the gate of transistor M26. The drain of transistor M28, the output of the sample-and-hold circuit SH, the drain of transistor M30, the other end of capacitor C3, and the adjustment signal output circuit are connected. The gate of transistor M27 is connected to the drain of transistor M27, the gate of transistor M28, the drain of transistor M29, and the positive terminal of current source IB4. The gate of transistor M29 is connected to the output of inverter INV4. The gate of transistor M30 is connected to the output of rising edge detector PG3. The input of rising edge detector PG3 is connected to the DCM mode determination circuit.

[0027] In one embodiment of the present invention, the adjustment signal output circuit includes transistors M31 to M34, a current source IB6, a comparator COMP2, a capacitor C4, a NAND gate NAND5, and an inverter INV5; wherein,

[0028] The source of transistor M31, one end of capacitor C4, and the negative terminal of current source IB6 are all grounded to GND. The gate of transistor M31 is connected to the gate of transistor M32 and the output of NAND gate NAND5. The drain of transistor M31 is connected to the drain of transistor M32, the inverting input of comparator COMP2, and the other end of capacitor C4. The source of transistor M32 is connected to the drain of transistor M33. The sources of transistors M33 and M34 are both connected to power supply VDD. The gate of transistor M33 is connected to the gate of transistor M34, the drain of transistor M34, and the positive terminal of current source IB6. The positive input of comparator COMP2 is connected to the output of sample-and-hold circuit SH. The two inputs of NAND gate NAND5 are connected to the DCM mode determination circuit and the output of inverter INV5, respectively. The input of inverter INV5 is connected to the gate of the output power transistor.

[0029] The beneficial effects of this invention are:

[0030] This invention proposes an adaptive precise zero-crossing adjustment circuit that solves the problems of traditional zero-crossing comparators, such as being affected by process deviations, having low accuracy, and high power consumption. Through a more rationally designed circuit structure, it achieves precise zero-crossing detection. Specifically, in DCM mode, this invention uses a body diode monitoring circuit to monitor the on-state of the output power transistor in real time to generate a logic control signal. An adjustment circuit then adjusts the inductor's charging and discharging time based on the logic pulse signal, achieving precise zero-crossing detection and reducing reverse inductor current flow. Compared to zero-crossing comparators, this invention first generates an initial ramp voltage in the adjustment circuit, adjusting from this initial ramp voltage to reach the target ramp voltage. In discontinuous current mode, this avoids the problem of the initial zero-crossing point being too far from the precise zero-crossing point, enabling faster locking of the precise zero-crossing point and improving the locking speed. It also avoids the power consumption caused by continuous adjustments due to inaccurate zero-crossing, significantly improving the efficiency of the switching power supply in DCM mode. This invention can be used in Boost-like topologies, offering a wider range of applications.

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of an adaptive precise zero-crossing adjustment circuit provided in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of another adaptive precise zero-crossing adjustment circuit provided in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the specific circuit structure of the DCM mode determination circuit provided in the embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the specific circuit structure of the body diode monitoring circuit provided in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of the adjustment circuit provided in an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the specific circuit structure of the adjustment circuit provided in the embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of the specific circuit structure of a single-inductor dual-output DC / DC switching power supply provided in an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram showing the waveform change of the inductor current of the single-inductor dual-output DC / DC switching power supply after entering DCM mode when the output voltage is 4.6V, according to an embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0041] Please see Figure 1 This invention provides an adaptive precise zero-crossing adjustment circuit for detecting the zero-crossing point of the output power transistor in a single-inductor dual-output DC / DC switching power supply. The drain of the output power transistor is connected to an inductor, the gate of the output power transistor is connected to the input terminal of the drive control signal DR, and the source of the output power transistor serves as the output terminal of the single-inductor dual-output DC / DC switching power supply. The zero-crossing adjustment circuit includes:

[0042] The DCM mode detection circuit connects the gate, source, and drain of the output power transistor. Under the control of the drive control signal DR, it determines the mode based on the voltage V at the connection point between the drain of the output power transistor and the inductor. X And the output voltage V of a single-inductor dual-output DC / DC switching power supply OP Determine and output the DCM mode entry signal;

[0043] The body diode monitoring circuit is connected to the source and drain of the output power transistor and is used to monitor the voltage V. X and output voltage V OP Real-time monitoring of sudden voltage changes at connection nodes, comparison of the sudden voltage change with a reference voltage, and output of a logic pulse signal based on the comparison result;

[0044] The adjustment circuit, connected to the gate of the output power transistor, the DCM mode judgment circuit, and the body diode monitoring circuit, is used to generate an initial ramp voltage under the control of the drive control signal DR, the DCM mode entry signal, and the logic pulse signal. It adjusts the initial ramp voltage to the target ramp voltage and calculates the adjustment time required to adjust from 0V to the target ramp voltage. This adjustment time is used as the control time of the drive control signal DR for the gate of the output power transistor, thereby adjusting the zero-crossing point of the output power transistor.

[0045] Further, please see Figure 2 In this embodiment of the invention, the zero-crossing adjustment circuit further includes:

[0046] The counting circuit is connected to the gate of the output power transistor and the DCM mode judgment circuit. It is used to count the rising edges of the drive control signal DR under the control of the DCM mode entry signal. If the number of rising edges reaches the preset number, a counting control signal is generated. The counting circuit has a built-in rising edge detector to detect the rising edge of the drive control signal DR.

[0047] The adjustment circuit is also connected to the counting circuit. It is also used to generate an initial ramp voltage under the control of the drive control signal DR, the DCM mode entry signal, the logic pulse signal and the counting control signal, adjust the initial ramp voltage to the target ramp voltage, and count the adjustment time required to adjust from 0V to the target ramp voltage.

[0048] In this embodiment of the invention, a counting circuit generates a technical control signal to control the subsequent preset position circuit to generate a more reasonable initial ramp voltage.

[0049] Next, each part of the circuit will be described in detail.

[0050] In this embodiment of the invention, the DCM mode determination circuit is as follows: Figure 3 As shown, it includes a comparator COMP1 and a flip-flop DFF; wherein,

[0051] The positive input of comparator COMP1 is connected to the drain of the output power transistor, the negative input of comparator COMP1 is connected to the source of the output power transistor, the output of comparator COMP1 is connected to the input D of flip-flop DFF, the clock input CLK of flip-flop DFF is connected to the gate of the output power transistor, and the output Q of flip-flop DFF serves as the output of the DCM mode determination circuit.

[0052] Furthermore, in this embodiment of the invention, the body diode monitoring circuit is as follows: Figure 4 As shown, it includes crystal M1 to transistor M13, Schmitt trigger, inverters INV1 to INV3, current source IB1, current source IB2, and capacitor C1; wherein,

[0053] The drain of transistor M1 is connected to the gate of transistor M1, the gate of transistor M2, the gate of transistor M7, and the negative terminal of current source IB1. The sources of transistors M1, M2, M7, M10, and M14, as well as the negative terminal of current source IB2, are all grounded to GND. The drain of transistor M2 is connected to the source of transistor M3. The gate of transistor M3 is connected to the drain of transistor M3, the gate of transistor M4, the drain of transistor M4, the drain of transistor M6, the gate of transistor M8, and the drain of the output power transistor. The source of transistor M4 is connected to the drain and gate of transistor M5. The source of transistor M5 is connected to the gate of transistor M6, the source of transistor M9, the source of transistor M12, and the source of transistor M13. The positive terminal of current source IB1 is connected to the source of the output power transistor. The source of transistor M6 is connected to the drain of transistor M8, the drain of transistor M9, the gate of transistor M9, and one end of capacitor C1. The drain of transistor M7 is connected to the source of transistor M8. The gate of transistor M10 is connected to the drain of transistor M10 and the source of transistor M11. The gate of transistor M11 is connected to the drain of transistor M11, the drain of transistor M12, the other end of capacitor C1, and the input of Schmitt trigger. The gate of transistor M12 is connected to the gate of transistor M13, the drain of transistor M13, and the positive terminal of current source IB2. The output of the Schmitt trigger is connected sequentially to inverters INV1 through INV3. The output of inverter INV3 serves as the output of the body diode monitoring circuit. The bias current provided by current source IB1 is 5μA, and the bias current provided by current source IB2 is 2μA. The body diode monitoring circuit of this invention monitors the voltage between the source and drain of the output power transistor in real time, and can be used to detect the turn-on status of the output power transistor to adjust the charging and discharging time of the inductor.

[0054] Examples of embodiments of the present invention Figure 4 As shown, the Schmitt trigger includes transistors M14 to M19; wherein,

[0055] The gate of transistor M14 is connected to the gates of transistors M15, M16, M17, and M11. The sources of transistors M14 and M19 are grounded to GND. The drain of transistor M14 is connected to the sources of transistors M15 and M18. The drain of transistor M15 is connected to the drain of transistor M16, the gate of transistor M18, the gate of transistor M19, and the input of inverter INV1. The source of transistor M16 is connected to the drain of transistors M17 and M19. The source of transistor M17 and the drain of transistor M18 are both connected to the power supply VDD, for example, VDD is 5V here. In this embodiment of the invention, the Schmitt trigger is used to provide a reference voltage. For example, if the Schmitt trigger provides a reference voltage of 2.5V, during the real-time monitoring process of the body diode monitoring circuit, if the charging voltage of capacitor C1 reaches 2.5V, the Schmitt trigger will flip, and the final logic control signal OUT output by the body diode monitoring circuit will be 1, while the initial logic control signal OUT output by the body diode monitoring circuit will be 0.

[0056] Furthermore, embodiments of the present invention include, for example... Figure 5 As shown, the adjustment circuit includes:

[0057] The preset circuit connects the gate of the output power transistor and the counting circuit, and is used to generate the initial ramp voltage under the control of the drive control signal DR and the counting control signal;

[0058] The reference signal adjustment circuit is connected to the gate of the output power transistor, the preset circuit, the counting circuit, the body diode monitoring circuit, and the DCM mode judgment circuit. It is used to adjust the initial ramp voltage to the target ramp voltage under the control of the counting control signal, the logic pulse signal, and the DCM mode entry signal.

[0059] The adjustment signal output circuit is connected to the reference signal adjustment circuit, the DCM mode judgment circuit, and the gate of the output power transistor. It is used to calculate the adjustment time required to adjust from 0V to the target ramp voltage under the control of the DCM mode entry signal and the drive control signal DR.

[0060] Furthermore, embodiments of the present invention include, for example... Figure 6 As shown, the preset circuit includes transistors M20 to M23, current source IB3, sample-and-hold circuit SH, capacitor C2, and OR gate OR; wherein,

[0061] The sources of transistors M20 and M21 are both connected to power supply VDD. The gate of transistor M20 is connected to the gate of transistor M21, the drain of transistor M20, and the positive terminal of current source IB3. The drain of transistor M21 is connected to the source of transistor M22. The gate of transistor M22 is connected to the output of OR gate and the gate of transistor M23. The drain of transistor M22 is connected to the drain of transistor M23, one end of capacitor C2, and the data input of sample-and-hold circuit SH. The clock input of sample-and-hold circuit SH is connected to the gate of output power transistor. The output of sample-and-hold circuit SH is connected to reference signal adjustment circuit. The source of transistor M23, one end of capacitor C2, and the negative terminal of current source IB3 are all grounded to GND. The two inputs of OR gate are connected to the gate of output power transistor and the counting circuit, respectively. The bias current provided by current source IB3 is 10μA.

[0062] Furthermore, embodiments of the present invention include, for example... Figure 6 As shown, the reference signal adjustment circuit includes NAND gates NAND1 to NAND4, rising edge detectors PG1 to PG3, a delay unit Delay, an RS flip-flop, an inverter INV4, transistors M24 to M30, current source IB4, current source IB5, and capacitor C3; wherein,

[0063] The two inputs of NAND gate NAND1 are connected to the counting circuit and the gate of the output power transistor, respectively. The output of NAND gate NAND1 is connected to the input of rising edge detector PG1. The two inputs of NAND gate NAND2 are connected to the counting circuit and the output of delay unit Delay, respectively. The output of NAND gate NAND2 is connected to the input S of RS flip-flop. The input of delay unit Delay is connected to the gate of the output power transistor. The input of rising edge detector PG2 is connected to the body diode monitoring circuit. The output of rising edge detector PG2 is connected to the input R of RS flip-flop. The three inputs of NAND gate NAND3 are connected to the DCM mode judgment circuit, the output of rising edge detector PG1, and the output NQ of RS flip-flop, respectively. The output of NAND gate NAND3 is connected to the input of inverter INV4. The three inputs of NAND gate NAND4 are connected to the DCM mode judgment circuit, the output of rising edge detector PG1, and the output Q of RS flip-flop, respectively. The output of NAND gate NAND4 is connected to transistor M26. With gate connection, the sources of transistors M26, M25, M24, and M30, one end of capacitor C3, and the negative terminal of current source IB4 are all grounded to GND. The drain of transistor M26 is connected to the gate of transistor M24, the drain of transistor M24, the gate of transistor M25, and the negative terminal of current source IB5. The positive terminal of current source IB5, the source of transistor M27, the source of transistor M28, and the source of transistor M29 are all connected to the power supply VDD. The drain of transistor M25 is connected to the crystal... The drain of transistor M28, the output of the sample-and-hold circuit SH, the drain of transistor M30, the other end of capacitor C3, and the adjustment signal output circuit are connected. The gate of transistor M27 is connected to the drain of transistor M27, the gate of transistor M28, the drain of transistor M29, and the positive terminal of current source IB4. The gate of transistor M29 is connected to the output of inverter INV4. The gate of transistor M30 is connected to the output of rising edge detector PG3. The input of rising edge detector PG3 is connected to the DCM mode determination circuit. The bias current provided by current sources IB4 and IB5 is 10μA each.

[0064] Furthermore, embodiments of the present invention include, for example... Figure 6 As shown, the adjustment signal output circuit includes transistors M31 to M34, current source IB6, comparator COMP2, capacitor C4, NAND gate NAND5, and inverter INV5; wherein,

[0065] The source of transistor M31, one end of capacitor C4, and the negative terminal of current source IB6 are all grounded to GND. The gate of transistor M31 is connected to the gate of transistor M32 and the output of NAND gate NAND5. The drain of transistor M31 is connected to the drain of transistor M32, the inverting input of comparator COMP2, and the other end of capacitor C4. The source of transistor M32 is connected to the drain of transistor M33. The sources of transistors M33 and M34 are both connected to power supply VDD. The gate of transistor M33 is connected to the gate of transistor M34, the drain of transistor M34, and the positive terminal of current source IB6. The positive input of comparator COMP2 is connected to the output of sample-and-hold circuit SH. The two inputs of NAND gate NAND5 are connected to the DCM mode determination circuit and the output of inverter INV5, respectively. The input of inverter INV5 is connected to the gate of output power transistor. The bias current provided by current source IB6 is 10μA.

[0066] The principle of the adaptive precise zero-crossing adjustment circuit proposed in this invention will be explained below:

[0067] Firstly, assuming the specific circuit of a single-inductor dual-output DC / DC switching power supply is as follows: Figure 7 As shown, Figure 7 Chinese V DR3 for Figure 1 The drive control signal DR, and V DR3 The connected power transistor is the output power transistor. The drain of the output power transistor is connected to the inductor L, and the source of the output power transistor serves as the output terminal of the single-inductor dual-output DC / DC switching power supply. In this power supply, when the current in inductor L flows in the reverse direction, at the start of the next charging cycle, the current in inductor L is less than 0, causing the voltage V to... X Below voltage V OP Therefore, the DCM mode determination circuit compares the voltage V at the falling edge of the drive control signal DR. X With voltage V OP The state at the start of the charging cycle is used to simply determine whether the adaptive precise zero-crossing adjustment circuit has entered DCM mode. When the initial DCM mode entry signal MODE is 0, it means that DCM mode has not been entered. At this time, only the DCM mode judgment circuit is working. When DCM mode is entered, the comparator COMP1 flips, and the DCM mode entry signal flips to 1, indicating that DCM mode has been entered.

[0068] After entering DCM mode, the counting circuit starts working, counting the rising edges of the drive control signal DR. COUNT is the signal output by the counting circuit. If the preset count is set to 25, the counting control signal COUNT is set to 1 when the number of rising edges reaches 25. When COUNT = 0, the preset circuit composed of transistors M20, M21, M22, M23, capacitor C2, and sample-and-hold circuit SH works. This circuit module is used to record the time when the discharge output power transistor is turned on after entering DCM mode. Transistor M22 charges capacitor C2 with current source IB3 to record the discharge time of the inductor current of inductor L. At this time, the discharge time is determined by the output of the adjustment circuit. Since COUNT is 0, other modules in the adjustment circuit do not work, so that the discharge time is converted into a voltage value V1. This voltage value V1 is then transmitted to capacitor C3 through the sample-and-hold circuit SH to determine the initial value of capacitor C3, i.e., V2, to preset the adjustment circuit in the adaptive zero-crossing adjustment circuit, i.e., to give an initial ramp voltage. The determination of the initial ramp voltage can reduce the gap between the initial point of the adaptive zero-crossing circuit and the precise zero-crossing point, thereby accelerating the search for the precise zero-crossing point.

[0069] Afterwards, the formal adjustment work begins. The specific adjustment process is as follows: As shown in Table 1, when the DCM mode entry signal MODE is 1 and the counting control signal COUNT output by the counting circuit is 1, the preset circuit is disconnected, and the remaining parts of the adjustment circuit, namely the reference signal adjustment circuit and the adjustment signal output circuit, begin to work. At the moment the output power transistor is turned off, an adjustment time is generated by the rising edge detector PG1. During the adjustment time, the drive control signal DR is 1. Since the body diode monitoring circuit is working in real time, it monitors the degree of turn-on of the output power transistor after it is turned off. If the output power transistor is turned off too late, the inductor current of inductor L will reverse, and the voltage V will decrease. X Below voltage V OP This indicates that the body diode of the output power transistor is almost not turned on, therefore the body diode monitoring circuit outputs OUT = 0. At this time, the input S of the RS flip-flop is active, so the output Q of the RS flip-flop is 1 and NQ is 0. Figure 6 When the gate voltage V4 of transistor M29 is 0 and the gate voltage V5 of transistor M26 is 0, transistor M25 discharges through transistor M24 via current source IB5 to capacitor C3, thus reducing the discharge time of the inductor current in the next cycle. Conversely, if the output power transistor turns off too early, the inductor current in inductor L will continue to flow in the forward direction, resulting in a higher voltage V after the output power transistor turns off. XA sudden change occurs, causing the body diode monitoring circuit to output OUT=1. At this time, the rising edge detector PG1 is valid for rising edge detection, so the input terminal R of the RS flip-flop is valid. Then the output terminal Q of the RS flip-flop is 0 and NQ=1. Consequently, the gate voltage V4 of transistor M29 is 1 and the gate voltage V5 of transistor M26 is 1. At this time, transistor M28 charges capacitor C3 through transistor M29 using current source IB4, which is used to extend the discharge time of the inductor current in the next cycle. By monitoring the turn-on status of the body diode of the output power transistor in real time and continuously adjusting the discharge time of the inductor current of inductor L, a relatively stable voltage value V2, i.e., the target ramp voltage, is eventually reached. The target ramp voltage is dynamically generated according to the actual situation. Then, transistor M33 charges capacitor C4 through transistor M22 using current source IB6, causing the voltage value V3 to continuously increase from 0V. The voltage values ​​V3 and V2 are continuously compared by comparator COMP2. When the voltage value V3 reaches the voltage value V2, comparator COMP2 flips and outputs the adjustment time required from 0V to the voltage value V2. This adjustment time is used as the control time of the gate drive control signal DR of the output power transistor, realizing accurate zero-crossing detection of the output power transistor.

[0070] Table 1 shows the output of each signal during the adjustment process.

[0071] MODE COUNT DR OUT V4 V5 0 0 or 1 0 or 1 0 or 1 0 1 1 0 0 or 1 0 or 1 0 1 1 1 0 0 or 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1

[0072] Figure 8 The adjustment results are given. Figure 8 The horizontal axis represents the adjustment time, the left vertical axis represents the change in inductor current of inductor L, and the right vertical axis represents the change in voltage V2. Figure 8 It can be seen that the zero-crossing adjustment circuit proposed in this invention stops working at 2.33ms after 25 statistical cycles, and provides an initial ramp voltage, which is adjusted between 2.33ms and 2.425ms, achieving a stable output after 2.425ms. Among these, Figure 8 The green line represents Figure 6 The graph shows the voltage change of V2, with the pink line representing the waveform of the inductor current change of inductor L.

[0073] In summary, the adaptive precise zero-crossing adjustment circuit proposed in this invention solves the problems of traditional zero-crossing comparators, such as being affected by process deviations, low accuracy, and high power consumption. Through a more rationally designed circuit structure, it achieves precise zero-crossing detection. Specifically, in DCM mode, this invention uses a body diode monitoring circuit to monitor the on-state of the output power transistor in real time to generate a logic control signal. An adjustment circuit then adjusts the inductor's charging and discharging time based on the logic pulse signal, achieving precise zero-crossing detection and reducing reverse inductor current flow. Compared to a zero-crossing comparator, this invention generates an initial ramp voltage in the adjustment circuit, adjusting from this initial ramp voltage to reach the target ramp voltage. In discontinuous current mode, this avoids the problem of the initial zero-crossing point being too far from the precise zero-crossing point, enabling faster locking of the precise zero-crossing point and improving the locking speed. It also avoids the power consumption caused by continuous adjustments due to inaccurate zero-crossing, significantly improving the efficiency of the switching power supply in DCM mode. This invention can be used in Boost-like topologies, offering a wider range of applications.

[0074] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0075] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0076] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An adaptive precise zero-crossing adjustment circuit, characterized in that, This method is applied to the zero-crossing detection of the output power transistor in a single-inductor dual-output DC / DC switching power supply. The drain of the output power transistor is connected to an inductor, the gate of the output power transistor is connected to the input terminal of the drive control signal DR, and the source of the output power transistor serves as the output terminal of the single-inductor dual-output DC / DC switching power supply. The zero-crossing adjustment circuit includes: The DCM mode determination circuit, connected to the gate, source, and drain of the output power transistor, is used, under the control of the drive control signal DR, to determine the mode based on the voltage V at the connection node between the drain and the inductor of the output power transistor. X And the output voltage V of a single-inductor dual-output DC / DC switching power supply OP Determine and output the DCM mode entry signal; A body diode monitoring circuit, connected to the source and drain of the output power transistor, is used to monitor the voltage V. X and the output voltage V OP Real-time monitoring of sudden voltage changes at connection nodes, comparison of the sudden voltage change with a reference voltage, and output of logic pulse signals based on the comparison result; A counting circuit, connected to the gate of the output power transistor and the DCM mode determination circuit, is used to count the rising edges of the drive control signal DR under the control of the DCM mode entry signal. If the number of rising edges reaches a preset number, a counting control signal is generated. The counting circuit has a built-in rising edge detector for detecting the rising edge of the drive control signal DR. The adjustment circuit includes: a preset position circuit connected to the gate of the output power transistor and the counting circuit, used to generate an initial ramp voltage under the control of the drive control signal DR and the counting control signal; a reference signal adjustment circuit connected to the gate of the output power transistor, the preset position circuit, the counting circuit, the body diode monitoring circuit and the DCM mode judgment circuit, used to adjust the initial ramp voltage to a target ramp voltage under the control of the counting control signal, the logic pulse signal and the DCM mode entry signal; and an adjustment signal output circuit connected to the reference signal adjustment circuit, the DCM mode judgment circuit and the gate of the output power transistor, used to calculate the adjustment time required to adjust from 0V to the target ramp voltage under the control of the DCM mode entry signal and the drive control signal DR, so as to use the adjustment time as the control time of the drive control signal DR of the gate of the output power transistor to realize the adjustment of the zero crossing point of the output power transistor.

2. The adaptive precise zero-crossing adjustment circuit according to claim 1, characterized in that, The DCM mode determination circuit includes a comparator COMP1 and a flip-flop DFF; wherein... The positive input terminal of comparator COMP1 is connected to the drain of the output power transistor, the negative input terminal of comparator COMP1 is connected to the source of the output power transistor, the output terminal of comparator COMP1 is connected to the input terminal D of flip-flop DFF, the clock terminal CLK of flip-flop DFF is connected to the gate of the output power transistor, and the output terminal Q of flip-flop DFF serves as the output terminal of the DCM mode determination circuit.

3. The adaptive precise zero-crossing adjustment circuit according to claim 1, characterized in that, The body diode monitoring circuit includes crystal M1 to transistor M13, Schmitt trigger, inverters INV1 to INV3, current source IB1, current source IB2, and capacitor C1; wherein... The drain of transistor M1 is connected to the gate of transistor M1, the gate of transistor M2, the gate of transistor M7, and the negative terminal of current source IB1. The sources of transistors M1, M2, M7, M10, and M14, and the negative terminal of current source IB2 are all grounded to GND. The drain of transistor M2 is connected to the source of transistor M3. The gate of transistor M3 is connected to the drain of transistor M3, the gate of transistor M4, the drain of transistor M4, the drain of transistor M6, the gate of transistor M8, and the drain of the output power transistor. The source of transistor M4 is connected to the drain and gate of transistor M5. The source of transistor M5 is connected to the gate of transistor M6, the source of transistor M9, the source of transistor M12, and the source of transistor M13. The positive terminal of current source IB1 is connected to the source of the output power transistor. The source of transistor M6 is connected to the drain of transistor M8, the drain of transistor M9, the gate of transistor M9, and one end of capacitor C1. The drain of transistor M7 is connected to the source of transistor M8. The gate of transistor M10 is connected to the drain of transistor M10 and the source of transistor M11. The gate of transistor M11 is connected to the drain of transistor M11, the drain of transistor M12, the other end of capacitor C1, and the input of Schmitt trigger. The gate of transistor M12 is connected to the gate of transistor M13, the drain of transistor M13, and the positive terminal of current source IB2. The output of Schmitt trigger is connected sequentially to inverters INV1 to INV3. The output of inverter INV3 serves as the output of the body diode monitoring circuit.

4. The adaptive precise zero-crossing adjustment circuit according to claim 3, characterized in that, The Schmitt trigger includes transistors M14 to M19; wherein... The gate of transistor M14 is connected to the gates of transistors M15, M16, M17, and M11. The sources of transistors M14 and M19 are grounded to GND. The drain of transistor M14 is connected to the sources of transistors M15 and M18. The drain of transistor M15 is connected to the drain of transistor M16, the gate of transistor M18, the gate of transistor M19, and the input of inverter INV1. The source of transistor M16 is connected to the drain of transistors M17 and M19. The source of transistor M17 and the drain of transistor M18 are both connected to the power supply VDD.

5. The adaptive precise zero-crossing adjustment circuit according to claim 1, characterized in that, The preset bit circuit includes transistors M20 to M23, current source IB3, sample-and-hold circuit SH, capacitor C2, and OR gate; wherein... The sources of transistors M20 and M21 are both connected to power supply VDD. The gate of transistor M20 is connected to the gate of transistor M21, the drain of transistor M20, and the positive terminal of current source IB3. The drain of transistor M21 is connected to the source of transistor M22. The gate of transistor M22 is connected to the output terminal of OR gate and the gate of transistor M23. The drain of transistor M22 is connected to the drain of transistor M23, one end of capacitor C2, and the data input terminal of sample-and-hold circuit SH. The clock input terminal of sample-and-hold circuit SH is connected to the gate of the output power transistor. The output terminal of sample-and-hold circuit SH is connected to the reference signal adjustment circuit. The source of transistor M23, one end of capacitor C2, and the negative terminal of current source IB3 are all grounded to GND. The two input terminals of OR gate are connected to the gate of the output power transistor and the counting circuit, respectively.

6. The adaptive precise zero-crossing adjustment circuit according to claim 5, characterized in that, The reference signal adjustment circuit includes NAND gates NAND1 to NAND4, rising edge detectors PG1 to PG3, a delay unit Delay, an RS flip-flop, an inverter INV4, transistors M24 to M30, current source IB4, current source IB5, and capacitor C3; wherein... The two inputs of NAND gate NAND1 are connected to the counting circuit and the gate of the output power transistor, respectively. The output of NAND gate NAND1 is connected to the input of rising edge detector PG1. The two inputs of NAND gate NAND2 are connected to the counting circuit and the output of delay unit Delay, respectively. The output of NAND gate NAND2 is connected to the input S of RS flip-flop. The input of delay unit Delay is connected to the gate of the output power transistor. The input of rising edge detector PG2 is connected to the body diode monitoring circuit. The output of rising edge detector PG2 is connected to the input R of RS flip-flop. The three inputs of NAND gate NAND3 are connected to the DCM mode determination circuit, the output of rising edge detector PG1, and the output NQ of RS flip-flop, respectively. The output of NAND gate NAND3 is connected to the input of inverter INV4. The three inputs of NAND gate NAND4 are connected to the DCM mode determination circuit, the output of rising edge detector PG1, and the output Q of RS flip-flop, respectively. The output of NAND gate NAND4 is connected to the crystal. The gate of transistor M26 is connected to the ground. The sources of transistors M26, M25, M24, and M30, one end of capacitor C3, and the negative terminal of current source IB4 are all grounded to GND. The drain of transistor M26 is connected to the gate of transistor M24, the drain of transistor M24, the gate of transistor M25, and the negative terminal of current source IB5. The positive terminal of current source IB5, the source of transistor M27, M28, and M29 are all connected to the power supply VDD. The drain of transistor M25 is connected to the gate of transistor M26. The drain of transistor M28, the output of the sample-and-hold circuit SH, the drain of transistor M30, the other end of capacitor C3, and the adjustment signal output circuit are connected. The gate of transistor M27 is connected to the drain of transistor M27, the gate of transistor M28, the drain of transistor M29, and the positive terminal of current source IB4. The gate of transistor M29 is connected to the output of inverter INV4. The gate of transistor M30 is connected to the output of rising edge detector PG3. The input of rising edge detector PG3 is connected to the DCM mode determination circuit.

7. The adaptive precise zero-crossing adjustment circuit according to claim 5, characterized in that, The adjustment signal output circuit includes transistors M31 to M34, a current source IB6, a comparator COMP2, a capacitor C4, a NAND gate NAND5, and an inverter INV5; wherein... The source of transistor M31, one end of capacitor C4, and the negative terminal of current source IB6 are all grounded to GND. The gate of transistor M31 is connected to the gate of transistor M32 and the output of NAND gate NAND5. The drain of transistor M31 is connected to the drain of transistor M32, the inverting input of comparator COMP2, and the other end of capacitor C4. The source of transistor M32 is connected to the drain of transistor M33. The sources of transistors M33 and M34 are both connected to power supply VDD. The gate of transistor M33 is connected to the gate of transistor M34, the drain of transistor M34, and the positive terminal of current source IB6. The positive input of comparator COMP2 is connected to the output of sample-and-hold circuit SH. The two inputs of NAND gate NAND5 are connected to the DCM mode determination circuit and the output of inverter INV5, respectively. The input of inverter INV5 is connected to the gate of the output power transistor.

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