Chip testing method and chip testing device

Abstract

The application discloses a chip testing method and a chip testing device, and relates to the technical field of chip testing, in particular to a chip testing method and a chip testing device. The chip testing method comprises the following steps: obtaining a first testing instruction from an upper computer; reading interface information of a plurality of connected test card seats according to the first testing instruction to obtain a test card seat list; receiving a first configuration parameter sent by any test card seat in the plurality of test card seats; determining a first target test card seat sending the first configuration parameter according to the first configuration parameter, the first target test card seat being any test card seat in the test card seat list, and the first target test card seat loading a first target chip to be tested; loading a first driver program in the first target test card seat to test the first target chip to obtain a test result corresponding to the first target chip. Therefore, the corresponding driver program can be flexibly loaded for testing according to the configuration parameter sent by the different test card seats, so that the compatibility of function testing on various different models of storage chips is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory testing, in particular to a chip testing method and a chip testing device. BACKGROUND

[0002] NAND Flash is widely used in embedded systems as a storage device due to its large capacity and low price. Among them, SPI Nand, as a type of NAND Flash storage chip, is a NAND flash technology based on SPI (Serial Peripheral Interface) bus. It combines the high-density storage of NAND flash with the low-pin count and simple control of SPI bus, providing an efficient and low-power storage solution.

[0003] However, at present, there are many SPI NAND manufacturers and product models, and there are great differences in quality, so when functional testing is performed on the many product models of SPI NAND, specific MCUs (Micro Control Units) or FPGAs (Field Programmable Gate Arrays) corresponding to different product models are often needed to perform functional testing to improve the qualified rate of SPI NAND chips leaving the factory. This results in low compatibility of the functional testing of SPI NAND by the testing equipment. SUMMARY

[0004] The present application provides a chip testing method and a chip testing device, aiming to solve the problem of low compatibility of functional testing of SPI NAND by testing equipment.

[0005] In order to achieve the above-mentioned purpose, the present application adopts a chip testing method and a chip testing device to improve the compatibility of functional testing of SPI NAND.

[0006] In a first aspect, the present application provides a chip testing method, comprising:

[0007] obtaining a first test instruction from a host computer;

[0008] reading interface information of a plurality of test card holders connected according to the first test instruction to obtain a test card holder list;

[0009] receiving a first configuration parameter sent by any test card holder in the plurality of test card holders;

[0010] determining a first target test card holder sending the first configuration parameter according to the first configuration parameter, the first target test card holder being any test card holder in the test card holder list, and the first target test card holder loading a first target chip to be tested;

[0011] loading a first driver program in the first target test socket to test the first target chip to obtain a test result corresponding to the first target chip.

[0012] In some embodiments, the first configuration parameter includes a chip identifier, a chip name, a chip storage capacity, a chip page size, a chip block size, a number of chip planes, a chip strap region size, and a register parameter related to chip configuration of the chip type of the first target chip.

[0013] In some embodiments, the first target test socket is determined according to the first configuration parameter, including:

[0014] According to the first configuration parameter, the configuration parameters of a plurality of test sockets in the test socket list are matched to obtain a first target test socket consistent with the information in the first configuration parameter.

[0015] In some embodiments, the first target test socket is determined according to the first configuration parameter, including:

[0016] Obtaining a second test instruction from the target test socket;

[0017] In response to the second test instruction, loading a first driver program in the first target test socket;

[0018] Based on the first driver program, testing the first target chip to obtain a test result corresponding to the first target chip.

[0019] In some embodiments, the first target chip is tested to obtain a test result corresponding to the first target chip, including:

[0020] Writing test data into the first target chip;

[0021] Reading the test data written in the first target chip to obtain reading data;

[0022] Comparing and verifying the test data and the reading data to obtain a verification result;

[0023] According to the verification result, determining a test result corresponding to the first target chip.

[0024] In some embodiments, the first target chip includes a plurality of storage blocks, and each storage block includes a plurality of storage pages.

[0025] The comparison and verification of the test data and the read data obtains a verification result, including:

[0026] According to the test data and the read data corresponding to the target storage page, a verification result corresponding to the target storage page is obtained, the target storage page being any storage page in the plurality of storage pages;

[0027] A verification result corresponding to each storage page in the plurality of storage blocks is determined;

[0028] The verification result corresponding to the first target chip is determined according to the verification result, including:

[0029] According to the verification result corresponding to each storage page in the plurality of storage blocks, the first target chip is analyzed to obtain a verification result corresponding to the first target chip.

[0030] In some embodiments, after the step of loading the first driver in the first target test socket to test the first target chip to obtain a test result corresponding to the first target chip, the chip testing method further includes:

[0031] A second configuration parameter is received, the second configuration parameter being a configuration parameter received after the first configuration parameter;

[0032] According to the second configuration parameter, a second target test socket corresponding thereto is determined, the second target test socket having a second target chip to be tested loaded therein;

[0033] In a case where the second target test socket exists in the test socket list and is different from the first target test socket, a second driver in the second target test socket is loaded to test the second target chip to obtain a test result corresponding to the second target chip.

[0034] In some embodiments, after the step of loading the first driver in the first target test socket to test the first target chip to obtain a test result corresponding to the first target chip, the chip testing method further includes:

[0035] In a case where the second target test socket does not exist in the test socket list, a calculation parameter in the first driver is modified according to the second configuration parameter to generate a third driver corresponding thereto;

[0036] The third driver is written into a corresponding storage module;

[0037] A second target chip in the second target test socket is tested based on the third driver to obtain a test result corresponding to the second target chip.

[0038] In a second aspect, the present application further provides a chip testing device, which comprises a power supply, a plurality of test card seats and a main controller. The power supply is used to supply power for the chip testing device. The plurality of test card seats are connected with the main controller of the chip testing device. The main controller comprises a memory and a processor. The memory stores a computer program. The processor executes the computer program to realize the steps of the chip testing method.

[0039] In some embodiments, the plurality of test card seats are in communication with the main controller. The main controller is in communication with a host computer. Each of the plurality of test card seats is used to load a storage chip of a different chip type for chip testing of the loaded storage chip of the different chip type. The main controller is an MT7968 chip.

[0040] In the embodiments of the present application, the main controller of the chip testing device can obtain a first test instruction from the host computer. According to the first test instruction, interface information of the plurality of connected test card seats is read to obtain a test card seat list. A first configuration parameter sent by any test card seat of the plurality of test card seats is received. According to the first configuration parameter, a first target test card seat sending the first configuration parameter is determined. The first target test card seat is any test card seat in the test card seat list. The first target test card seat loads a first target chip to be tested. A first driver program in the first target test card seat is loaded to test the first target chip to obtain a test result corresponding to the first target chip.

[0041] The technical scheme of the present application has the following beneficial effects. First, the plurality of test card seats can be connected with a plurality of different types of chips to be tested at the same time, greatly improving the parallel processing capability of the test. Then, the test card seat list is obtained by reading the interface information of the plurality of connected test card seats, which can comprehensively understand the resources available for testing. Next, the first configuration parameter sent by any test card seat of the plurality of test card seats is received. According to these parameters, the first target test card seat sending the parameters can be accurately determined, even in the plurality of card seats. Finally, the first driver program in the first target test card seat is loaded to test the first target chip to obtain the test result. In this way, instead of relying on a specific MCU or FPGA corresponding to a specific product model, the corresponding driver program can be flexibly loaded for testing according to the configuration parameters sent by different test card seats, thereby effectively improving the compatibility of the functional test of various different types of SPI NAND chips. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description only some of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0043] Figure 1 is a structural schematic diagram of an interactive system provided by an embodiment of the present application;

[0044] Figure 2 is a flowchart of a chip testing method disclosed by an embodiment of the present application;

[0045] Figure 3 is another flowchart of a chip testing method disclosed by an embodiment of the present application.

[0046] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0048] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications will also change accordingly.

[0049] It should also be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there can be a middle element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or there can be a middle element.

[0050] In addition, the descriptions involving "first", "second" and the like in the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of the ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0052] In order to enable those skilled in the art to better understand the scheme of the present application, the application environment of the scheme of the present application is described first. The chip testing method provided by the present application can be applied to the system architecture as shown in Figure 1 .

[0053] Please refer to Figure 1 , Figure 1 is a system architecture schematic diagram of the test system 100 provided by the embodiments of the present application. As shown in Figure 1 , the test system 100 can include a power supply 110, a plurality of test card seats 120 and a main controller 130. The power supply 110 can be connected to the plurality of test card seats 120 and the main controller 130, and each test card seat in the plurality of test card seats 120 is in communication connection with the main controller 130.

[0054] Among them, the power supply 110 provides necessary power supply for the whole system, ensures that each component can work normally.

[0055] The plurality of test card seats 120 can be respectively the card seats for testing a plurality of different types of chips, for example, the plurality of test card seats 120 can include: Emmc chip seat, SPI-NAND chip seat and SPI Nor chip seat.

[0056] The Emmmc chip socket connects to the Emmmc chip, establishing a physical connection and signal transmission between the chip and the system. This allows the system to perform read / write operations or other related controls on the Emmmc chip, enabling corresponding test procedures. The SPI-NAND chip socket connects to the SPI-NAND chip, providing an interface for the chip to communicate with the system, perform data storage or retrieval functions, and enable corresponding test procedures. The SPI Nor chip socket connects to the SPI Nor chip, enabling communication between the chip and the system, supporting system operations on the SPI Nor chip, and enabling corresponding test procedures.

[0057] The main controller 130, as the core controller of the system, is responsible for controlling and managing the entire hardware system, coordinating the work of various parts, and realizing functions such as data processing and transmission. This main controller 130 can be a main controller based on the MT7986 chip series.

[0058] The aforementioned test system 100 is an example of a chip testing method disclosed in this application. It is provided to better explain the various steps of the chip testing method in this application and does not limit this application.

[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0060] This invention proposes a chip testing method.

[0061] Please see Figure 2 , Figure 2 This is a schematic flowchart of a chip testing method disclosed in an embodiment of this application. The chip testing method can be applied to the main controller of a chip testing device. Figure 2 As shown, the chip testing method may include the following steps.

[0062] Step 201: Obtain the first test command from the host computer.

[0063] The first test instruction can be a test instruction sent by the host computer according to a preset test procedure or user operation. This first test instruction can be used to start the main controller of the chip device to execute chip testing methods. For example, the first test instruction can be an instruction to perform read / write tests or functional verification on a specific chip.

[0064] The upper computer can be a computer or other device with control and sending instruction capability, which can realize interaction with the user and communication and data connection with the main controller.

[0065] It should be noted that the main controller of the chip testing device waits and receives the first test instruction sent by the upper computer after establishing connection with the upper computer. This instruction is the key signal to start the test process, and the test system will execute corresponding test operations according to the content of the instruction. It emphasizes the communication and cooperation relationship between the test system and the upper computer. The upper computer is responsible for sending instructions to control the test, and the test system is responsible for executing instructions and completing corresponding test tasks.

[0066] Step 202, according to the first test instruction, reading the interface information of the plurality of test sockets connected, obtaining a test socket list.

[0067] Among them, the test socket list includes a plurality of test sockets connected to the main controller of the chip testing device, and the plurality of test sockets includes a plurality of card devices for testing connected to the main controller at the same time, which can accommodate different types of chips to be tested. The test socket list is a list containing all the information of the test socket list after reading the plurality of test sockets connected. The interface information of the plurality of test sockets can include the number, position, connection state and other information of the socket.

[0068] It should be noted that after the main controller of the chip testing device receives the first test instruction, it can detect and read information of all test sockets connected to the main controller according to the requirements of the instruction. Through this process, the main controller can determine which test sockets are in the connected state, and arrange the related information of these sockets into a list form. This test socket list is very important for subsequent test operations, which can help the system accurately select and control the test sockets that need to be tested, and ensure the accuracy and efficiency of the test.

[0069] Step 203, receiving the first configuration parameter sent by any test socket in the plurality of test sockets.

[0070] Among them, the first configuration parameter refers to the parameter information used to describe the related settings of the socket or the chip loaded therein, and the first configuration parameter is sent from any test socket in the plurality of test sockets.

[0071] The first configuration parameter can include at least one of a chip identifier, a chip name, a chip storage capacity, a chip page size, a chip block size, a number of chip planes, a chip strap area size, and a register parameter related to the chip configuration corresponding to the first target chip tested by the corresponding chip socket.

[0072] It should be noted that each test socket in the above test socket list has corresponding configuration parameters corresponding to the chip model that can be tested, and the configuration parameters corresponding to each test socket are different. In actual application, the first configuration parameter plays a crucial role. It is sent from any one of the plurality of test sockets, and is used to describe the relevant settings of the socket or the chip loaded therein in detail.

[0073] For example, the chip identifier can be a unique code for accurately identifying a specific model of chip, such as "IC001"; the chip name can explicitly indicate the specific type of chip, such as "high-speed storage chip"; the chip storage capacity can be "64GB", indicating the amount of data that the chip can store; the chip page size can be "4KB", affecting the way data is read and written; the chip block size, such as "128KB", is related to the organization and management of storage; the number of chip planes, for example, "4", determines the structure and performance of the chip; the size of the chip's external band region, such as "32KB", is used to store some additional information; and the register parameters related to the chip configuration can include read / write speed, operating voltage, etc., such as a read / write speed of "50MB / s" and an operating voltage of "1.8V".

[0074] It should be noted that each test socket in the test socket list has unique configuration parameters corresponding to the chip model that can be tested, and these configuration parameters are different. This means that each test socket can send specific first configuration parameters according to the type of chip loaded therein, to ensure that the test system can accurately identify and handle the testing needs of different chips. For example, one test socket may correspond to a chip with a specific storage capacity and page size, while another test socket may correspond to a chip of a different specification, and the first configuration parameters sent by them will be different according to the differences in the chips, so that the test system can accurately match and test various chips.

[0075] After the main controller determines the test socket list corresponding to the plurality of test sockets currently connected, it can determine that the controller is in a receiving state, waiting for and obtaining the first configuration parameters sent from any one of the plurality of test sockets, to perform chip testing on the target chip in the any one test socket. This means that no matter which test socket sends the configuration parameters, the system can receive and process them in a timely manner. This design allows the system to flexibly adapt to the needs of different test sockets, effectively supporting various testing situations. By receiving these configuration parameters, the system can perform appropriate testing preparation and operation according to the specific situation, ensuring the accuracy and reliability of the test.

[0076] Step 204, determining the first target test socket that sent the first configuration parameter according to the first configuration parameter.

[0077] The first target test socket is any test socket in the test socket list, and the first target test socket is loaded with the first target chip to be tested.

[0078] The first target test socket refers to a test socket determined according to the received first configuration parameter. The first target test socket is a test socket in the test socket list whose configuration parameter is consistent with the first configuration parameter.

[0079] The first target chip refers to a chip to be tested loaded in the first target test socket. The chip is the object of the test.

[0080] It should be noted that the system determines the specific test socket sending the first configuration parameter through analysis of the first configuration parameter. The socket is the first target test socket. The socket is selected from the previously obtained test socket list, and the first target chip to be tested is loaded in the socket. Such a design enables the system to accurately locate the specific socket and chip to be tested, thereby enabling the system to perform subsequent test operations in a targeted manner, improving the efficiency and accuracy of the test.

[0081] Step 205, loading the first driver in the first target test socket to test the first target chip to obtain the test result corresponding to the first target chip.

[0082] The first driver refers to a driver corresponding to the chip type of the first target chip in the first target test socket. The driver enables the test system to effectively communicate and interact with the chip, thereby enabling the test operation on the chip.

[0083] The test result refers to the test information obtained after testing the first target chip. The information can reflect whether the performance and function of the chip meet the expected standard.

[0084] It should be noted that after determining that the test socket corresponding to the received first configuration parameter is the first target test socket, the microcontroller can load the first driver in the first target test socket that matches the first target chip, and perform specific test operations on the first target chip through the driver. During the test, the system collects and analyzes relevant data to ultimately obtain the test result corresponding to the first target chip. The test result can provide an important basis for judging the quality and performance of the chip, so as to facilitate further processing and decision-making.

[0085] In Figure 2In the described method embodiment, the main controller of the chip testing device can achieve the function of connecting multiple different models of chips to be tested at the same time by setting multiple test card seats, greatly improving the parallel processing capability of the test. Secondly, the main controller of the chip testing device can obtain the first test instruction from the host computer, read the interface information of the multiple connected test card seats according to the instruction, and then obtain the test card seat list to comprehensively understand the resources available for testing. Next, the main controller receives the first configuration parameter sent by any test card seat in the multiple test card seats, and accurately judges the first target test card seat according to the parameters, so as to realize accurate positioning even in the case of multiple card seats. Finally, the main controller loads the first driver program in the first target test card to test the first target chip, thereby obtaining the test result. Through the above technical means, the application achieves significant technical effects. On the one hand, it is no longer dependent on specific MCUs or FPGAs corresponding to specific product models, and can flexibly load the corresponding driver program for testing according to the configuration parameters sent by different test card seats, effectively improving the compatibility of functional testing of various different models of SPI NAND chips. On the other hand, it greatly improves the efficiency of the test, saves time and cost, and at the same time ensures the accuracy and reliability of the test. In summary, the technical scheme of the application has important practical application value and significance.

[0086] Please refer to Figure 3 , Figure 3 is another flowchart of a chip testing method disclosed by the embodiments of the application. The chip testing method can be applied to a microcontroller of a chip testing device. As shown in Figure 3 , the chip testing method can include the following steps.

[0087] Step 301, obtaining a first test instruction from a host computer.

[0088] Step 302, according to the first test instruction, reading the interface information of the multiple connected test card seats to obtain a test card seat list.

[0089] Step 303, receiving a first configuration parameter sent by any test card seat in the multiple test card seats.

[0090] The specific content of steps 301 to 303 can also refer to the description of steps 201 to 203, which will not be repeated here.

[0091] Step 304, according to the matching of the first configuration parameter and the configuration parameters corresponding to the multiple test card seats in the test card seat list, obtaining a first target test card seat matching the information in the first configuration parameter.

[0092] The test socket list contains a plurality of test sockets, each of which has corresponding configuration parameters set according to the chip model that can be tested by the test socket, and the configuration parameters are different from each other.

[0093] After receiving the first configuration parameters, the system compares them with the configuration parameters of each test socket in the test socket list one by one. For example, the system checks whether the chip identifier is consistent, whether the chip name is consistent, whether the chip storage capacity, page size, block size, plane number, external tape area size, and register parameters match, and so on.

[0094] In the matching process, only when all the information in the first configuration parameters is completely consistent with the configuration parameters of a test socket, the test socket is determined as the first target test socket.

[0095] Through this accurate matching process, the system can accurately find the test socket corresponding to the first configuration parameters, so as to ensure that the subsequent test can be performed on the correct chip, and improve the accuracy and efficiency of the test.

[0096] Step 305, obtaining the second test instruction from the first target test socket.

[0097] The second test instruction is a test instruction from the first target test socket, and the second test instruction is used for the test socket to send a test signal to the microcontroller.

[0098] After the microcontroller determines the first target test socket, the microcontroller can be in a standby state, waiting for the second test instruction of the first target test socket. The microcontroller can obtain the second test instruction from the first target test socket.

[0099] Specifically, the first target test socket is loaded with a chip to be tested, and it sends a second test instruction to the microcontroller to inform the microcontroller that the chip in the socket needs to be tested or corresponding operation is performed. After receiving the instruction, the microcontroller will control the test process or interact with the chip according to the requirements of the instruction. This communication mechanism enables the microcontroller to accurately understand the requirements of the first target test socket and perform corresponding operations, thereby realizing effective testing of the chip.

[0100] Step 306, loading the first driver corresponding to the first target test socket in response to the second test instruction.

[0101] The first driver is a driver that matches the chip type of the chip to be tested in the target test socket, and the first driver is a test program for testing the first target chip in the first target test socket.

[0102] It should be noted that after the microcontroller receives the second test instruction from the target test socket, the first driver corresponding to the target test socket can be loaded according to the requirements of the second test instruction. This process is to ensure that the microcontroller can correctly control and test the chip in the target test socket. By loading the appropriate driver, the microcontroller can effectively communicate with the chip and perform the test operations specified in the instruction to obtain accurate test results.

[0103] Step 307, test the first target chip based on the first driver to obtain the test result corresponding to the first target chip.

[0104] Among them, the first driver is a program specially designed for the first target chip, which can enable the test system to effectively interact and control the chip, thereby realizing various test operations on the chip.

[0105] It should be noted that the microcontroller can use the first driver to perform specific tests on the first target chip. During the test process, the first driver will communicate and operate with the first target chip according to the predetermined test process, such as reading and writing tests, function verification, etc. Through these test operations, the system will collect various data and information about the first target chip, and then obtain the test result corresponding to the chip according to these data and information. This test result can reflect the performance of the first target chip in various indicators, and the test result is obtained, so as to judge whether the chip meets the relevant standards and requirements according to the test result.

[0106] Step 308, receive the second configuration parameter.

[0107] The second configuration parameter is a configuration parameter received after the first configuration parameter.

[0108] The second configuration parameter includes the chip identifier, chip name, chip storage capacity, chip page size, chip block size, number of chip planes, chip external tape area size, and register parameters related to the chip configuration of the chip type corresponding to the second target chip.

[0109] After completing the test on the first target chip in the first target test socket, the microcontroller can also receive the second configuration parameter from any one of the plurality of test sockets in the test socket list.

[0110] Step 309, determine the corresponding second target test socket according to the second configuration parameter.

[0111] The second target test socket is loaded with a second target chip to be tested.

[0112] The step 308 and the step 309 can be considered as steps consistent with the step 303 and the step 304. After the test on any test socket of the plurality of test sockets is completed, the microcontroller of the chip testing device can receive the second configuration parameter from any test socket of the plurality of test sockets again to test the second target chip in the second target test socket.

[0113] The step 310 is to load the second driver in the second target test socket to test the second target chip and obtain the test result corresponding to the second target chip when the second target test socket exists in the test socket list and is different from the first target test socket.

[0114] After the second target test socket is determined, it can be judged whether the second target test socket exists in the test socket list. If the second target test socket exists in the plurality of test sockets in the test socket list, it can be determined that the corresponding driver has been stored in the storage module to test the chip of the type. If it is judged that the second target test socket is different from the first target test socket, it can be determined that the chip to be tested this time is different from the chip to be tested last time. When the chip types to be tested before and after are different, the second driver stored in the storage module is directly called to test the second target chip in the second target test socket.

[0115] The step 311 is to modify the calculation parameter in the first driver according to the second configuration parameter to generate a corresponding third driver when the second target test socket does not exist in the test socket list.

[0116] When it is judged whether the second target test socket exists in the test socket list, if the second target test socket does not exist in the plurality of test sockets in the test socket list, it can be determined that the second target test socket is a chip type that has not been tested in the previous test process. In this case, the standard driver needs to be modularly modified and compiled according to the second configuration parameter corresponding to the second target test socket to generate a third driver corresponding to the second configuration parameter.

[0117] The step 312 is to write the third driver into the corresponding storage module.

[0118] After the third driver is generated, the third driver can be written into the corresponding storage module to store the test program in the third driver.

[0119] The step 313 is to test the second target chip in the second target test socket based on the third driver to obtain the test result corresponding to the second target chip.

[0120] After the third driving program is written into the corresponding storage module for storage, when the third driving program is called, the test program in the third driving program is used to perform chip testing on the chip type corresponding to the second configuration parameter.

[0121] In Figure 3 In the method embodiment described, the main controller of the chip testing device can achieve the function of simultaneously connecting multiple different models of chips to be tested by setting multiple test card seats, greatly improving the parallel processing capability of the test. Secondly, the main controller of the chip testing device can obtain the first test instruction from the upper computer, read the interface information of the multiple test card seats connected according to the instruction, and then obtain the test card seat list to comprehensively understand the resources available for testing. Next, the main controller receives the first configuration parameter sent by any test card seat in the multiple test card seats, and accurately judges the first target test card seat sending the parameter according to these parameters, so as to realize accurate positioning even in the case of multiple card seats. Finally, the main controller loads the first driving program in the first target test card to test the first target chip, thereby obtaining the test result. Through the above technical means, the present application achieves significant technical effects. On the one hand, it is no longer dependent on specific MCUs or FPGAs corresponding to specific product models, and can flexibly load the corresponding driving program for testing according to the configuration parameters sent by different test card seats, effectively improving the compatibility of functional testing of various different models of SPI NAND chips. On the other hand, it greatly improves the efficiency of testing, saves time and cost, and at the same time ensures the accuracy and reliability of the test. In summary, the technical solution of the present application has important practical application value and significance.

[0122] It should be understood that the same or corresponding information in different embodiments described above can be referred to each other.

[0123] It should be understood that, although Figure 2 , Figure 3 The steps in the flowchart of the method are displayed in sequence according to the direction of the arrows, but these steps are not necessarily executed in sequence according to the direction of the arrows. Unless otherwise stated herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other order. Moreover, Figure 2 and Figure 3 At least part of the steps in and can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0124] The above description is only a specific implementation of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present application.

Claims

1. A method of testing a chip, characterized by, The chip testing method comprises the following steps: obtaining a first test instruction from a host computer; reading interface information of a plurality of test sockets connected according to the first test instruction to obtain a test socket list; receiving a first configuration parameter sent by any test socket in the plurality of test sockets; determining a first target test socket sending the first configuration parameter according to the first configuration parameter, the first target test socket being any test socket in the test socket list, and the first target test socket loading a first target chip to be tested; loading a first driver in the first target test socket to test the first target chip to obtain a test result corresponding to the first target chip; wherein the first configuration parameter comprises a chip identifier, a chip name, a chip storage capacity, a chip page size, a chip block size, a number of chip planes, a chip external tape area size, and a register parameter related to chip configuration of the chip type corresponding to the first target chip; determining the first target test socket sending the first configuration parameter according to the first configuration parameter comprises: matching the configuration parameters corresponding to the plurality of test sockets in the test socket list according to the first configuration parameter to obtain a first target test socket matching the information in the first configuration parameter; loading a first driver in the first target test socket to test the first target chip to obtain a test result corresponding to the first target chip comprises: obtaining a second test instruction from the first target test socket; loading the first driver in the first target test socket in response to the second test instruction; testing the first target chip based on the first driver to obtain a test result corresponding to the first target chip; wherein the test socket list contains a plurality of test sockets, and each test socket has corresponding configuration parameters; after the step of loading the first driver in the first target test socket to test the first target chip to obtain a test result corresponding to the first target chip, the chip testing method further comprises: receiving a second configuration parameter, the second configuration parameter being a configuration parameter received after the first configuration parameter; determining a corresponding second target test socket according to the second configuration parameter, the second target test socket loading a second target chip to be tested; in the case that the second target test socket exists in the test socket list and is different from the first target test socket, loading a second driver in the second target test socket to test the second target chip to obtain a test result corresponding to the second target chip; after the step of loading the first driver in the first target test socket to test the first target chip to obtain a test result corresponding to the first target chip, the chip testing method further comprises: In a case where the second target test socket does not exist in the test socket list, a calculation parameter in the first driver is modified according to the second configuration parameter, and a third driver corresponding to the modification is generated; The third driver is written into a corresponding storage module; A second target chip in the second target test socket is tested based on the third driver, and a test result corresponding to the second target chip is obtained; The second configuration parameter includes a chip identifier, a chip name, a chip storage capacity, a chip page size, a chip block size, a number of chip planes, a chip external tape area size, and a register parameter related to chip configuration of the chip type corresponding to the second target chip.

2. The chip testing method according to claim 1, wherein The testing of the first target chip and the obtaining of the test result corresponding to the first target chip include: Test data is written into the first target chip; Read data is obtained by reading the test data written into the first target chip; The test data and the read data are compared and verified to obtain a verification result; The test result corresponding to the first target chip is determined according to the verification result.

3. The chip testing method according to claim 2, wherein The first target chip includes a plurality of storage blocks, and each storage block includes a plurality of storage pages. The comparison and verification of the test data and the read data to obtain the verification result include: A target storage page is any one of the plurality of storage pages, and a verification result corresponding to the target storage page is obtained by comparing and verifying the test data and the read data corresponding to the target storage page; Verification results corresponding to each storage page in the plurality of storage blocks are determined; The determination of the test result corresponding to the first target chip according to the verification result includes: The first target chip is analyzed according to the verification result corresponding to each storage page in the plurality of storage blocks to obtain a verification result corresponding to the first target chip.

4. A chip testing apparatus characterized by comprising: It includes: A power supply for supplying power to the chip testing device; A plurality of test sockets connected to a main controller of the chip testing device; A main controller including a memory and a processor, the memory storing a computer program, and the processor implementing the steps of the chip testing method of any one of claims 1 to 3 when executing the computer program.

5. The chip testing apparatus according to claim 4, wherein The plurality of test sockets communicate with the main controller, and the main controller communicates with a host computer; Each test socket in the plurality of test sockets is used to load a storage chip of a different chip type for chip testing of the loaded storage chip of the different chip type; The main controller is an MT7968 chip.

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