A TBC solar cell with doped material, preparation method and equipment

Abstract

The present invention discloses a TBC solar cell with doped materials, a preparation method and equipment, comprising the following steps: S1: placing a silicon wafer to be processed in an SDE tank for SDE treatment, and using a KOH treatment solution; S2: using PECVD (plasma enhanced chemical vapor deposition) to in-situ dope the back of the silicon wafer obtained in S1 to prepare a tunneling layer and a boron-doped polysilicon layer; S3: using a picosecond laser to process the back of the silicon wafer obtained in S2 to form a first laser ablation zone; S4: placing the silicon wafer obtained in S3 in an RCA tank for RCA cleaning; S5: using PECVD to in-situ dope the first laser ablation zone of the silicon wafer obtained in S4 to prepare a tunneling layer and an arsenic-doped polysilicon layer. The present invention solves the problem of low cell efficiency caused by poor passivation uniformity of phosphorus-doped polysilicon in TBC cells by in-situ doping of arsenic-doped polysilicon layers on silicon wafers, and the cell efficiency can be improved by up to 0.5%.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell manufacturing, and in particular to a TBC solar cell with doped materials, a preparation method and equipment. Background Art

[0002] With the photovoltaic industry's growing demand for cost-effectiveness, the research and development and mass production of high-efficiency batteries are imperative. Among them, TBC back-contact batteries have no electrode grid line obstruction on the front, high conversion efficiency and beautiful component appearance. They can be used in many application scenarios such as BIPV (building integrated photovoltaics) and CIPV (in-vehicle integrated photovoltaics), and have great development potential and broad market prospects.

[0003] The current mainstream TBC battery uses phosphorus-doped polysilicon as the doping material, such as the N-type TBC solar cell and its preparation method disclosed in patent CN116387409A on July 4, 2023, and the TBC battery preparation method and TBC battery disclosed in patent CN116741877A on September 12, 2023. However, phosphorus-doped polysilicon has two disadvantages as the doping of n-type silicon wafers. The first is that phosphorus-doped polysilicon has poor uniformity, which leads to uneven contact cell resistance of metal and semiconductor MIS (metal oxide semiconductor) structure, excessive local contact resistance, resulting in efficiency dispersion, which greatly reduces the efficiency of actual industrial production; the second is that phosphorus-doped polysilicon is easily affected by the annealing temperature and produces local inward expansion. After the inward expansion of phosphorus-doped polysilicon, passivation failure is caused, Voc is reduced, and battery efficiency is reduced. In order to control the local inward expansion, the temperature control accuracy of the annealing furnace tube is required to be very strict. Therefore, a TBC solar cell with doped materials, a preparation method and an apparatus are urgently needed to solve the above problems. Summary of the invention

[0004] The object of the present invention is to provide a TBC solar cell with doped materials, a preparation method and an apparatus to solve the above-mentioned deficiencies in the prior art.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A method for preparing a TBC solar cell with a doped material, characterized by comprising the following steps:

[0007] S1: Place the silicon wafer to be processed into the SDE tank for SDE treatment, and use KOH treatment solution;

[0008] S2: The back side of the silicon wafer obtained in S1 is in-situ doped by PECVD (plasma enhanced chemical vapor deposition) to prepare a tunneling layer and a boron-doped polysilicon layer;

[0009] S3: treating the back side of the silicon wafer obtained in S2 with a picosecond laser to form a first laser ablation area;

[0010] S4: placing the silicon wafer obtained in S3 into an RCA tank for RCA cleaning;

[0011] S5: using PECVD to in-situ dope the first laser ablation area of ​​the silicon wafer obtained in S4 to prepare a tunneling layer and an arsenic-doped polysilicon layer;

[0012] S6: performing annealing treatment on the back side of the silicon wafer obtained in S5;

[0013] S7: treating the back side of the silicon wafer obtained in S6 with a picosecond laser to form a second laser ablation area;

[0014] S8: placing the silicon wafer obtained in S7 into a texturing tank for texturing cleaning, and using a KOH treatment solution;

[0015] S9: performing ALD (atomic layer deposition) coating on the back side of the silicon wafer obtained in S8 to form a passivation layer;

[0016] S10: The front and back sides of the silicon wafer obtained in S9 are subjected to MOCVD (metal organic chemical vapor deposition) vacuum evaporation to prepare a MgF2 anti-reflection layer and a SiNx / ZnS anti-reflection layer;

[0017] S11: Prepare a positive electrode and a negative electrode on the back side of the silicon wafer obtained in S10.

[0018] Furthermore, B2H6 or BF3, SiH4, H2, and N2O are used as reaction gases in S2, the flow rate of B2H6 is 200-1000sccm, the flow rate of SiH4 is 100-1000sccm, the flow rate of N2O is 500-3000sccm, the in-situ doping temperature is 300-700°C, the square resistance of boron doping is 50-150ohm / sq, and the thickness of the boron-doped polysilicon layer is 80-200nm.

[0019] Furthermore, the picosecond laser wavelength used in S3 is 532nm, the laser repetition frequency is 500KHz-2000KHz, the spot width is 20-80um, and the laser energy is 5-30W; the picosecond laser wavelength used in S7 is 355nm, the laser repetition frequency is 1000KHz-2000KHz, the spot width is 30-150um, and the laser energy is 5-20W.

[0020] Furthermore, AsH3, SiH4, H2, and N2O are used as reaction gases in S5, the flow rate of AsH3 is 100-800sccm, the flow rate of SiH4 is 100-900sccm, the flow rate of N2O is 500-1000sccm, the in-situ doping temperature is 300-600°C, the square resistance of arsenic doping is 100-200ohm / sq, and the thickness of the arsenic-doped polysilicon layer is 80-200nm.

[0021] Furthermore, in S6, N2 and H2 mixed gases are used for annealing, and the annealing temperature is 650-1050°C.

[0022] Furthermore, the material of the passivation layer in S9 is one or more of AlOx, GaOx, and InOx, and the thickness of the passivation layer is 20-100 nm.

[0023] Furthermore, the overall thickness of the MgF2 anti-reflection layer and the SiNx / ZnS anti-reflection layer in S10 is 20-100 nm.

[0024] A TBC solar cell of doped materials is manufactured based on the above-mentioned preparation method, comprising a silicon wafer, wherein the front side of the silicon wafer is provided with a MgF2 anti-reflection layer and a SiNx / ZnS anti-reflection layer, and the back side of the silicon wafer is provided with a first composite dielectric layer and a second composite dielectric layer alternately adjacent to each other, wherein the first composite dielectric layer comprises a tunneling layer and a boron-doped polysilicon layer, and the second composite dielectric layer comprises a tunneling layer and an arsenic-doped polysilicon layer, and the outsides of the first composite dielectric layer and the second composite dielectric layer are provided with a passivation layer, a MgF2 anti-reflection layer and a SiNx / ZnS anti-reflection layer in sequence from the inside to the outside, and the first composite dielectric layer and the second composite dielectric layer are connected to a positive electrode and a negative electrode, respectively.

[0025] A device, based on the above-mentioned preparation method, is used to prepare MgF2 anti-reflection layers and SiNx / ZnS anti-reflection layers on the front and back surfaces of the silicon wafer obtained in S9, comprising a processing table, a transition frame is movably arranged on the processing table, two relatively arranged flaps are hinged on the transition frame, the flaps have a first state of horizontal expansion and a second state of upward vertical closure, a driving component for driving the transition frame to move is arranged in the processing table, a linkage component is arranged between the transition frame and the flap, during the switching process at both ends of the transition frame's moving stroke, the linkage component links the flap to switch from the first state to the second state, and then switches back to the first state, and the switched two flaps correspond to the center positions of the processing table respectively.

[0026] Furthermore, the linkage assembly includes a slide rail provided at the end of the transition frame, a linkage rod is provided in the slide rail and can be raised and lowered, a sliding pin is provided on the side wall of the flap, a sliding groove matching the sliding pin is provided on the linkage rod, a rocker arm is hinged on the processing table, and the free end of the rocker arm is hinged to the linkage rod.

[0027] In the above technical solution, the beneficial effects of the present invention are:

[0028] The method for preparing TBC solar cells with doped materials solves the problem of low cell efficiency caused by poor passivation uniformity of phosphorus-doped polysilicon in TBC cells by in-situ doping of arsenic-doped polysilicon layers on silicon wafers, and the cell efficiency can be improved by more than 0.5; and MgF2 and SiNx / ZnS multilayer anti-reflection layers are deposited on the front and back sides of the silicon wafers by MOCVD to improve the QE (quantum efficiency) response of the cell, improve the light absorption efficiency of the cell, and improve the cell conversion efficiency.

[0029] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

[0030] This application document provides an overview of various implementations or examples of the technology described in the present disclosure, and is not a comprehensive disclosure of the entire scope or all features of the disclosed technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0032] Figure 1 A schematic diagram of the structure of a solar cell provided by an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the structure of the device provided by an embodiment of the present invention in the first state of the flip plate;

[0034] Figure 3 A schematic diagram of the structure of the equipment base and the sealing cover provided in an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the structure of a drive assembly of a device provided in an embodiment of the present invention;

[0036] Figure 5 A schematic diagram of the structure of the device provided by an embodiment of the present invention in the second state of the flip plate;

[0037] Figure 6 The embodiment of the present invention provides Figure 5 A schematic diagram of the enlarged structure at A in the middle;

[0038] Figure 7 A schematic diagram of the structure of the device provided by an embodiment of the present invention during the flap switching state;

[0039] Figure 8 The embodiment of the present invention provides Figure 7 Schematic diagram of the enlarged structure at point B in the middle.

[0040] Description of reference numerals:

[0041] 1. Silicon wafer; 2. Tunneling layer; 3. Boron-doped polysilicon layer; 4. Passivation layer; 5. MgF2 anti-reflection layer; 6. SiNx / ZnS anti-reflection layer; 7. Arsenic-doped polysilicon layer; 8. Positive electrode; 9. Negative electrode; 10. Processing table; 11. Transition frame; 12. Flip plate; 13. Slide rail; 14. Link rod; 15. Sliding pin; 16. Sliding groove; 17. Rocker rod; 18. Base; 19. Sealing cover; 20. Pipeline integrator; 21. Motor; 22. Drive rod; 23. Drive sleeve; 24. Spiral groove; 25. Sliding cam. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Example 1

[0044] A method for preparing a TBC solar cell with a doped material, comprising the following steps:

[0045] S1: Place the silicon wafer 1 to be processed into the SDE tank for SDE treatment to remove the damage on the surface of the silicon wafer 1, reduce the weight by 0.1-0.8g, and control the reflectivity at 45%; the SDE growth method adopts KOH treatment solution; the resistivity of the silicon wafer 1 is 1-5Ω·cm, and the thickness is 130μm;

[0046] S2: The back side of the silicon wafer 1 obtained in S1 is in-situ doped by PECVD (plasma enhanced chemical vapor deposition) to prepare a tunneling layer 2 and a boron-doped polysilicon layer 3; B2H6 or BF3, SiH4, H2, N2O are used as reaction gases, the flow rate of B2H6 is 200-1000sccm, the flow rate of SiH4 is 100-1000sccm, the flow rate of N2O is 500-3000sccm, the in-situ doping temperature is 300-700°C, the boron-doped square resistance is 50-150ohm / sq, and the thickness of the boron-doped polysilicon layer 3 is 80-200nm;

[0047] S3: The silicon wafer 1 obtained in S2 is subjected to back surface treatment using a picosecond laser to form a first laser ablation zone; the picosecond laser wavelength is 532nm, the laser repetition frequency is 500KHz-2000KHz, the spot width is 20-80um, and the laser energy is 5-30W;

[0048] S4: placing the silicon wafer 1 obtained in S3 into an RCA tank for RCA cleaning; removing the tunneling layer 2 and the boron-doped polysilicon layer 3 plated on the front side of the silicon wafer 1;

[0049] S5: in-situ doping the first laser ablation area of ​​the silicon wafer 1 obtained in S4 by PECVD to prepare a tunneling layer 2 and an arsenic-doped polysilicon layer 7; AsH3, SiH4, H2, and N2O are used as reaction gases, the flow rate of AsH3 is 100-800sccm, the flow rate of SiH4 is 100-900sccm, the flow rate of N2O is 500-1000sccm, the in-situ doping temperature is 300-600°C, the square resistance of arsenic doping is 105ohm / sq, and the thickness of the arsenic-doped polysilicon layer 7 is 80-200nm;

[0050] S6: annealing the back side of the silicon wafer 1 obtained in S5; using a mixed gas of N2 and H2 for annealing at a temperature of 650-1050° C.;

[0051] S7: The back of the silicon wafer 1 obtained in S6 is processed by a picosecond laser to form a second laser ablation zone; the second laser ablation zone mainly acts on the boron doped area and the GAP area on the back of the silicon wafer 1; the picosecond laser wavelength is 355nm, the laser repetition frequency is 1000KHz-2000KHz, the spot width is 30-150um, and the laser energy is 5-20W;

[0052] S8: placing the silicon wafer 1 obtained in S7 into a texturing tank for texturing cleaning, and using a KOH treatment solution as a texturing growth method; performing de-coating and texturing treatment on the front side of the silicon wafer 1, and removing BSG and PSG on the back side, reducing the weight by 0.1-0.8g, and controlling the reflectivity at 3-9%;

[0053] S9: ALD (atomic layer deposition) is performed on the back of the silicon wafer 1 obtained in S8 to form a passivation layer 4; the material of the passivation layer 4 is one or more of AlOx, GaOx, and InOx, and the thickness of the passivation layer 4 is 20-100 nm;

[0054] S10: The front and back sides of the silicon wafer 1 obtained in S9 are subjected to MOCVD (metal organic chemical vapor deposition) vacuum evaporation to prepare a MgF2 anti-reflection layer 5 and a SiNx / ZnS anti-reflection layer 6; the overall thickness of the MgF2 anti-reflection layer 5 and the SiNx / ZnS anti-reflection layer 6 is 20-100 nm;

[0055] S11: prepare a positive electrode 8 and a negative electrode 9 on the back side of the silicon wafer 1 obtained in S10; the electrode preparation method is preferably printing metal electrodes, laser transfer or electroplating.

[0056] Example 2

[0057] A method for preparing a TBC solar cell with a doped material, comprising the following steps:

[0058] S1: Place the silicon wafer 1 to be processed into the SDE tank for SDE treatment to remove the damage on the surface of the silicon wafer 1, reduce the weight by 0.1-0.8g, and control the reflectivity at 45%; the SDE growth method adopts KOH treatment solution; the resistivity of the silicon wafer 1 is 1-5Ω·cm, and the thickness is 130μm;

[0059] S2: The back side of the silicon wafer 1 obtained in S1 is in-situ doped by PECVD to prepare a tunneling layer 2 and a boron-doped polysilicon layer 3; B2H6 or BF3, SiH4, H2, N2O are used as reaction gases, the flow rate of B2H6 is 200-1000sccm, the flow rate of SiH4 is 100-1000sccm, the flow rate of N2O is 500-3000sccm, the in-situ doping temperature is 300-700°C, the boron-doped sheet resistance is 50-150ohm / sq, and the thickness of the boron-doped polysilicon layer 3 is 80-200nm;

[0060] S3: The silicon wafer 1 obtained in S2 is subjected to back surface treatment using a picosecond laser to form a first laser ablation zone; the picosecond laser wavelength is 532nm, the laser repetition frequency is 500KHz-2000KHz, the spot width is 20-80um, and the laser energy is 5-30W;

[0061] S4: placing the silicon wafer 1 obtained in S3 into an RCA tank for RCA cleaning; removing the tunneling layer 2 and the boron-doped polysilicon layer 3 plated on the front side of the silicon wafer 1;

[0062] S5: in-situ doping the first laser ablation area of ​​the silicon wafer 1 obtained in S4 by PECVD to prepare a tunneling layer 2 and an arsenic-doped polysilicon layer 7; AsH3, SiH4, H2, and N2O are used as reaction gases, the flow rate of AsH3 is 100-800sccm, the flow rate of SiH4 is 100-900sccm, the flow rate of N2O is 500-1000sccm, the in-situ doping temperature is 300-600°C, the square resistance of arsenic doping is 150ohm / sq, and the thickness of the arsenic-doped polysilicon layer 7 is 80-200nm;

[0063] S6: performing annealing on the back side of the silicon wafer 1 obtained in S5; using a mixed gas of N2 and H2 for annealing at a temperature of 650-1050° C.;

[0064] S7: The back of the silicon wafer 1 obtained in S6 is processed by a picosecond laser to form a second laser ablation zone; the second laser ablation zone mainly acts on the boron doped area and the GAP area on the back of the silicon wafer 1; the picosecond laser wavelength is 355nm, the laser repetition frequency is 1000KHz-2000KHz, the spot width is 30-150um, and the laser energy is 5-20W;

[0065] S8: placing the silicon wafer 1 obtained in S7 into a texturing tank for texturing cleaning, and using a KOH treatment solution as a texturing growth method; performing de-coating and texturing treatment on the front side of the silicon wafer 1, and removing BSG and PSG on the back side, reducing the weight by 0.1-0.8g, and controlling the reflectivity at 3-9%;

[0066] S9: ALD coating is performed on the back of the silicon wafer 1 obtained in S8 to form a passivation layer 4; the material of the passivation layer 4 is one or more of AlOx, GaOx, and InOx, and the thickness of the passivation layer 4 is 20-100 nm;

[0067] S10: The front and back sides of the silicon wafer 1 obtained in S9 are subjected to MOCVD vacuum evaporation to prepare a MgF2 anti-reflection layer 5 and a SiNx / ZnS anti-reflection layer 6; the overall thickness of the MgF2 anti-reflection layer 5 and the SiNx / ZnS anti-reflection layer 6 is 20-100 nm;

[0068] S11: prepare a positive electrode 8 and a negative electrode 9 on the back side of the silicon wafer 1 obtained in S10; the electrode preparation method is preferably printing metal electrodes, laser transfer or electroplating.

[0069] Example 3

[0070] A method for preparing a TBC solar cell with a doped material, comprising the following steps:

[0071] S1: Place the silicon wafer 1 to be processed into the SDE tank for SDE treatment to remove the damage on the surface of the silicon wafer 1, reduce the weight by 0.1-0.8g, and control the reflectivity at 45%; the SDE growth method adopts KOH treatment solution; the resistivity of the silicon wafer 1 is 1-5Ω·cm, and the thickness is 130μm;

[0072] S2: The back side of the silicon wafer 1 obtained in S1 is in-situ doped by PECVD to prepare a tunneling layer 2 and a boron-doped polysilicon layer 3; B2H6 or BF3, SiH4, H2, N2O are used as reaction gases, the flow rate of B2H6 is 200-1000sccm, the flow rate of SiH4 is 100-1000sccm, the flow rate of N2O is 500-3000sccm, the in-situ doping temperature is 300-700°C, the boron-doped sheet resistance is 50-150ohm / sq, and the thickness of the boron-doped polysilicon layer 3 is 80-200nm;

[0073] S3: The silicon wafer 1 obtained in S2 is subjected to back surface treatment using a picosecond laser to form a first laser ablation zone; the picosecond laser wavelength is 532nm, the laser repetition frequency is 500KHz-2000KHz, the spot width is 20-80um, and the laser energy is 5-30W;

[0074] S4: placing the silicon wafer 1 obtained in S3 into an RCA tank for RCA cleaning; removing the tunneling layer 2 and the boron-doped polysilicon layer 3 plated on the front side of the silicon wafer 1;

[0075] S5: in-situ doping the first laser ablation area of ​​the silicon wafer 1 obtained in S4 by PECVD to prepare a tunneling layer 2 and an arsenic-doped polysilicon layer 7; AsH3, SiH4, H2, and N2O are used as reaction gases, the flow rate of AsH3 is 100-800sccm, the flow rate of SiH4 is 100-900sccm, the flow rate of N2O is 500-1000sccm, the in-situ doping temperature is 300-600°C, the sheet resistance of arsenic doping is 195ohm / sq, and the thickness of the arsenic-doped polysilicon layer 7 is 80-200nm;

[0076] S6: performing annealing on the back side of the silicon wafer 1 obtained in S5; using a mixed gas of N2 and H2 for annealing at a temperature of 650-1050° C.;

[0077] S7: The back of the silicon wafer 1 obtained in S6 is processed by a picosecond laser to form a second laser ablation zone; the second laser ablation zone mainly acts on the boron doped area and the GAP area on the back of the silicon wafer 1; the picosecond laser wavelength is 355nm, the laser repetition frequency is 1000KHz-2000KHz, the spot width is 30-150um, and the laser energy is 5-20W;

[0078] S8: placing the silicon wafer 1 obtained in S7 into a texturing tank for texturing cleaning, and using a KOH treatment solution as a texturing growth method; performing de-coating and texturing treatment on the front side of the silicon wafer 1, and removing BSG and PSG on the back side, reducing the weight by 0.1-0.8g, and controlling the reflectivity at 3-9%;

[0079] S9: ALD coating is performed on the back of the silicon wafer 1 obtained in S8 to form a passivation layer 4; the material of the passivation layer 4 is one or more of AlOx, GaOx, and InOx, and the thickness of the passivation layer 4 is 20-100 nm;

[0080] S10: The front and back sides of the silicon wafer 1 obtained in S9 are subjected to MOCVD vacuum evaporation to prepare a MgF2 anti-reflection layer 5 and a SiNx / ZnS anti-reflection layer 6; the overall thickness of the MgF2 anti-reflection layer 5 and the SiNx / ZnS anti-reflection layer 6 is 20-100 nm;

[0081] S11: prepare a positive electrode 8 and a negative electrode 9 on the back side of the silicon wafer 1 obtained in S10; the electrode preparation method is preferably printing metal electrodes, laser transfer or electroplating.

[0082] Embodiment 1, embodiment 2 and embodiment 3 are mainly optimized and improved on the difference in arsenic doping square resistance. The control group is a TBC battery with conventional doping materials; the arsenic doping square resistance of embodiment 1 is: 105ohm / sq; the arsenic doping square resistance of embodiment 2 is: 150ohm / sq; the arsenic doping square resistance of embodiment 3 is: 195ohm / sq; the silicon wafer 1 obtained in the above embodiments is finally subjected to IV test to test the IV battery performance, appearance and EL parameters of the battery.

[0083] Table 1 shows the IV test results of silicon wafer 1 obtained after treatment of the control group and Examples 1, 2, and 3.

[0084] category Eta Uoc Isc FF IRev2 R R count Control group 26.63 0.7320 13.9495 86.10 0.067 0.00092 3644 215 Implementation Group 1 27.03 0.7343 14.0218 86.68 0.069 0.00088 3786 245 Implementation Group 2 27.15 0.7372 14.0395 86.59 0.072 0.00091 3594 246 Implementation Group 3 26.95 0.7379 14.0368 85.89 0.068 0.00096 3679 247

[0085] Compared with the control group, the battery efficiency of Examples 1, 2, and 3 of the present invention is improved, and the battery efficiency of Example 2 is improved most significantly, up to 0.5%; this is due to the difference in the diffusion coefficient of arsenic in silicon and the diffusion coefficient of phosphorus in silicon. The diffusion distribution uniformity of arsenic-doped polysilicon is better than that of phosphorus-doped, and the degree of internal expansion is much smaller than that of phosphorus-doped polysilicon.

[0086] In addition, the mainstream TBC battery passivation material uses AlOx / SiNx / SiONx as the passivation material, such as the N-type TBC solar cell and its preparation method disclosed in patent CN116387409A, the TBC battery preparation method and TBC battery disclosed in CN116741877A, or the TBC battery preparation method disclosed in CN116845140A. The MgF2 and SiNx / ZnS multilayer anti-reflection layer provided by the present invention has a higher QE (quantum efficiency) response than the AlOx / SiNx / SiONx film layer, more absorption rate in the visible light band, higher Jsc current density, and higher efficiency.

[0087] A TBC solar cell with doped materials, reference Figure 1 , which is manufactured based on the above-mentioned preparation method, includes a silicon wafer 1, a MgF2 anti-reflection layer 5 and a SiNx / ZnS anti-reflection layer 6 are arranged on the front side of the silicon wafer 1, and a first composite dielectric layer and a second composite dielectric layer are arranged alternately adjacent to each other on the back side of the silicon wafer 1, the first composite dielectric layer includes a tunneling layer 2 and a boron-doped polysilicon layer 3, the second composite dielectric layer includes a tunneling layer 2 and an arsenic-doped polysilicon layer 7, and a passivation layer 4, a MgF2 anti-reflection layer 5 and a SiNx / ZnS anti-reflection layer 6 are arranged on the outside of the first composite dielectric layer and the second composite dielectric layer in sequence from the inside to the outside, and the first composite dielectric layer and the second composite dielectric layer are respectively connected to a positive electrode 8 and a negative electrode 9.

[0088] Specifically, the front side of the silicon wafer 1 is processed by S7 to present a pyramid structure, and the MgF2 anti-reflection layer 5 and the SiNx / ZnS anti-reflection layer 6 formed on the surface thereof are of corresponding structures, which can reduce the reflection of surface light and increase the absorption of light energy; the first composite dielectric layer is formed by S2 and S3, and after S3, the first composite dielectric layers are located between the first composite dielectric layers; the second composite dielectric layer is formed by S5 and S7, and after S7, the separated parts between the adjacent first composite dielectric layers and the second composite dielectric layers are located between the second laser ablation zones; the passivation layer 4, the MgF2 anti-reflection layer 5 and the SiNx / ZnS anti-reflection layer 6 cover the entire back side of the silicon wafer 1 layer by layer from the inside to the outside.

[0089] A device, reference Figure 2-8The invention is based on the above-mentioned preparation method and is used for preparing MgF2 anti-reflection layer 5 and SiNx / ZnS anti-reflection layer 6 on both sides of the silicon wafer 1 obtained in S9. The invention comprises a processing table 10, on which a transition frame 11 is movably arranged. Two relatively arranged flaps 12 are hingedly connected to the transition frame 11. The flaps 12 have a first state of horizontal expansion and a second state of upward vertical closure. A driving component for driving the transition frame 11 to move is arranged in the processing table 10. A linkage component is arranged between the transition frame 11 and the flaps 12. During the switching process at both ends of the moving stroke of the transition frame 11, the linkage component links the flaps 12 to switch from the first state to the second state and then switch back to the first state, and the two flaps 12 are switched to correspond to the center positions of the processing table 10 respectively.

[0090] Specifically, the equipment also includes a frame, a reaction chamber assembly and a lifting assembly. The reaction chamber assembly includes a base 18 and a sealing cover 19. The processing table 10 is fixedly arranged on the base 18. The sealing cover 19 is provided with a pipeline integrator 20. The pipeline integrator 20 is used to connect the pipeline for conveying the reaction gas. The base 18 is fixed on the frame of the equipment or on the table on the frame. The sealing cover 19 is controlled to rise and fall through the lifting assembly, thereby realizing the control of opening and closing of the entire reaction chamber assembly for taking and placing the silicon wafer 1. The above specific structure and principle are prior art and will not be repeated. The transition frame 11 is movable in contact with the upper surface of the processing table 10. The transition frame 11 is H-shaped, and the two opposite sides of its moving direction are respectively hinged with flaps 12, and the rotation axis of the flap 12 is parallel to the length direction of the transition frame 11; in the first state, the two flaps 12 are relatively unfolded to form a horizontal plane and are in contact with the upper surface of the processing table 10. At this time, one of the flaps 12 corresponds to the center position of the processing table 10, and the other flap 12 is close to the edge of the processing table 10; in the second state, the two flaps 12 are both vertically erected upward and parallel to each other. At this time, the transition frame 11 corresponds to the center position of the processing table 10. In addition, the spacing width between the two erected flaps 12 is not less than the thickness of the silicon wafer 1, and is similar to the thickness of the silicon wafer 1; the transition state of the two flaps 12 in the process of switching between the first state and the second state is V-shaped; the silicon wafer 1 to be processed is initially placed on the processing table 10, and is on the flap 12 in the first state corresponding to the center position of the processing table 10.In actual use of the present technical solution, the reaction chamber assembly is opened, and each flap 12 is in the first state. The silicon wafer 1 to be processed is accurately placed on the flap 12 corresponding to the center position of the processing table 10, the reaction chamber assembly is closed and sealed, and then MOCVD vacuum evaporation is started. The MgF2 anti-reflection layer 5 and the SiNx / ZnS anti-reflection layer 6 are prepared on the upward side of the silicon wafer 1. After a predetermined period of time, the driving assembly drives the transition frame 11 to move from one end of the moving stroke to the other end. Then, the two flaps 12 begin to switch from the first state to the second state under the action of the linkage assembly, so that the silicon wafer 1 is also driven to stand up, and when the transition frame 11 passes the center position of the processing table 10, the flap 12 reaches the vertical standing position, and the silicon wafer 1 can be attached to the other flap 12 due to the inertia generated by the flap 12, and flipped at this time. The plate 12 continues to switch from the second state to the first state, and the silicon wafer 1 is turned over and remains on the other flip plate 12, and the flip plate 12 is switched to the center position of the corresponding processing table 10 at this time, and then the MOCVD vacuum evaporation treatment of the other side of the silicon wafer 1 can continue. In the above process, the silicon wafer 1 remains in the center position of the corresponding processing table 10 to stabilize the processing quality. In addition, the automatic turning over operation of the silicon wafer 1 in the reaction chamber assembly is realized to avoid repeated opening and closing of the reaction chamber assembly, that is, to maintain the temperature in the reaction chamber assembly, reduce repeated heating operations, prevent leakage of gas reactants, and reduce exhaust gas treatment operations. Furthermore, during the entire process of double-sided processing of the silicon wafer 1, the concentration of the reactants in the reaction chamber assembly is maintained at an appropriate value, thereby balancing the processing quality of both sides of the silicon wafer 1 to be constant and avoiding quality differences in the processing layers on both sides.

[0091] Compared with the prior art, a device proposed in an embodiment of the present invention can be provided with a linkage component, and while the driving component drives the transition frame 11 to move its position, the two flaps 12 can be linked to move upward and then unfolded, so that the silicon wafer 1 on one side of the flap 12 can be turned over and transferred to the other flap 12. At the same time, under the movement of the transition frame 11, the flap 12 to be transferred can be switched to the center position of the corresponding processing table 10, thereby stabilizing the processing quality, avoiding repeated opening and closing of the reaction chamber component, preventing the leakage of gas reactants, and reducing exhaust gas treatment operations. Furthermore, during the entire process of double-sided processing of the silicon wafer 1, the concentration of the reactants in the reaction chamber component is maintained at an appropriate value, thereby balancing the processing quality of both sides of the silicon wafer 1 to be constant, and avoiding the problem of quality difference in the processing layers on both sides.

[0092] Furthermore, the driving assembly includes a motor 21 installed in the processing table 10, and the output end of the motor 21 is coaxially connected to a driving rod 22, and a driving sleeve 23 is connected to the driving rod 22 through a spiral transmission assembly. The driving sleeve 23 is fixedly connected to the transition frame 11 by sliding through a connecting portion on the upper surface of the processing table 10. Specifically, the spiral transmission assembly includes a spiral groove 24 set on the driving rod 22, and the pitch of the middle section of the spiral groove 24 is greater than the pitch setting at both ends. The inner wall of the driving sleeve 23 is provided with a sliding protrusion 25 that is slidably connected to the spiral groove 24. When the driving sleeve 23 passes through the middle section of the spiral groove 24, the corresponding transition frame 11 passes through the center position of the processing table 10, that is, the second state of the corresponding flap 12. In actual use of the present technical solution, the motor 21 drives the driving rod 22 to rotate, and the driving rod 22 drives the driving sleeve 23 to move through the transmission of the spiral groove 24 and the sliding protrusion 25, and the driving sleeve 23 drives the transition frame 11 to move, thereby realizing the switching of the transition frame 11 from one end of the moving stroke to the other end; further, when the transition frame 11 is close to the center position of the processing table 10, the two flaps 12 are in the second state, and the silicon wafer 1 is driven to stand up. At this time, the sliding protrusion 25 passes through a section where the pitch of the spiral groove 24 becomes larger, and the rotation speed of the driving rod 22 remains unchanged, thereby accelerating the movement of the driving sleeve 23, which also drives the transition frame 11 to accelerate its movement. Therefore, under this accelerated inertia, it is ensured that the silicon wafer 1 is attached to the target flap 12, thereby avoiding the problem of failure of the silicon wafer 1 to flip over.

[0093] As the preferred technical scheme of this embodiment, the linkage assembly includes a slide rail 13 provided at the end of the transition frame 11, a linkage rod 14 which can be raised and lowered is provided in the slide rail 13, a sliding pin 15 is provided on the side wall of the flap 12, a sliding groove 16 matching the sliding pin 15 is provided on the linkage rod 14, a rocker arm 17 is hinged on the processing table 10, and the free end of the rocker arm 17 is hinged to the linkage rod 14. Specifically, the slide rail 13 is vertically arranged and the linkage rod 14 is horizontally arranged; the lifting and lowering of the linkage rod 14 on the slide rail 13 drives the sliding pin 15 to lift and lower through the sliding groove 16, and then triggers the flap 12 to rotate, and the sliding pin 15 also slides relatively in the sliding groove 16; a hinge shaft which slides through the side wall of the slide rail 13 is provided at the middle position of the linkage rod 14, and one end of the rocker arm 17 is hinged to the hinge shaft; the hinge position of the rocker arm 17 and the processing table 10 corresponds to the middle position of the processing table 10. In actual use, when the transition frame 11 moves close to the center position of the processing table 10, one end of the swing rod 17 articulated linkage rod 14 is relatively close to the end of the processing table 10 articulated by the swing rod 17 in the horizontal direction, so the swing rod 17 is forced to drive the linkage rod 14 to rise, and the linkage rod 14 drives the two flaps 12 to switch from the first state to the second state through the sliding pin 15 and the sliding groove 16; when the transition frame 11 moves to the center position of the processing table 10, the swing rod 17 is in an upright state, the linkage rod 14 rises to the highest point, and the two flaps 12 are correspondingly in the second state; when the transition frame 11 moves away from the center position of the processing table 10 again, the swing rod 17 drives the linkage rod 14 to descend, and the two flaps 12 begin to rotate and switch from the second state to the first state; finally, the transition frame 11 moves from one end of the moving stroke to the other end, and the two flaps 12 switch back to the first state.

[0094] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a TBC solar cell with a doped material, characterized in that: The following steps are involved: S1: placing the silicon wafer to be processed (1) into an SDE tank for SDE treatment, and using KOH treatment solution; S2: The back side of the silicon wafer (1) obtained in S1 is in-situ doped by PECVD to prepare a tunneling layer (2) and a boron-doped polysilicon layer (3); S3: treating the back side of the silicon wafer (1) obtained in S2 with a picosecond laser to form a first laser ablation zone; S4: placing the silicon wafer (1) obtained in S3 into an RCA tank for RCA cleaning; S5: using PECVD to in-situ dope the first laser ablation region of the silicon wafer (1) obtained in S4 to prepare a tunneling layer (2) and an arsenic-doped polysilicon layer (7); S6: performing annealing treatment on the back side of the silicon wafer (1) obtained in S5; S7: treating the back side of the silicon wafer (1) obtained in S6 with a picosecond laser to form a second laser ablation area; S8: placing the silicon wafer (1) obtained in S7 into a texturing tank for texturing cleaning, and using a KOH treatment solution; S9: performing ALD coating on the back side of the silicon wafer (1) obtained in S8 to form a passivation layer (4); S10: The front and back sides of the silicon wafer (1) obtained in S9 are subjected to MOCVD vacuum evaporation to prepare a MgF2 anti-reflection layer (5) and a SiNx / ZnS anti-reflection layer (6); S11: Prepare a positive electrode (8) and a negative electrode (9) on the back side of the silicon wafer (1) obtained in S10.

2. The method for preparing a TBC solar cell with a doped material according to claim 1, characterized in that: In S2, B2H6 or BF3, SiH4, H2, N2O are used as reaction gases, the flow rate of B2H6 is 200-1000sccm, the flow rate of SiH4 is 100-1000sccm, the flow rate of N2O is 500-3000sccm, the in-situ doping temperature is 300-700°C, the boron-doped square resistance is 50-150ohm / sq, and the thickness of the boron-doped polysilicon layer (3) is 80-200nm.

3. The method for preparing a TBC solar cell with a doped material according to claim 1, characterized in that: The picosecond laser wavelength used in S3 is 532nm, the laser repetition frequency is 500KHz-2000KHz, the spot width is 20-80um, and the laser energy is 5-30W; the picosecond laser wavelength used in S7 is 355nm, the laser repetition frequency is 1000KHz-2000KHz, the spot width is 30-150um, and the laser energy is 5-20W.

4. The method for preparing a TBC solar cell with a doped material according to claim 1, characterized in that: In S5, AsH3, SiH4, H2, and N2O are used as reaction gases, the flow rate of AsH3 is 100-800sccm, the flow rate of SiH4 is 100-900sccm, the flow rate of N2O is 500-1000sccm, the in-situ doping temperature is 300-600°C, the square resistance of arsenic doping is 100-200ohm / sq, and the thickness of the arsenic-doped polysilicon layer (7) is 80-200nm.

5. The method for preparing a TBC solar cell with a doped material according to claim 1, characterized in that: In S6, N2 and H2 mixed gas are used for annealing, and the annealing temperature is 650-1050°C.

6. The method for preparing a TBC solar cell with a doped material according to claim 1, characterized in that: The material of the passivation layer (4) in S9 is one or more of AlOx, GaOx, and InOx, and the thickness of the passivation layer (4) is 20-100 nm.

7. The method for preparing a TBC solar cell with a doped material according to claim 1, characterized in that: The overall thickness of the MgF2 anti-reflection layer (5) and the SiNx / ZnS anti-reflection layer (6) in S10 is 20-100 nm.

8. A TBC solar cell with doped materials, which is manufactured based on the preparation method according to any one of claims 1 to 7, characterized in that: The invention comprises a silicon wafer (1), wherein a MgF2 anti-reflection layer (5) and a SiNx / ZnS anti-reflection layer (6) are arranged on the front side of the silicon wafer (1), and a first composite dielectric layer and a second composite dielectric layer are arranged alternately adjacent to each other on the back side of the silicon wafer (1), wherein the first composite dielectric layer comprises a tunneling layer (2) and a boron-doped polysilicon layer (3), and the second composite dielectric layer comprises a tunneling layer (2) and an arsenic-doped polysilicon layer (7), and a passivation layer (4), a MgF2 anti-reflection layer (5) and a SiNx / ZnS anti-reflection layer (6) are arranged on the outside of the first composite dielectric layer and the second composite dielectric layer in sequence from the inside to the outside, and the first composite dielectric layer and the second composite dielectric layer are connected to a positive electrode (8) and a negative electrode (9) respectively.

9. A device, based on the preparation method according to any one of claims 1 to 7, for preparing a MgF2 anti-reflection layer (5) and a SiNx / ZnS anti-reflection layer (6) on both sides of a silicon wafer (1) obtained in S9, characterized in that: The invention comprises a processing table (10), wherein a transition frame (11) is movably arranged on the processing table (10), and two flaps (12) are hingedly arranged opposite to each other on the transition frame (11), and the flaps (12) have a first state of being horizontally extended and a second state of being vertically closed upwards, and a driving component for driving the transition frame (11) to move is arranged in the processing table (10), and a linkage component is arranged between the transition frame (11) and the flaps (12), and during the switching process at both ends of the moving stroke of the transition frame (11), the linkage component links the flaps (12) to switch from the first state to the second state and then switch back to the first state, and the two flaps (12) are switched to correspond to the center positions of the processing table (10) respectively.

10. The device according to claim 9, characterized in that The linkage assembly comprises a slide rail (13) provided at the end of a transition frame (11), a linkage rod (14) being provided in the slide rail (13) so as to be liftable, a sliding pin (15) being provided on the side wall of the flap (12), a sliding groove (16) matching the sliding pin (15) being provided on the linkage rod (14), and a swing rod (17) being hinged on the processing table (10), and a free end of the swing rod (17) being hinged to the linkage rod (14).

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