Pulse width modulation driving circuit, method and testing device

Abstract

The present invention provides a pulse width modulation (PWM) driving circuit, method and testing equipment, which relate to the technical field of integrated circuit design. The PWM driving circuit includes: a PWM signal generation and processing circuit for generating a low-voltage PWM signal with a high slew rate, and amplifying the low-voltage PWM signal; an AC coupling driving circuit for increasing the amplitude of the PWM signal output by the PWM signal generation and processing circuit to the amplitude of the power rail of the first adjustable positive and negative power supply; a driving capability enhancement circuit for enhancing the driving current capability of the PWM signal output by the AC coupling driving circuit; a PWM signal output processing circuit for maintaining the same slew rate as the PWM signal output by the driving capability enhancement circuit, and adjusting the output swing to achieve output of a high-power, high-swing, high-slew rate PWM signal. The embodiment of the present invention can achieve output of a high-power, high-swing, high-slew rate PWM signal.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a pulse width modulation driving circuit, method and testing equipment. Background Art

[0002] like Figure 1 As shown, the high-power PWM (Pulse-width modulation) driving circuit in the prior art includes a high-voltage operational amplifier, a PMOS (Q6) and an NMOS (Q5), and the NMOS and the PMOS form a MOS amplification circuit with a push-pull structure. The working principle is: the low-voltage PWM signal passes through the high-voltage operational amplifier, and the driving current of the MOS amplification circuit with a push-pull structure is increased to achieve high-power output.

[0003] However, in practical applications, there are fewer high-voltage op amps to choose from, and their driving capability and slew rate are limited. If the design requires a higher voltage swing or a larger slew rate (for example, 1000V / us), the existing high-power PWM drive circuit is difficult to meet the design requirements. Summary of the invention

[0004] In view of the problems raised in the background technology, the present invention provides a pulse width modulation driving circuit, method and testing equipment. The pulse width modulation (PWM) driving circuit of the present invention has the characteristics of high swing amplitude and high slew rate, and is used to meet the output of high power, high voltage swing amplitude and high slew rate.

[0005] The technical solution of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a pulse width modulation (PWM) driving circuit, comprising:

[0007] A PWM signal generation and processing circuit, used for generating a low-voltage PWM signal with a high slew rate and amplifying the low-voltage PWM signal;

[0008] An AC coupling drive circuit, comprising at least a first adjustable positive and negative power supply for supplying power to the AC coupling drive circuit, and a circuit for increasing the amplitude of the PWM signal output by the PWM signal generation and processing circuit to the amplitude of the power rail of the first adjustable positive and negative power supply;

[0009] A driving capability enhancement circuit, used to enhance the driving current capability of the PWM signal output by the AC coupling driving circuit;

[0010] The PWM signal output processing circuit is used to maintain the same slew rate as the PWM signal output by the driving capability enhancement circuit and adjust the output swing amplitude to output a PWM signal with high power, high swing amplitude and high slew rate.

[0011] Optionally, the PWM signal generation processing circuit includes:

[0012] A high slew rate low voltage PWM generator, used for generating a high slew rate low voltage PWM signal;

[0013] The high-speed low-voltage operational amplifier is used to perform a first-stage amplification on the low-voltage PWM signal.

[0014] Optionally, the high slew rate is a slew rate greater than 1000 v / us.

[0015] Optionally, the AC coupling driving circuit includes: a second capacitor C2, a third capacitor C3, a first resistor R1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PNP transistor Q1 and a first NPN transistor Q2;

[0016] The output end of the PWM signal generation and processing circuit is connected to one end of the second capacitor C2 and the third capacitor C3 respectively;

[0017] The other end of the second capacitor C2 is connected to one end of the first resistor R1 and the base of the first PNP transistor Q1 respectively; the first positive high-voltage adjustable power supply is connected to the other end of the first resistor R1, and is connected to the emitter of the first PNP transistor Q1 through the fifth resistor R5;

[0018] The other end of the third capacitor C3 is connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2 respectively; the first negative high-voltage adjustable power supply is connected to the other end of the fourth resistor R4, and is connected to the emitter of the first NPN transistor Q2 through the sixth resistor R6;

[0019] The collector of the first PNP transistor Q1 and the collector of the first NPN transistor Q2 are connected to the driving capability enhancement circuit, respectively.

[0020] Optionally, the AC coupling driving circuit further includes: a first capacitor C1, a fourth capacitor C4, a second resistor R2 and a third resistor R3; the first capacitor C1 is connected in parallel with the second resistor R2, and the fourth capacitor C4 is connected in parallel with the third resistor R3;

[0021] The other end of the second capacitor C2 is respectively connected to one end of the first resistor R1 and the base of the first PNP transistor Q1, including: the other end of the second capacitor C2 is respectively connected to the second resistor R2 and one end of the first capacitor C1, and the other end of the second resistor R2 and the other end of the first capacitor C1 are respectively connected to one end of the first resistor R1 and the base of the first PNP transistor Q1;

[0022] The other end of the third capacitor C3 is respectively connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2, including: the other end of the third capacitor C3 is respectively connected to the third resistor R3 and one end of the fourth capacitor C4, and the other end of the third resistor R3 and the other end of the fourth capacitor C4 are respectively connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2.

[0023] Optionally, the driving capability enhancement circuit includes: a seventh resistor R7, an eighth resistor R8, a second NPN transistor Q3, and a second PNP transistor Q4;

[0024] The collector of the first PNP transistor Q1 is connected to the base of the second NPN transistor Q3, and the collector of the first NPN transistor Q2 is connected to the base of the second PNP transistor Q4;

[0025] The collector of the second NPN transistor Q3 is connected to the first positive high-voltage adjustable power supply, and the collector of the second PNP transistor Q4 is connected to the first negative high-voltage adjustable power supply;

[0026] The emitter of the second NPN transistor Q3 is connected to the emitter of the second PNP transistor Q4 via the seventh resistor R7 and the eighth resistor R8.

[0027] Optionally, the PWM signal output processing circuit includes a second positive high-voltage adjustable power supply, a second negative high-voltage adjustable power supply, and a MOS amplifying circuit with a push-pull structure composed of NMOS and PMOS; the MOS amplifying circuit includes an NMOS transistor Q5 and a PMOS transistor Q6;

[0028] The drain of the NMOS transistor Q5 is connected to the second positive high voltage adjustable power supply, and the gate is connected to the emitter of the second NPN transistor Q3;

[0029] The source of the PMOS transistor Q6 is connected to the second negative high-voltage adjustable power supply, and the gate is connected to the emitter of the second PNP transistor Q4.

[0030] Optionally, the second positive high-voltage adjustable power supply is a high-power positive high-voltage adjustable power supply, and the second negative high-voltage adjustable power supply is a high-power negative high-voltage adjustable power supply;

[0031] The swing amplitude of the output PWM signal is adjusted by adjusting the voltage difference between the second positive high-voltage adjustable power supply and the second negative high-voltage adjustable power supply.

[0032] In a second aspect, an embodiment of the present invention provides a driving method of a PWM driving circuit, which is applied to the PWM driving circuit described in the first aspect, and the driving method includes:

[0033] Using a PWM signal generation and processing circuit to generate a low-voltage PWM signal with a high slew rate, and amplifying the low-voltage PWM signal;

[0034] Using an AC coupling drive circuit to increase the amplitude of the PWM signal output by the PWM signal generation and processing circuit to the amplitude of the power rail of the first adjustable positive and negative power supply;

[0035] Using a driving capability enhancement circuit to enhance the driving current capability of the PWM signal output by the AC coupling driving circuit;

[0036] The PWM signal output processing circuit is used to maintain the same slew rate as the PWM signal output by the driving capability enhancement circuit, and to adjust the output swing amplitude, so as to output a PWM signal with high power, high swing amplitude and high slew rate.

[0037] Optionally, the high slew rate is a slew rate greater than 1000 v / us.

[0038] In a third aspect, an embodiment of the present invention provides a testing device, comprising the PWM driving circuit described in the first aspect.

[0039] The beneficial effects of the above technical solution of the present invention are:

[0040] The PWM drive circuit provided by the embodiment of the present invention includes a PWM signal generation and processing circuit, which is used to generate a low-voltage PWM signal with a high slew rate and amplify the low-voltage PWM signal; an AC coupling drive circuit, which is used to increase the amplitude of the PWM signal output by the PWM signal generation and processing circuit to the amplitude of the power rail of the first adjustable positive and negative power supply; a driving capability enhancement circuit, which is used to enhance the driving current capability of the PWM signal output by the AC coupling drive circuit; and a PWM signal output processing circuit, which is used to maintain the same slew rate as the PWM signal output by the driving capability enhancement circuit, and adjust the output swing amplitude to achieve the output of a high-power, high-swing-amplitude, high-slew-rate PWM signal. The embodiment of the present invention uses a PWM signal generation and processing circuit to generate a low-voltage PWM signal with a high slew rate, and sequentially undergoes a first-stage amplification, AC coupling, enhanced driving current, output swing adjustment and other processes, and adopts a multi-stage amplification and current expansion method to achieve the output of a high-power, high-swing-amplitude, high-slew-rate PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a structural schematic diagram of an existing high-power PWM drive circuit;

[0042] Figure 2 This is a first structural schematic diagram of a PWM drive circuit disclosed in an embodiment of the present invention;

[0043] Figure 3A second structural schematic diagram of a PWM drive circuit disclosed in an embodiment of the present invention;

[0044] Figure 4 A third structural schematic diagram of the PWM drive circuit disclosed in an embodiment of the present invention;

[0045] Figure 5 The present invention discloses a flow chart of a driving method of a PWM driving circuit. DETAILED DESCRIPTION

[0046] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will be described in detail in conjunction with the accompanying drawings and specific embodiments. In the following description, specific details such as specific configurations and components are provided only to help fully understand the embodiments of the present invention. Therefore, it should be clear to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. In addition, for clarity and brevity, the description of known functions and structures is omitted.

[0047] It should be understood that the references to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0048] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0049] Example 1

[0050] like Figure 2 As shown, the PWM driving circuit provided by the embodiment of the present invention includes: a PWM signal generating and processing circuit 100, an AC coupling driving circuit 200, a driving capability enhancement circuit 300 and a PWM signal output processing circuit 400. Specifically:

[0051] The PWM signal generation and processing circuit 100 is used to generate a low-voltage PWM signal with a high slew rate and amplify the low-voltage PWM signal.

[0052] In the embodiment of the present invention, a high slew rate refers to a slew rate greater than 1000v / us. The PWM signal generation and processing circuit 100 in the embodiment of the present invention generates a low-voltage PWM signal with a slew rate greater than 1000v / us and undergoes a first-stage amplification process, and the processed PWM signal reaches a voltage capable of driving the subsequent stage driving capability enhancement circuit 300.

[0053] Further integration Figure 3 , Figure 4 As an optional implementation of the embodiment of the present invention, the PWM signal generation and processing circuit 100 may include a low-voltage PWM generator with a high slew rate and a high-speed low-voltage operational amplifier. The low-voltage PWM generator with a high slew rate is used to generate a low-voltage PWM signal with a high slew rate, and the high-speed low-voltage operational amplifier is used to perform a first-stage amplification on the low-voltage PWM signal.

[0054] Generally, the voltage range of the low-voltage PWM signal generated by the low-voltage PWM generator is 0-1V. The present invention uses a high-speed low-voltage operational amplifier to perform a first-stage amplification on the low-voltage PWM signal, so that the voltage range of the amplified PWM signal can reach -8V to 8V, which can effectively improve the amplitude and driving ability of the PWM signal. Compared with the prior art, the embodiment of the present invention uses a low-voltage PWM generator with a high slew rate to generate and output a PWM signal with a high slew rate (such as a slew rate greater than 1000v / us), which meets the design requirements of a high slew rate. At the same time, the low-voltage PWM generator can output a voltage range according to demand, and the voltage swing can reach ±100V. And the embodiment of the present invention uses a high-speed low-voltage operational amplifier, which is relatively low in cost compared to a high-voltage operational amplifier. In practical applications, the power supply voltage of the high-speed low-voltage operational amplifier is a maximum of ±16V, the slew rate is 8000v / us, and the bandwidth is 900MHZ. The PWM signal output after being processed by the high-speed low-voltage operational amplifier in the embodiment of the present invention is a positive and negative jump PWM signal, such as a positive and negative 8V jump PWM signal, and its rising and falling edges are about 10ns.

[0055] The AC coupling driving circuit 200 is used to increase the amplitude of the PWM signal output by the PWM signal generation processing circuit 100 to the amplitude of the power rail of the first adjustable positive and negative power supply.

[0056] In practical applications, the AC coupling driving circuit 200 enhances the amplitude of the input PWM signal to the amplitude of the power rail of the first adjustable positive and negative power supply. Figure 3 , 4 , the first adjustable positive power supply is the adjustable positive power supply 1 in the figure, and the first adjustable negative power supply is the adjustable negative power supply 1 in the figure.

[0057] The specific AC coupling driving circuit 200 may include coupling capacitors and resistors, PNP transistors, NPN transistors, and adjustable positive / negative power supplies. The use of capacitor coupling can effectively reduce the power consumption of resistors.

[0058] Further integration Figure 3 As an optional implementation of the embodiment of the present invention, the AC coupling drive circuit 200 may include: a second capacitor C2, a third capacitor C3, a first resistor R1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PNP transistor Q1, a first NPN transistor Q2, a first positive high-voltage adjustable power supply (adjustable positive power supply 1), and a first negative high-voltage adjustable power supply (adjustable negative power supply 1).

[0059] The output end of the high-speed low-voltage operational amplifier is connected to one end of the second capacitor C2 and the third capacitor C3 respectively; the other end of the second capacitor C2 is connected to one end of the first resistor R1 and the base of the first PNP transistor Q1 respectively; the first positive high-voltage adjustable power supply is connected to the other end of the first resistor R1, and is connected to the emitter of the first PNP transistor Q1 through the fifth resistor R5;

[0060] The other end of the third capacitor C3 is connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2 respectively; the first negative high-voltage adjustable power supply is connected to the other end of the fourth resistor R4, and is connected to the emitter of the first NPN transistor Q2 through the sixth resistor R6;

[0061] The collector of the first PNP transistor Q1 and the collector of the first NPN transistor Q2 are connected to the driving capability enhancement circuit 300 , respectively.

[0062] In the embodiment of the present invention, the first positive high-voltage adjustable power supply (adjustable positive power supply 1) and the first negative high-voltage adjustable power supply (adjustable negative power supply 1) are used to power the AC coupling driving circuit 200. The second capacitor C2 and the third capacitor C3 are used for AC coupling. The first resistor R1 and the fourth resistor R4 are used to absorb the overshoot of the voltage generated by the AC coupling.

[0063] Specifically, the embodiment of the present invention utilizes capacitors C2 and C3 to prevent the voltage variation characteristics of the first positive high-voltage adjustable power supply and the first negative high-voltage adjustable power supply, so that the base voltages of the first PNP transistor Q1 and the first NPN transistor Q2 jump synchronously with the PWM signal output by the previous-stage PWM signal generation and processing circuit 100. In this way, by adjusting the amplitude of the PWM signal output by the PWM signal generation and processing circuit 100, the magnitude of the base voltage jump of the first PNP transistor Q1 and the first NPN transistor Q2 is controlled, so that the first PNP transistor Q1 and the first NPN transistor Q2 are sufficiently turned on, thereby ensuring that the output can reach the PWM waveform of the power rails of the first adjustable positive and negative power supplies.

[0064] As an optional implementation of the embodiment of the present invention, Figure 4 As shown, in Figure 3 Based on the above, the AC coupling driving circuit 200 may further include: a first capacitor C1, a fourth capacitor C4, a second resistor R2 and a third resistor R3; the first capacitor C1 is connected in parallel with the second resistor R2, and the fourth capacitor C4 is connected in parallel with the third resistor R3.

[0065] At this time, the second capacitor C2 is connected to the first resistor R1 and the base of the first PNP transistor Q1 through a parallel circuit formed by the first capacitor C1 and the second resistor R2. Specifically, the other end of the second capacitor C2 is connected to the second resistor R2 and one end of the first capacitor C1, respectively, and the other end of the second resistor R2 and the other end of the first capacitor C1 are connected to one end of the first resistor R1 and the base of the first PNP transistor Q1, respectively.

[0066] At this time, the third capacitor C3 is connected to the fourth resistor R4 and the base of the first NPN transistor Q2 through a parallel circuit formed by the fourth capacitor C4 and the third resistor R3. Specifically, the other end of the third capacitor C3 is connected to the third resistor R3 and one end of the fourth capacitor C4, respectively, and the other end of the third resistor R3 and the other end of the fourth capacitor C4 are respectively connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2.

[0067] In practical applications, the first capacitor C1 and the fourth capacitor C4 are used as acceleration capacitors to drive the first PNP transistor Q1 and the first NPN transistor Q2 to open and close faster. At the same time, considering the AC coupling method adopted by the circuit, the driving waveform slew rate of the PWM signal output by the front-stage PWM signal generation and processing circuit 100 is very high, and overshoot is very likely to occur. In this way, the present invention uses resistors R1 and R2 to absorb the overshoot generated by driving the first PNP transistor Q1, so as to effectively protect the positive power rail and the low-voltage high-speed operational amplifier in the front-stage circuit. Similarly, resistors R3 and R4 are used to absorb the overshoot generated by driving the first NPN transistor Q2, so as to effectively protect the negative power rail and the low-voltage high-speed operational amplifier in the front-stage circuit, thereby ensuring that the output can reach the PWM waveform of the power rail. Since the entire circuit is open-loop, the output rail-to-rail signal is conducive to controlling the amplitude of all drive signals, so that each level of circuit works in a controllable, safe and reliable state.

[0068] The driving capability enhancement circuit 300 is used to enhance the driving current capability of the PWM signal output by the AC coupling driving circuit 200 .

[0069] In practical applications, only a current with a larger driving capability can ensure that the slew rate of the PWM signal output by the PWM signal output processing circuit 400 is consistent with that of the previous circuit. Therefore, in the embodiment of the present invention, the driving capability enhancement circuit 300 enhances the driving current capability of the PWM signal output by the AC coupling driving circuit 200. Figure 3 , Figure 4 As shown, as an optional implementation of the embodiment of the present invention, the driving capability enhancement circuit 300 includes: a seventh resistor R7, an eighth resistor R8, a second NPN transistor Q3, and a second PNP transistor Q4.

[0070] The collector of the first PNP transistor Q1 is connected to the base of the second NPN transistor Q3, and the collector of the first NPN transistor Q2 is connected to the base of the second PNP transistor Q4;

[0071] The collector of the second NPN transistor Q3 is connected to the first positive high-voltage adjustable power supply (adjustable positive power supply 1), and the collector of the second PNP transistor Q4 is connected to the first negative high-voltage adjustable power supply (adjustable negative power supply 1);

[0072] The emitter of the second NPN transistor Q3 is connected to the emitter of the second PNP transistor Q4 via the seventh resistor R7 and the eighth resistor R8.

[0073] In the embodiment of the present invention, the first positive high-voltage adjustable power supply (adjustable positive power supply 1) and the first negative high-voltage adjustable power supply (adjustable negative power supply 1) are also used to power the driving capability enhancement circuit 300. The seventh resistor R7 and the eighth resistor R8 are used to ensure that the NMOS transistor Q5 and the PMOS transistor Q6 have a path for discharging residual power.

[0074] In the embodiment of the present invention, the larger the driving current of the PWM signal output by the driving capability enhancement circuit 300 is, the higher the upper and lower tubes (corresponding to the attached Figure 4 The faster the NMOS transistor Q5 and the PMOS transistor Q6 in the circuit are turned on, the higher the slew rate of the PWM signal finally output by the overall circuit can be ensured. Therefore, if the NMOS transistor Q5 and the PMOS transistor Q6 are fully turned on within a specified time (such as 100ns), the second NPN transistor Q3 and the second PNP transistor Q4 are required to output a PWM signal with a larger current driving capability, such as a current driving capability of 3A, 5A, etc.

[0075] According to the formula I=C*(dV / dt), the slew rate (dV / dt) of the PWM signal output by the driving capability enhancement circuit 300 and the input capacitance C of the NMOS transistor Q5 and the PMOS transistor Q6 in the PWM signal output processing circuit 400 determine the magnitude I of the actual working instantaneous driving current. According to the conger simulation, the actual instantaneous current of the present invention can reach 3A. The present invention ensures the output of a current with a larger driving capability through the driving capability enhancement circuit 300, thereby ensuring that the slew rate of the PWM signal output by the PWM signal output processing circuit 400 is consistent with that of the previous circuit.

[0076] The PWM signal output processing circuit 400 is used to maintain the same slew rate as the PWM signal output by the driving capability enhancement circuit 300 and adjust the output swing amplitude to output a PWM signal with high power, high swing amplitude and high slew rate.

[0077] Further integration Figure 4 As shown, as an optional implementation of the embodiment of the present invention, the PWM signal output processing circuit 400 includes a second positive high-voltage adjustable power supply (adjustable positive power supply 2), a second negative high-voltage adjustable power supply (adjustable negative power supply 2), and a MOS amplification circuit with a push-pull structure composed of NMOS and PMOS. The MOS amplification circuit includes an NMOS transistor Q5 and a PMOS transistor Q6, the drain of the NMOS transistor Q5 is connected to the second positive high-voltage adjustable power supply (adjustable positive power supply 2), and the gate is connected to the emitter of the second NPN transistor Q3; the source of the PMOS transistor Q6 is connected to the second negative high-voltage adjustable power supply (adjustable negative power supply 2), and the gate is connected to the emitter of the second PNP transistor Q4.

[0078] In the embodiment of the present invention, the second positive high-voltage adjustable power supply (adjustable positive power supply 2) and the second negative high-voltage adjustable power supply (adjustable negative power supply 2) are used to power the PWM signal output processing circuit 400, and the voltage values ​​are respectively the amplitudes of the positive and negative voltages of the output PWM signal. In practical applications, the second positive high-voltage adjustable power supply (adjustable positive power supply 2) and the second negative high-voltage adjustable power supply (adjustable negative power supply 2) are respectively high-power positive high-voltage adjustable power supplies and high-power negative high-voltage adjustable power supplies, such as TDK_lamda G300-11.5. As a high-voltage power supply for the power supply of the post-amplifier circuit, the voltage difference between the positive and negative high-voltage adjustable power supplies can be continuously increased according to actual needs to adjust the swing of the output PWM signal, thereby achieving the purpose of meeting the output higher swing requirements.

[0079] The embodiment of the present invention controls the difference between the second positive high-voltage adjustable power supply (adjustable positive power supply 2) and the second negative high-voltage adjustable power supply (adjustable negative power supply 2), and it is necessary to ensure that the difference is greater than the threshold voltage VT of the NMOS transistor Q5 and the PMOS transistor Q6, so as to control the opening degree of the MOS.

[0080] NMOS and PMOS form a push-pull structure, and the PWM signal of the previous stage (i.e., the driving signal output by the second NPN transistor Q3 and the second PNP transistor Q4) synchronously drives the rapid opening and closing of the NMOS transistor Q5 and the PMOS transistor Q6, thereby maintaining the same slew rate as the driving signal. Further, by adjusting the output of the second positive high-voltage adjustable power supply (adjustable positive power supply 2) and the second negative high-voltage adjustable power supply (adjustable negative power supply 2), the output swing can be adjusted to achieve the PWM driving capability of outputting high power, high slew rate and high swing.

[0081] It should be noted that in the embodiment of the present invention, high swing refers to a swing greater than ±100V. The embodiment of the present invention can achieve a larger output swing by selecting Q1, Q2, Q3, Q4, Q5, and Q6 that meet the requirements. High power refers to the driving capability of the PWM signal. In practical applications, due to its high slew rate, the instantaneous current can reach 20A when driving certain capacitive loads.

[0082] The high-swing-rate and high-slew-rate PWM driving circuit provided by the embodiment of the present invention utilizes a high-slew-rate and low-voltage PWM generator to generate a high-slew-rate and low-voltage PWM signal, which is then amplified by a high-speed and low-voltage operational amplifier, and then the amplitude of the PWM signal is enhanced by AC coupling, so that the output can reach the PWM waveform of the power rail, and then the driving current capability of the PWM signal is enhanced by a transistor current expansion method of a push-pull structure, and the MOS amplifier circuit of the push-pull structure of the last stage is driven to increase the current output capability of the overall circuit. The embodiment of the present invention adopts a circuit scheme of multi-stage amplification and current expansion to realize the output of a high-power, high-swing-rate and high-slew-rate PWM signal.

[0083] Example 2

[0084] like Figure 5 As shown, an embodiment of the present invention further provides a driving method of a PWM driving circuit, which is applied to the PWM driving circuit described above. The driving method includes:

[0085] Step 101: Generate a low-voltage PWM signal with a high slew rate by using a PWM signal generation and processing circuit, and amplify the low-voltage PWM signal.

[0086] The PWM signal generation and processing circuit may include a low-voltage PWM generator for generating a low-voltage PWM signal with a high slew rate and a high-speed low-voltage operational amplifier for performing a first-stage amplification on the low-voltage PWM signal; the high slew rate is a slew rate greater than 1000v / us.

[0087] Step 102: using an AC coupling drive circuit to increase the amplitude of the PWM signal output by the PWM signal generation and processing circuit to the amplitude of the power rail of the first adjustable positive and negative power supply.

[0088] The AC coupling driving circuit includes: a second capacitor C2, a third capacitor C3, a first resistor R1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PNP transistor Q1, a first NPN transistor Q2, a first positive high-voltage adjustable power supply, and a first negative high-voltage adjustable power supply;

[0089] The output end of the PWM signal generation and processing circuit is connected to one end of the second capacitor C2 and one end of the third capacitor C3 respectively;

[0090] The other end of the second capacitor C2 is connected to one end of the first resistor R1 and the base of the first PNP transistor Q1 respectively; the first positive high-voltage adjustable power supply is connected to the other end of the first resistor R1, and is connected to the emitter of the first PNP transistor Q1 through the fifth resistor R5;

[0091] The other end of the third capacitor C3 is connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2 respectively; the first negative high-voltage adjustable power supply is connected to the other end of the fourth resistor R4, and is connected to the emitter of the first NPN transistor Q2 through the sixth resistor R6;

[0092] The collector of the first PNP transistor Q1 and the collector of the first NPN transistor Q2 are connected to the driving capability enhancement circuit, respectively.

[0093] And further preferably, the AC coupling driving circuit may further include: a first capacitor C1, a fourth capacitor C4, a second resistor R2 and a third resistor R3; the first capacitor C1 is connected in parallel with the second resistor R2, and the fourth capacitor C4 is connected in parallel with the third resistor R3;

[0094] The other end of the second capacitor C2 is respectively connected to one end of the first resistor R1 and the base of the first PNP transistor Q1, including: the other end of the second capacitor C2 is respectively connected to the second resistor R2 and one end of the first capacitor C1, and the other end of the second resistor R2 and the other end of the first capacitor C1 are respectively connected to one end of the first resistor R1 and the base of the first PNP transistor Q1;

[0095] The other end of the third capacitor C3 is respectively connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2, including: the other end of the third capacitor C3 is respectively connected to the third resistor R3 and one end of the fourth capacitor C4, and the other end of the third resistor R3 and the other end of the fourth capacitor C4 are respectively connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2.

[0096] Step 103: utilizing a driving capability enhancement circuit to enhance the driving current capability of the PWM signal output by the AC coupling driving circuit.

[0097] The driving capability enhancement circuit includes: a seventh resistor R7, an eighth resistor R8, a second NPN transistor Q3, and a second PNP transistor Q4;

[0098] The collector of the first PNP transistor Q1 is connected to the base of the second NPN transistor Q3, and the collector of the first NPN transistor Q2 is connected to the base of the second PNP transistor Q4;

[0099] The collector of the second NPN transistor Q3 is connected to the first positive high-voltage adjustable power supply, and the collector of the second PNP transistor Q4 is connected to the first negative high-voltage adjustable power supply;

[0100] The emitter of the second NPN transistor Q3 is connected to the emitter of the second PNP transistor Q4 via the seventh resistor R7 and the eighth resistor R8.

[0101] Step 104 , using a PWM signal output processing circuit to maintain the same slew rate as the PWM signal output by the driving capability enhancement circuit, and adjusting the output swing amplitude to output a PWM signal with high power, high swing amplitude and high slew rate.

[0102] The PWM signal output processing circuit includes a second positive high-voltage adjustable power supply, a second negative high-voltage adjustable power supply, and a MOS amplifying circuit with a push-pull structure composed of NMOS and PMOS; the MOS amplifying circuit includes an NMOS transistor Q5 and a PMOS transistor Q6;

[0103] The drain of the NMOS transistor Q5 is connected to the second positive high voltage adjustable power supply, and the gate is connected to the emitter of the second NPN transistor Q3;

[0104] The source of the PMOS transistor Q6 is connected to the second negative high-voltage adjustable power supply, and the gate is connected to the emitter of the second PNP transistor Q4.

[0105] Optionally, the second positive high-voltage adjustable power supply is a high-power positive high-voltage adjustable power supply, and the second negative high-voltage adjustable power supply is a high-power negative high-voltage adjustable power supply; by adjusting the voltage difference between the second positive high-voltage adjustable power supply and the second negative high-voltage adjustable power supply, the swing amplitude of the output PWM signal is adjusted.

[0106] It should be noted that the driving method of the PWM driving circuit is a method corresponding to the PWM driving circuit in the aforementioned embodiment 1. All implementation means in the above-mentioned PWM driving circuit embodiment are applicable to the embodiment of the driving method of the PWM driving circuit and can achieve the same technical effect.

[0107] Example 3

[0108] An embodiment of the present invention further provides a testing device, such as automatic testing equipment (ATE), comprising the PWM driving circuit described in the above embodiment 1.

[0109] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pulse width modulation (PWM) driving circuit, characterized in that: include: A PWM signal generation and processing circuit, used for generating a low-voltage PWM signal with a high slew rate and amplifying the low-voltage PWM signal; An AC coupling drive circuit, comprising at least a first adjustable positive and negative power supply for supplying power to the AC coupling drive circuit, and configured to increase the amplitude of the PWM signal output by the PWM signal generation and processing circuit to the amplitude of the power rail of the first adjustable positive and negative power supply; A driving capability enhancement circuit, used to enhance the driving current capability of the PWM signal output by the AC coupling driving circuit; A PWM signal output processing circuit, used to maintain the same slew rate as the PWM signal output by the driving capability enhancement circuit, and adjust the output swing amplitude to output a PWM signal with high power, high swing amplitude and high slew rate; The AC coupling driving circuit further includes: a second capacitor C2, a third capacitor C3, a first resistor R1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PNP transistor Q1 and a first NPN transistor Q2; The output end of the PWM signal generation and processing circuit is connected to one end of the second capacitor C2 and one end of the third capacitor C3 respectively; The other end of the second capacitor C2 is connected to one end of the first resistor R1 and the base of the first PNP transistor Q1 respectively; the first positive high-voltage adjustable power supply is connected to the other end of the first resistor R1, and is connected to the emitter of the first PNP transistor Q1 through the fifth resistor R5; The other end of the third capacitor C3 is connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2 respectively; the first negative high-voltage adjustable power supply is connected to the other end of the fourth resistor R4, and is connected to the emitter of the first NPN transistor Q2 through the sixth resistor R6; The collector of the first PNP transistor Q1 and the collector of the first NPN transistor Q2 are respectively connected to the driving capability enhancement circuit; The driving capability enhancement circuit includes: a seventh resistor R7, an eighth resistor R8, a second NPN transistor Q3, and a second PNP transistor Q4; The collector of the first PNP transistor Q1 is connected to the base of the second NPN transistor Q3, and the collector of the first NPN transistor Q2 is connected to the base of the second PNP transistor Q4; The collector of the second NPN transistor Q3 is connected to the first positive high-voltage adjustable power supply, and the collector of the second PNP transistor Q4 is connected to the first negative high-voltage adjustable power supply; The emitter of the second NPN transistor Q3 is connected to the emitter of the second PNP transistor Q4 via a seventh resistor R7 and an eighth resistor R8; The PWM signal output processing circuit includes a second positive high-voltage adjustable power supply, a second negative high-voltage adjustable power supply, and a MOS amplification circuit with a push-pull structure composed of NMOS and PMOS; the MOS amplification circuit includes an NMOS transistor Q5 and a PMOS transistor Q6; The drain of the NMOS transistor Q5 is connected to the second positive high voltage adjustable power supply, and the gate is connected to the emitter of the second NPN transistor Q3; The source of the PMOS transistor Q6 is connected to the second negative high-voltage adjustable power supply, and the gate is connected to the emitter of the second PNP transistor Q4.

2. The PWM driving circuit according to claim 1, characterized in that: The PWM signal generation processing circuit comprises: A high slew rate low voltage PWM generator, used for generating a high slew rate low voltage PWM signal; The high-speed low-voltage operational amplifier is used to perform a first-stage amplification on the low-voltage PWM signal.

3. The PWM driving circuit according to claim 2, characterized in that: The high slew rate is a slew rate greater than 1000v / us.

4. The PWM driving circuit according to claim 1, characterized in that: The AC coupling driving circuit further includes: a first capacitor C1, a fourth capacitor C4, a second resistor R2 and a third resistor R3; the first capacitor C1 is connected in parallel with the second resistor R2, and the fourth capacitor C4 is connected in parallel with the third resistor R3; The other end of the second capacitor C2 is respectively connected to one end of the first resistor R1 and the base of the first PNP transistor Q1, including: the other end of the second capacitor C2 is respectively connected to the second resistor R2 and one end of the first capacitor C1, and the other end of the second resistor R2 and the other end of the first capacitor C1 are respectively connected to one end of the first resistor R1 and the base of the first PNP transistor Q1; The other end of the third capacitor C3 is respectively connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2, including: the other end of the third capacitor C3 is respectively connected to the third resistor R3 and one end of the fourth capacitor C4, and the other end of the third resistor R3 and the other end of the fourth capacitor C4 are respectively connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2.

5. The PWM driving circuit according to claim 1, characterized in that: The second positive high-voltage adjustable power supply is a high-power positive high-voltage adjustable power supply, and the second negative high-voltage adjustable power supply is a high-power negative high-voltage adjustable power supply; The swing amplitude of the output PWM signal is adjusted by adjusting the voltage difference between the second positive high-voltage adjustable power supply and the second negative high-voltage adjustable power supply.

6. A driving method for a PWM driving circuit, characterized in that: Applied to the PWM drive circuit according to any one of claims 1 to 5, the drive method comprises: Using a PWM signal generation and processing circuit to generate a low-voltage PWM signal with a high slew rate, and amplifying the low-voltage PWM signal; Using an AC coupling drive circuit to increase the amplitude of the PWM signal output by the PWM signal generation and processing circuit to the amplitude of the power rail of the first adjustable positive and negative power supply; Using a driving capability enhancement circuit to enhance the driving current capability of the PWM signal output by the AC coupling driving circuit; The PWM signal output processing circuit is used to maintain the same slew rate as the PWM signal output by the driving capability enhancement circuit, and to adjust the output swing amplitude, so as to output a PWM signal with high power, high swing amplitude and high slew rate; The AC coupling driving circuit further includes: a second capacitor C2, a third capacitor C3, a first resistor R1, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PNP transistor Q1 and a first NPN transistor Q2; The output end of the PWM signal generation and processing circuit is connected to one end of the second capacitor C2 and one end of the third capacitor C3 respectively; The other end of the second capacitor C2 is connected to one end of the first resistor R1 and the base of the first PNP transistor Q1 respectively; the first positive high-voltage adjustable power supply is connected to the other end of the first resistor R1, and is connected to the emitter of the first PNP transistor Q1 through the fifth resistor R5; The other end of the third capacitor C3 is connected to one end of the fourth resistor R4 and the base of the first NPN transistor Q2 respectively; the first negative high-voltage adjustable power supply is connected to the other end of the fourth resistor R4, and is connected to the emitter of the first NPN transistor Q2 through the sixth resistor R6; The collector of the first PNP transistor Q1 and the collector of the first NPN transistor Q2 are respectively connected to the driving capability enhancement circuit; The driving capability enhancement circuit includes: a seventh resistor R7, an eighth resistor R8, a second NPN transistor Q3, and a second PNP transistor Q4; The collector of the first PNP transistor Q1 is connected to the base of the second NPN transistor Q3, and the collector of the first NPN transistor Q2 is connected to the base of the second PNP transistor Q4; The collector of the second NPN transistor Q3 is connected to the first positive high-voltage adjustable power supply, and the collector of the second PNP transistor Q4 is connected to the first negative high-voltage adjustable power supply; The emitter of the second NPN transistor Q3 is connected to the emitter of the second PNP transistor Q4 via a seventh resistor R7 and an eighth resistor R8; The PWM signal output processing circuit includes a second positive high-voltage adjustable power supply, a second negative high-voltage adjustable power supply, and a MOS amplification circuit with a push-pull structure composed of NMOS and PMOS; the MOS amplification circuit includes an NMOS transistor Q5 and a PMOS transistor Q6; The drain of the NMOS transistor Q5 is connected to the second positive high voltage adjustable power supply, and the gate is connected to the emitter of the second NPN transistor Q3; The source of the PMOS transistor Q6 is connected to the second negative high-voltage adjustable power supply, and the gate is connected to the emitter of the second PNP transistor Q4.

7. A testing device, characterized in that: It comprises the PWM drive circuit as described in any one of claims 1 to 5.

Images