Chip aging method and device

Abstract

A chip aging method and device, the aging device is connected to a chip driving circuit, the driving circuit includes an inverter and at least one selection transistor; the device is connected to the inverter input end and the selection transistor gate, the inverter output end is connected to the selection transistor drain, the selection transistor source and the second power supply end of the inverter are connected to a low voltage; the first power supply end of the inverter is connected to a high voltage, the method includes outputting to the inverter a first level for forming a DC electric field between the input and output of the inverter; or outputting to the inverter a second level for controlling conduction between the first power supply end and the output end, and outputting to the gate of the selection transistor a third level for forming a DC electric field between the source and drain of the selection transistor, so that the driving circuit with quality problems fails after accelerated aging, avoiding the failure of one or more rows of chips due to dielectric breakdown or hot carrier degradation in the driving circuit after leaving the factory.

Description

[0001] This application is a divisional application. The application number of the original application is 202310261232.1, and the original application date is March 13, 2023. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of semiconductor detection, and in particular to a chip aging method and device. Background Art

[0003] At present, chip drive circuit failures often lead to chip row or multiple row failures. For example, the drive circuit of a dynamic random access memory (DRAM) chip is provided with multiple sub-word lines, each of which is connected to multiple storage cells. If the drive circuit fails, the storage cells connected to the sub-word lines cannot receive the drive voltage, which leads to the chip row or multiple row failures.

[0004] However, existing aging test methods cannot stimulate row or multi-row failures of a type of memory chips such as DRAM, which results in defective chips with potential problems entering the market, causing the reliability of computer equipment using defective chips to decrease.

[0005] Therefore, how to improve the speed and accuracy of chip aging detection in response to the problem of row or multi-row failure of chips is an urgent problem to be solved. Summary of the invention

[0006] The present application provides a chip aging method and device for improving the speed and accuracy of chip aging detection.

[0007] In a first aspect, the present application provides a chip aging method, wherein a driving circuit of the chip includes an inverter and at least one selection transistor;

[0008] The aging device is respectively connected to the input terminal of the inverter and the gate of the at least one selection transistor; the output terminal of the inverter is connected to the drain of the at least one selection transistor; the first power supply terminal of the inverter is connected to a high voltage; the second power supply terminal of the inverter and the source of each selection transistor are connected to a low voltage;

[0009] The aging method comprises:

[0010] The aging device outputs a first level to the inverter, wherein the first level is used to form a DC electric field between an input terminal and an output terminal of the inverter;

[0011] Alternatively, the aging method comprises:

[0012] The aging device outputs a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal;

[0013] And output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

[0014] Based on the above scheme, the inverter inputs the first level, and since the inverter function of the inverter will output the opposite level, a maximum potential difference is formed between the input and output ends of the inverter, that is, a maximum electric field is formed in the dielectric layer. The maximum electric field can accelerate the dielectric breakdown phenomenon of the dielectric layer over time, thereby accelerating the aging of the driving circuit.

[0015] The traditional chip aging solution uses alternating current to continuously change the level of the inverter input terminal, which causes the electric field applied to the dielectric layer to change, namely, AC stress. The technical solution of the present application maintains a stable level and does not change the input level of the inverter input terminal, which is equivalent to applying an electric field of a DC nature, namely, DC stress. The accelerating effect of DC stress on TDDB is greater than that of AC stress, so this solution can further accelerate the aging of the drive circuit.

[0016] In addition, based on the above scheme, after the aging device controls the path between the first power supply terminal and the output terminal to be turned on, the drain voltage of the selection transistor is connected to a high voltage. At the same time, the aging device outputs a third level to control the path between the source and drain of the selection transistor to be turned on, and the source of the selection transistor is connected to a low voltage. Therefore, there is a maximum voltage difference between the source and drain of the selection transistor, thereby forming a maximum electric field to accelerate the degradation of hot carriers, thereby accelerating the aging of the drive circuit.

[0017] Furthermore, since the electric field applied between the source and drain of the selection transistor is a DC electric field, namely, DC stress, the accelerating effect of DC stress on HCI is greater than that of AC stress, and thus the aging of the driving circuit can be further accelerated.

[0018] In summary, the chip aging method of the present application can accelerate the aging of the driving circuit in the chip, causing the driving circuit with quality problems to age and fail, thereby improving the speed and accuracy of chip detection and avoiding the problem of row or multiple row failures in chips leaving the factory.

[0019] In one implementation, when the aging device outputs the first level to the inverter, the method further includes:

[0020] The aging device outputs a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

[0021] Based on the above solution, the voltage change at the output end of the inverter caused by the source and drain of the selection transistor being turned on is avoided, and the stability of the DC electric field in the dielectric layer is further ensured.

[0022] In one implementation, when the aging device outputs the first level to the inverter, the method further includes:

[0023] The aging device adjusts the ambient temperature of the driving circuit to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

[0024] Since the higher the temperature, the shorter the failure time of TDDB in the dielectric layer, this solution places the driving circuit in an environment higher than the operating temperature of the driving circuit, that is, forms a high temperature condition, accelerates the breakdown of the dielectric over time, and thus accelerates the aging of the driving circuit.

[0025] In one implementation, when the aging device outputs the second level to the inverter, the method further includes:

[0026] The aging device adjusts the ambient temperature of the driving circuit to be lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

[0027] Since the lower the temperature, the shorter the time for the selection transistor to undergo HCI, this solution places the drive circuit in an environment below normal temperature, such as 25°C, to form a low temperature condition, which accelerates the degradation of hot carriers and thus accelerates the aging of the drive circuit.

[0028] In a second aspect, the present application provides a chip aging method, wherein the driving circuit of the chip includes an inverter, a status decoder and at least one selection transistor;

[0029] The aging device is respectively connected to the input end of the inverter and the first end of the status decoder; the second end of the status decoder is respectively connected to the gate of the at least one selection transistor; the output end of the inverter is connected to the drain of the at least one selection transistor; the first power supply end of the inverter is connected to a high voltage; the second power supply end of the inverter and the source of each selection transistor are connected to a low voltage;

[0030] The aging method comprises:

[0031] The aging device outputs a first level to the inverter, wherein the first level is used to form a DC electric field between an input terminal and an output terminal of the inverter;

[0032] Alternatively, the aging method comprises:

[0033] The aging device outputs a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal;

[0034] The level decoder is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

[0035] In one implementation, when the aging device outputs the first level to the inverter, the method further includes:

[0036] The aging device controls the level decoder to output a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

[0037] In one implementation, when the aging device outputs the first level to the inverter, the method further includes:

[0038] The aging device adjusts the ambient temperature of the driving circuit to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

[0039] In one implementation, when the aging device outputs the second level to the inverter, the method further includes:

[0040] The aging device adjusts the ambient temperature of the driving circuit to be lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

[0041] In a third aspect, the present application provides an aging device, the aging device comprising a controller and a level output unit; the aging device is connected to a driving circuit of a chip;

[0042] The driving circuit includes an inverter and at least one selection transistor;

[0043] The controller is connected to the level output unit; the level output unit is respectively connected to the input end of the inverter and the gate of the at least one selection transistor; the output end of the inverter is connected to the drain of the at least one selection transistor; the first power supply end of the inverter is connected to a high voltage; the second power supply end of the inverter and the source of each selection transistor are connected to a low voltage;

[0044] The level output unit is used to output the level;

[0045] The controller is used to control the level output unit to output a first level to the inverter, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter;

[0046] or,

[0047] The controller is used to control the level output unit to output a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal;

[0048] The level output unit is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

[0049] In one implementation, when controlling the level output unit to output the first level to the inverter, the controller is further configured to:

[0050] The level output unit is controlled to output a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

[0051] In one embodiment, the aging device further includes a temperature control layer, and the temperature control layer is used to provide an ambient temperature for the driving circuit.

[0052] In one implementation, when controlling the level output unit to output the first level to the inverter, the controller is further configured to:

[0053] The temperature of the temperature control layer is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

[0054] In one implementation, when controlling the level output unit to output the second level to the inverter, the controller is further configured to:

[0055] The temperature of the temperature control layer is adjusted to be higher than or lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

[0056] In a fourth aspect, the present application provides an aging device, the aging device comprising a controller and a level output unit; the aging device is connected to a driving circuit of a chip;

[0057] The driving circuit includes an inverter, a status decoder and at least one selection transistor;

[0058] The controller is connected to the level output unit and the first end of the level decoder respectively; the second end of the level decoder is connected to the gate of the at least one selection transistor respectively; the level output unit is connected to the input end of the inverter; the output end of the inverter is connected to the drain of the at least one selection transistor; the first power supply end of the inverter is connected to a high voltage; the second power supply end of the inverter and the source of each selection transistor are connected to a low voltage;

[0059] The level output unit is used to output the level;

[0060] The controller is used to control the level output unit to output a first level to the inverter, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter;

[0061] or,

[0062] The controller is used to control the level output unit to output a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal;

[0063] The level decoder is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

[0064] In one implementation, when controlling the level output unit to output the first level to the inverter, the controller is further configured to:

[0065] The level decoder is controlled to output a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

[0066] In one embodiment, the aging device further includes a temperature control layer, and the temperature control layer is used to provide an ambient temperature for the driving circuit.

[0067] In one implementation, when controlling the level output unit to output the first level to the inverter, the controller is further configured to:

[0068] The temperature of the temperature control layer is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

[0069] In one implementation, when controlling the level output unit to output the second level to the inverter, the controller is further configured to:

[0070] The temperature of the temperature control layer is adjusted to be higher than or lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

[0071] In a fifth aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the chip aging method as described in the first aspect or the second aspect is implemented.

[0072] In a sixth aspect, the present application further provides a computer storage medium storing a computer program, which, when executed by a processor, can implement the chip aging method as described in the first aspect or the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 A schematic diagram of a driving circuit structure of a DRAM chip;

[0074] Figure 2 A schematic diagram of a driving circuit provided in an embodiment of the present application;

[0075] Figure 3 A schematic diagram of the structure of another driving circuit provided in an embodiment of the present application;

[0076] Figure 4 A schematic diagram of an accelerated test simulation provided in an embodiment of the present application;

[0077] Figure 5 A schematic diagram of the structure of another driving circuit provided in an embodiment of the present application;

[0078] Figure 6 A schematic diagram of the structure of an aging device provided in an embodiment of the present application;

[0079] Figure 7 A schematic diagram of the structure of another aging device provided in an embodiment of the present application;

[0080] Figure 8 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0081] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0082] To facilitate understanding of the embodiments of the present application, the following explains the terms involved in the embodiments of the present application:

[0083] 1. Chip aging detection

[0084] Chip aging detection is an electrical stress test method that uses voltage and temperature changes to accelerate the electrical failure of devices. The detection process basically simulates the actual aging process of the chip. By accelerating chip aging, the reliability of the device is detected, or it is used to discover early failures of the device.

[0085] 2. Time dependent dielectric breakdown (TDDB)

[0086] Time-dependent dielectric breakdown TDDB means that the electric field applied to the dielectric layer is lower than the intrinsic breakdown field strength of the dielectric layer, and does not cause intrinsic breakdown. However, after a period of time, breakdown is triggered due to the generation and accumulation of traps in the dielectric layer during the application of electrical stress.

[0087] For example, assuming that the aging and breakdown of the oxide layer is a thermodynamic process, the thermal stress and the applied electric field increase the angle of the silicon-oxygen covalent bond Si-O-Si from the initial 120° to more than 150°, forming an oxygen vacancy structure and a Si-Si weak bond. After the Si-Si bond breaks, a hole trap appears. The enhanced electric field accelerates the breaking of the covalent bond, leading to the breakdown of the oxide layer.

[0088] 3. Hot Carrier Injection (HCI)

[0089] The HCI effect in metal-oxide-semiconductor (MOS) tubes originates from the continuous reduction of device feature size. Since the input voltage of the device does not decrease proportionally, the lateral and longitudinal electric fields in the channel increase significantly. The high electric field accelerates the movement of carriers, thereby converting the carriers into hot carriers with high energy. When the carrier energy is large enough, it can be directly injected or tunneled into silicon dioxide SiO2 to form trapped charges, causing the cut-off voltage and linear region transconductance of the MOS tube to drift.

[0090] In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order; "and / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship; "multiple" refers to two or more.

[0091] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the application background.

[0092] At present, the failure of the chip's driving circuit often leads to the failure of the chip's rows or multiple rows. Taking the dynamic random access memory (DRAM) chip as an example, in order to improve the density of DRAM storage cells during production, the word line driving circuit is usually equipped with multiple sub-word lines, each of which is connected to multiple storage cells, such as Figure 1 As shown, the DRAM driving circuit includes a first word line 101, a second word line ( Figure 1 1021-102n), at least one selection line ( Figure 1 1031-103n), an inverter N1 and at least one selection transistor ( Figure 1 Each second word line is connected to a plurality of DRAM memory cells.

[0093] once Figure 1 If the DRAM driving circuit shown fails, the DRAM storage unit connected to the second word line cannot receive the driving voltage, which leads to the failure of a row or multiple rows of the chip.

[0094] In the manufacturing process of DRAM chips, the first word line and the second word line are distributed in different layers and connected through metal contacts (MCs), and the wiring spacing is extremely small. Failures of shorting between metal contacts and word lines and misalignment of metal contacts often occur, which greatly increases the risk of TDDB, thereby reducing the driving capability of the driving circuit.

[0095] In addition, during use, the voltage difference between the source and drain of the selection transistor is often large, which greatly increases the risk of HCI, thereby reducing the driving capability of the driving circuit.

[0096] However, the current chip aging test method cannot trigger the failure of the driving circuit of a type of chip such as DRAM, which leads to the flow of defective chips with potential problems into the market, causing the reliability of computer equipment using defective chips to decrease.

[0097] Therefore, how to improve the speed and accuracy of chip aging detection in response to the problem of row or multi-row failure of chips is an urgent problem to be solved.

[0098] Based on the above problems, the embodiments of the present application provide a chip aging method and device for improving the speed and accuracy of chip aging detection.

[0099] The chip aging method provided by the exemplary embodiment of the present application is described below in combination with the application scenarios described above and with reference to the accompanying drawings. It should be noted that the above application scenarios are only shown to facilitate understanding of the principles of the present application, and the implementation methods of the present application are not limited in this regard.

[0100] like Figure 2 As shown, a driving circuit of the present application includes an inverter N1 and at least one selection transistor.

[0101] The aging device 204 is connected to the input end of the inverter N1 through the first word line 101, the aging device 204 is connected to the gate of at least one selection transistor through the selection line, and the first power supply terminal Vhigh of the inverter N1 is connected to the high voltage; the output end of the inverter N1 is connected to the drain of at least one selection transistor through the second word line, and the second power supply terminal Vbb of the inverter N1 and the source of each selection transistor are connected to the low voltage.

[0102] For example, Figure 3 As shown, the inverter N1 includes a P-type transistor and an N-type transistor ( Figure 3 The upper transistor in the inverter N1 is a P-type transistor, and the lower transistor is an N-type transistor). The gate of the P-type transistor is connected to the gate of the N-type transistor to form the input terminal of the inverter N1; the source of the P-type transistor is connected to the drain of the N-type transistor to form the output terminal of the inverter N1; the drain of the P-type transistor constitutes the first power supply terminal Vhigh of the inverter N1; and the source of the N-type transistor constitutes the second power supply terminal Vbb of the inverter N1.

[0103] The principle of accelerating the time-dependent breakdown of the excited medium TDDB is explained below in combination with the driving circuit structure:

[0104] When the thickness of the field oxide layer between the first word line and the second word line is much greater than 5 nm, the dielectric breakdown phenomenon generally obeys the thermochemical breakdown model, which is shown in Formula 1:

[0105]

[0106] Where TTF represents the failure time; A is a constant related to materials and processes; γ is the electric field acceleration factor related to temperature; E ox is the electric field applied on the dielectric layer; E a is the activation energy, that is, the energy required for crystal atoms to leave the equilibrium position and migrate to another new equilibrium or non-equilibrium position, that is, the energy required to start a physical and chemical process; k is the Boltzmann constant, and T represents the temperature.

[0107] From formula 1, we can see that:

[0108] The failure time TTF caused by dielectric breakdown is mainly affected by E ox and the influence of temperature T.

[0109] It should be noted that E ox The dielectric layer characterized may be a field oxide layer. The greater the electric field applied to the dielectric layer, the shorter the failure time TTF. In addition, the effect of temperature T on TTF obeys the Arrhenius equation. The higher the temperature T, the shorter the failure time TTF.

[0110] In addition, the effects of DC stress and AC stress on TDDB failure time are also different. By applying DC stress with a voltage of 2.9V, high-frequency AC stress, and low-frequency AC stress to the input end of inverter N1, we get Figure 4 As shown in the accelerated test simulation diagram. Figure 4 As shown, the high-frequency AC stress frequency is 1kHz, the low-frequency AC stress frequency is 100Hz, the horizontal axis of the simulation graph is the accelerated test time, and the vertical axis is the shape factor β of the Weibull distribution. The larger the β value, the lower the reliability and the higher the failure rate.

[0111] observe Figure 4 It can be seen that the TDDB failure time of the medium is strongly related to the frequency of change of the applied electric field, that is, the stress frequency applied to the dielectric layer. Under the same acceleration time, when the voltage stress of the same magnitude is applied, the β value corresponding to the DC stress is greater than the β value corresponding to the AC stress, and the β value corresponding to the high-frequency AC stress is greater than the β value corresponding to the low-frequency AC stress.

[0112] Therefore, compared with high-frequency and low-frequency AC stress, DC stress has the greatest accelerating effect on TDDB.

[0113] For example, for a DRAM chip with an operating frequency of 100 KHz and an operating temperature of 55° C., the acceleration factor of DC stress can reach more than 100 times. a When the accelerated test temperature is 105°C, the temperature acceleration is about 33 times, and the combined acceleration effect of high temperature and DC stress is about 3300 times.

[0114] Based on the above principle of accelerated excitation of TDDB, the chip aging method of this application is introduced below:

[0115] Embodiment 1

[0116] The chip aging method of the present application includes:

[0117] The aging device 204 outputs a first level to the inverter N1.

[0118] It should be noted that the first level is used to form a direct current electric field between the input terminal and the output terminal of the inverter N1.

[0119] Exemplarily, the aging device 204 outputs a high level to the inverter N1. After the inverting action of the inverter N1, the output end of the inverter N1 outputs a low level. Therefore, the oxide layer between the input end and the output end of the inverter N1 forms a maximum voltage difference, that is, a maximum electric field is formed. This electric field can accelerate the time-dependent breakdown of the excitation medium, thereby accelerating the aging of the driving circuit.

[0120] At the same time, since the traditional DRAM chip aging method uses alternating current to continuously change the input level of the inverter N1, the electric field applied to the dielectric layer is constantly changing, so AC stress is applied. The technical solution disclosed in the present application maintains the input level of the input end of the inverter N1 stable, which is equivalent to applying an electric field of a DC nature, that is, applying DC stress, so it can further accelerate the time-dependent breakdown of the excitation medium, thereby accelerating the aging of the driving circuit.

[0121] Embodiment 2

[0122] The chip aging method of the present application includes:

[0123] The aging device 204 outputs the first level to the inverter N1 and outputs the fourth level to the gate of the selection transistor.

[0124] It should be noted that the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

[0125] Exemplarily, the aging device 204 outputs a high level to the inverter N1. After the inversion of the inverter N1, the output terminal of the inverter N1 outputs a low level, so a maximum electric field is formed between the input terminal and the output terminal of the inverter N1.

[0126] At the same time, the technical solution disclosed in the present application maintains the input level of the input end of the inverter N1 stable, which is equivalent to applying a DC stress.

[0127] In addition, taking the selection transistor as an N-type transistor as an example, the aging device 204 outputs a low level, i.e., the fourth level, to the gate of the selection transistor, and the path between the source and drain of the selection transistor is cut off, thereby avoiding voltage fluctuations at the output end of the inverter caused by the conduction of the source and drain of the selection transistor, further ensuring the stability of the DC electric field, and accelerating the time-dependent breakdown of the excitation medium.

[0128] Embodiment 3

[0129] The chip aging method of the present application includes:

[0130] The aging device 204 outputs the first level to the inverter N1 and outputs the fourth level to the gate of the selection transistor, so as to adjust the ambient temperature of the driving circuit to be higher than the first preset temperature.

[0131] It should be noted that the first preset temperature is the operating temperature of the driving circuit, such as 55°C.

[0132] For example, when the aging device 204 controls the dielectric layer of the inverter to generate a DC electric field, the ambient temperature of the driving circuit is adjusted to be higher than the operating temperature by adjusting the temperature in the greenhouse and reducing the speed of the test fan, thereby forming a high temperature condition and further accelerating the time-induced breakdown of the dielectric.

[0133] The following is an explanation of the principle of accelerated hot carrier injection HCI in combination with the driving circuit structure:

[0134] When the channel length is the same, the larger the voltage difference between the source and the drain of the selection transistor is, the more susceptible the selection transistor is to hot carrier degradation, and similar to the above-mentioned TDDB acceleration test, DC stress has a greater excitation effect on HCI than AC stress.

[0135] In addition, low temperature environment can induce hot carrier degradation of the select transistor.

[0136] For example, for a DRAM chip with an operating frequency of 100 KHz and an operating temperature of 55° C., when the activation energy of hot carrier degradation E a When the accelerated test temperature is -0.2ev, and the temperature acceleration is about 10 times when the accelerated test temperature is -25℃, the combined acceleration effect of low temperature and DC stress is about 500 to 1000 times.

[0137] Based on the above principle of accelerated excitation of HCI, the chip aging method of the present application is introduced below:

[0138] Embodiment 1

[0139] The chip aging method of the present application includes:

[0140] The aging device 204 outputs the second level to the inverter N1 and outputs the third level to the gate of the selection transistor.

[0141] It should be noted that the second level is used to control the conduction of the path between the first power supply terminal Vhigh and the output terminal; the third level is used to form a direct current electric field between the source and drain of the selection transistor.

[0142] For example, Figure 3As shown, the first power supply terminal Vhigh is connected to a 3.8V high voltage, and the voltage of the second power supply terminal Vbb is connected to a -0.3V low voltage. The aging device 204 applies a low level, i.e., the second level, to the inverter N1, thereby controlling the drain voltage of the selection transistor to be 3.8V; the aging device 204 outputs a high level, i.e., the third level, to the gate of the selection transistor, thereby controlling the path between the source and drain of the selection transistor to be turned on; and because the source of the selection transistor is connected to -0.3V, a maximum voltage difference of 4.1V is formed between the source and drain of the selection transistor, i.e., a maximum electric field is formed. This electric field can accelerate the degradation of the excitation hot carriers, thereby accelerating the aging of the drive circuit.

[0143] At the same time, during the HCI aging treatment of the driving circuit, the present application maintains the second level and the third level stable, which is equivalent to applying an electric field of a DC nature to the selection transistor, that is, DC stress. DC stress has a greater accelerating excitation effect on hot carrier degradation than AC stress, so it can further accelerate the aging of the driving circuit.

[0144] Embodiment 2

[0145] The chip aging method of the present application includes:

[0146] The aging device 204 outputs the second level to the inverter N1, outputs the third level to the gate of the selection transistor, and adjusts the ambient temperature of the driving circuit to be lower than the second preset temperature.

[0147] It should be noted that the second preset temperature is room temperature, such as 25°C.

[0148] Exemplarily, when the aging device 204 controls the DC electric field to be formed between the source and drain of the selection transistor, the ambient temperature of the driving circuit is adjusted to be lower than the normal temperature by means of greenhouse temperature adjustment, reducing the speed of the test fan, etc., to form a low temperature condition, further accelerating the excitation of hot carrier degradation.

[0149] In summary, the chip aging method disclosed in this application is based on the principle of accelerated excitation of TDDB and HCI, and accelerates the aging of the driving circuit by forming a maximum DC electric field and adjusting the ambient temperature. The driving circuit with quality problems fails after aging, thereby improving the speed and accuracy of chip aging detection and avoiding the problem of row or multiple row failures of chips after leaving the factory.

[0150] Based on the same technical concept, the embodiment of the present application also provides a chip aging method, such as Figure 5 As shown, the driving circuit of the chip includes an inverter N1, a status decoder 501 and at least one selection transistor;

[0151] The aging device 204 is respectively connected to the input end of the inverter N1 and the first end of the status decoder 501; the second end of the status decoder 501 is respectively connected to the gate of at least one selection transistor; the output end of the inverter N1 is connected to the drain of at least one selection transistor; the first power supply end Vhigh of the inverter N1 is connected to a high voltage; the second power supply end of the inverter N1 and the source of each selection transistor are connected to a low voltage.

[0152] Based on the above-mentioned accelerated excitation TDDB principle, another chip aging method of the present application is introduced below:

[0153] Embodiment 1

[0154] The chip aging method of the present application includes:

[0155] The aging device 204 outputs a first level to the inverter N1.

[0156] Exemplarily, the aging device 204 outputs a high level to the inverter N1. After the inverting action of the inverter N1, the output end of the inverter N1 outputs a low level. Therefore, the oxide layer between the input end and the output end of the inverter N1 forms a maximum voltage difference, that is, a maximum electric field is formed. This electric field can accelerate the time-dependent breakdown of the excitation medium, thereby accelerating the aging of the driving circuit.

[0157] At the same time, the technical solution disclosed in the present application maintains the input level of the input end of the inverter N1 stable, which is equivalent to applying an electric field of a DC nature, that is, applying DC stress, so it can further accelerate the time-dependent breakdown of the excitation medium, thereby accelerating the aging of the drive circuit.

[0158] Embodiment 2

[0159] The chip aging method of the present application includes:

[0160] The aging device 204 outputs the first level to the inverter N1, and controls the level decoder 501 to output the fourth level to the gate of the selection transistor.

[0161] Exemplarily, the aging device 204 outputs a high level to the inverter N1. After the inversion of the inverter N1, the output terminal of the inverter N1 outputs a low level, so a maximum electric field is formed between the input terminal and the output terminal of the inverter N1.

[0162] At the same time, the technical solution disclosed in the present application maintains the input level of the input end of the inverter N1 stable, which is equivalent to applying a DC stress.

[0163] In addition, taking the selection transistor as an N-type transistor as an example, the status decoder 501 outputs a low level, that is, the fourth level, to the gate of the selection transistor according to the control signal of the aging device 204, and the path between the source and drain of the selection transistor is cut off, thereby avoiding the voltage fluctuation at the output end of the inverter caused by the source and drain of the selection transistor being turned on, further ensuring the stability of the DC electric field, and accelerating the time-dependent breakdown of the excitation medium.

[0164] Embodiment 3

[0165] The chip aging method of the present application includes:

[0166] The aging device 204 outputs the first level to the inverter N1 and outputs the fourth level to the gate of the selection transistor, so as to adjust the ambient temperature of the driving circuit to be higher than the first preset temperature.

[0167] It should be noted that the first preset temperature is the operating temperature of the driving circuit, such as 55°C.

[0168] For example, when the aging device 204 controls the dielectric layer of the inverter to generate a DC electric field, the ambient temperature of the driving circuit is adjusted to be higher than the operating temperature by adjusting the temperature in the greenhouse and reducing the speed of the test fan, thereby forming a high temperature condition and further accelerating the time-induced breakdown of the dielectric.

[0169] Based on the above-mentioned accelerated excitation HCI principle, another chip aging method of the present application is introduced below:

[0170] Embodiment 1

[0171] The chip aging method of the present application includes:

[0172] The aging device 204 outputs the second level to the inverter N1, and controls the level decoder 501 to output the third level to the gate of the selection transistor.

[0173] Exemplarily, the aging device 204 applies a low level, i.e., the second level, to the inverter N1, thereby controlling the drain voltage of the selection transistor to access the high voltage. The aging device 204 outputs a control signal to the status decoder 501, and the control signal is used to instruct the status decoder 501 to output a third level to the gates of the selection transistors M1 to M6, thereby turning on the path between the source and drain of the selection transistor.

[0174] At this time, the maximum voltage difference is formed between the source and drain of the selection transistor, that is, the maximum electric field is formed. This electric field can accelerate the degradation of hot carriers, thereby accelerating the aging of the driving circuit.

[0175] At the same time, during the HCI aging treatment of the driving circuit, the present application maintains the second level and the third level stable, which is equivalent to applying an electric field of a DC nature to the selection transistor, that is, DC stress. DC stress has a greater accelerating excitation effect on hot carrier degradation than AC stress, so it can further accelerate the aging of the driving circuit.

[0176] Embodiment 2

[0177] The chip aging method of the present application includes:

[0178] The aging device 204 outputs the second level to the inverter N1, controls the level decoder 501 to output the third level to the gate of the selection transistor, and adjusts the ambient temperature of the driving circuit to be lower than the second preset temperature.

[0179] It should be noted that the second preset temperature is room temperature, such as 25°C.

[0180] Exemplarily, the aging device 204 outputs the second level to the inverter N1 and controls the level decoder 501 to output the third level to the gate of the selection transistor to turn on the path between the source and drain of the selection transistor and form a maximum DC electric field between the source and drain of the selection transistor.

[0181] At the same time, the aging device 204 adjusts the ambient temperature of the driving circuit to be lower than the normal temperature by means of greenhouse temperature adjustment, reducing the speed of the test fan, etc., to form a low-temperature condition, further accelerating the degradation of the excited hot carriers.

[0182] Based on the same technical concept, the embodiment of the present application also provides an aging device. The implementation of the device can refer to the implementation of the above-mentioned chip aging method, and the repeated parts will not be repeated.

[0183] like Figure 6 As shown, the aging device 204 includes a controller 601 and a level output unit 602; the aging device 204 is connected to the driving circuit of the chip;

[0184] The driving circuit includes an inverter N1 and at least one selection transistor;

[0185] The controller 601 is connected to the level output unit 602; the level output unit 602 is respectively connected to the input terminal of the inverter N1 and the gate of at least one selection transistor; the output terminal of the inverter N1 is connected to the drain of at least one selection transistor; the first power supply terminal Vhigh of the inverter N1 is connected to a high voltage; the second power supply terminal of the inverter N1 and the source of each selection transistor are connected to a low voltage;

[0186] A level output unit 602, used for outputting a level;

[0187] The controller 601 is used to control the level output unit 602 to output a first level to the inverter N1, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter N1;

[0188] or,

[0189] The controller 601 is used to control the level output unit 602 to output a second level to the inverter N1, wherein the second level is used to control the conduction of a path between the first power supply terminal Vhigh and the output terminal;

[0190] And the level output unit 602 is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current field between the source and drain of the selection transistor.

[0191] In one embodiment, when the level output unit 602 is controlled to output the first level to the inverter N1, the controller 601 is further configured to:

[0192] The control level output unit 602 outputs a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

[0193] In one embodiment, the aging device 204 further includes a temperature control layer 603, and the temperature control layer 603 is used to provide an ambient temperature for the driving circuit.

[0194] In one embodiment, when the level output unit 602 is controlled to output the first level to the inverter N1, the controller 601 is further configured to:

[0195] The temperature of the temperature control layer 603 is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

[0196] In one embodiment, when the control level output unit 602 outputs the second level to the inverter N1, the controller 601 is further configured to:

[0197] The temperature of the temperature control layer 603 is adjusted to be higher than or lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

[0198] Based on the same technical concept, the embodiment of the present application also provides another aging device. The implementation of the device can refer to the implementation of the above-mentioned chip aging method, and the repeated parts will not be repeated.

[0199] like Figure 7 As shown, the aging device 204 includes a controller 601 and a level output unit 602; the aging device 204 is connected to the driving circuit of the chip;

[0200] The driving circuit includes an inverter N1, a status decoder 501 and at least one selection transistor;

[0201] The controller 601 is connected to the level output unit 602 and the first end of the level decoder 501 respectively; the second end of the level decoder 501 is connected to the gate of at least one selection transistor respectively; the level output unit 602 is connected to the input end of the inverter N1; the output end of the inverter N1 is connected to the drain of at least one selection transistor; the first power supply end Vhigh of the inverter N1 is connected to a high voltage; the second power supply end of the inverter N1 and the source of each selection transistor are connected to a low voltage;

[0202] A level output unit 602, used for outputting a level;

[0203] The controller 601 is used to control the level output unit 602 to output a first level to the inverter N1, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter N1;

[0204] or,

[0205] The controller 601 is used to control the level output unit 602 to output a second level to the inverter N1, wherein the second level is used to control the conduction of a path between the first power supply terminal Vhigh and the output terminal;

[0206] And the level decoder 501 is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current field between the source and drain of the selection transistor.

[0207] In one embodiment, when the level output unit 602 is controlled to output the first level to the inverter N1, the controller 601 is further configured to:

[0208] The control level decoder 501 outputs a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

[0209] In one embodiment, the aging device 204 further includes a temperature control layer 603, and the temperature control layer 603 is used to provide an ambient temperature for the driving circuit.

[0210] In one embodiment, when the level output unit 602 is controlled to output the first level to the inverter N1, the controller 601 is further configured to:

[0211] The temperature of the temperature control layer 603 is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

[0212] In one embodiment, when the control level output unit 602 outputs the second level to the inverter N1, the controller 601 is further configured to:

[0213] The temperature of the temperature control layer 603 is adjusted to be higher than or lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

[0214] Based on the same technical concept, the embodiment of the present application also provides a computer device, such as Figure 8 As shown, the computer device includes a processor 801 and a memory 802. The memory 802 stores a computer program. When the processor 801 executes the computer program, any of the above-mentioned aging detection methods is implemented.

[0215] Exemplarily, the processor 801 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0216] It should be noted that the memory 802 mentioned in the embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0217] It should be noted that when the processor 801 is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory 802 (storage module) can be integrated into the processor.

[0218] It should be noted that the memory 802 described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0219] Based on the same technical concept, an embodiment of the present application also provides a computer storage medium, including a program or an instruction, which enables any of the above methods to be executed when the program or the instruction is run on a computer.

[0220] Based on the same technical concept, an embodiment of the present application also provides a chip, which is coupled to a memory and is used to read and execute program instructions stored in the memory so that any of the above methods is executed.

[0221] Based on the same technical concept, an embodiment of the present application also provides a computer program product, including instructions, which, when run on a computer, enables any of the above methods to be executed.

[0222] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0223] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0224] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be noted that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0225] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0226] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0227] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of protection of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip aging method, It is characterized in that The chip is executed by an aging device, wherein the driving circuit of the chip includes an inverter, a status decoder and at least one selection transistor; The first end of the status decoder is connected to the aging device; the second end of the status decoder is respectively connected to the gate of the at least one selection transistor; the input end of the inverter is connected to the aging device, and the output end of the inverter is connected to the drain of the at least one selection transistor; The first power supply terminal of the inverter is connected to a high voltage; The second power supply terminal of the inverter and the source of each selection transistor are connected to a low voltage; The aging method comprises: Outputting a first level to the inverter, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter; Alternatively, the aging method comprises: Outputting a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal; The level decoder is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

2. The method according to claim 1, It is characterized in that When the first level is output to the inverter, the method further comprises: The level decoder is controlled to output a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

3. The method according to claim 1 or 2, It is characterized in that When the first level is output to the inverter, the method further comprises: The ambient temperature of the driving circuit is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

4. The method according to claim 1 or 2, It is characterized in that When the second level is output to the inverter, the method further comprises: The ambient temperature of the driving circuit is adjusted to be lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

5. A chip aging method, It is characterized in that The method is performed by an aging device, wherein the driving circuit of the chip includes an inverter and at least one selection transistor; The input end of the inverter is connected to the aging device, the output end of the inverter is connected to the drain of the at least one selection transistor; the gate of the at least one selection transistor is connected to the aging device; The first power supply terminal of the inverter is connected to a high voltage; The second power supply terminal of the inverter and the source of each selection transistor are connected to a low voltage; The aging method comprises: Outputting a first level to the inverter, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter; Alternatively, the aging method comprises: Outputting a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal; And output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

6. The method according to claim 5, It is characterized in that When the first level is output to the inverter, the method further comprises: A fourth level is output to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

7. The method according to claim 5 or 6, It is characterized in that When the first level is output to the inverter, the method further comprises: The ambient temperature of the driving circuit is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

8. The method according to claim 5 or 6, It is characterized in that When the second level is output to the inverter, the method further comprises: The ambient temperature of the driving circuit is adjusted to be lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

9. An aging device, It is characterized in that The aging device includes a controller and a level output unit; the aging device is connected to a driving circuit of the chip; The driving circuit includes an inverter and at least one selection transistor; The controller is connected to the level output unit; the input end of the inverter is connected to the level output unit, the output end of the inverter is connected to the drain of the at least one selection transistor, and the gate of the at least one selection transistor is connected to the level output unit; The first power supply terminal of the inverter is connected to a high voltage; The second power supply terminal of the inverter and the source of each selection transistor are connected to a low voltage; The level output unit is used to output the level; The controller is used to control the level output unit to output a first level to the inverter, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter; or, The controller is used to control the level output unit to output a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal; The level output unit is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

10. The device according to claim 9, It is characterized in that When controlling the level output unit to output the first level to the inverter, the controller is further used for: The level output unit is controlled to output a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

11. The device according to claim 9 or 10, It is characterized in that The aging device further comprises a temperature control layer, and the temperature control layer is used to provide an ambient temperature for the driving circuit.

12. The device according to claim 11, It is characterized in that When controlling the level output unit to output the first level to the inverter, the controller is further used for: The temperature of the temperature control layer is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

13. The device according to claim 11, It is characterized in that When controlling the level output unit to output the second level to the inverter, the controller is further used for: The temperature of the temperature control layer is adjusted to be higher than or lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

14. An aging device, It is characterized in that The aging device includes a controller and a level output unit; the aging device is connected to a driving circuit of the chip; The driving circuit includes an inverter, a status decoder and at least one selection transistor; The first end of the status decoder is connected to the controller and the level output unit respectively; the second end of the status decoder is connected to the gate of the at least one selection transistor respectively; the input end of the inverter is connected to the level output unit; the output end of the inverter is connected to the drain of the at least one selection transistor; the first power supply end of the inverter is connected to a high voltage; the second power supply end of the inverter and the source of each selection transistor are connected to a low voltage; The level output unit is used to output the level; The controller is used to control the level output unit to output a first level to the inverter, wherein the first level is used to form a direct current electric field between an input terminal and an output terminal of the inverter; or, The controller is used to control the level output unit to output a second level to the inverter, wherein the second level is used to control the conduction of a path between the first power supply terminal and the output terminal; The level decoder is controlled to output a third level to the gate of the selection transistor, wherein the third level is used to form a direct current electric field between the source and drain of the selection transistor.

15. The device according to claim 14, It is characterized in that When controlling the level output unit to output the first level to the inverter, the controller is further used for: The level decoder is controlled to output a fourth level to the gate of the selection transistor, wherein the fourth level is used to control the path between the source and drain of the selection transistor to be turned off.

16. The device according to claim 14 or 15, It is characterized in that The aging device further comprises a temperature control layer, and the temperature control layer is used to provide an ambient temperature for the driving circuit.

17. The device according to claim 16, It is characterized in that When controlling the level output unit to output the first level to the inverter, the controller is further used for: The temperature of the temperature control layer is adjusted to be higher than a first preset temperature, wherein the first preset temperature is the operating temperature of the driving circuit.

18. The device according to claim 16, It is characterized in that When controlling the level output unit to output the second level to the inverter, the controller is further used for: The temperature of the temperature control layer is adjusted to be higher than or lower than a second preset temperature, wherein the second preset temperature is a normal temperature.

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