Address generation system

Abstract

Embodiments of the present application provide an address generation method and device, computer equipment and a storage medium. The method comprises: receiving a target instruction, dividing a general purpose register address corresponding to the target instruction into a low address and a high address; adding the low address and an immediate number, and determining whether there is a borrow or carry of the high address in the adding process; if not, performing a permission check on the high address; if so, pausing the current pipeline stage for one beat, performing a borrow or carry calculation on the high address, and storing the calculated addition value in a designated memory, so as to perform a permission check on the high address of the addition value after the pause; determining a memory access address of the target instruction according to the addition value of the low address and the immediate number and the high address that passes the permission check, only adding the low address and the immediate number after truncation, and only checking the high address at the APC, so that the timing of the AGU adder is optimized while the timing of the APC is disconnected.

Description

[0001] This application is a divisional application of patent application number 202410479875.8, entitled "Address Generation Method, Apparatus, Computer Equipment and Storage Medium". Technical Field

[0002] This application relates to the field of processor technology, and more specifically, to an address generation system. Background Technology

[0003] Existing AGUs (address generation units) are typically located within the processor's execution module. The AGU is used to generate the addresses corresponding to memory access operations. The structure of the execution module is as follows: Figure 1 As shown.

[0004] In related technologies, the adder section of the AGU adds the source operand at the first register index of the instruction to the sign-extended immediate value, for example, the instruction: load x10, imm(x9); Figure 2 As shown, for a 32-bit processor, the address width of the x9 is 32 bits, and the immediate value (imm) is generally 12 bits. The address addition part is 32 bits of data plus 12 bits of data. If the processor core is 64-bit, it is 64 bits of data plus 12 bits of data.

[0005] See Figure 1 After obtaining the correct memory access address from the adder, the instruction passes through the APC (address permission check) unit. This unit restricts the memory access location based on the processor's settings. Unauthorized accesses will not access memory (or will not cause memory access that alters the processor's data or state), resulting in a synchronization exception. If authorized, for read accesses, the corresponding data at the accessed memory address is retrieved and a read completion response is returned; for write accesses, the data is written to the corresponding accessed memory address and a write completion response is returned. Memory access operations are then sent to the corresponding memory module via the LSU (load store unit) after the AGU.

[0006] The AGU generates the memory access address for read / write instructions. These instructions need to add the source operand indexed by the first register to the sign-extended immediate value to obtain the final memory access address. Therefore, theoretically, an adder is required. However, current technology for 32-bit processors uses a 32-bit address plus a 12-bit immediate value. This results in poor adder area and timing. For 64-bit processors, a 64-bit address plus a 12-bit immediate value is used, further impacting timing. After obtaining the address from the adder, APC is used for memory protection, which also includes combinational logic. Therefore, after the AGU's adder and APC's memory protection, the address generation timing becomes very long. If the AGU and APC were completed in one clock cycle, it would limit the processor's maximum clock frequency, thus affecting processor performance. Summary of the Invention

[0007] This application provides an address generation method, apparatus, computer device, and storage medium.

[0008] A first aspect of this application provides an address generation method, comprising:

[0009] Receive the target instruction and divide the general purpose register address corresponding to the target instruction into low-order address and high-order address;

[0010] Sum the low-order address with the immediate value and determine whether there is a borrow or carry to the high-order address during the summation process;

[0011] If there is no borrow or carry to the high-order address during the summation process, an access control check is performed on the high-order address.

[0012] If there is a borrow or carry operation on the high-order address during the summation process, the current pipeline stage pauses for one clock cycle to perform the borrow or carry operation on the high-order address and stores the calculated summation value in the designated memory. In the next clock cycle after the pause, the high-order address of the summation value is used for permission checks.

[0013] The memory access address of the target instruction is determined by summing the low-order address and the immediate value, and by the high-order address that passed the permission check.

[0014] In an optional embodiment of this application, the number of bits in the low-order address is greater than or equal to the number of bits in the immediate value.

[0015] In an optional embodiment of this application, the summing of the low-order address and the immediate value includes:

[0016] If the number of bits in the low-order address is equal to the number of bits in the immediate value, simply add the low-order address and the immediate value.

[0017] If the number of bits in the lower address is greater than the number of bits in the immediate value, the number of bits in the immediate value is sign-extended to obtain an immediate value with the same number of bits as the lower address. The lower address and the extended immediate value are then summed.

[0018] In an optional embodiment of this application, determining whether the summing process involves a borrow or carry to the higher-order address includes:

[0019] If the immediate value is positive, determine whether there is a carry to the higher-order address during the summation process;

[0020] If the immediate value is negative, determine whether the summing process involves borrowing from the higher-order address.

[0021] In an optional embodiment of this application, determining the memory access address of the target instruction based on the sum of the low-order address and the immediate value and the high-order address that passed the permission check includes:

[0022] The sum of the low-order address and the immediate value, along with the high-order address that passed the permission check, are concatenated to obtain the memory access address of the target instruction.

[0023] In an optional embodiment of this application, the method further includes:

[0024] If the high-order address fails the permission check, an exception flag is generated and sent to the exception handling unit.

[0025] In an optional embodiment of this application, the method further includes:

[0026] If the target instruction is a read instruction, retrieve the data at the memory access address of the target instruction and return a response indicating that the read is complete.

[0027] If the target instruction is a write instruction, the data in the target instruction is written to the memory access address of the target instruction, and a write completion response is returned.

[0028] A second aspect of this application provides an address generation apparatus, comprising:

[0029] The partitioning module is used to receive the target instruction and divide the general purpose register address corresponding to the target instruction into low-order and high-order addresses.

[0030] The first determining module is used to sum the low-order address and the immediate value, and determine whether there is a borrow or carry to the high-order address during the summing process;

[0031] The pause module is used to pause the current pipeline for one clock cycle when there is a borrow or carry to the high-order address during the summation process, and to perform the borrow or carry calculation on the high-order address.

[0032] The checking module is used to perform permission checks on the high-order address if there is no borrow or carry to the high-order address during the summing process, and to store the calculated sum value in the designated memory if there is a borrow or carry to the high-order address during the summing process, so that permission checks on the high-order address of the sum value can be performed in the next clock after the pause.

[0033] The second determination module is used to determine the memory access address of the target instruction based on the sum of the low-order address and the immediate value and the high-order address that has passed the permission check.

[0034] A third aspect of this application provides a computer device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0035] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims. Attached Figure Description

[0036] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0037] Figure 1 This is a schematic diagram of the structure of an execution unit in the prior art;

[0038] Figure 2 This is a schematic diagram illustrating the summation process of a 32-bit address and a 12-bit immediate value using an AGU adder in the prior art.

[0039] Figure 3 A flowchart illustrating an address generation method provided in one embodiment of this application;

[0040] Figure 4 This is a schematic diagram illustrating the process of adding a 32-bit address and a 12-bit immediate value using an address generation method provided in one embodiment of this application.

[0041] Figure 5 A schematic diagram of the structure of an address generation circuit for summing a 32-bit address and a 12-bit immediate value, provided in one embodiment of this application;

[0042] Figure 6 This is a schematic diagram of an address generation device provided in one embodiment of this application;

[0043] Figure 7 This is a schematic diagram of the address generation system structure provided in one embodiment of this application;

[0044] Figure 8 This is a schematic diagram of an address generation system structure provided in another embodiment of this application;

[0045] Figure 9 This is a schematic diagram of a computer device structure provided in one embodiment of this application. Detailed Implementation

[0046] In the process of developing this application, the inventors discovered that currently, using a 32-bit or 64-bit address plus a 12-bit immediate value results in poor adder area and timing.

[0047] To address the aforementioned issues, this application provides an address generation method that receives a target instruction and divides the general purpose register address corresponding to the target instruction into a low-order address and a high-order address. The low-order address is summed with an immediate value, and it is determined whether the summing process involves a borrow or carry to the high-order address. If the summing process does not involve a borrow or carry to the high-order address, a permission check is performed on the high-order address. If the summing process involves a borrow or carry to the high-order address, the current pipeline stage pauses for one clock cycle to borrow from the high-order address. Alternatively, a carry calculation can be performed, and the calculated sum is stored in a designated memory. In the next clock cycle after the pause, the high-order address of the sum is checked for permissions. The memory access address of the target instruction is determined based on the sum of the low-order address and the immediate value, and the high-order address that has passed the permission check. In 32-bit or 64-bit processors, the low-order and high-order bits are truncated when the AGU generates the address, and only the low-order bits and the immediate value are summed. At the APC, only the high-order bits are checked, which optimizes the timing of the AGU adder and disconnects the timing of the APC, thus optimizing the timing of the execution module.

[0048] The solutions in this application embodiment can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0049] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0050] Please see Figure 3 The address generation method provided in this application includes:

[0051] S1 receives the target instruction and divides the general purpose register address corresponding to the target instruction into a low-order address and a high-order address, wherein the number of bits in the low-order address is greater than or equal to the number of bits in the immediate value.

[0052] In this embodiment, when the immediate value is 12 bits and the general purpose register address is 32 bits, the number of bits in the low-order address can be, but is not limited to, 12, and the number of bits in the high-order address is 20. The number of bits in the low-order address can exceed 12.

[0053] In this embodiment, when the immediate value is 12 bits and the general purpose register address is 64 bits, the number of bits in the low-order address can be 12, and the number of bits in the high-order address is 52. The number of bits in the low-order address can exceed 12.

[0054] S2 sums the low-order address with the immediate value and determines whether there is a borrow or carry to the high-order address during the summing process.

[0055] In an optional embodiment of this application, the summing of the low-order address and the immediate value includes:

[0056] If the number of bits in the low-order address is equal to the number of bits in the immediate value, simply add the low-order address and the immediate value.

[0057] If the number of bits in the lower address is greater than the number of bits in the immediate value, the number of bits in the immediate value is sign-extended to obtain an immediate value with the same number of bits as the lower address. The lower address and the extended immediate value are then summed.

[0058] In an optional embodiment of this application, the sign extension of the immediate number includes:

[0059] Pad the least significant bit of the immediate value with zeros so that the number of bits in the resulting immediate value is equal to the number of bits in the least significant bit address.

[0060] The immediate value padded with zeros is sign-extended to obtain the extended immediate value, which is then used as the immediate value to sum with the lower-order address.

[0061] In an optional embodiment of this application, determining whether the summing process involves a borrow or carry to the higher-order address includes:

[0062] If the immediate value is positive, determine whether there is a carry to the higher-order address during the summation process;

[0063] If the immediate value is negative, determine whether the summing process involves borrowing from the higher-order address.

[0064] S3, if there is no borrow or carry to the high-order address during the summation process, perform an access control check on the high-order address.

[0065] S4, if there is a borrow or carry operation on the high-order address during the summation process, the current pipeline stage pauses for one clock cycle, performs the borrow or carry operation on the high-order address, and stores the calculated summation value in the designated memory. In the next clock cycle after the pause, the high-order address of the summation value is used for permission check.

[0066] In this embodiment, permission checks are performed on high-order addresses that do not have borrow or carry, or high-order addresses after borrow or carry. Compared with permission checks on complete memory access addresses in the prior art, there is no need to perform 32-bit or 64-bit addition calculations, which reduces the area of ​​the AGU adder, optimizes timing, optimizes the timing of the execution module, and reduces the number of bits for permission checks, which simplifies the permission check logic and further optimizes the timing of the execution module.

[0067] S5 determines the memory access address of the target instruction based on the sum of the low-order address and the immediate value, and the high-order address that has passed the permission check.

[0068] In an optional embodiment of this application, determining the memory access address of the target instruction based on the sum of the low-order address and the immediate value and the high-order address that passed the permission check includes:

[0069] The sum of the low-order address and the immediate value, along with the high-order address that passed the permission check, are concatenated to obtain the memory access address of the target instruction.

[0070] In an optional embodiment of this application, the method further includes:

[0071] If the high-order address fails the permission check, an exception flag is generated and sent to the exception handling unit.

[0072] In an optional embodiment of this application, the method further includes:

[0073] If the target instruction is a read instruction, retrieve the data at the memory access address of the target instruction and return a response indicating that the read is complete.

[0074] If the target instruction is a write instruction, the data in the target instruction is written to the memory access address of the target instruction, and a write completion response is returned.

[0075] See Figure 4Taking a 32-bit processor as an example, the 32-bit address of the instruction is divided into two parts, ab, of the lower 12 bits [11:0] and the higher 20 bits [31:12] (for a 64-bit processor, it is the lower 12 bits and the higher 52 bits). When performing addition calculations, only the 12th bit a part needs to be added or subtracted from the 12-bit imm immediate value to generate a 12-bit address as the offset address. When reading the address, only the b part needs to be concatenated with the a part to generate the corresponding memory access address. In practical applications, if no carry or borrow occurs, the accurate address can be generated in time by simply concatenating the b part with the a part. If a carry or borrow occurs, the simple concatenation will not be able to generate the address and will still affect the timing. Therefore, if a carry or borrow occurs, the pipeline will pause for one cycle. During this pause period, the carry or borrow value will be added to the b part. After a brief pause, the pipeline timing restarts, thus disconnecting the AGU's adder from the APC timing, thereby enhancing processor performance.

[0076] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0077] See Figure 5 Taking a 32-bit processor as an example, the pipeline register sends the 32-bit address of the instruction to rs1 (register 1). Register 1 divides the 32-bit address of the instruction into the lower 12 bits and the higher 20 bits. The higher 20 bits are sent to the MUX (data selector). The lower 12 bits are summed with the immediate value imm, and it is determined whether the lower address generates a carry or borrow with the higher address. If a carry or borrow occurs, the current pipeline stage pauses for one clock cycle, performs a carry or borrow calculation on the higher address, and stores the calculated sum as the pause address in the MUX. In the next clock cycle after the pause, APC selects the higher address of the pause address from the MUX for permission checks, and concatenates the higher address that passes the permission check with the sum of the lower address and the immediate value to form the memory access address of the target instruction. If no carry or borrow occurs, the higher 20 bits sent from register 1 to the MUX are used for permission checks, and the sum of the lower address and the immediate value and the higher address that passes the permission check are concatenated to form the memory access address of the target instruction.

[0078] Please see Figure 6 One embodiment of this application provides an address generation apparatus, comprising:

[0079] The partitioning module 11 is used to receive the target instruction and divide the general purpose register address corresponding to the target instruction into low-order address and high-order address;

[0080] The first determining module 12 is used to sum the low-order address and the immediate value, and determine whether there is a borrow or carry to the high-order address during the summing process;

[0081] The pause module 14 is used to pause the current pipeline for one clock cycle when there is a borrow or carry to the high-order address in the summation process, and to perform borrow or carry calculation on the high-order address.

[0082] The checking module 13 is used to perform permission checks on the high-order address if there is no borrow or carry to the high-order address in the summing process, and to store the calculated sum value in the designated memory if there is a borrow or carry to the high-order address in the summing process, so that permission checks on the high-order address of the sum value can be performed in the next clock after the pause.

[0083] The second determining module 15 is used to determine the memory access address of the target instruction based on the sum of the low-order address and the immediate value and the high-order address that has passed the permission check.

[0084] For specific limitations regarding the address generation device described above, please refer to the limitations on the address generation method above, which will not be repeated here. Each module in the address generation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0085] The address generation device of this application can be applied to, for example... Figure 7The address generation system shown includes an instruction fetch unit, a decoding unit, an execution unit, and an exception handling unit connected in sequence. The instruction fetch unit is used to fetch instructions and send the fetched instructions to the decoding unit. The decoding unit is used to receive instructions, decode the received instructions to obtain the general purpose register address and immediate value of the instructions, and send them to the execution unit. The execution unit is used to receive the general purpose register address and immediate value of the instructions, dispatch, execute, and deliver them. Read or write instructions need to be dispatched further by the AGU subunit of the ALU (Arithmetic Logic Unit). The main function of the AGU is to generate the memory access address for the read or write instruction. The AGU divides the general purpose register address corresponding to the target instruction into low-order and high-order addresses; it sums the low-order address with the immediate value and determines whether there is a borrow or carry to the high-order address during the summing process; if there is a borrow or carry to the high-order address during the summing process, the current pipeline stage pauses for one clock cycle to perform borrow or carry calculation on the high-order address; if there is no borrow or carry to the high-order address during the summing process, the APC performs a permission check on the high-order address; if there is a borrow or carry to the high-order address during the summing process, it stores the calculated sum value in the designated memory so that in the next clock cycle after the pause, the high-order address of the sum value is checked for permission to determine whether the address is valid; the AGU determines the memory access address of the target instruction based on the sum value of the low-order address and the immediate value and the high-order address that has passed the permission check. If a high-order address fails the permission check, an exception flag is generated and sent to the exception handling unit, which then generates an exception accordingly.

[0086] The address generation device of this application can be applied to, for example... Figure 8The address generation system shown includes an instruction fetch unit, a decoding unit, an execution unit, and an exception handling unit. The instruction fetch unit fetches instructions and sends them to the decoding unit. The decoding unit, connected to the instruction fetch unit, receives instructions, decodes them to obtain the general purpose register address and immediate value of the instructions, and then pipes them to the execution unit. The execution unit, connected to the decoding unit, has other units that receive the general purpose register address and immediate value of the instructions, dispatch, execute, and deliver them. These other units can be any one or more of the instruction fetch unit, decoding unit, and execution unit. Read or write instructions need to be dispatched further by the AGU subunit of the ALU (Arithmetic Logic Unit). The main function of the AGU is to generate the memory access address for the read or write instruction. The AGU divides the general purpose register address corresponding to the target instruction into low-order and high-order addresses; it sums the low-order address with the immediate value and determines whether there is a borrow or carry to the high-order address during the summing process; if there is a borrow or carry to the high-order address during the summing process, the current pipeline stage pauses for one clock cycle to perform borrow or carry calculation on the high-order address; if there is no borrow or carry to the high-order address during the summing process, the APC performs a permission check on the high-order address; if there is a borrow or carry to the high-order address during the summing process, it stores the calculated sum value in the designated memory so that in the next clock cycle after the pause, the high-order address of the sum value is checked for permission to determine whether the address is valid; the AGU determines the memory access address of the target instruction based on the sum value of the low-order address and the immediate value and the high-order address that has passed the permission check. If a high-order address fails the permission check, an exception flag is generated and flows through the pipeline to the exception handling unit. The exception handling unit generates an exception accordingly. There are other units between the exception handling unit and the execution unit. These other units can be any one or more of the instruction fetch unit, decoding unit, and execution unit.

[0087] In one embodiment, a computer device is provided, the internal structure of which can be as shown in the figure. Figure 9As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements one of the address generation methods described above. It includes: memory and a processor; the memory stores a computer program; and the processor, when executing the computer program, implements any step of the address generation method described above.

[0088] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, can perform any of the steps in the address generation method described above.

[0089] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0091] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0092] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0093] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0094] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An address generation system, characterized in that, It includes an instruction fetch unit, a decoding unit, an execution unit, and an exception handling unit connected in sequence. The execution unit includes an arithmetic logic unit and an address permission checking unit. The arithmetic logic unit includes an address generation unit. The instruction fetch unit is used to fetch instructions and send the fetched instructions to the decoding unit; The decoding unit is used to receive instructions, decode the received instructions to obtain the general purpose register address and immediate value of the instructions, and send the general purpose register address and immediate value of the instructions to the execution unit. The execution unit is used to receive the general purpose register address and immediate value of the instruction, and to dispatch, execute, and deliver the instruction; The address generation unit of the arithmetic logic unit is used to further dispatch read or write instructions, generate the memory access address of the read or write instruction, divide the general purpose register address corresponding to the target instruction into low-order address and high-order address; sum the low-order address with the immediate value, and determine whether there is a borrow or carry to the high-order address in the summing process; if there is a borrow or carry to the high-order address in the summing process, the current pipeline stage pauses for one clock cycle to perform borrow or carry calculation on the high-order address; the memory access address of the target instruction is determined based on the sum of the low-order address and the immediate value and the high-order address that has passed the permission check; The address permission check unit is used to perform permission checks on the high-order address when there is no borrow or carry to the high-order address during the summation process; if there is a borrow or carry to the high-order address during the summation process, the current pipeline stage pauses for one clock cycle, performs borrow or carry calculation on the high-order address, and stores the calculated sum value in a designated memory, so that in the next clock cycle after the pause, the high-order address of the sum value is checked for permission to determine whether the address is valid; if a high-order address fails the permission check, an exception flag is generated and transmitted to the exception handling unit; An exception handling unit is used to generate exceptions based on exception flags. in, The summation of the low-order address and the immediate value includes: when the number of bits in the low-order address is equal to the number of bits in the immediate value, directly summing the low-order address and the immediate value; when the number of bits in the low-order address is greater than the number of bits in the immediate value, sign-extending the number of bits in the immediate value to obtain an immediate value with the same number of bits in the low-order address, and summing the low-order address and the extended immediate value. Determining whether the summing process involves a borrow or carry to the higher-order address includes: determining whether the summing process involves a carry to the higher-order address when the immediate value is positive; and determining whether the summing process involves a borrow to the higher-order address when the immediate value is negative.

2. The address generation system according to claim 1, characterized in that, The number of bits in the lower-order address is greater than or equal to the number of bits in the immediate value.

3. The address generation system according to claim 1, characterized in that, The step of determining the memory access address of the target instruction based on the sum of the low-order address and the immediate value, and the high-order address that has passed the permission check, includes: The sum of the low-order address and the immediate value, along with the high-order address that passed the permission check, are concatenated to obtain the memory access address of the target instruction.

4. The address generation system according to claim 1, characterized in that, The execution unit is provided with other units between it and the decoding unit, which are used to receive the general purpose register address and immediate value of the instruction, and to dispatch, execute and deliver the instruction. The other units are any one or any combination of the instruction fetch unit, the decoding unit and the execution unit.

5. The address generation system according to claim 1, characterized in that, Other units are provided between the exception handling unit and the execution unit. These other units can be any one or any combination of the instruction fetching unit, the decoding unit, and the execution unit.

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