Fault information determination methods, devices and terminal equipment

Abstract

This application provides a method, apparatus, and terminal device for determining fault information. The method includes: acquiring configuration information of a memory, the configuration information including a first address of the memory and cell addresses of each storage cell in the memory; acquiring test information obtained by testing the memory, the test information including at least one stored data corresponding to each storage cell in the memory, the operating order of each storage cell, and a second address of the memory; and determining fault information present during the testing of the memory based on the memory configuration information and the memory test information. This improves the accuracy of determining the presence of faults during chip testing.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus and terminal device for determining fault information. Background Technology

[0002] The chip and test circuit can be connected via the access path sharing (sharebus) interface to test the memory in the chip through the test circuit.

[0003] Before testing the memory in a chip using a test circuit, simulation testing tools (such as Electronic Design Automation, EDA) can be used to perform simulated testing, thereby verifying the entire testing process. In related technologies, testing can be performed using simulation testing tools as follows: The description files for each memory in the chip are obtained. Based on the description files for each memory, the tester determines the test procedure and configuration file for the chip. According to the test procedure and configuration file, simulated testing is performed to obtain the test results.

[0004] In the above process, the test procedures and configuration files for the test chip are determined manually based on the description files of each memory chip. Inaccurate configuration files can lead to inaccurate test circuits, resulting in situations where not all memory chips in the chip are tested or internal memory faults cannot be accurately detected. This results in low accuracy in determining the presence of faults during chip testing. Summary of the Invention

[0005] This application provides a fault information determination method, apparatus, and terminal device to solve the problem of low accuracy in determining the presence of faults during chip testing.

[0006] In a first aspect, embodiments of this application provide a method for determining fault information, including:

[0007] Obtain the configuration information of the memory, which includes the first address of the memory and the cell address of each memory cell in the memory;

[0008] Obtain test information obtained by testing the memory, the test information including at least one stored data corresponding to each storage cell in the memory, the operating order of each storage cell, and the second address of the memory;

[0009] Based on the configuration information and test information of the memory, fault information existing during the testing process of the memory is determined.

[0010] In one possible implementation, based on the memory's configuration information and the memory's test information, fault information present during the testing process of the memory is determined, including:

[0011] Based on the first address of the memory, the operating order of each memory cell in the memory, and the second address of the memory, address fault information existing during the testing of the memory is determined;

[0012] Based on the cell address of each storage cell in the memory, at least one stored data corresponding to each storage cell, and the operating order of each storage cell, determine the data fault information and sequence fault information that exist during the testing of the memory.

[0013] The fault information identified during the testing of the memory includes any one or more of the following: address fault information, data fault information, and sequence fault information.

[0014] In one possible implementation, address fault information present during the testing of the memory is determined based on a first address of the memory, the operating order of the memory cells, and a second address of the memory, including:

[0015] Obtain the test period of the memory;

[0016] Based on the operating order of each storage cell in the memory, at least one operating segment of each memory is determined;

[0017] Based on the test period of the memory and at least one runtime segment of the memory within the memory, address fault information present during the test of the memory is determined.

[0018] In one possible implementation, based on the test period of the memory and at least one runtime segment of the memory within the memory, memory address fault information present during the test of the memory is determined, including:

[0019] If at least one of the runtime segments does not match the test time period, then the runtime segment that does not match the test time period is determined as the target time period;

[0020] The address fault information is determined to include the memory identifier, the memory test period, and the target time period.

[0021] In one possible implementation, based on the cell address of each storage cell in the memory, at least one piece of stored data corresponding to each storage cell, and the operating order of each storage cell, data fault information and sequence fault information existing during the testing of the memory are determined, including:

[0022] The sequence fault information is determined based on the cell address of each storage cell in the memory and the operating order of each storage cell;

[0023] The data fault information is determined based on at least one stored data corresponding to each storage unit.

[0024] In one possible implementation, the sequence fault information is determined based on the cell address of each memory cell and the operating order of each memory cell, including:

[0025] The testing order of each cell in the memory is determined based on the cell address of each memory cell.

[0026] If the test order and the execution order do not match, then in the test order, at least one target storage unit that does not match the execution order is identified;

[0027] The determination of the sequential fault information includes at least one target storage unit, a first order of each target storage unit in the test order, and a second order of each target storage unit in the running order.

[0028] In one possible implementation, the stored data includes first stored data and second stored data; determining the data fault information based on at least one stored data corresponding to each storage unit includes:

[0029] Acquire at least one test data for each storage unit, the test data including first test data and second test data;

[0030] Obtain the data signals corresponding to each storage unit;

[0031] The data fault information of the memory is determined based on the data signal corresponding to each memory cell, at least one test data of each memory cell, and at least one stored data of each memory cell.

[0032] In one possible implementation, determining the data fault information of the memory based on the data signal corresponding to each memory cell, at least one test data of each memory cell, and at least one stored data of each memory cell includes:

[0033] If among the data signals corresponding to each storage unit, there is a preset signal, then at least one storage unit corresponding to the preset signal is determined as the first candidate storage unit.

[0034] For any given storage unit, if the first test data does not match the first stored data, and / or the second test data does not match the second stored data, then the storage unit is determined as a second candidate storage unit, thus obtaining at least one second candidate storage unit.

[0035] The data fault information is determined to include at least one first candidate storage unit, at least one second candidate storage unit, and at least one test data and at least one stored data corresponding to each second candidate storage unit.

[0036] In one possible implementation, the method further includes;

[0037] Get the preset storage path;

[0038] According to the preset storage path, store the fault information corresponding to the test memory.

[0039] Secondly, embodiments of this application provide a fault information determination device, the device comprising:

[0040] The first acquisition module is used to acquire the configuration information of the memory, the configuration information including the first address of the memory and the cell address of each storage cell in the memory;

[0041] The second acquisition module is used to acquire test information obtained by testing the memory. The test information includes at least one stored data corresponding to each storage unit in the memory, the operating order of each storage unit, and the second address of the memory.

[0042] The determination module is used to determine fault information existing during the testing process of the memory based on the configuration information and test information of the memory.

[0043] In one possible implementation, the determining module is specifically used for:

[0044] Based on the first address of the memory, the operating order of each memory cell in the memory, and the second address of the memory, address fault information existing during the testing of the memory is determined;

[0045] Based on the cell address of each storage cell in the memory, at least one stored data corresponding to each storage cell, and the operating order of each storage cell, determine the data fault information and sequence fault information that exist during the testing of the memory.

[0046] The fault information identified during the testing of the memory includes any one or more of the following: address fault information, data fault information, and sequence fault information.

[0047] In one possible implementation, the determining module is specifically used for:

[0048] Obtain the test period of the memory;

[0049] Based on the operating order of each storage cell in the memory, at least one operating segment of each memory is determined;

[0050] Based on the test period of the memory and at least one runtime segment of the memory within the memory, address fault information present during the test of the memory is determined.

[0051] In one possible implementation, the determining module is specifically used for:

[0052] If at least one of the runtime segments does not match the test time period, then the runtime segment that does not match the test time period is determined as the target time period;

[0053] The address fault information is determined to include the memory identifier, the memory test period, and the target time period.

[0054] In one possible implementation, the determining module is specifically used for:

[0055] The sequence fault information is determined based on the cell address of each storage cell in the memory and the operating order of each storage cell;

[0056] The data fault information is determined based on at least one stored data corresponding to each storage unit.

[0057] In one possible implementation, the determining module is specifically used for:

[0058] The testing order of each cell in the memory is determined based on the cell address of each memory cell.

[0059] If the test order and the execution order do not match, then in the test order, at least one target storage unit that does not match the execution order is identified;

[0060] The determination of the sequential fault information includes at least one target storage unit, a first order of each target storage unit in the test order, and a second order of each target storage unit in the running order.

[0061] In one possible implementation, the determining module is specifically used for:

[0062] Acquire at least one test data for each storage unit, the test data including first test data and second test data;

[0063] Obtain the data signals corresponding to each storage unit;

[0064] The data fault information of the memory is determined based on the data signal corresponding to each memory cell, at least one test data of each memory cell, and at least one stored data of each memory cell.

[0065] In one possible implementation, the determining module is specifically used for:

[0066] If among the data signals corresponding to each storage unit, there is a preset signal, then at least one storage unit corresponding to the preset signal is determined as the first candidate storage unit.

[0067] For any given storage unit, if the first test data does not match the first stored data, and / or the second test data does not match the second stored data, then the storage unit is determined as a second candidate storage unit, thus obtaining at least one second candidate storage unit.

[0068] The data fault information is determined to include at least one first candidate storage unit, at least one second candidate storage unit, and at least one test data and at least one stored data corresponding to each second candidate storage unit.

[0069] In one possible implementation, the device further includes a storage module.

[0070] The storage module is used for;

[0071] Get the preset storage path;

[0072] According to the preset storage path, store the fault information corresponding to the test memory.

[0073] Thirdly, this application provides a chip on which a computer program is stored, and when the computer program is executed by the chip, it implements the method described in any of the first aspects.

[0074] Fourthly, this application provides a chip module on which a computer program is stored, and when the computer program is executed by the chip module, it implements the method described in any of the first aspects.

[0075] Fifthly, embodiments of this application provide a terminal device, including:

[0076] At least one processor; and

[0077] A memory communicatively connected to the at least one processor; wherein,

[0078] The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described in any of the first aspects.

[0079] In a sixth aspect, embodiments of this application provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the method described in any one of the first aspects.

[0080] In a seventh aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method described in any one of the first aspects.

[0081] The fault information determination method, apparatus, and terminal device provided in this application embodiment acquire the configuration information of the memory, including the first address of the memory and the cell addresses of each memory cell. They acquire test information obtained from testing the memory, including at least one stored data corresponding to each memory cell, the operating order of each memory cell, and the second address of the memory. Based on the memory configuration information and the memory test information, they determine the fault information present during the memory testing process. In the above process, fault information present during the memory testing process can be determined based on the memory configuration information and the memory test information. This avoids the situation where the test process and configuration file of the test chip are determined manually based on the description files of each memory, which could lead to inaccurate test circuits due to inaccurate configuration files, resulting in incomplete testing of the memory in the chip or inaccurate testing of internal memory faults. This improves the accuracy of determining the presence of faults during chip testing. Attached Figure Description

[0082] Figure 1 A schematic diagram illustrating the application scenarios provided in the embodiments of this application;

[0083] Figure 2 A flowchart illustrating a fault information determination method provided in an embodiment of this application;

[0084] Figure 3 A schematic diagram illustrating the process of obtaining the description file provided in this application embodiment;

[0085] Figure 4 A flowchart illustrating another fault information determination method provided in an embodiment of this application;

[0086] Figure 5 This is a schematic diagram illustrating the process of determining sequential fault information provided in an embodiment of this application;

[0087] Figure 6A schematic diagram illustrating the process of acquiring data signals corresponding to each storage unit, provided in an embodiment of this application.

[0088] Figure 7 A schematic diagram illustrating the process of determining a second candidate storage unit provided in an embodiment of this application;

[0089] Figure 8 A schematic diagram illustrating the fault information determination process provided in the embodiments of this application;

[0090] Figure 9 This is a schematic diagram of the structure of a fault information determination device provided in an embodiment of this application;

[0091] Figure 10 This is a schematic diagram of another fault information determination device provided in an embodiment of this application;

[0092] Figure 11 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0093] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0094] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0095] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with relevant laws, regulations and standards, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0096] To facilitate understanding, the following will be combined with... Figure 1The application scenarios applicable to the embodiments of this application will be described.

[0097] Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. Please refer to [link / reference]. Figure 1 The system includes chip 101 and test circuit 102. Chip 101 is equipped with a Sharebus interface, two 32×64 physical memories, and two 64×32 physical memories. Test circuit 101 can transmit data with each memory in chip 101 via the Sharebus interface, thereby testing each memory in chip 101. Before testing the memory in chip 101 through test circuit 102, the entire process can be simulated using simulation testing tools.

[0098] In related technologies, testing can be performed using simulation testing tools as follows: The description files for each memory module in the chip are obtained. Testers determine the test procedure and configuration file for the chip based on these description files. Simulation testing is then conducted based on the test procedure and configuration file to obtain the test results. However, in this process, because the test procedure and configuration file are determined manually based on the description files, inaccurate configuration files can lead to inaccurate test circuits, resulting in incomplete testing of all memory modules or inaccurate testing of internal memory faults. This results in low accuracy in determining the presence of faults during chip testing.

[0099] In this embodiment, the configuration information of the memory is obtained, including the first address of the memory and the cell addresses of each memory cell. Test information obtained from testing the memory is also obtained, including at least one piece of stored data corresponding to each memory cell, the operating order of each memory cell, and the second address of the memory. Based on the memory configuration information and the memory test information, fault information present during the memory testing process is determined. In the above process, fault information present during the memory testing process can be determined based on the memory configuration information and the memory test information. This avoids the situation where the test process and configuration file of the test chip are determined manually based on the description files of each memory, which could lead to inaccurate test circuits due to inaccurate configuration files, resulting in incomplete testing of the memory in the chip or inaccurate testing of internal memory faults. This improves the accuracy of determining the presence of faults during chip testing.

[0100] The method described in this application will now be illustrated through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; identical or similar content will not be repeated in different embodiments.

[0101] Figure 2 This is a flowchart illustrating a fault information determination method provided in an embodiment of this application. Please refer to... Figure 2 The method may include:

[0102] S201. Obtain the configuration information of the memory.

[0103] The execution entity in this application embodiment can be a terminal device, or a chip, chip module, or fault information determination device installed in the terminal device. The fault information determination device can be implemented by software or by a combination of software and hardware. The terminal device can be a computer.

[0104] The configuration information includes the first address of the memory and the cell address of each memory cell.

[0105] The first address of the memory is the address of the physical memory. The cell address of each storage cell in the memory can include at least one or more of the following: the row address, column address, and block address of each storage cell in the physical memory.

[0106] The configuration information of each memory in the chip can be determined based on the chip's description file (memlib). The memory refers to physical memory. The description file can include a memory cluster description file (cluster memlib), a logical memory description file (logical memlib), and a physical memory description file (physical memlib). The memory cluster description file describes the access methods for each logical memory that can be accessed through the same shared bus interface. The logical memory description file describes the individual physical memories included in the logical memory and their access methods. The physical memory description file describes the internal structure and parameters of the physical memory.

[0107] Each memory cluster includes at least one logical memory, and the logical memory includes at least one physical memory.

[0108] Below, in conjunction with Figure 3 The process of obtaining the description file is explained. Figure 3 This is a schematic diagram illustrating the process of obtaining the description file as provided in an embodiment of this application. Please refer to... Figure 3 This includes interfaces 301 to 302. Interfaces 301 and 302 can be pages provided by the terminal device. Referring to interface 301, when a user clicks the icon corresponding to the test application on the terminal device, the terminal device responds to the user's click and displays an operation page. The operation page includes a drop-down menu corresponding to a memory cluster description file, a drop-down menu corresponding to at least one logical memory description file, a drop-down menu corresponding to at least one physical memory description file, and a text input box.

[0109] Please refer to interface 302. The user selects description file A from the drop-down menu corresponding to the memory cluster description file, selects description file A1 from the drop-down menu corresponding to logical memory description file 1, selects description file A11 from the drop-down menu corresponding to physical memory description file 1, and selects description file A12 from the drop-down menu corresponding to physical memory description file 2, then clicks the OK icon. The terminal device responds to the user's input selection operation by obtaining description file A, description file A1, description file A11, and description file A12.

[0110] A first script for determining fault information can be generated using a preset computer language. This first script includes fields such as address bits, data bits, and address bits of each internal memory unit corresponding to the physical memory and Sharebus interface. After determining the first chip to be tested and the test procedure, the address bits, data bits, and address bits of each internal memory unit corresponding to the physical memory and Sharebus interface can be filled into the corresponding fields in the first script based on multiple description files and test procedures for the first chip, thereby generating a test monitoring script. The Sharebus interface and each physical memory unit in the first chip can then be monitored using this test monitoring script.

[0111] The test monitoring scripts include a Sharebus monitoring script and a memory monitoring script for each physical memory. At least one physical memory is located in the first chip.

[0112] S202. Obtain the test information obtained from testing the memory.

[0113] The test information includes at least one stored data corresponding to each storage cell in the memory, the operating order of each storage cell, and the second address of the memory.

[0114] The second address of the memory can be the address used to access the actual physical memory during chip testing.

[0115] Test information obtained from testing the memory can be obtained through test monitoring scripts.

[0116] S203. Based on the memory configuration information and memory test information, determine the fault information that exists during the memory test process.

[0117] Test information obtained from testing the memory can be obtained in the following ways: based on the first address of the memory, the operating order of each memory cell, and the second address of the memory, determine the address fault information present during the testing process; based on the cell address of each memory cell, at least one piece of stored data corresponding to each memory cell, and the operating order of each memory cell, determine the data fault information and sequence fault information present during the testing process; the fault information present during the testing process includes any one or more of the following: address fault information, data fault information, and sequence fault information.

[0118] Address fault information is used to indicate that the physical memory accessed during the test is different from the physical memory configured to be accessed. For example, in runtime segment A1, the physical memory configured to be accessed is memory A1. However, during the test, the physical memory accessed is memory A2.

[0119] Data fault information is used to indicate that during the test, the data read into the memory cell is different from the set read data, and / or the data written into the memory cell is different from the set write data.

[0120] Sequence fault information is used to indicate that during the test, the operating order of the memory cells is different from the set operating order.

[0121] The fault information determination method provided in this application embodiment obtains the configuration information of the memory. It also obtains test information obtained from testing the memory. Based on the memory configuration information and the memory test information, it determines the fault information present during the memory testing process. In the above process, fault information present during memory testing can be determined based on the memory configuration information and the memory test information. This avoids the situation where manually determining the test process and configuration file of the test chip based on the description files of each memory chip can lead to inaccurate test circuits due to inaccurate configuration files, resulting in incomplete testing of the memory in the chip or inaccurate testing of internal memory faults. This improves the accuracy of determining the presence of faults during chip testing.

[0122] Based on any of the above embodiments, the following, in conjunction with Figure 4 The detailed process of determining fault information is explained.

[0123] Figure 4 This is a flowchart illustrating another fault information determination method provided in an embodiment of this application. Please refer to... Figure 4 The method includes:

[0124] S401. Obtain the configuration information of the memory.

[0125] It should be noted that the execution process of S401 can be found in S201, and will not be repeated here.

[0126] S402. Obtain the test information obtained from testing the memory.

[0127] It should be noted that the execution process of S402 can be found in S202, and will not be repeated here.

[0128] S403, Obtain the test period of the memory.

[0129] The test period for each memory can be determined based on the configuration file. Users can set the configuration file for this test according to the description file and store the configuration file in the preset storage space of the terminal device.

[0130] For example, test circuit B is connected to memory cluster B via a sharebus interface. Memory cluster B includes physical memory B1 and physical memory B2. The terminal device retrieves a configuration file from a preset storage space and determines the specific test period for each physical memory within the configuration file, as shown in Table 1.

[0131] Table 1

[0132]

[0133]

[0134] S404. Determine at least one runtime segment for each memory based on the operating order of each memory cell in the memory.

[0135] By testing the memory monitoring script corresponding to the physical memory in the monitoring script, the running order of each storage unit in the memory can be obtained, thereby determining at least one running segment of each memory.

[0136] For example, the specific details of at least one runtime segment for each memory determined by the terminal device can be shown in Table 2:

[0137] Table 2

[0138]

[0139] S405. Based on the test period of the memory and at least one running segment of the memory in the memory, determine the address fault information that exists during the test of the memory.

[0140] Address fault information during memory testing can be determined as follows, based on the memory's test period and at least one runtime segment of the memory: if at least one runtime segment does not match the test period, the runtime segment that does not match the test period is determined as the target period; the address fault information includes the memory's identifier, the memory's test period, and the target period.

[0141] For example, as illustrated above, if at least one runtime segment of physical memory B1 does not match the test period, then the runtime segment 2024 / 07 / 03 15:01~2024 / 07 / 03 15:00:02, which does not match the test period, is determined as the target period. The runtime segment of physical memory B2 does not match the test period. Since physical memory B2 does not have a target period, the target period is determined to be 0. Therefore, the terminal device determines that the address fault information includes physical memory B1, the test period for physical memory B1 is 2024 / 07 / 03 15:01~2024 / 07 / 03 15:00:02, and the target period is 2024 / 07 / 03 15:02~2024 / 07 / 03 15:00:03. And physical memory B2, the test period for physical memory B2 is 2024 / 07 / 03 15:02~2024 / 07 / 03 15:00:03, and the target time period for physical memory B2 is 0.

[0142] S406. Determine the testing order of each memory cell based on the cell address of each memory cell.

[0143] Based on the test scenario and test requirements, determine the access time for each unit address. Then, based on the access time of each unit address, determine the test order for each memory unit in the memory.

[0144] S407. If the test order and the execution order do not match, then in the test order, identify at least one target storage unit that does not match the execution order.

[0145] For any given storage unit, if the execution order of the storage unit during operation is different from the first order in the test cycle, then it can be determined that the test order and the execution order do not match.

[0146] S408, Determine the sequence fault information including at least one target storage unit, the first order of each target storage unit in the test order, and the second order of each target storage unit in the running order.

[0147] Below, in conjunction with Figure 5 The process of determining sequential fault information is explained. Figure 5 This is a schematic diagram illustrating the process of determining sequential fault information provided in an embodiment of this application. Please refer to... Figure 5 The test sequence 501 and the execution sequence 502 are used to determine the access order of each memory cell in the physical memory based on the test scenario and test requirements. The execution sequence 502 is the access order of each memory cell in the physical memory during the test. Assume the test operation sequence is to traverse the row address, column address, and block address of each memory cell. Assume the 5-bit address of the memory is [block[0], column[1:0], row[1:0]]. The test sequence 501 for memory cells 1-32 corresponds to 1-32 in the test sequence 501. In the execution sequence 502, the second order of memory cells 5-24 does not match the test sequence 501. The second order of memory cells 5-24 are 9-12, 17-20, 25-28, 5-8, 13-16, and 21-24, respectively. Therefore, the terminal device determines that at least one target memory cell includes memory cells 5-24. The first sorting of storage units 5 to 24 is 5 to 24 respectively, and the second sorting is 9 to 12, 17 to 20, 25 to 28, 5 to 8, 13 to 16, and 21 to 24 respectively.

[0148] S409. Obtain at least one test data for each storage unit.

[0149] The test data includes first test data and second test data. The test data is the first test data that the storage unit should read during the test, and the second test data that the storage unit should write during the test, as determined by the configuration file.

[0150] S410: Obtain the data signal corresponding to each storage unit.

[0151] Data signals are used to indicate whether a read or write operation has been performed on a memory cell. If a read or write operation is performed, the level of the corresponding data signal will change. If no read or write operation is performed, the level of the corresponding data signal will remain unchanged.

[0152] Below, in conjunction with Figure 6 The process of acquiring the data signals corresponding to each storage unit is explained. Figure 6 This is a schematic diagram illustrating the process of acquiring data signals corresponding to each storage unit, as provided in an embodiment of this application. Please refer to... Figure 6 This includes memory 601, which can be a physical memory within the chip. During testing, memory 601 transmits control signals, address signals, and data signals corresponding to each memory cell. If the level of the data signal changes, it indicates that the memory cell is performing a read / write operation. If the level of the data signal remains unchanged, it indicates that the memory cell is not performing a read / write operation.

[0153] S411. Determine the data fault information of the memory based on the data signal corresponding to each memory cell, at least one test data of each memory cell, and at least one stored data of each memory cell.

[0154] The stored data includes first stored data and second stored data. The stored data consists of the first stored data actually read into the storage unit during the test and the second stored data actually written into the storage unit during the test.

[0155] Data fault information of the memory can be determined in the following manner based on the data signal corresponding to each memory cell, at least one test data of each memory cell, and at least one stored data of each memory cell: If there is a preset signal among the data signals corresponding to each memory cell, then at least one memory cell corresponding to the preset signal is determined as the first candidate memory cell; for any memory cell, if the first test data does not match the first stored data, and / or the second test data does not match the second stored data, then the memory cell is determined as the second candidate memory cell, thus obtaining at least one second candidate memory cell; the determined data fault information includes at least one first candidate memory cell, at least one second candidate memory cell, and at least one test data and at least one stored data corresponding to each second candidate memory cell.

[0156] Preset signals can be configured in advance and stored in the terminal device's preset storage space. The corresponding level of the preset signal changes accordingly. If the data signal is the preset signal, it indicates that the storage unit has performed a read / write operation, confirming that the storage unit has been tested. If the data signal is not the preset signal, it indicates that the storage unit has not performed a read / write operation, confirming that the storage unit has not been tested.

[0157] Below, in conjunction with Figure 7 The process of determining the second candidate memory cell is explained. Figure 7 This is a schematic diagram illustrating the process of determining a second candidate memory cell according to an embodiment of this application. It includes a memory 701, which can be a physical memory in a chip with 4 rows and 4 columns. The memory 701 includes 16 memory cells. Black memory cells represent data 1 written during the test, and white memory cells represent data 0 written during the test. Therefore, the first test data for memory cell 5 can be determined to be 0. If the first stored data for memory cell 5 is 1, it can be determined that the first test data and the first stored data do not match. Therefore, the terminal device can determine that the second candidate memory cell of memory 701 is memory cell 5.

[0158] S412. Determine the fault information present during the testing of the memory, including any one or more of the following: address fault information, data fault information, and sequence fault information.

[0159] Fault information may include any one or more of address fault information, data fault information, and sequence fault information. This application does not impose any restrictions.

[0160] If no address fault, data fault, or sequence fault information is found, it indicates that no fault occurred during the chip test. At this point, the terminal device generates a prompt message and either stores or displays it. The prompt message indicates that no fault occurred during this chip test.

[0161] S413. Fault information that exists during the testing of the storage memory.

[0162] Fault information present during the testing of the memory can be stored in the following way: obtain a preset storage path; and store the fault information corresponding to the test memory according to the preset storage path.

[0163] A preset storage path can be set in advance and stored in the preset storage space of the terminal device. Users can then retrieve fault information that occurred during the memory testing process using the preset storage path on the terminal device.

[0164] The fault information determination method provided in this application embodiment obtains the configuration information of the memory. It obtains test information obtained from testing the memory. It obtains the test period of the memory. Based on the operating order of each memory cell, it determines at least one operating segment of each memory. Based on the test period of the memory and at least one operating segment of the memory, it determines address fault information existing during the testing process. Based on the cell address of each memory cell, it determines the test order of each cell in the memory. If the test order and the operating order do not match, it identifies at least one target memory cell that does not match the operating order in the test order. The determined sequence fault information includes at least one target memory cell, a first order of each target memory cell in the test order, and a second order of each target memory cell in the operating order. It obtains at least one test data for each memory cell. It obtains the data signal corresponding to each memory cell. Based on the data signal corresponding to each memory cell, at least one test data for each memory cell, and at least one stored data for each memory cell, it determines the data fault information of the memory. The determined fault information includes address fault information, data fault information, and sequence fault information. In the above process, fault information existing during the testing process of the memory can be determined based on the memory configuration information and the memory test information. This avoids the pitfalls of manually determining test procedures and configuration files for each memory chip based on its description files. Inaccurate configuration files can lead to inaccurate test circuits, resulting in incomplete testing of all memory components or inaccurate detection of internal memory faults. This improves the accuracy of fault detection during chip testing.

[0165] Based on any of the above embodiments, the following, in conjunction with Figure 8 The process of determining fault information is illustrated with an example.

[0166] Figure 8 This is a schematic diagram illustrating the fault information determination process provided in an embodiment of this application. Please refer to... Figure 8 This includes terminal device 801. Terminal device 801 can be a computer, and it includes a memory cluster monitoring module, memory monitoring module 1, and memory monitoring module 2. The memory clusters, sharebus interfaces, and test circuits in the chip can be pre-configured using description files and configuration files to generate corresponding simulation modules in the terminal device's simulation test tool. The memory cluster monitoring module of terminal device 801 then acquires the physical memory accessed at various times during the test. Additionally, the memory test information is obtained through the various memory monitoring modules of terminal device 801. The specific configuration information of the memory acquired by terminal device 801 is shown in Table 3.

[0167] Table 3

[0168]

[0169] According to the configuration file, terminal device 801 controls the test circuit to perform simulated tests on each memory in the memory cluster via the shared bus interface. The test information obtained through memory monitoring module 1 and memory monitoring module 2 is shown in Table 4.

[0170] Table 4

[0171]

[0172] The specific details of at least one runtime segment for each memory determined by the terminal device 801 are shown in Table 5:

[0173] Table 5

[0174]

[0175]

[0176] The specific test periods for acquiring physical memory B1 and physical memory B2 by terminal device 801 are shown in Table 6:

[0177] Table 6

[0178] Physical memory Test period Physical memory B1 2024 / 07 / 03 15:46～2024 / 07 / 03 15:00:47 Physical memory B2 2024 / 07 / 03 15:48～2024 / 07 / 03 15:00:49

[0179] Based on Tables 5 and 6, it can be determined that the test period of physical memory B1 matches the runtime period, and the test period of physical memory B2 also matches the runtime period. Therefore, terminal device 801 can determine that there is no address fault during the test.

[0180] The terminal device 801 determines the testing order of each memory cell based on its address, as shown in Table 7.

[0181] Table 7

[0182]

[0183] According to Tables 4 and 7, terminal device 801 determines that the test order and execution order of physical memory B2 do not match. Therefore, in the test order, at least one target memory cell that does not match the execution order includes memory cell B7 and memory cell B8. Thus, the specific sequence fault information determined by terminal device 801 is shown in Table 8:

[0184] Table 8

[0185] Target storage unit First sort Second sorting Storage unit B7 7 8 Storage unit B8 8 7

[0186] Terminal device 801 determines that there are no faults in the data based on at least one stored data corresponding to each storage unit. Therefore, terminal device 801 determines that the fault information present during the testing of the memory includes the sequential fault information shown in Table 8. Terminal device 801 obtains a preset storage path A from the preset storage space and stores the fault information according to the preset storage path A.

[0187] The fault information determination process provided in this application embodiment involves: acquiring memory configuration information; acquiring test information obtained from testing the memory; acquiring the memory test period; determining at least one runtime segment for each memory based on the operating order of each memory cell; determining address fault information present during the memory test based on the memory test period and at least one runtime segment of the memory; determining the test order of each memory cell based on the cell address of each memory cell; determining at least one target memory cell that does not match the operating order in the test order if the test order and the operating order do not match; determining sequence fault information including at least one target memory cell, a first order of each target memory cell in the test order, and a second order of each target memory cell in the operating order; acquiring at least one test data for each memory cell; acquiring the data signal corresponding to each memory cell; and determining data fault information for the memory based on the data signal corresponding to each memory cell, at least one test data for each memory cell, and at least one stored data for each memory cell. The determined fault information includes address fault information, data fault information, and sequence fault information. In the above process, fault information present during the memory test can be determined based on the memory configuration information and the memory test information. This avoids the pitfalls of manually determining test procedures and configuration files for each memory chip based on its description files. Inaccurate configuration files can lead to inaccurate test circuits, resulting in incomplete testing of all memory components or inaccurate detection of internal memory faults. This improves the accuracy of fault detection during chip testing.

[0188] Figure 9 This is a schematic diagram of a fault information determination device provided in an embodiment of this application. The fault information determination device can be a chip or a chip module. Please refer to... Figure 9 The fault information determination device 10 may include:

[0189] The first acquisition module 11 is used to acquire the configuration information of the memory, the configuration information including the first address of the memory and the cell address of each storage cell in the memory;

[0190] The second acquisition module 12 is used to acquire test information obtained by testing the memory. The test information includes at least one stored data corresponding to each storage unit in the memory, the running order of each storage unit, and the second address of the memory.

[0191] The determination module 13 is used to determine fault information existing during the testing process of the memory based on the configuration information and test information of the memory.

[0192] In one possible implementation, the determining module 13 is specifically used for:

[0193] Based on the first address of the memory, the operating order of each memory cell in the memory, and the second address of the memory, address fault information existing during the testing of the memory is determined;

[0194] Based on the cell address of each storage cell in the memory, at least one stored data corresponding to each storage cell, and the operating order of each storage cell, determine the data fault information and sequence fault information that exist during the testing of the memory.

[0195] The fault information identified during the testing of the memory includes any one or more of the following: address fault information, data fault information, and sequence fault information.

[0196] In one possible implementation, the determining module 13 is specifically used for:

[0197] Obtain the test period of the memory;

[0198] Based on the operating order of each storage cell in the memory, at least one operating segment of each memory is determined;

[0199] Based on the test period of the memory and at least one runtime segment of the memory within the memory, address fault information present during the test of the memory is determined.

[0200] In one possible implementation, the determining module 13 is specifically used for:

[0201] If at least one of the runtime segments does not match the test time period, then the runtime segment that does not match the test time period is determined as the target time period;

[0202] The address fault information is determined to include the memory identifier, the memory test period, and the target time period.

[0203] In one possible implementation, the determining module 13 is specifically used for:

[0204] The sequence fault information is determined based on the cell address of each storage cell in the memory and the operating order of each storage cell;

[0205] The data fault information is determined based on at least one stored data corresponding to each storage unit.

[0206] In one possible implementation, the determining module 13 is specifically used for:

[0207] The testing order of each cell in the memory is determined based on the cell address of each memory cell.

[0208] If the test order and the execution order do not match, then in the test order, at least one target storage unit that does not match the execution order is identified;

[0209] The determination of the sequential fault information includes at least one target storage unit, a first order of each target storage unit in the test order, and a second order of each target storage unit in the running order.

[0210] In one possible implementation, the determining module 13 is specifically used for:

[0211] Acquire at least one test data for each storage unit, the test data including first test data and second test data;

[0212] Obtain the data signals corresponding to each storage unit;

[0213] The data fault information of the memory is determined based on the data signal corresponding to each memory cell, at least one test data of each memory cell, and at least one stored data of each memory cell.

[0214] In one possible implementation, the determining module 13 is specifically used for:

[0215] If among the data signals corresponding to each storage unit, there is a preset signal, then at least one storage unit corresponding to the preset signal is determined as the first candidate storage unit.

[0216] For any given storage unit, if the first test data does not match the first stored data, and / or the second test data does not match the second stored data, then the storage unit is determined as a second candidate storage unit, thus obtaining at least one second candidate storage unit.

[0217] The data fault information is determined to include at least one first candidate storage unit, at least one second candidate storage unit, and at least one test data and at least one stored data corresponding to each second candidate storage unit.

[0218] The fault information determination device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0219] Figure 10 This is a schematic diagram of another fault information determination device provided in an embodiment of this application. Figure 9 Based on the illustrated embodiments, please refer to Figure 10The fault information determination device 10 also includes a storage module 14.

[0220] The storage module 14 is used for;

[0221] Get the preset storage path;

[0222] Store the fault information corresponding to the test memory according to the preset storage path.

[0223] The fault information determination device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0224] Figure 11 This is a schematic diagram of the structure of the terminal device provided in an embodiment of this application. Please refer to... Figure 11 The terminal device 20 may include a memory 21 and a processor 22. Exemplarily, the memory 21 and the processor 22 are interconnected via a bus 23.

[0225] Memory 21 is used to store program instructions;

[0226] The processor 22 is used to execute the program instructions stored in the memory, so that the terminal device 20 performs the method shown in the above method embodiment.

[0227] The terminal device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0228] This application provides a computer-readable storage medium storing computer-executable instructions, which are used to implement the above-described method when executed by a processor.

[0229] This application embodiment may also provide a computer program product, including a computer program that, when executed by a processor, can implement the above-described method.

[0230] All or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), and any combination thereof.

[0231] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0232] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0233] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0234] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

[0235] In this application, the term "comprising" and its variations can refer to non-limiting inclusion; the term "or" and its variations can refer to "and / or". The terms "first", "second", etc., in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. In this application, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

Claims

1. A method for determining fault information, characterized in that, include: Obtain the configuration information of the memory, which includes the first address of the memory and the cell address of each memory cell in the memory; The configuration information is determined based on the memory cluster description file, logical memory description file, and physical memory description file; the memory cluster description file describes the access method for accessing each logical memory through a shared interface with the same access path; the logical memory description file describes each physical memory included in the logical memory and its access method; the physical memory description file describes the internal structure and parameters of the physical memory. Obtain test information obtained by testing the memory, the test information including at least one stored data corresponding to each storage cell in the memory, the operating order of each storage cell, and the second address of the memory; Based on the configuration information and test information of the memory, determine the fault information that exists during the testing process of the memory; The fault information includes address fault information, data fault information and sequence fault information. The address fault information is used to indicate that the physical memory accessed by the memory during the test is different from the physical memory set. The data fault information is used to indicate that during the test, the data read into the memory cell is different from the set data to be read, and / or the data written into the memory cell is different from the set data to be written. The sequence fault information is used to indicate that the operating order of the memory cells during the test is different from the set operating order.

2. The method according to claim 1, characterized in that, Based on the configuration information and test information of the memory, fault information existing during the testing process of the memory is determined, including: Based on the first address of the memory, the operating order of each memory cell in the memory, and the second address of the memory, address fault information existing during the testing of the memory is determined; Based on the cell address of each storage cell in the memory, at least one stored data corresponding to each storage cell, and the operating order of each storage cell, data fault information and sequence fault information existing in the testing process of the memory are determined.

3. The method according to claim 2, characterized in that, Based on the first address of the memory, the operating order of each memory cell in the memory, and the second address of the memory, address fault information present during the testing of the memory is determined, including: Obtain the test period of the memory; Based on the operating order of each storage cell in the memory, at least one operating segment of each memory is determined; Based on the test period of the memory and at least one runtime segment of the memory within the memory, address fault information present during the test of the memory is determined.

4. The method according to claim 3, characterized in that, Based on the test period of the memory and at least one runtime segment of the memory within the memory, determine the memory address fault information present during the test of the memory, including: If at least one of the runtime segments does not match the test time period, then the runtime segment that does not match the test time period is determined as the target time period; The address fault information is determined to include the memory identifier, the memory test period, and the target time period.

5. The method according to any one of claims 2-4, characterized in that, Based on the cell address of each storage cell in the memory, at least one piece of stored data corresponding to each storage cell, and the operating order of each storage cell, data fault information and sequence fault information existing during the testing of the memory are determined, including: The sequence fault information is determined based on the cell address of each storage cell in the memory and the operating order of each storage cell; The data fault information is determined based on at least one stored data corresponding to each storage unit.

6. The method according to claim 5, characterized in that, The sequence fault information is determined based on the cell address and operating order of each memory cell in the memory, including: The testing order of each cell in the memory is determined based on the cell address of each memory cell. If the test order and the execution order do not match, then in the test order, at least one target storage unit that does not match the execution order is identified; The determination of the sequential fault information includes at least one target storage unit, a first order of each target storage unit in the test order, and a second order of each target storage unit in the running order.

7. The method according to claim 5, characterized in that, The stored data includes first stored data and second stored data; The data fault information is determined based on at least one piece of stored data corresponding to each storage unit, including: Acquire at least one test data for each storage unit, the test data including first test data and second test data; Obtain the data signals corresponding to each storage unit; The data fault information of the memory is determined based on the data signal corresponding to each memory cell, at least one test data of each memory cell, and at least one stored data of each memory cell.

8. The method according to claim 7, characterized in that, Based on the data signal corresponding to each storage unit, at least one test data for each storage unit, and at least one stored data for each storage unit, the data fault information of the memory is determined, including: If among the data signals corresponding to each storage unit, there is a preset signal, then at least one storage unit corresponding to the preset signal is determined as the first candidate storage unit. For any given storage unit, if the first test data does not match the first stored data, and / or the second test data does not match the second stored data, then the storage unit is determined as a second candidate storage unit, thus obtaining at least one second candidate storage unit. The data fault information is determined to include at least one first candidate storage unit, at least one second candidate storage unit, and at least one test data and at least one stored data corresponding to each second candidate storage unit.

9. The method according to any one of claims 1-8, characterized in that, The method further includes; Get the preset storage path; According to the preset storage path, store the fault information corresponding to the test memory.

10. A fault information determination device, characterized in that, The device includes: The first acquisition module is used to acquire configuration information of the memory, including the first address of the memory and the cell address of each memory cell in the memory; the configuration information is determined based on a memory cluster description file, a logical memory description file, and a physical memory description file; the memory cluster description file is used to describe the access method of accessing each logical memory through a shared interface with the same access path; the logical memory description file is used to describe each physical memory included in the logical memory and its access method; the physical memory description file is used to describe the internal structure and parameters of the physical memory; The second acquisition module is used to acquire test information obtained by testing the memory. The test information includes at least one stored data corresponding to each storage unit in the memory, the operating order of each storage unit, and the second address of the memory. The determination module is used to determine fault information existing during the testing of the memory based on the configuration information and test information of the memory. The fault information includes address fault information, data fault information, and sequence fault information. The address fault information is used to indicate that the physical memory accessed by the memory during the test is different from the set physical memory. The data fault information is used to indicate that the data read into the memory cell during the test is different from the set read data, and / or the data written into the memory cell is different from the set write data. The sequence fault information is used to indicate that the running order of the memory cells during the test is different from the set running order.

11. A terminal device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 9.

12. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, in, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 9.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 9.

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