A design method for ultra-thin single-crystal silicon imaging chips for visible-near infrared

Abstract

The present invention provides a design method for ultra-thin single-crystal silicon imaging chips for visible-near infrared, which relates to the field of photoelectric detection technology. The method includes selecting a P-type silicon wafer as a substrate for an imaging chip, and designing an ultra-thin silicon strip as a unit device of the imaging chip; designing a readout circuit of the imaging chip based on the ultra-thin silicon strip; based on the readout circuit of the imaging chip, in order to generate a temperature difference, by changing the local electrical and optical properties of the ultra-thin silicon strip array, reducing the influence of the symmetry of the ultra-thin silicon strip, and obtaining the final imaging chip. The present invention realizes fast and efficient silicon-based infrared detection, and has the advantages of few defects, low noise, low cost, strong compatibility and easy large-area preparation.

Description

Technical Field

[0001] The invention relates to the field of photoelectric detection technology, and in particular to a design method for a visible-near infrared oriented ultra-thin single crystal silicon imaging chip. Background Art

[0002] In the field of visible light and near-infrared detection, although a variety of silicon-based photodetectors have been designed and applied, the existing technology still has many limitations. For example, although low-doped P-type silicon thin film nanostrips have achieved significant improvements in photoelectric response, their detection research is limited to the visible light range, and the photoresponse and response time have not reached the ideal level. The dual-band infrared silicon photodetector based on plasma nanostructure, although it has achieved dual-band detection, is difficult to be widely used due to its complex structure and high preparation cost. In addition, although the black silicon photodetector with high response performance can operate in a wider spectral range, it relies on heavy doping technology, which leads to more defects and noise in the device, and requires cumbersome pre-annealing process to ensure stable operation.

[0003] In summary, current silicon-based infrared detection technology generally faces problems such as high cost, complex structure, long response time or limited detection range, and an innovative solution is urgently needed to overcome these technical difficulties. Summary of the invention

[0004] To this end, an embodiment of the present invention provides a design method for an ultra-thin single-crystal silicon imaging chip for the visible-near infrared, which is used to solve the problems of limited detection wavelength range, insufficient response time and performance, complex structure and high cost, and reliance on heavy doping technology in the prior art silicon-based infrared detection technology, as well as noise and defect problems caused by it.

[0005] In order to solve the above problems, an embodiment of the present invention provides a design method for an ultra-thin single-crystal silicon imaging chip for visible-near infrared, the method comprising:

[0006] Select P-type silicon wafer as the substrate of the imaging chip, and design ultra-thin silicon strips as the unit device of the imaging chip;

[0007] Design of readout circuits for imaging chips based on arrays of ultra-thin silicon strips;

[0008] Based on the readout circuit of the imaging chip, in order to generate a temperature difference, the local electrical and optical properties of the ultra-thin silicon strip array are changed to reduce the influence of the symmetry of the ultra-thin silicon strips, thereby obtaining the final imaging chip.

[0009] Preferably, the resistivity of the P-type silicon wafer ranges from 8.5Ωcm to 11.5Ωcm.

[0010] Preferably, the size range of the ultra-thin silicon strip is: 2.5 μm to 3.5 μm in width, 16 μm to 20 μm in length, and 10 nm to 50 nm in thickness.

[0011] Preferably, the method for designing a readout circuit of an imaging chip based on an ultra-thin silicon strip array comprises:

[0012] On a SiO2 / Si substrate with an array of ultra-thin silicon strips, a layer of lateral metal electrodes is prepared, and the lateral metal electrodes are connected to a region within a set range at the left end of the ultra-thin silicon strips;

[0013] A layer of silicon dioxide with a set thickness is covered on the lateral metal electrode as an insulating layer;

[0014] A layer of longitudinal metal electrode is prepared on the silicon dioxide insulating layer, and the longitudinal metal electrode is connected to an area within a set range at the right end of the ultra-thin silicon strip.

[0015] Preferably, the method of connecting the lateral metal electrode to the area within a set range at the left end of the ultra-thin silicon strip is:

[0016] Connect the lateral metal electrode to the 1μm~3μm wide area at the left end of the ultra-thin silicon strip.

[0017] Preferably, the method of covering a layer of silicon dioxide with a set thickness as an insulating layer on the lateral metal electrode is:

[0018] A 60nm~120nm layer of silicon dioxide is covered on the lateral metal electrode as an insulating layer.

[0019] Preferably, the method of connecting the longitudinal metal electrode to the area within a set range at the right end of the ultra-thin silicon strip is:

[0020] Connect the longitudinal metal electrode to the 1μm~3μm wide area at the right end of the ultra-thin silicon strip.

[0021] Preferably, based on the readout circuit of the imaging chip, in order to generate a temperature difference, the method of reducing the influence of the symmetry of the ultra-thin silicon strips by changing the local electrical and optical properties of the ultra-thin silicon strip array to obtain the final imaging chip includes:

[0022] A silicon dioxide layer of a set thickness is covered on the left half of the ultra-thin silicon strip as a heat insulation layer;

[0023] A gold layer of a set thickness is plated on the area on the left half of the ultra-thin silicon strip that is already covered with the silicon dioxide layer as a light-blocking layer.

[0024] Preferably, the method of covering the left half of the ultra-thin silicon strip with a silicon dioxide layer of a set thickness as a heat insulation layer and plating a gold-plated layer of a set thickness as a light-blocking layer on the left half of the ultra-thin silicon strip covered with the silicon dioxide layer comprises:

[0025] A 60nm~120nm silicon dioxide layer is covered on the left half of the ultra-thin silicon strip as a heat insulation layer;

[0026] A 60nm~120nm gold layer is plated on the area on the left half of the ultra-thin silicon strip that is covered with a silicon dioxide layer as a light-blocking layer.

[0027] The embodiment of the present invention further provides a design system for ultra-thin single-crystal silicon imaging chips for visible-near infrared, which is used to implement the design method for ultra-thin single-crystal silicon imaging chips for visible-near infrared, and specifically includes:

[0028] The material selection and unit device design module is used to select P-type silicon wafer as the substrate of the imaging chip and design ultra-thin silicon strips as the unit devices of the imaging chip;

[0029] The readout circuit design module is used to design the readout circuit of the imaging chip based on the ultra-thin silicon strip array;

[0030] The symmetry optimization module is used in the readout circuit based on the imaging chip. In order to generate a temperature difference, the local electrical and optical properties of the ultra-thin silicon strip array are changed to reduce the influence of the symmetry of the ultra-thin silicon strips and obtain the final imaging chip.

[0031] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0032] (1) High performance and low noise: The present invention adopts an ultra-thin single-crystal silicon imaging chip designed with P-type lightly doped silicon material, which reduces material defects and noise and does not require complex pre-annealing treatment or refrigeration components, thereby achieving higher photoelectric response and lower noise levels.

[0033] (2) Low cost and wide applicability: Compared with silicon-based infrared detectors based on plasma, the present invention has a simpler configuration, lower cost, and theoretically has no detection band limitation, and can be applied to a wide spectral range from visible light to near infrared. In addition, since the device is completely made of single-crystal silicon and is extremely thin, it has extremely high compatibility and wide application potential.

[0034] (3) Easy preparation and large-area processing: The imaging chip of the present invention has a relatively simple processing process, which is convenient for large-scale production and large-area preparation. This efficient production method helps to reduce production costs, improve production efficiency, and meet the needs of various application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the implementation cases of the present invention or the technical solutions in the prior art, the following is a brief description of the drawings required for use in the embodiments. By referring to the drawings, the features and advantages of the present invention will be more clearly understood. The drawings are schematic and should not be understood as limiting the present invention in any way. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0036] Figure 1 A flowchart of a design method for a visible-near infrared ultra-thin single-crystal silicon imaging chip provided in an embodiment;

[0037] Figure 2 is a scanning electron microscope structure diagram of the detector in the embodiment;

[0038] Figure 3 is a graph showing the relationship between the thickness of the silicon strip and the device response rate in the embodiment;

[0039] Figure 4 A working principle diagram of an ultra-thin silicon strip array unit structure in an embodiment;

[0040] Figure 5 The structure diagram of the ultra-thin silicon strip array in the embodiment is shown in FIG. Figure 5 The left half is the structure of the ultra-thin silicon strip array under an optical microscope. Figure 5 The right half is the structure diagram of the ultra-thin silicon strip array unit under an electron microscope;

[0041] Figure 6 This is a process flow chart of preparing a 4×4 focal plane array in an embodiment;

[0042] Figure 7 It is a block diagram of a design system for a visible-near infrared ultra-thin single-crystal silicon imaging chip provided in an embodiment. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Embodiment 1

[0044] In order to solve the problems of limited detection wavelength range, insufficient response time and performance, complex structure and high cost, as well as noise and defects caused by reliance on heavy doping technology in the existing silicon-based infrared detection technology. Figure 1 As shown, an embodiment of the present invention provides a design method for a visible-near infrared ultra-thin single-crystal silicon imaging chip, the method comprising:

[0045] Step S1: Select a P-type silicon wafer as the substrate of the imaging chip, and design an ultra-thin silicon strip as a unit device of the imaging chip;

[0046] Step S2: designing a readout circuit of the imaging chip based on the ultra-thin silicon strip array;

[0047] Step S3: Based on the readout circuit of the imaging chip, in order to generate a temperature difference, the local electrical and optical properties of the ultra-thin silicon strip array are changed to reduce the influence of the symmetry of the ultra-thin silicon strips, thereby obtaining the final imaging chip.

[0048] From the above technical solution, it can be seen that the present invention provides a design method for ultra-thin single-crystal silicon imaging chips for visible-near infrared. By using P-type lightly doped silicon materials to design ultra-thin single-crystal silicon imaging chips, it not only simplifies the device structure and reduces the preparation cost, but also overcomes the material bandgap limitation by reducing the thickness of the silicon strip and optimizing the photocurrent response distribution, expands the detection wavelength range, and improves the response time and performance. This method realizes fast and efficient silicon-based infrared detection, and has the advantages of few defects, low noise, low cost, strong compatibility and easy large-area preparation.

[0049] The present invention firstly prepares a single detector, whose structure and performance are as follows:

[0050] (1) Structure: The scanning electron microscope (SEM) structure diagram of the detector is shown in Figure 2 As shown. The device was fabricated by top-down nanofabrication of silicon on insulator (SOI) (silicon layer: P-type, boron-doped, resistivity: 10Ωcm, crystal orientation (100), thickness 220nm). P-type Si nanoribbons with a length of 20μm, a width of 2.5μm, and a thickness of 20nm were fabricated by electron beam etching (EBL) and deep silicon etching (STS HRM).

[0051] The left and right ends of the nanostrip are 2×2.5μm 2 The region is plated with 5nm Cr and 100nm Au as the device electrode.

[0052] (2) Performance analysis: The detector can detect optical signals in the visible-near infrared band and convert optical signals into electrical signals through the photothermoelectric effect. Response rate: In the near-infrared 1100nm~1800nm ​​band, the maximum response rate is close to 1.25μA / W under 0V bias, and the maximum response rate is close to 0.3mA / W under 1V bias. This shows that the detector can show good light response performance without the need for external bias, and applying a bias can further improve the response rate. Response time: When the incident light is 1310nm, its response time is 26.5ms without bias and 226μs under 1V bias, which shows that the detector has an extremely fast response speed, which is 1~3 orders of magnitude higher than traditional thermal detectors, which is of great significance for application scenarios that require high-speed response.

[0053] (3) The functional change of the device when a single variable is changed. The relationship between the thickness of the silicon strip and the device response rate is shown in the figure below. Figure 3 The experimental results show that when the thickness of the silicon strip is 10nm~20nm, the average response rate of the device in the near-infrared 1100nm~1800nm ​​band is the highest, indicating that within this thickness range, the silicon strip can effectively absorb light signals while maintaining a high carrier transmission efficiency.

[0054] According to the performance of the above detection device, the present invention proposes a design method for an ultra-thin single-crystal silicon imaging chip for visible-near infrared, which uses the above detection device as a unit device. The imaging chip can have the performance of detecting visible-near infrared light only by relying on single-crystal silicon, and then by designing a suitable readout circuit, it can be used in the field of detection imaging. The design method includes the following steps:

[0055] In step S1, in order to achieve perfect decoupling of carrier temperature and lattice and trigger the ballistic transport effect of carriers, the present invention selects P-type silicon wafer (P-type lightly doped silicon material) as the substrate of the imaging chip. This resistivity range is selected to optimize the photothermoelectric effect and carrier transport characteristics. Then, an ultra-thin silicon strip is designed as the unit device of the imaging chip.

[0056] As an optional specific implementation, the resistivity of the P-type silicon wafer ranges from 8.5Ωcm to 11.5Ωcm. This resistivity range is selected to optimize the photothermoelectric effect and carrier transport characteristics.

[0057] As an optional specific embodiment, the size range of the ultra-thin silicon strip is: 2.5μm~3.5μm in width, 16μm~20μm in length, and 10nm~50nm in thickness. These size parameters are optimized to ensure efficient light absorption, carrier transport, and fast response speed.

[0058] In step S2, based on an ultra-thin silicon strip array, Figure 4 The working principle of the ultra-thin silicon strip array unit structure is demonstrated, and the readout circuit of the imaging chip is designed. The circuit can read and transmit the optical signal on the ultra-thin silicon strip and convert it into an electrical signal, including:

[0059] First, a layer of lateral metal electrodes is prepared on a SiO2 / Si substrate with an array of ultra-thin silicon strips, and the lateral metal electrodes are connected to a set area at the left end of the ultra-thin silicon strips. These electrodes are used to collect electrical signals generated on the left side of the silicon strips.

[0060] It should be noted that, in the present embodiment, the ultra-thin silicon strip refers to the unit structure of the ultra-thin single-crystal silicon imaging chip, and the ultra-thin silicon strip array refers to the overall structure of the ultra-thin single-crystal silicon imaging chip.

[0061] As an optional specific implementation manner, the lateral metal electrode is connected to a 1 μm to 3 μm wide region at the left end of the ultra-thin silicon strip.

[0062] Then a layer of silicon dioxide with a set thickness is covered on the lateral metal electrode as an insulating layer. The role of the insulating layer is to prevent short circuits between electrodes and ensure stable signal transmission.

[0063] As an optional specific implementation manner, a layer of silicon dioxide with a thickness of 60 nm to 120 nm is covered on the lateral metal electrode as an insulating layer.

[0064] Finally, a layer of vertical metal electrodes is prepared on the silicon dioxide insulating layer, and the vertical metal electrodes are connected to the area within a set range at the right end of the ultra-thin silicon strip. These electrodes are used to export the electrical signal on the right side of the ultra-thin silicon strip and connect it to other parts of the readout circuit.

[0065] As an optional specific implementation manner, the longitudinal metal electrode is connected to a 1 μm to 3 μm wide region at the right end of the ultra-thin silicon strip.

[0066] In step S3, in order to reduce the influence of the symmetry of the ultra-thin silicon strips and improve the signal strength and detection sensitivity, the present invention is based on the designed readout circuit of the imaging chip, in order to generate a temperature difference, by changing the local electrical and optical properties of the ultra-thin silicon strip array, reducing the influence of the symmetry of the ultra-thin silicon strips, and obtaining the final imaging chip.

[0067] Furthermore, based on the readout circuit of the imaging chip, in order to generate a temperature difference, the method of reducing the influence of the symmetry of the ultra-thin silicon strips by changing the local electrical and optical properties of the ultra-thin silicon strip array includes:

[0068] A silicon dioxide layer of a set thickness is covered on the left half of the ultra-thin silicon strip as a heat insulation layer;

[0069] A gold layer of a set thickness is plated on the area on the left half of the ultra-thin silicon strip that is already covered with the silicon dioxide layer as a light-blocking layer.

[0070] As an optional specific implementation method, a 60nm~120nm silicon dioxide layer is covered on the left half of the ultra-thin silicon strip as a heat insulation layer; and a 60nm~120nm gold layer is plated on the left half of the ultra-thin silicon strip covered with the silicon dioxide layer as a light blocking layer.

[0071] like Figure 5 As shown, Figure 5 The left half is the structure of the ultra-thin silicon strip array under an optical microscope. Figure 5 The right half is a diagram of the ultra-thin silicon strip array unit structure under an electron microscope.

[0072] The following is a detailed introduction to the process flow of ultra-thin single-crystal silicon imaging chips (n×n, taking 4×4 focal plane array as an example) for visible-near infrared. Figure 6 As shown:

[0073] 1. Initial material preparation and cleaning

[0074] Material selection: A silicon-on-insulator (SOI) wafer of suitable size is selected, in which the silicon layer is P-type and doped with boron, with a resistivity of 10Ωcm, a crystal orientation of (100), and an initial thickness of 220nm.

[0075] Cleaning: The silicon wafer is thoroughly cleaned using the standard RCA cleaning process to remove organic matter, metal ions and other impurities on the surface.

[0076] 2. Silicon layer etching and thinning

[0077] Deep silicon etching: Deep silicon etching technology (such as STS HRM) is used to precisely thin the thickness of the top silicon layer from 220nm to 20nm to meet the needs of ultra-thin imaging chips.

[0078] Re-cleaning: Use the RCA cleaning process to clean the thinned silicon wafer to ensure that the surface is clean and free of residue.

[0079] 3. Preparation of Ultrathin Silicon Strips

[0080] Electron beam lithography: Electron beam lithography (EBL) is used to define the pattern of the silicon stripes.

[0081] Deep silicon etching: Deep silicon etching technology is used again to etch ultra-thin silicon strips with a length of 16μm and a width of 3μm according to the pattern defined by electron beam lithography.

[0082] 4. Preparation of lateral metal electrodes

[0083] Removal of photoresist: Remove PMMA photoresist by soaking in 60℃ hot acetone for 30 minutes.

[0084] Metal deposition: Using an aligned mask and electron beam evaporation technique, 5nm of Cr is deposited as an adhesion layer, followed by 60nm of Au as a conductive layer to form a lateral metal electrode. The electrode width is 1μm, covering the 1x2.5μm² area at the leftmost end of the ultra-thin silicon strip.

[0085] Photolithography stripping: The unnecessary metal parts are removed by photolithography stripping technology to complete the preparation of lateral electrodes.

[0086] 5. Preparation of insulation layer and thermal insulation layer

[0087] Remove the photoresist again: Repeat the previous steps to remove the PMMA photoresist.

[0088] Insulation and thermal insulation layer deposition: A 100nm SiO2 insulation layer is grown at 75°C using inductively coupled plasma chemical vapor deposition (ICPCVD) technology to cover the entire area near the ultra-thin silicon strip array (insulation layer) and the 7x2.5μm² area on the left half of the silicon strip not covered by the lateral electrode (thermal insulation layer).

[0089] Photolithography stripping: The unwanted SiO2 parts are removed by photolithography stripping technology.

[0090] 6. Longitudinal Metal Electrode Preparation

[0091] Photoresist removal: Remove the PMMA photoresist again.

[0092] Metal deposition: Using an aligned mask and electron beam evaporation technique, 5nm of Cr and 120nm of Au are deposited to form a vertical metal electrode covering the 1x2.5μm² area at the rightmost end of the ultra-thin silicon strip.

[0093] Photolithography stripping: Remove unnecessary metal parts and complete the preparation of vertical electrodes.

[0094] 7. Preparation of reflective layer and definition of photosensitive area

[0095] Photoresist removal: Remove PMMA photoresist.

[0096] Reflective layer deposition: On the 7×2.5μm² area on the left half of the ultra-thin silicon strip that is not covered by the lateral electrode, 5nm of Cr and 100nm of Au are deposited as reflective layers, which work together with the SiO2 insulation layer to form a heat-insulating and light-blocking structure.

[0097] Definition of photosensitive area: Through the above steps, the 7×2.5μm² area on the right half of the silicon strip of each unit device becomes the photosensitive area, which can receive and respond to visible-near infrared light signals without considering the impact of the symmetry of the silicon strip on the device performance.

[0098] At this point, the preparation process of ultra-thin single-crystal silicon imaging chip (4×4 focal plane array) for visible-near infrared has been completed. Embodiment 2

[0099] like Figure 7 As shown, the present invention provides a design system for ultra-thin single-crystal silicon imaging chips for visible-near infrared, which is used to implement the design method for ultra-thin single-crystal silicon imaging chips for visible-near infrared of the first embodiment, and specifically includes:

[0100] A material selection and unit device design module 100 is used to select a P-type silicon wafer as a substrate of an imaging chip and design an ultra-thin silicon strip as a unit device of the imaging chip;

[0101] A readout circuit design module 200 is used to design a readout circuit of an imaging chip based on an ultra-thin silicon strip array;

[0102] The symmetry optimization module 300 is used in a readout circuit based on an imaging chip. In order to generate a temperature difference, the influence of the symmetry of the ultra-thin silicon strips is reduced by changing the local electrical and optical properties of the ultra-thin silicon strip array to obtain the final imaging chip.

[0103] A design system for ultra-thin single-crystal silicon imaging chips for visible-near-infrared in this embodiment is used to implement the aforementioned design method for ultra-thin single-crystal silicon imaging chips for visible-near-infrared. Therefore, the specific implementation method of the design system for ultra-thin single-crystal silicon imaging chips for visible-near-infrared can be found in the embodiment part of the design method for ultra-thin single-crystal silicon imaging chips for visible-near-infrared in the aforementioned text. For example, the material and unit device design module 100, the readout circuit design module 200, and the symmetry optimization module 300 are respectively used to implement steps S1, S2, and S3 in the aforementioned design method for ultra-thin single-crystal silicon imaging chips for visible-near-infrared. Therefore, its specific implementation method can refer to the description of the corresponding embodiments of each part. In order to avoid redundancy, it will not be repeated here.

[0104] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from them are still within the protection scope of the invention.

Claims

1. A design method for ultra-thin single-crystal silicon imaging chip for visible-near infrared, characterized in that: include: A P-type silicon wafer is selected as the substrate of the imaging chip, and an ultra-thin silicon strip is designed as the unit device of the imaging chip, wherein the thickness of the ultra-thin silicon strip is 10nm to 50nm; Based on the ultra-thin silicon strip array, the readout circuit of the imaging chip is designed, including: On a SiO2 / Si substrate with an array of ultra-thin silicon strips, a layer of lateral metal electrodes is prepared, and the lateral metal electrodes are connected to a region within a set range at the left end of the ultra-thin silicon strips; A layer of silicon dioxide with a set thickness is covered on the lateral metal electrode as an insulating layer; A layer of longitudinal metal electrode is prepared on the silicon dioxide insulating layer, and the longitudinal metal electrode is connected to an area within a set range at the right end of the ultra-thin silicon strip; Based on the readout circuit of the imaging chip, in order to generate a temperature difference, the local electrical and optical properties of the ultra-thin silicon strip array are changed to reduce the influence of the symmetry of the ultra-thin silicon strips, thereby obtaining the final imaging chip.

2. The design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to claim 1, characterized in that: The resistivity of the P-type silicon wafer ranges from 8.5Ωcm to 11.5Ωcm.

3. The design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to claim 1, characterized in that: The size range of the ultra-thin silicon strip is: 2.5 μm to 3.5 μm in width and 16 μm to 20 μm in length.

4. The design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to claim 1, characterized in that: The method for connecting the lateral metal electrode to the area within a set range at the left end of the ultra-thin silicon strip is: The lateral metal electrode is connected to the 1 μm to 3 μm wide area at the left end of the ultra-thin silicon strip.

5. The design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to claim 1, characterized in that: The method of covering a layer of silicon dioxide with a set thickness as an insulating layer on the lateral metal electrode is: A 60nm to 120nm layer of silicon dioxide is covered on the lateral metal electrode as an insulating layer.

6. The design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to claim 1, characterized in that: The method for connecting the longitudinal metal electrode to the area within the set range at the right end of the ultra-thin silicon strip is: The longitudinal metal electrode is connected to the 1 μm to 3 μm wide area at the right end of the ultra-thin silicon strip.

7. The design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to claim 1, characterized in that: Based on the readout circuit of the imaging chip, in order to generate a temperature difference, the method of reducing the influence of the symmetry of the ultra-thin silicon strips by changing the local electrical and optical properties of the ultra-thin silicon strip array includes: A silicon dioxide layer of a set thickness is covered on the left half of the ultra-thin silicon strip as a heat insulation layer; A gold layer of a set thickness is plated on the area on the left half of the ultra-thin silicon strip that is already covered with the silicon dioxide layer as a light-blocking layer.

8. The design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to claim 7, characterized in that: The method of covering the left half of the ultra-thin silicon strip with a silicon dioxide layer of a set thickness as a heat insulation layer, and plating a gold-plated layer of a set thickness as a light-blocking layer on the left half of the ultra-thin silicon strip covered with the silicon dioxide layer comprises: A 60nm to 120nm silicon dioxide layer is covered on the left half of the ultra-thin silicon strip as a heat insulation layer; A 60nm to 120nm gold layer is plated on the area on the left half of the ultra-thin silicon strip that is covered with the silicon dioxide layer as a light-blocking layer.

9. A design system for ultra-thin single-crystal silicon imaging chips for visible-near infrared, characterized in that: The system is used to implement the design method of the ultra-thin single-crystal silicon imaging chip for visible-near infrared according to any one of claims 1 to 8, specifically comprising: The material selection and unit device design module is used to select P-type silicon wafer as the substrate of the imaging chip and design ultra-thin silicon strips as the unit devices of the imaging chip; The readout circuit design module is used to design the readout circuit of the imaging chip based on the ultra-thin silicon strip array; The symmetry optimization module is used in the readout circuit based on the imaging chip. In order to generate a temperature difference, the local electrical and optical properties of the ultra-thin silicon strip array are changed to reduce the influence of the symmetry of the ultra-thin silicon strips and obtain the final imaging chip.

Images