Wafer-level chip manufacturing method

Abstract

The invention discloses a wafer-level chip manufacturing method, comprising: providing a first wafer; forming a first bonding layer on the first wafer; providing a second wafer and at least four second chips; bonding the second chip on the second wafer; continuing to form a first dielectric layer on the second wafer bonded with the second chip; etching the first dielectric layer to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug interconnected with an electrode of the second chip; forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer; continuing to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnection structure to form a second reconstructed wafer; bonding the second reconstructed wafer to the first wafer; removing the second wafer; etching the first dielectric layer and the second dielectric layer. The system-level packaging integration is improved, and better line width and higher yield are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device packaging, and in particular to a wafer-level chip manufacturing method. Background Art

[0002] System in Package (Sip) can combine multiple active components with different functions, as well as passive components, micro-electromechanical systems (MEMS), optical components and other components into one unit to form a system or subsystem that can provide multiple functions, allowing heterogeneous IC integration. It effectively solves the problem that SOC (system on chip) cannot integrate analog, RF and digital functions. System in Package (SiP) integration is relatively simple, with shorter design cycle and time to market, lower cost, and can realize more complex systems.

[0003] In the prior art, when packaging a chip, the chip is first bonded to one side of the wafer without being electrically connected to the wafer, and then the plastic encapsulation process is performed to seal and fix the chip. Then, a through hole (with a conductive structure formed in the through hole) connecting the chip is formed on the other side of the wafer, and the chip's electrical signal is led out through the conductive structure. After the plastic encapsulation process, the wafer has a large warpage, and it is difficult to reduce the line width during photolithography. There is also the problem that the machine cannot hold the wafer. Therefore, how to improve the integration of system-level packaging and achieve better line width and higher yield is a current research topic. Summary of the invention

[0004] In order to solve the above problems, the object of the present invention is to provide a wafer-level chip manufacturing method comprising:

[0005] Providing a first wafer, wherein the first wafer comprises at least two identical first bare chips arranged in an array, and the bare chip surfaces have I / O metal pads;

[0006] forming a first bonding layer on the first wafer;

[0007] Providing a second wafer and at least four second chips, wherein the second chips have a device layer and an electrode layer connected to the device layer;

[0008] Bonding the second chips to the second wafer, wherein the positions of at least two second chips correspond to the positions of the first bare chips, and the electrode layer of the second chips faces away from the second wafer;

[0009] Continue to form a first dielectric layer on the second wafer bonded with the second chip;

[0010] Etching the first dielectric layer to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug interconnected with an electrode of the second chip;

[0011] forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer;

[0012] Continue to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnect structure to form a second reconstructed wafer;

[0013] Bonding the second reconstructed wafer to the first wafer, wherein the second dielectric layer of the second reconstructed wafer is opposite to the first bonding layer of the first wafer, and at least every two second chips correspond to the first bare chip;

[0014] removing the second wafer;

[0015] The first dielectric layer and the second dielectric layer are etched to form a through hole exposing the horizontal conductive structure and the I / O metal pad, and a conductive material is formed in the through hole to form a second vertical conductive plug.

[0016] The present invention realizes the interconnection of devices under different semiconductor processes by reconstructing the second wafer and interconnecting the second wafer with the first wafer, thereby reducing the chip area and increasing the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of a process flow of a wafer-level chip manufacturing method according to an embodiment of the present invention;

[0019] Figure 2 to Figure 6 FIG. 4 is a cross-sectional schematic diagram of a wafer-level chip manufacturing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0021] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In the present invention, it is an electrical device, so connection and interconnection both refer to conductive interconnection. Since the accompanying drawings are descriptions of the same device, the same numbers in the drawings represent the same components.

[0022] An embodiment of the present invention provides a wafer-level chip manufacturing method, a wafer-level chip manufacturing method comprising:

[0023] Providing a first wafer, wherein the first wafer comprises at least two identical first bare chips arranged in an array, and the bare chip surfaces have I / O metal pads;

[0024] forming a first bonding layer on the first wafer;

[0025] Providing a second wafer and at least four second chips, wherein the second chips have a device layer and an electrode layer connected to the device layer;

[0026] Bonding the second chips to the second wafer, wherein the positions of at least two second chips correspond to the positions of the first bare chips, and the electrode layer of the second chips faces away from the second wafer;

[0027] Continue to form a first dielectric layer on the second wafer bonded with the second chip;

[0028] Etching the first dielectric layer to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug interconnected with an electrode of the second chip;

[0029] forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer;

[0030] Continue to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnect structure to form a second reconstructed wafer;

[0031] Bonding the second wafer to the first wafer, wherein the second dielectric layer of the second reconstructed wafer is opposite to the first bonding layer of the first wafer, and at least every two second chips correspond to the first bare chip;

[0032] removing the second wafer;

[0033] The first dielectric layer and the second dielectric layer are etched to form a through hole exposing the horizontal conductive structure and the I / O metal pad, and a conductive material is formed in the through hole to form a second vertical conductive plug.

[0034] In one embodiment, the material of the second dielectric layer is the same as that of the first bonding layer, and in the step of bonding the first wafer to the second wafer, the first bonding layer and the second bonding layer are attached to each other.

[0035] In one embodiment, the method further includes continuously forming a second bonding layer on the second dielectric layer.

[0036] In one embodiment, the first wafer and the second wafer are identical and their edges overlap during bonding.

[0037] In one embodiment, after taking out the second wafer, the method further includes removing the bonding material between the second chip and the second wafer.

[0038] In one embodiment, the first dielectric layer and the second dielectric layer are made of different materials.

[0039] In one embodiment, the step of etching the first dielectric layer and the second dielectric layer to form a through hole comprises:

[0040] Etching the second dielectric layer to form a first sub-via exposing an edge of the horizontal conductive structure;

[0041] Etching is continued to form a second sub-via connected to the first sub-via, the second sub-via stops at the surface of the I / O metal pad, and the cross-sectional area of ​​the second sub-via is larger than the area of ​​the exposed horizontal conductive structure.

[0042] In one embodiment, the step of etching the first dielectric layer and the second dielectric layer to form a through hole requires optical alignment.

[0043] In one embodiment, the first dielectric layer is silicon dioxide, and the second dielectric layer is silicon nitride.

[0044] In one embodiment, the second vertical conductive plug is located in a peripheral area of ​​the second chip.

[0045] In one embodiment, before the step of etching the first dielectric layer and the second dielectric layer to form a through hole, the method further includes:

[0046] Providing a third wafer substrate and a third chip, wherein the third chip has a device layer and an electrode layer connected to the device layer;

[0047] Bonding a third chip to a third wafer substrate, wherein the position of the third chip corresponds to the positions of the first bare chip and the second chip, and the electrode layer of the third chip faces away from the third wafer;

[0048] Continue to form a first dielectric layer on the third wafer substrate bonded with the third chip;

[0049] Etching the first dielectric layer to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug interconnected with an electrode of the third chip;

[0050] forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer;

[0051] Continue to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnect structure to form a third wafer;

[0052] forming a third bonding layer on the second wafer;

[0053] Bonding the third wafer to the second wafer, wherein the second dielectric layer of the third wafer is opposite to the third bonding layer of the first wafer;

[0054] The third wafer is removed.

[0055] The embodiments are described in detail below with reference to the accompanying drawings. Figure 1 This is a flowchart of a wafer-level chip manufacturing method according to an embodiment of the present invention. Figure 1 , the wafer-level chip manufacturing method:

[0056] S10: providing a first wafer, wherein the first wafer comprises at least two identical first bare chips arranged in an array, and surfaces of the bare chips have I / O metal pads.

[0057] Specifically, in this embodiment, Figure 2 As shown, the first wafer 100 includes a semiconductor substrate 100, and the semiconductor substrate is silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors. In this embodiment, it is a silicon substrate, and an epitaxial layer 101 is formed on the silicon substrate. A plurality of first bare chips 102 arranged in an array composed of semiconductor devices are formed in the epitaxial layer 101 and the silicon substrate 100. For example, the first bare chip 102 can be a logic circuit composed of MOS transistors or a semiconductor device such as MEMS, a sensor, etc. An insulating layer 103 is also formed on the epitaxial layer 101. The material of the insulating layer includes silicon dioxide and silicon nitride, etc. The insulating layer covers the semiconductor device, and a metal solder joint 104 interconnected with the semiconductor device is provided on the insulating layer. For example, in this embodiment, the I / O metal solder joint is interconnected with the semiconductor device through a contact hole 105.

[0058] S20: forming a first bonding layer on the first wafer.

[0059] Specifically, the first bonding layer may be silicon dioxide, which will be in a hot-melt state after being heated.

[0060] S30: providing a second wafer and at least four second chips, wherein the second chips have electrode layers connecting device layers.

[0061] Specifically, the second wafer can be silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductor wafers. In the present embodiment, it is a silicon wafer. The second chip can be a logic circuit composed of MOS transistors or a semiconductor device such as MEMS, a sensor, etc. In the present embodiment, it is preferred that the device is formed by a semiconductor process different from the first bare chip, so that the problem that chips with different process cannot be formed on the same production line and the problem of increased volume caused by packaging chips with different processes can be solved by wafer packaging.

[0062] S40: bonding the second chips to the second wafer, with positions of at least two second chips corresponding to positions of the first bare chips, and electrode layers of the second chips facing away from the second wafer.

[0063] like Figure 3 As shown, specifically, a second bonding layer can be formed on the second wafer 200, and the second bonding layer can be a pyrolysis film or a photolysis film. The pyrolysis film loses its viscosity when it is higher than the set temperature. Different pyrolysis films lose their viscosity at different temperatures, such as failure at 70 to 80 degrees, failure at around 200 degrees, and failure at temperatures above 400 degrees. The photolysis film loses its viscosity when exposed to ultraviolet light. Then the second chip 300 is bonded to the second wafer 200. It should be noted that since the second wafer 200 is used as a carrier for bonding the second chip 210 and the first bare chip, when bonding the second chip 210, it is necessary to match the position of the first bare chip on the first wafer. Specifically, the second chip 210 is placed on the second bonding layer for bonding, and the electrode layer 201 is located on the surface.

[0064] S50 : Continue to form a first dielectric layer 220 on the second wafer 200 bonded with the second chip 210 .

[0065] For details, please refer to Figure 3 In this embodiment, after bonding the second chip 210, the second wafer 200 is filled with dielectric material to form a first dielectric layer 220. The first dielectric layer 220 serves as protection and support for the second chip 210 and is also used for subsequent bonding and interconnection. The first dielectric layer 220 can be one or a combination of two or more of silicon dioxide, silicon nitride, epoxy resin, silica gel, polyimide, benzocyclobutene, silicon oxide, phosphorus silicon glass, and fluorine-containing glass.

[0066] S60: etching the first dielectric layer 220 to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug 230 interconnected with the electrode 201 of the second chip.

[0067] Specifically, refer to Figure 4 , the first dielectric layer can be etched by dry or wet etching, and a through hole is etched in the first dielectric layer corresponding to the electrode that needs to be connected and cooperated with the first chip. Then the through hole is filled by chemical vapor deposition, physical vapor deposition or electroplating. In this embodiment, the filled deposited conductive material can be one of the following metal materials: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), or palladium (Pd) or a laminate formed by the above metals. The conductive material can be formed by physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering and evaporation.

[0068] S70: forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer.

[0069] Continue to refer Figure 3 Specifically, a horizontal conductive structure 240 interconnected with the first vertical conductive plug 230 is formed on the first dielectric layer, which can be formed by chemical vapor deposition, physical vapor deposition or electroplating. The deposited conductive material can be one of the following metal materials: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), or palladium (Pd), or a stack of the above metals. The conductive material can be formed by physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering and evaporation.

[0070] In this embodiment, one end of the horizontal conductive structure 240 extends to the periphery of the second chip 210 for subsequent interconnection with the first bare chip.

[0071] S80 : Continue to form a second dielectric layer 260 on the first dielectric layer 220 and the horizontal conductive interconnect structure 240 to form a second reconstructed wafer.

[0072] refer to Figure 4Specifically, a second dielectric layer 250 is filled on the first dielectric layer 220, so as to be used for interlayer support and to form subsequent bonding and interconnection. The second dielectric layer 250 can be specifically one or a combination of two or more of a silicon dioxide layer, silicon nitride, epoxy resin, silica gel, polyimide, benzocyclobutene, silicon oxide, phosphosilicate glass, and fluorine-containing glass. In this embodiment, preferably, the second dielectric layer and the first dielectric layer are made of different materials, for example, the first dielectric layer is a silicon dioxide layer, and the second dielectric layer is silicon nitride or a photoresist material, so that in the subsequent etching step of forming through holes, it can be performed step by step, thereby forming through holes with different shapes, and preventing subsequent interconnection.

[0073] S90: Reference Figure 5 , bonding the second reconstructed wafer to the first wafer, wherein the second dielectric layer of the second reconstructed wafer is opposite to the first bonding layer of the first wafer, and at least every two second chips correspond to the first bare chip.

[0074] Specifically, since the present invention is a new chip wafer-level manufacturing method, in this embodiment, the first wafer and the second wafer have the same size. When bonding the first wafer and the second reconstructed wafer, the edges of the first wafer and the second wafer need to overlap, and then the first bare chip and the second chip to be interconnected need to be optically aligned. In the direction perpendicular to the wafer surface, the IO metal welding of the first wafer overlaps or partially overlaps with the horizontal conductive structure, for example, Figure 6 As shown, one of the horizontal conductive structures 2011 completely covers the IO metal pad when projected in a direction perpendicular to the first wafer, and the other horizontal conductive structure 2012 partially covers the IO metal pad when projected in a direction perpendicular to the first wafer.

[0075] Specifically, a third bonding layer is formed on the second reconstructed wafer, and the third bonding layer can be made of the same material as the first bonding layer. Specifically, the first bonding layer of the first wafer and the third bonding layer of the second reconstructed wafer can be laminated, and then heated at a high temperature to melt the first bonding layer and the third bonding layer, thereby bonding them.

[0076] S100: removing the second wafer.

[0077] refer to Figure 6 Specifically, in this embodiment, the second bonding layer uses a photolytic film or a pyrolytic film, so when the second wafer is removed, it loses its viscosity at high temperature. Different pyrolytic films lose their viscosity at different temperatures, such as failing at 70 to 80 degrees, failing at around 200 degrees, and failing at temperatures above 400 degrees. The photolytic film loses its viscosity when irradiated with ultraviolet light.

[0078] S110: etching the first dielectric layer and the second dielectric layer to form a through hole exposing the horizontal conductive structure and the I / O metal pad, forming a conductive material in the through hole to form a second vertical conductive plug.

[0079] Continue to refer Figure 6 Specifically, in this embodiment, optical alignment is used to etch the first dielectric layer to form a first sub-via, exposing the horizontal conductive structure 2011, wherein the bottom surface of the first sub-via is completely projected on the horizontal conductive structure 2011, and then the second dielectric layer is etched to form a second sub-via, wherein the second sub-via exposes the IO metal pad, wherein the bottom surface of the second sub-via is completely projected on the IO metal pad. In other words, the first sub-via and the second sub-via are completely through structures with the same radial size. In another embodiment, the radial sizes of the first sub-via and the second sub-via may also be different.

[0080] In another horizontal conductive 2012 region, optical alignment is used to etch the first dielectric layer to form a first sub-via, exposing the horizontal conductive structure 2012, wherein the bottom surface of the first sub-via is partially projected on the horizontal conductive structure 2012, and then the second dielectric layer is etched to form a second sub-via, wherein the second sub-via exposes the IO metal pad, wherein the bottom surface of the second sub-via is completely projected on the IO metal pad, in other words, the first sub-via and the second sub-via are completely through structures with the same radial size. In another embodiment, the radial sizes of the first sub-via and the second sub-via are different, and the first sub-via will continue to etch downward to the second dielectric layer when the first sub-via is etched to the position of the first dielectric layer, and will stop at the surface of the horizontal conductive structure when the first sub-via is etched to the position of the horizontal conductive structure, thereby achieving interconnection without damaging the horizontal conductive structure.

[0081] Then, the conductive material deposited in the first sub-contact hole and the second sub-contact hole by chemical vapor deposition, physical vapor deposition or electroplating can be one of the following metal materials: molybdenum (Mo), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), platinum (Pt), ruthenium (Ru), rhodium (Rh), iridium (Ir), chromium (Cr), titanium (Ti), gold (Au), osmium (Os), rhenium (Re), or palladium (Pd) or a laminate formed by the above metals. The conductive material can be formed by physical vapor deposition or chemical vapor deposition methods such as magnetron sputtering and evaporation.

[0082] In one embodiment, before the step of etching the first dielectric layer and the second dielectric layer to form a through hole, the method further includes:

[0083] Providing a third wafer substrate and a third chip, wherein the third chip has a device layer and an electrode layer connected to the device layer;

[0084] Bonding a third chip to a third wafer substrate, wherein the position of the third chip corresponds to the positions of the first bare chip and the second chip, and the electrode layer of the third chip faces away from the third wafer;

[0085] Continue to form a first dielectric layer on the third wafer substrate bonded with the third chip;

[0086] Etching the first dielectric layer to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug interconnected with an electrode of the third chip;

[0087] forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer;

[0088] Continue to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnect structure to form a third wafer;

[0089] forming a third bonding layer on the second reconstructed wafer;

[0090] Bonding a third wafer to a second reconstructed wafer, wherein the second dielectric layer of the third wafer is opposite to the third bonding layer of the first wafer;

[0091] The third wafer is removed.

[0092] In one embodiment, the method further includes cutting the first wafer and the second wafer into a plurality of devices, each device including at least one first bare chip and at least two second chips.

[0093] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A wafer-level chip manufacturing method, characterized in that: include: Providing a first wafer, wherein the first wafer comprises at least two identical first bare chips arranged in an array, and the bare chip surfaces have I / O metal pads; forming a first bonding layer on the first wafer; Providing a second wafer and at least four second chips, wherein the second chips have a device layer and an electrode layer connected to the device layer; Bonding the second chips to the second wafer, wherein the positions of at least two second chips correspond to the positions of the first bare chips, and the electrode layer of the second chips faces away from the second wafer; Continue to form a first dielectric layer on the second wafer bonded with the second chip; Etching the first dielectric layer to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug interconnected with an electrode of the second chip; forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer; Continue to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnect structure to form a second reconstructed wafer; Bonding the second reconstructed wafer to the first wafer, wherein the second dielectric layer of the second reconstructed wafer is opposite to the first bonding layer of the first wafer, and at least every two second chips correspond to the first bare chip; removing the second wafer; The first dielectric layer and the second dielectric layer are etched to form a through hole exposing the horizontal conductive structure and the I / O metal pad, and a conductive material is formed in the through hole to form a second vertical conductive plug.

2. The wafer-level chip manufacturing method according to claim 1, characterized in that: The material of the second dielectric layer is the same as that of the first bonding layer. In the step of bonding the second reconstructed wafer to the first wafer, the first bonding layer and the second bonding layer are attached to each other.

3. The wafer-level chip manufacturing method according to claim 1, characterized in that: The method also includes continuously forming a second bonding layer on the second dielectric layer.

4. The wafer-level chip manufacturing method according to claim 2, characterized in that: The first wafer and the second wafer have the same size, and their edges overlap during the bonding process.

5. The wafer-level chip manufacturing method according to claim 3, characterized in that: After taking out the second wafer, the method further includes removing the bonding material between the second chip and the second wafer.

6. The wafer-level chip manufacturing method according to claim 4, characterized in that: The first dielectric layer and the second dielectric layer are made of different materials.

7. The wafer-level chip manufacturing method according to claim 5, characterized in that: The step of etching the first dielectric layer and the second dielectric layer to form a through hole comprises: Etching the second dielectric layer to form a first sub-via exposing an edge of the horizontal conductive structure; Etching is continued to form a second sub-via connected to the first sub-via, the second sub-via stops at the surface of the I / O metal pad, and the cross-sectional area of ​​the second sub-via is larger than the area of ​​the exposed horizontal conductive structure.

8. The wafer-level chip manufacturing method according to claim 6, characterized in that: The step of etching the first dielectric layer and the second dielectric layer to form a through hole requires optical alignment.

9. The wafer-level chip manufacturing method according to claim 7, characterized in that: The second vertical conductive plug is located in a peripheral area of ​​the second chip.

10. The wafer-level chip manufacturing method according to claim 8, characterized in that: Before the step of etching the first dielectric layer and the second dielectric layer to form a through hole, the step further includes: Providing a third wafer substrate and a third chip, wherein the third chip has a device layer and an electrode layer connected to the device layer; Bonding a third chip to a third wafer substrate, wherein the position of the third chip corresponds to the positions of the first bare chip and the second chip, and the electrode layer of the third chip faces away from the third wafer; Continue to form a first dielectric layer on the third wafer substrate bonded with the third chip; Etching the first dielectric layer to form a through hole, and depositing a conductive material in the through hole to form a first vertical conductive plug interconnected with an electrode of the third chip; forming a horizontal conductive structure interconnected with the first vertical conductive plug on the first dielectric layer; Continue to form a second dielectric layer on the first dielectric layer and the horizontal conductive interconnect structure to form a third wafer; forming a third bonding layer on the second reconstructed wafer; Bonding a third wafer to the second reconstructed wafer, wherein the second dielectric layer of the third wafer is opposite to the third bonding layer of the first wafer; The third wafer is removed.

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