Package structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a packaging structure and a manufacturing method thereof, the packaging structure comprising: a main processing chip; a chip stack group located at least one side of the main processing chip, the chip stack group comprising chips stacked, each layer of the chips comprising at least two chip functional areas arranged at intervals, and the bottommost chip further comprising a bottom layer connecting area located between the adjacent two chip functional areas of the bottommost layer and connected with the chip functional areas; the chip functional areas of the multilayer chips are arranged in alignment in the stacking direction; a first packaging layer at least covering the sidewalls of the chip stack group; and a second packaging layer at least filled between the chip stack group and the main processing chip and covering at least part of the surface of the first packaging layer. The embodiment of the present disclosure can at least reduce the size of the packaging structure and avoid the problem of separation between the packaging layer and the chip.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the field of semiconductor, and particularly relates to a packaging structure and a manufacturing method thereof. BACKGROUND

[0002] 2.5D and 3D packaging are two advanced heterogeneous chip packaging, which can realize high-density line connection of multiple chips and thus integration into one packaging structure. For example, the packaging structure can include a chip stack group and a main processing chip arranged side by side.

[0003] With the increasing integration of the main processing chip, the size of the main processing chip is getting smaller and smaller. However, it is difficult to reduce the size of the chip stack group, so the size of the chip stack group and the main processing chip may not match, and the overall size of the packaging structure is large. In addition, the packaging layer in the packaging structure is prone to delamination. SUMMARY

[0004] The embodiments of the present disclosure provide a packaging structure and a manufacturing method thereof, which at least advantageously reduce the overall size of the packaging structure, match the size of the chip stack group with the size of the main processing chip, and advantageously avoid the problem of delamination of the packaging layer.

[0005] According to some embodiments of the present disclosure, the embodiments of the present disclosure provide a packaging structure, which includes: a main processing chip; a chip stack group located on at least one side of the main processing chip, the chip stack group including chips stacked, each layer of the chips including at least two chip functional areas arranged at intervals, and the bottom layer of the chips further including a bottom layer connection area located between the adjacent two chip functional areas of the bottom layer and connected with the chip functional areas; the chip functional areas of the multiple layers of the chips are arranged in alignment in the stacking direction; a first packaging layer at least covering the side wall of the chip stack group; and a second packaging layer at least filled between the chip stack group and the main processing chip and covering at least part of the surface of the first packaging layer.

[0006] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a manufacturing method of a packaging structure, the manufacturing method comprising: providing a plurality of chips, and stacking the plurality of chips to form a chip stack; each layer of the chips comprising at least two chip functional areas arranged at intervals, and the bottom layer of the chips further comprising a bottom layer connection area arranged between the adjacent chip functional areas of the bottom layer and connected with the chip functional areas; the chip functional areas of the plurality of layers of the chips being arranged in alignment in a stacking direction; performing a first packaging process to form a first packaging layer covering at least the sidewalls of the chip stack; providing a main processing chip, and arranging the chip stack on at least one side of the main processing chip; and performing a second packaging process to form a second packaging layer, the second packaging layer being arranged to at least fill the space between the chip stack and the main processing chip and cover at least part of the surface of the first packaging layer.

[0007] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: the at least two chip functional areas of the bottom layer of the chips are connected through the bottom layer connection area. That is, the bottom layer connection area is not cut. In this way, the width of the bottom layer connection area can be reduced to match the main processing chip of a smaller size. In addition, the chip stack is wrapped as a whole by the first packaging layer, so that the filling gap of the second packaging layer is reduced, which helps to avoid the problem of delamination of the packaging layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles behind the present disclosure. It is readily apparent to one skilled in the art that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative labor.

[0009] Figure 1 A perspective view of a packaging structure in the related art is shown.

[0010] Figure 2 A top view of a packaging structure in the related art is shown.

[0011] Figure 3 A cross-sectional view of a chip stack in the related art is shown.

[0012] Figure 4 A top view of a packaging structure provided in an embodiment of the present disclosure is shown.

[0013] Figures 5-6 Cross-sectional views of different chip stacks provided in embodiments of the present disclosure are shown, respectively.

[0014] Figures 7-10Corresponding structural diagrams of steps in a manufacturing method of a packaging structure provided in embodiments of the present disclosure are shown respectively. DETAILED DESCRIPTION

[0015] As can be known from the background, it is difficult to reduce the size of the chip stack group, and therefore, the size of the chip stack group and the main processing chip can not be matched, and the overall size of the packaging structure is large. In addition, the packaging layer in the packaging structure is prone to delamination. This will be analyzed and described below.

[0016] Figure 1 A perspective view of a packaging structure in the related art is shown, Figure 2 A top view of a packaging structure in the related art is shown, Figure 3 A cross-sectional view of a chip stack in the related art is shown. Reference Figures 1-3 In the related art, each layer of chip 100 of chip stack 10b actually only includes one chip functional area, and multiple chip stack 10b are arranged at intervals to form chip stack group 10a, which is arranged side by side on at least one side of main processing chip 200. In order to facilitate the placement of multiple chip stack 10b on the interposer and reserve space positions for subsequent filling of second packaging layer 420, the distance between adjacent chip stack 10b is usually large. Therefore, the size of chip stack group 10a is difficult to match the size of main processing chip 200.

[0017] In addition, in the related art, first packaging layer 410 is usually formed on the side wall of chip stack 10b and the side wall of main processing chip, and first packaging layer 410 and the structure wrapped thereby form a package. Thereafter, second packaging layer 420 is filled between adjacent packages. Since multiple chip stack 10b are independently arranged, there are many gaps in the packaging structure. When filling second packaging layer 420, due to the difference in matching between materials, the phenomenon of separation of second packaging layer 420 from the package is prone to occur.

[0018] This disclosure provides a packaging structure in which the bottom chip of a chip stack includes at least two chip functional regions and a bottom-level connection region located between adjacent chip functional regions. That is, the bottom-level connection region is not cut, and adjacent chip functional regions are connected through the bottom-level connection region. In some embodiments of this disclosure, the chip functional regions may be dies containing a specific number of banks. In one embodiment, the number of banks in each chip functional region is the same. In one embodiment, each chip in the chip stack includes a large chip composed of two dies. In this disclosure, this design reduces the width of the bottom-level connection region and the spacing between chip functional regions arranged in the same layer, thereby reducing the overall size of the chip stack. Furthermore, the first packaging layer and the chip stack it covers form a complete package, eliminating the need for a second packaging layer inside, thus reducing the filling gap and helping to avoid delamination between the second packaging layer and the package.

[0019] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0020] like Figures 4-6 As shown, one embodiment of this disclosure provides a packaging structure, which includes: a main processing chip 2; a chip stack 1a located on at least one side of the main processing chip 2, the chip stack 1a including stacked chips 1, each layer of chip 1 including at least two spaced chip functional regions 12, the bottom layer of chip 1 including a bottom connection region 13 located between two adjacent chip functional regions 12 at the bottom layer and connected to the chip functional regions 12; the chip functional regions 12 of the multilayer chip 1 are aligned in the stacking direction; a first packaging layer 41 covering at least the sidewall of the chip stack 1a; and a second packaging layer 42 filling at least between the chip stack 1a and the main processing chip 2, and the second packaging layer 42 covering at least a portion of the surface of the first packaging layer 41.

[0021] This design has at least the following advantages:

[0022] First, the two chip functional areas 12 are connected and configured through the bottom connection area 13, thus eliminating the need for a dicing channel between the two chip functional areas 12 to divide each individual chip functional area 12. The width of the bottom connection area 13 can be flexibly adjusted to fit the size of the main processing chip 2, thereby reducing the overall package size. Since the bottom connection area 13 does not need to be cut, damage to the bottommost chip 1 caused by cutting the bottom connection area 13 can be avoided.

[0023] Secondly, the chip stack group 1a is equivalent to including at least two chip stacks, and adjacent chip stacks can be connected at least through the bottom connection area 13. The bottom connection area 13 and the bottom chip functional area 12 can be regarded as an integrated structure. Compared with the case that the chip stack group 1a has multiple chip stacks arranged separately, the bottom connection area 13 can increase the stability of the chip stack group 1a, so that the first packaging layer 41 is not easy to separate from the chip stack group 1a.

[0024] Thirdly, the first packaging layer 41 and the multiple chip stacks wrapped by the first packaging layer 41 constitute a packaging body. Therefore, the number of packaging bodies is less, the gap between the packaging bodies is less, and the second packaging layer 42 is not easy to separate from the packaging body when filling the gap between the packaging bodies. Therefore, the reliability of the packaging structure is better.

[0025] The packaging structure will be described in detail below with reference to the accompanying drawings.

[0026] In some embodiments, the main processing chip 2 can be a central processing unit (CPU), a graphic processing unit (GPU), an accelerated processing unit (APU), or a neural-network processing unit (NPU). The chip stack group 1a can be a high bandwidth memory (HBM). The bottom chip 1 in the chip stack group 1a can be a logic chip, and the non-bottom chips 1 can be storage chips, such as dynamic random access memories (DRAMs). In other embodiments, all the chips 1 in the chip stack group 1a can also be storage chips.

[0027] Figure 4 A top view of the packaging structure is shown to be more intuitive, Figure 4 Part of the structure in the packaging structure is shown. Referring to Figure 4 In some embodiments, the opposite two sides of the chip stack group 1a are arranged in alignment with the opposite two sides of the main processing chip 2. That is, the width of the bottom connection area 13 can be adjusted so that the length of the chip stack group 1a can be equal to the length of the main processing chip 2 to ensure the matching degree of the sizes of the two. It should be noted that the length direction of the chip stack group 1a is the arrangement direction of the chip stacks.

[0028] Continuing to refer to Figure 4The number of the chip stack group 1a can be two, and the chip stack group 1a is arranged on opposite sides of the main processing chip 2 to make the chip stack group 1a symmetrically arranged relative to the main processing chip 2, thereby improving the communication speed between the chip stack group 1a and the main processing chip 2. The number of the chip functional areas 12 of each layer of the chip stack group 1a can be 2-8, that is, each chip stack group 1a can include 2-8 connected chip stacks.

[0029] With reference to Figures 5-6 , Figures 5-6 The different cross-sectional views of the two chip stack groups 1a are shown respectively, and the package structure further includes an interposer 7, and the chip stack group 1a and the main processing chip 2 are arranged on the interposer 7. The interposer 7 can have through-silicon vias and wiring layers and the like, thereby realizing the interconnection between the chip stack group 1a and the main processing chip 2. For example, the interposer 7 has physical port layers (Physical Layer, PHY) of the chip stack group 1a and the main processing chip 2, and the wiring layer can be connected between the physical port layers of the two, thereby forming the communication channel of the two. Since the size of the chip stack group 1a is reduced, the pitch of the multiple physical ports of the chip stack group 1a can be adjusted to adapt to the pitch of the multiple physical ports of the main processing chip 2, thereby simplifying the setting mode of the wiring layer.

[0030] The interposer 7 is manufactured using the same semiconductor processing technology as the IC device, so the line width and the line pitch formed on the interposer 7 are much smaller than the line width and the pitch available on the package substrate, thereby facilitating the realization of the ultra-wide communication channel of the chip stack. In other embodiments, the chip stack group 1a and the main processing chip 2 can also be arranged on the package substrate.

[0031] It should be noted that if the multiple chip stacks of the chip stack group 1a are independent of each other, multiple mounting steps are required to arrange the multiple chip stacks on the interposer 7; while in the embodiment of the present disclosure, the multiple chip stacks of the chip stack group 1a are connected as a whole, so only one mounting step is required to arrange them on the interposer 7, thereby improving the production efficiency. Similarly, only one filling process can be used to form the second underfill layer 82 between the chip stack group 1a and the interposer 7 to reduce the production cost. The second underfill layer 82 can have the functions of adhesion and fixation, and can also buffer thermal stress to avoid warping of the interposer 7 and the chip 1.

[0032] With reference to Figures 5-6The packaging structure further comprises a first redistribution layer 61, which is arranged across the bottom connection region 13 and is electrically connected to the chip functional regions 12 on the opposite sides of the bottom connection region 13. For example, the ports of the two bottommost chip functional regions 12 having the same signal can be electrically connected by the first redistribution layer 61, so as to reduce the number of interconnection structures between the bottommost chip 1 and the interposer 7, thereby facilitating the increase of the distance between the interconnection structures, and further simplifying the manufacturing process of the interconnection structures and reducing the degree of signal interference.

[0033] In addition, the first redistribution layer 61 is usually made of a material with high thermal conductivity, such as metal. Therefore, the first redistribution layer 61 can transfer part of the heat generated by the bottommost chip functional region 12 to the bottom connection region 13, so as to increase the heat dissipation effect of the bottommost chip functional region 12.

[0034] In some embodiments, the first redistribution layer 61 comprises a power supply line. This is because the power supply line usually generates a large amount of heat, and arranging it in the bottom connection region 13 can avoid the problem of heat accumulation in the bottommost chip functional region 12. For example, the power supply line can be a power supply line or a ground line. In addition, the first redistribution layer 61 can also comprise a communication line.

[0035] The interconnection structure between the bottommost chip 1 and the interposer 7 can comprise a first solder bump 31. A plurality of first solder bumps 31 are arranged on the lower surface of the bottommost chip 1. Among them, part of the first solder bumps 31 are arranged on the lower surface of the chip functional region 12, and part of the first solder bumps 31 are also arranged on the lower surface of the bottom connection region 13. In addition, the bottommost chip 1 further comprises a plurality of first conductive vias 51, part of the first conductive vias 51 penetrate the chip functional region 12, and part of the first conductive vias 51 penetrate the bottom connection region 13; the first redistribution layer 61 is further electrically connected to the first solder bump 31 and the first conductive via 51.

[0036] For example, the first solder bump 31 is a composite structure of a copper pillar and a solder layer. The first conductive via 51 can be a through-silicon via (TSV).

[0037] It should be noted that when the first conductive via 51 and the first solder bump 31 are also arranged in the bottom connection region 13, part of the communication channels and part of the power supply channels of the bottommost chip functional region 12 can be transferred to the bottom connection region 13, so as to increase the distance between each communication channel and each power supply channel of the chip functional region 12, thereby facilitating the reduction of process difficulty and reducing signal interference.

[0038] In some embodiments, the first conductive via 51 of the bottom connection region 13 can be a dummy conductive via, and the first solder bump 31 of the bottom connection region 13 can be a dummy solder bump. The dummy conductive via and the dummy solder bump do not serve the purpose of signal transmission or power supply. Since the dummy conductive via and the dummy solder bump are usually made of materials with high thermal conductivity, such as metal, they can also serve the purpose of improving the heat dissipation effect. In addition, the dummy solder bump can also enhance the connection strength between the bottommost chip 1 and the interposer 7, thereby improving the reliability of the packaging structure.

[0039] In some embodiments, referring to Figure 5 , the plurality of non-bottom chips 1 further include a top connection region 14, which is located between and connected to the chip functional regions 12 arranged in the same layer. In other words, the non-bottom chips 1 are not subjected to cutting processing, which can improve the structural strength of the chip stack 1a, avoid damage to the non-bottom chips 1 during cutting processing, and improve the efficiency of the stacked chips 1. For example, all non-bottom chips 1 include a top connection region 14, which is conducive to uniform manufacturing processes and reduces production costs.

[0040] Continuing to refer to Figure 5 , the packaging structure further includes a second redistribution layer 62, which spans the top connection region 14 and is electrically connected to the chip functional regions 12 on both sides of the top connection region 14. For example, the two non-bottom chip functional regions 12 arranged in the same layer and having the same signal port can be electrically connected by the second redistribution layer 62, which can reduce the number of interconnection structures between the two adjacent layers of chips 1, thereby facilitating an increase in the spacing of the interconnection structures, simplifying the manufacturing process of the interconnection structures, and reducing the degree of signal interference.

[0041] In addition, the second redistribution layer 62 can transfer part of the heat generated by the non-bottom chip functional region 12 to the top connection region 14, which can increase the heat dissipation effect of the chip functional region 12.

[0042] In some embodiments, the second redistribution layer 62 includes a power supply line, which can avoid the accumulation of excessive heat generated by the power supply line in the chip functional region 12. For example, the power supply line can be a power supply line or a ground line. In addition, the second redistribution layer 62 can also include a communication line.

[0043] Continuing to refer to Figure 5The interconnection structure between two adjacent non-bottom chips 1 can include second solder bumps 32. The second solder bumps 32 are located on the lower surface of the non-bottom chip 1, and part of the second solder bumps 32 are located on the lower surface of the chip functional area 12, and part of the second solder bumps 32 are located on the lower surface of the upper connection area 14. The second redistribution layer 62 is also electrically connected with the second solder bumps 32. The second solder bumps 32 of the upper connection area 14 can enhance the connection strength of the adjacent chips 1. For example, the lower surface of all non-bottom upper connection areas 14 is provided with second solder bumps 32.

[0044] In addition, the non-bottom chip 1 also includes a plurality of second conductive vias 52, part of which penetrate the chip functional area 12, and part of which penetrate the upper connection area 14. The second redistribution layer 62 is also electrically connected with the second conductive vias 52. For example, except for the topmost upper connection area 14, the second conductive vias 52 are provided in the remaining non-bottom upper connection areas 14.

[0045] Therefore, the space of the upper connection area 14 is fully utilized, and the second conductive vias 52 and the second solder bumps 32 are arranged in the upper connection area 14, so that the communication channel, the power supply channel and the heat dissipation channel of the non-bottom chip 1 can be flexibly adjusted.

[0046] In other embodiments, the second conductive vias 52 of the upper connection area 14 can be pseudo conductive vias, and the second solder bumps 32 of the upper connection area 14 can also be pseudo solder bumps. The pseudo conductive vias and the pseudo solder bumps do not play a role in signal transmission or power supply. The pseudo conductive vias and the pseudo solder bumps mainly play a role in improving the heat dissipation effect. In addition, the pseudo solder bumps can also enhance the connection strength between the chips 1, thereby improving the reliability of the packaging structure.

[0047] In some embodiments, in the direction parallel to the upper surface of the chip 1, the width of the upper connection area 14 is equal to the width of the bottom connection area 13. In this way, the uniformity of the packaging structure can be improved, and the production process can be simplified.

[0048] Continuing to refer to Figure 5 The first bottom filling layer 81 can reduce the influence of external forces such as vibration, drop and thermal stress on the second solder bumps 32, and avoid the problem of fracture of the second solder bumps 32. In addition, the first bottom filling layer 81 can also protect the second solder bumps 32 from damage by moisture, atmosphere or pollution in the environment, thereby improving the service life of the packaging structure.

[0049] When the non-bottom chip 1 includes the upper connection region 14, only one continuous first underfill layer 81 is formed between the adjacent chips 1, i.e., only one underfill process is used to form the first underfill layer 81 across the functional regions 12 of the chips. Therefore, the production efficiency is higher and the production cost is lower.

[0050] In addition, the first encapsulation layer 41 can cover the outer peripheral wall of the non-bottom chip 1 and cover part of the upper surface of the bottommost chip 1. When all the non-bottom chips 1 include the upper connection region 14, the interior of the chip stack 1a does not need to be filled with the first encapsulation layer 41, thereby reducing the probability of separation of the first encapsulation layer 41 from the chip 1.

[0051] The first encapsulation layer 41 can protect the chip stack 1a from the external environment, such as resisting external moisture, solvent, and resisting thermal shock and mechanical vibration during installation of the encapsulation structure. The material of the first encapsulation layer 41 can include organic adhesives, filler particles, curing agents, catalysts, coupling agents, wetting agents, flame retardants, defoamers, and other additives.

[0052] Reference Figure 6 In some embodiments, the plurality of non-bottom chips 1 form at least two spaced sub-stacks 15; the sub-stacks 15 are arranged in a direction parallel to the upper surface of the chip 1. The sub-stack 15 includes the stacked functional regions 12 of the chips, and the functional regions 12 in the same layer belong to different sub-stacks 15, respectively. That is, the non-bottom chip 1 can only include the spaced functional regions 12 and does not include the upper connection region 14 (see Figure 5 ). Since the size of the single functional region 12 is smaller than the size of the entire chip 1, the single functional region 12 has a smaller tendency to warp if thermal mismatch occurs.

[0053] The first encapsulation layer 41 can cover the outer peripheral wall of the non-bottom chip 1 and cover part of the upper surface of the bottommost chip 1. In addition, the first encapsulation layer 41 is also located between the adjacent sub-stacks 15 to protect and fix the sub-stacks 15.

[0054] Continuing to refer to Figure 6 , the encapsulation structure can further include a heat dissipation structure 9 penetrating through the first encapsulation layer 41 between the adjacent sub-stacks 15 and connected to the bottommost chip 1. For example, the heat dissipation structure 9 extends in the stacking direction, and the upper surface of the heat dissipation structure 9 is flush with the upper surface of the first encapsulation layer 41. The heat dissipation structure 9 can quickly dissipate the heat of the bottommost chip 1 outward. For example, the bottommost chip 1 can be a logic chip, and the logic chip generates a large amount of heat. The heat dissipation structure 9 can avoid the accumulation of heat in the logic chip, thereby ensuring the performance of the logic chip.

[0055] In addition, the heat dissipation structure 9 can also be connected with the first conductive via hole 51 or the first wiring layer 61 of the bottom connection area 13, so that a continuous heat dissipation channel is formed, thereby improving the heat dissipation effect.

[0056] With reference to the foregoing Figure 6 , a first bottom filling layer 81 can also be arranged between two adjacent chip functional areas 12, and a plurality of first bottom filling layers 81 in the same layer are spaced apart from each other.

[0057] With reference to the foregoing Figures 3-5 , the first encapsulation layer 41 can be a plurality of layers, and the first encapsulation layer 41 can also encapsulate the main processing chip 2. For example, the main processing chip 2 and the first encapsulation layer 41 encapsulating the main processing chip 2 together form a package, and the chip stack group 1a and the first encapsulation layer 41 encapsulating the chip stack group 1a together form another package. The second encapsulation layer 42 can be filled between adjacent packages and can also encapsulate the outer peripheral wall of each package. The second encapsulation layer 42 can play a role of bonding and protecting each package. Since there is less gap between the packages, the filling quality of the second encapsulation layer 42 can be improved, and the risk of delamination between the second encapsulation layer 42 and the package can be reduced.

[0058] In some embodiments, the material of the second encapsulation layer 42 is the same as that of the first encapsulation layer 41, so that they have the same thermal expansion coefficient to avoid separation. In other embodiments, the material of the second encapsulation layer 42 is different from that of the first encapsulation layer 41. For example, the second encapsulation layer 42 can be provided with more filling particles to improve the heat dissipation effect of the encapsulation structure.

[0059] In summary, the embodiments of the present disclosure change the structure of the package, so that there are a plurality of chip stacks connected in one package. Therefore, the interface between the package and the second encapsulation layer 42 can be reduced, thereby improving the reliability of the package. At the same time, the chip stack group 1a can correspond to the design of the main processing chip 2 to reduce the size of the encapsulation structure and improve the production efficiency.

[0060] With reference to the foregoing Figures 7-10 and Figures 5-6 , another embodiment of the present disclosure provides a manufacturing method of an encapsulation structure. The manufacturing method can manufacture the encapsulation structure provided in the foregoing embodiments. The details of the encapsulation structure can be referred to the foregoing embodiments. The manufacturing method of the encapsulation structure provided in an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in order to facilitate the description and clearly show the steps of the manufacturing method of the encapsulation structure, Figures 7-10 and Figures 5-6 are schematic diagrams of partial structures of the encapsulation structure.

[0061] With reference to the foregoing Figure 7 and Figure 8The plurality of chips 1 are provided, and the plurality of chips 1 are stacked to form a chip stack group la; each layer of chips 1 includes at least two chip functional areas 12 arranged at intervals, and the bottommost chip 1 further includes a bottom layer connection area 13 located between the adjacent chip functional areas 12 of the bottommost layer and connected with the chip functional areas 12; and the chip functional areas 12 of the plurality of layers of chips 1 are arranged in alignment in the stacking direction.

[0062] For example, a wafer 10 is provided, and the wafer 10 includes a plurality of chips 1. The chips 10 in the wafer 10 are defined as first chips, and the first chips will be the bottommost chips 1 of a chip stack group la formed subsequently. The first chips include at least two chip functional areas 12 and a bottom layer connection area 13. The first chips can be logic chips.

[0063] The wafer 10 further includes a scribe lane area 16 located between the adjacent first chips. In some embodiments, the width of the scribe lane area 16 can be greater than the width of the bottom layer connection area 13. The greater width of the scribe lane area 16 can provide a more sufficient buffer area for the chips 1 to avoid damage to the bottommost chips 1 in the subsequent scribing process. The smaller width of the bottom layer connection area 13 can reduce the overall size of the bottommost chips 1 to ensure that the size of the chip stack group la formed subsequently can be matched with the size of a main processing chip 2.

[0064] A plurality of chips 1 are provided as non-bottom chips 1, and the non-bottom chips 1 are defined as second chips. The second chips are stacked on the wafer 10, and the second chips can be memory chips. Referring to Figure 7 The second chips include a plurality of two chip functional areas 12 arranged at intervals, so that each layer of the second chips needs to undergo a plurality of stacking steps. Referring to Figure 8 The second chips include at least two chip functional areas 12 and an upper layer connection area 14 connected between the chip functional areas 12, so that each layer of the second chips only needs to undergo one stacking step. The upper layer connection area 14 is located between the adjacent chip functional areas 12 and connected with the chip functional areas 12.

[0065] In some embodiments, the second chips are stacked on the wafer 10 by flip-chip bonding, and the non-bottom chip functional areas 12 are arranged in alignment with the bottommost chip functional areas 12 (i.e., the chip functional areas 12 in the wafer 10). The adjacent chips 1 can be electrically connected by the second bonding bumps 32.

[0066] In some embodiments, before stacking the chips 1, a first redistribution layer 61 is also formed on the surface of the bottom chip 1 (the first chip), the first redistribution layer 61 crossing the bottom connection region 13 and electrically connecting with the chip functional region 12 on both sides of the bottom connection region 13. For example, the first redistribution layer 61 is formed by electroplating, and can be formed on the upper surface or the lower surface of the bottom chip 1. In other embodiments, the first redistribution layer 61 can also be formed on the lower surface of the bottom chip 1 after the chips 1 are stacked.

[0067] In some embodiments, before stacking the chips 1, a plurality of first solder bumps 31 are also formed on the lower surface of the bottom chip 1 (the first chip), part of the first solder bumps 31 being located on the lower surface of the chip functional region 12 and part of the first solder bumps 31 being located on the lower surface of the bottom connection region 13. The first redistribution layer 61 is electrically connected with the first solder bumps 31. In other embodiments, the first solder bumps 31 can also be formed on the lower surface of the bottom chip 1 after the chips 1 are stacked. For example, the first solder bumps 31 are formed by electroplating of a composite layer of copper and solder.

[0068] In some embodiments, before stacking the chips 1, a plurality of first conductive vias 51 are also formed in the bottom chip 1 (the first chip), part of the first conductive vias 51 penetrating the chip functional region 12 and part of the first conductive vias 51 penetrating the bottom connection region 13. The first redistribution layer 61 is electrically connected with the first conductive vias 51. For example, the first conductive vias 51 are formed by etching and then depositing a metal layer in the vias.

[0069] Reference Figure 8 In the non-bottom chip 1 (the second chip), an upper connection region 14 is also formed between the adjacent chip functional regions 12 and connected with the chip functional regions 12. In this case, before stacking the chips 1, a second redistribution layer 62 is also formed on the surface of the non-bottom chip 1, the second redistribution layer 62 crossing the upper connection region 14 and electrically connecting with the chip functional region 12 on both sides of the upper connection region 14. The second redistribution layer 62 can be formed on the upper surface or the lower surface of the chip 1.

[0070] Before stacking the chips 1, a second solder bump 32 can also be formed on the lower surface of the non-bottom chip 1. Part of the second solder bump 32 is located on the lower surface of the chip functional region 12 and part of the second solder bump 32 is located on the lower surface of the upper connection region 14.

[0071] In addition, a plurality of second conductive vias 52 can be formed in the non-bottom chip 1 between the stacked chips 1. Some of the second conductive vias 52 pass through the chip functional area 12, and some of the second conductive vias 52 pass through the upper connection area 14.

[0072] With reference to Figures 9-10 , a first encapsulation process is performed to form a first encapsulation layer 41 covering at least the sidewalls of the chip stack group 1a. For example, the first encapsulation layer 41 covers the sidewalls of the non-bottom chip 1 and covers part of the upper surface of the bottom chip 1. For example, the first encapsulation layer 41 is formed by a molding process.

[0073] With reference to Figure 9 When the non-bottom chip 1 does not include the upper connection area 14, that is, the chip stack group 1a includes at least two spaced sub-stacks 15, the first encapsulation layer 41 also fills between the adjacent sub-stacks 15, so as to play a role of bonding and fixing the sub-stacks 15.

[0074] With reference to Figure 9 After the first encapsulation layer 41 is formed, a laser punching process can be further performed on the first encapsulation layer 41 between the adjacent sub-stacks 15 to form a heat dissipation via that passes through the first encapsulation layer 41 and exposes the upper surface of the bottom connection area 13. Thereafter, a metal layer can be formed in the heat dissipation via by an electroplating process to serve as a heat dissipation structure 9. The heat dissipation structure 9 can be connected to the bottom connection area 13, so as to timely transfer the heat generated by the bottom chip 1 outward. It should be noted that the heat dissipation structure 9 can make full use of the space between the adjacent sub-stacks 15, and thus does not affect the size of the chip stack group 1a.

[0075] With reference to Figures 5-6 The first encapsulation layer 41 and the wafer 10 are cut to form a plurality of chip stack groups 1a. For example, the scribe lane area 16 and the first encapsulation layer 41 above it are cut, so as to separate a plurality of first chips from the wafer 10, and the chip stack group 1a and the first encapsulation layer 41 covering it constitute an encapsulation body.

[0076] With reference to Figures 4-6 A main processing chip 2 is provided, and the chip stack group 1a is arranged on at least one side of the main processing chip 2. For example, the chip stack group 1a and the main processing chip 2 are both soldered on the interposer 7, and there are two chip stack groups 1a, which are located on opposite sides of the main processing chip 2. In this way, the storage capacity can be improved while ensuring the symmetry of the structure.

[0077] With reference to Figure 4Before the main processing chip 2 is welded on the interposer 7, a first encapsulation layer 41 encapsulating the main processing chip 2 is formed, and the main processing chip 2 and the first encapsulation layer 41 encapsulating the main processing chip 2 constitute an encapsulation body.

[0078] With reference to the foregoing Figure 4 A second encapsulation process is performed to form a second encapsulation layer 42 at least filled between the chip stack group 1a and the main processing chip 2, and the second encapsulation layer 42 at least covers part of the surface of the first encapsulation layer 41. For example, the second encapsulation layer 42 can encapsulate the chip stack group 1a and the main processing chip 2.

[0079] Since the number of encapsulation bodies is reduced, the gap between the encapsulation bodies is reduced, thereby facilitating the reduction of bubbles generated when filling the second encapsulation layer 42, and avoiding the problem of delamination of the second encapsulation layer 42.

[0080] For example, the second encapsulation layer 42 is formed by a molding process, that is, the chip stack group 1a and the main processing chip 2 are encapsulated again by using a flowable molding material, and then the molding material is heated and solidified. In some embodiments, the material of the second encapsulation layer 42 can be the same as that of the first encapsulation layer 41, which facilitates the increase of the bonding strength of the two and avoids delamination of the two.

[0081] In summary, the chips 1 are heterogeneously stacked to provide a chip stack group 1a containing a plurality of connected chip stacks, thereby reducing the encapsulation process, reducing production cost, and improving product reliability. The plurality of encapsulation bodies are encapsulated by a second encapsulation process, and since the gap between the encapsulation bodies is reduced, the delamination phenomenon caused by the matching problem of the thermal expansion coefficient of the material can be avoided. In addition, the bottom connection area 13 can be adjusted according to the design of the main processing chip 2, so that the chip stack group 1a matches the physical port layer of the main processing chip 2 on the interposer 7.

[0082] In the description of the present specification, the description referring to the terms "some embodiments", "for example", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0083] Although the embodiments of the present disclosure have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be construed as limiting the present disclosure, and those ordinarily skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present disclosure, and any changes or modifications made according to the claims and the specification of the present disclosure shall be within the scope of the present disclosure.

Claims

1. A packaging structure, characterized in that, include: Main processing chip; A chip stack group is located on at least one side of the main processing chip. The chip stack group includes stacked chips. Each layer of the chips includes at least two spaced chip functional areas. The bottom layer of the chip also includes a bottom layer connection area. The bottom layer connection area is located between two adjacent chip functional areas at the bottom layer and is connected to the chip functional areas. The chip functional areas of the multiple layers of chips are aligned in the stacking direction. The first wiring layer spans the bottom connection area and is electrically connected to the chip functional areas on both sides of the bottom connection area. The bottom surface of the chip at the bottom layer has a plurality of first solder bumps, some of which are located on the bottom surface of the chip functional area and some of which are located on the bottom surface of the bottom connection area. The bottom layer of the chip also includes multiple first conductive vias, some of which penetrate the functional area of ​​the chip and some of which penetrate the bottom connection area. The first redistribution layer is electrically connected to the first solder bump and the first conductive via; The first encapsulation layer covers at least the sidewalls of the chip stack; The second encapsulation layer fills at least between the chip stack and the main processing chip, and at least covers a portion of the surface of the first encapsulation layer.

2. The packaging structure according to claim 1, characterized in that, The first wiring layer includes power supply lines.

3. The packaging structure according to any one of claims 1-2, characterized in that, The multiple non-bottom-level chips also include upper-level connection areas, which are located between adjacent chip functional areas disposed on the same layer and connected to the chip functional areas.

4. The packaging structure according to claim 3, characterized in that, Also includes: The second wiring layer spans the upper connection area and is electrically connected to the chip functional areas on opposite sides of the upper connection area.

5. The packaging structure according to claim 4, characterized in that, The lower surface of the non-bottom layer chip has a plurality of second solder bumps, some of which are located on the lower surface of the chip functional area and some of which are located on the lower surface of the upper layer connection area. The non-bottom layer chip also includes multiple second conductive vias, some of which penetrate the chip's functional area and some of which penetrate the upper layer connection area; The second redistribution layer is also electrically connected to the second solder bump and the second conductive via.

6. The packaging structure according to any one of claims 1-2, characterized in that, The multi-layered, non-bottom-layered chips constitute at least two spaced-apart sub-stacks; each sub-stack includes stacked chip functional areas, and multiple chip functional areas on the same layer belong to different sub-stacks. The first encapsulation layer is also located between adjacent sub-stacks.

7. The packaging structure according to claim 6, characterized in that, Also includes: A heat dissipation structure extends through the first packaging layer located between adjacent sub-stacks and is connected to the bottommost chip.

8. The packaging structure according to claim 1, characterized in that, The two opposite sides of the chip stack are respectively aligned with the two opposite sides of the main processing chip.

9. A method for manufacturing a packaging structure, characterized in that, Multiple chips are provided and stacked to form a chip stack group; each layer of chips includes at least two spaced chip functional areas, and the bottom layer of chips also includes a bottom layer connection area, which is located between adjacent chip functional areas at the bottom layer and connected to the chip functional areas; the chip functional areas of the multiple layers of chips are aligned in the stacking direction. A first wiring layer is formed on the bottommost chip surface. The first wiring layer spans the bottom connection area and is electrically connected to the chip functional areas on both sides of the bottom connection area. Multiple first solder bumps are formed on the lower surface of the bottom layer of the chip, some of the first solder bumps are located on the lower surface of the chip functional area, and some of the first solder bumps are located on the lower surface of the bottom layer connection area; Multiple first conductive vias are formed in the bottom layer of the chip, some of which penetrate the functional area of ​​the chip and some of which penetrate the bottom connection area. The first redistribution layer is electrically connected to the first solder bump and the first conductive via; A first packaging process is performed to form a first packaging layer that at least covers the sidewalls of the chip stack. A main processing chip is provided, and the chip stack group is disposed on at least one side of the main processing chip; A second packaging process is performed to form a second packaging layer, which at least fills the space between the chip stack and the main processing chip, and at least covers a portion of the surface of the first packaging layer.

10. The method for manufacturing the packaging structure according to claim 9, characterized in that, The non-bottom layer chip also includes an upper layer connection area, which is located between adjacent chip functional areas and connected to the chip functional areas; The manufacturing method further includes: forming a second redistribution layer on the surface of the chip (not the bottom layer), the second redistribution layer spanning the upper connection region and electrically connected to the chip functional regions on opposite sides of the upper connection region; and / or, The manufacturing method further includes: forming a plurality of second solder bumps on the lower surface of the chip (not the bottom layer), wherein some of the second solder bumps are located on the lower surface of the chip's functional area, and some of the second solder bumps are located on the lower surface of the upper layer connection area; and / or, The manufacturing method further includes: forming a plurality of second conductive vias in the non-bottom layer of the chip, some of the second conductive vias penetrating the functional area of ​​the chip, and some of the second conductive vias penetrating the upper layer connection area.

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