Signal receiving device, signal processing method and electronic equipment

Abstract

The present application provides a signal receiving device, a signal processing method and an electronic device, which relates to the field of electronic technology. The device includes: a first low-pass filter, a second low-pass filter, a DC bias module and a comparator, wherein the first low-pass filter performs filtering processing on a signal to be processed to obtain a first voltage signal, and the signal to be processed is transmitted to the receiving end through the CC pin of the USB Type-C interface; the DC bias module superimposes a DC bias on the first voltage signal to obtain a second voltage signal; the second low-pass filter performs filtering processing on the second voltage signal to obtain a third voltage signal, and the time constant of the second low-pass filter is greater than that of the first low-pass filter; the comparator is used to compare the second voltage signal and the third voltage signal to obtain a target BMC signal, and the target BMC signal is a standard BMC signal contained in the signal to be processed. The technical solution of the present application is implemented to achieve the effect of improving the accuracy of BMC signal reception.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a signal receiving device, a signal processing method and an electronic device. Background Art

[0002] In the BMC (Biphase Mark Coding) signal transmission process of USB PD (Power Delivery) communication, as the signal receiving end, it is necessary to accurately receive each bit of the signal. However, considering the existence of impedance such as wires and connectors during PD communication, there is a voltage drop on the power line and the ground line. The DC offset direction of the BMC signal at the Source (source end, or power supply end) and the Sink (power receiving end) is opposite. When the VBUS current increases from 0A, the BMC signal waveform drifts downward at the power supply Sink and drifts upward at the Source. Especially in high-current applications, the large voltage drop causes the BMC signal on the USB CC line to have a large DC offset. In addition, the switching power supply interference, USB2.0 communication noise, etc. are superimposed, which can easily cause BMC signal distortion and reception errors.

[0003] In the related art (CN113328715 A), a DC blocking capacitor C is used. HPF For BMC signals, they are similar to step responses, and the rising and falling edges of the signal can pass through C HPF , the high level and low level parts will gradually decay, so it is necessary to set two comparison thresholds according to the detected peak-to-peak value Vpeeak_ac. This requires a controllable constant current source to adjust the threshold voltage. The circuit implementation is relatively complex. The high-pass filtering characteristics of the isolation capacitor are general, and the selection of capacitor parameters is high. According to the capacitance value, it only has a certain filtering effect on specific low frequencies below the cutoff frequency, and has no effect on relatively high-frequency common-mode interference. It can be seen that although the DC isolation capacitor method in the relevant technology can filter out some low-frequency interference, the filtering effect is limited and is ineffective for high-frequency common-mode noise. In addition, the circuit is complex and the capacitor selection requirements are high, making it difficult to fully solve the problem of BMC signal reception accuracy. Summary of the invention

[0004] The purpose of the present application is to overcome the above technical problems. The present application provides a signal receiving device, a signal processing method and an electronic device.

[0005] In a first aspect, the present application provides a signal receiving device, comprising: a first low-pass filter, a second low-pass filter, a DC bias module and a comparator, wherein the input end of the first low-pass filter is electrically connected to the target pin, the first low-pass filter is used to filter the signal to be processed to obtain a first voltage signal, wherein the target pin is used to represent the USB of the receiving end. The CC pin of the Type-C interface, the signal to be processed is transmitted to the receiving end through the target pin; the output end of the first low-pass filter is electrically connected to the DC bias module, and the DC bias module is used to superimpose a DC bias on the first voltage signal to obtain a second voltage signal; the DC bias module is also electrically connected to the input end of the second low-pass filter, and the second low-pass filter is used to filter the second voltage signal to obtain a third voltage signal, wherein the time constant of the second low-pass filter is greater than the time constant of the first low-pass filter; the output end of the first low-pass filter is electrically connected to the in-phase input end of the comparator, and the output end of the second low-pass filter is electrically connected to the inverting input end of the comparator, and the comparator is used to compare the second voltage signal and the third voltage signal to obtain a target BMC signal, wherein the target BMC signal is a standard BMC signal contained in the signal to be processed.

[0006] By adopting the above technical solution, the second voltage signal is a voltage signal obtained after the signal to be processed is processed by the first low-pass filter and superimposed with a DC bias, and the third voltage signal is a voltage signal obtained after the second voltage signal is processed by the second low-pass filter; the signals at the in-phase terminal and the inverting terminal (or can be called the positive and negative terminals) of the comparator are taken from the original BMC signal itself, which is equivalent to canceling out their common voltage components, including power line voltage drop, interference and noise. That is, the signal to be processed can be understood as the original BMC signal, which may contain power supply interference, noise and positive and negative DC bias, etc. After the signal to be processed is processed by the first low-pass filter, DC bias and the second low-pass filter, and the second voltage signal and the third voltage signal are compared, the edge signal of the BMC waveform can be obtained, eliminating the influence of the common mode voltage. The comparator detects the signal state by comparing the voltage difference output by the two filters, which can improve the detection accuracy of the BMC signal and ensure that the signal can be accurately decoded even in a harsh electromagnetic environment; the comparator acts as an edge detector, comparing the second voltage signal and the third voltage signal after filtering to restore the standard BMC signal from the original BMC signal. The accuracy and anti-interference capability of BMC signal reception are improved, while the problems of complex circuit implementation and high parameter selection requirements caused by the use of DC blocking capacitors are avoided.

[0007] Optionally, the first low-pass filter includes a first resistor and a first capacitor, the DC bias module includes a second resistor, a third resistor and a DC voltage source, and the second low-pass filter includes a fourth resistor and a second capacitor, wherein the first end of the first resistor is electrically connected to the target pin, and the second end of the first resistor is electrically connected to the ground terminal through the first capacitor; the first end of the second resistor is electrically connected to the positive pole of the DC voltage source, the second end of the second resistor is electrically connected to the ground terminal through the third resistor, and the second end of the second resistor is also electrically connected to the second end of the first resistor; the first end of the fourth resistor is electrically connected to the second end of the second resistor, and the second end of the fourth resistor is electrically connected to the ground terminal through the second capacitor; the second end of the second resistor is electrically connected to the same-phase input terminal of the comparator, and the second end of the fourth resistor is electrically connected to the inverting input terminal of the comparator.

[0008] By adopting the above technical solution, the first low-pass filter includes a first resistor and a first capacitor, which are used to filter the signal to be processed to obtain a first voltage signal; the DC bias module includes a second resistor, a third resistor and a DC voltage source, which are used to superimpose a DC bias on the first voltage signal to obtain a second voltage signal; the second low-pass filter includes a fourth resistor and a second capacitor, which are used to filter the second voltage signal to obtain a third voltage signal. This solution realizes accurate filtering and DC bias superposition of the signal to be processed through a specific circuit, ensuring that the subsequent comparator can accurately obtain the target BMC signal. Reasonable selection of the values ​​of resistors and capacitors accurately controls the cutoff frequency of the low-pass filter and effectively filters out high-frequency noise; at the same time, the DC bias module stably provides the required bias voltage, eliminates the DC offset of the BMC signal, and optimizes the performance of signal processing; the design of the two-stage low-pass filter, combined with the effect of DC bias, not only filters out high-frequency and low-frequency noise, but also reduces signal distortion, significantly improves the quality of the BMC signal, and enables the receiving end to more accurately restore the standard BMC signal from the original BMC signal. Since the second voltage signal and the third voltage signal are directly derived from the original BMC signal that has undergone preliminary filtering and DC bias processing, the common voltage components (including some interference signals) in the two are offset by the comparator, effectively suppressing multiple interference sources and further improving the accuracy and reliability of signal reception. By comparing the second voltage signal and the third voltage signal, the comparator can accurately identify and extract the standard BMC signal, avoiding the problem of complex circuit adjustment of threshold voltage due to signal attenuation or distortion in traditional methods, simplifying the signal processing process, and improving the efficiency and accuracy of signal extraction.

[0009] Optionally, the above-mentioned signal receiving device also includes a fifth resistor and a sixth resistor, wherein the second end of the second resistor is electrically connected to the non-inverting input terminal of the comparator through the fifth resistor, the fifth resistor is connected between the second end of the second resistor and the non-inverting input terminal of the comparator, and the sixth resistor is connected between the non-inverting input terminal of the comparator and the output terminal of the comparator.

[0010] By adopting the above technical solution, the signal receiving device adds a fifth resistor and a sixth resistor, the fifth resistor is connected between the second end of the second resistor and the in-phase input end of the comparator, and the sixth resistor is connected between the in-phase input end of the comparator and the output end of the comparator; the fifth resistor and the sixth resistor play the role of hysteresis comparison, and the BMC signal can be effectively restored through the hysteresis comparison of the comparator. Through the fifth resistor and the sixth resistor, the threshold of the comparator can be adjusted more flexibly, so that it can detect the logical state of the BMC signal more accurately, which is very useful for maintaining the correct identification of the signal under different working conditions. Through the clever configuration of the fifth resistor and the sixth resistor, a positive feedback loop is formed between the in-phase input end and the output end of the comparator. This design realizes the function of the hysteresis comparator. This hysteresis effect effectively reduces the misjudgment caused by signal fluctuations and improves the accuracy of EMC signal reception.

[0011] Optionally, the time constant of the first low-pass filter is 200 ns, and the time constant of the second low-pass filter is 300 ns.

[0012] By adopting the above technical solution, the time constant of the second low-pass filter is greater than that of the first low-pass filter, which means that it reacts more slowly to changes in the signal and can further smooth the signal. Since the BMC signal itself is a rapidly changing pulse signal, the second low-pass filter will not significantly affect the basic shape of the signal, but it will further remove low-frequency noises below its cutoff frequency. The result of this is that the main characteristics of the BMC signal are retained while eliminating the remaining low-frequency noise; the role of the comparator is to determine the state of the signal based on the set threshold. One input end of the comparator is connected to the output of the first low-pass filter, and the other input end is connected to the output of the second low-pass filter. Since the second low-pass filter has a larger time constant, its output will be smoother than the first low-pass filter, so it can be used as a reference signal for the comparator. By comparing these two signals, the logical state of the BMC signal, that is, 0 or 1, can be accurately restored.

[0013] Optionally, the signal receiving device further includes a digital decoding module, wherein an input end of the digital decoding module is electrically connected to an output end of the comparator, and the digital decoding module is used to decode the target BMC signal to obtain original data bits.

[0014] By adopting the above technical solution, in the process of signal reception, especially for digital signals such as BMC, the received signals are often modulated or encoded and cannot be directly used for data processing or communication. Therefore, a special decoding module is required to convert the received signals into original data bits for subsequent processing and application; the digital decoding module can quickly and accurately decode the received BMC signals, convert the modulated or encoded signals into original data bits, and provide a reliable data source for subsequent data processing and application.

[0015] In a second aspect of the present application, a signal processing method is also provided, which is applied to any of the aforementioned signal receiving devices, including: receiving a signal to be processed, wherein the signal to be processed is transmitted to a receiving end through a target pin; processing the signal to be processed as follows to obtain a target BMC signal: filtering the signal to be processed through a first low-pass filter to obtain a first voltage signal; superimposing a DC bias on the first voltage signal through a DC bias module to obtain a second voltage signal; filtering the second voltage signal through a second low-pass filter to obtain a third voltage signal; comparing the second voltage signal and the third voltage signal through a comparator to obtain a target BMC signal, wherein the target BMC signal is a standard BMC signal contained in the signal to be processed.

[0016] By adopting the above technical solution, the received signal to be processed can be effectively filtered and processed to improve the purity of the signal. The signal to be processed can be understood as the original BMC signal, which may contain power supply interference, noise, positive and negative DC bias, etc. Specifically, the signal to be processed is initially filtered by the first low-pass filter to obtain a first voltage signal, and then the DC bias module is used to superimpose the DC bias to form a second voltage signal, and then further filtered by the second low-pass filter with a larger time constant to obtain a third voltage signal. Finally, the second voltage signal and the third voltage signal are compared by a comparator, because the second voltage signal and the third voltage signal are both taken from the original BMC signal itself, and the comparator is equivalent to canceling their common voltage components, including power line voltage drop, interference and noise, so as to accurately extract the standard BMC signal from the signal to be processed. The comparator detects the signal state by comparing the voltage difference output by the two filters, which can improve the detection accuracy of the BMC signal and ensure that the signal can be accurately decoded even in a harsh electromagnetic environment; the comparator acts as an edge detector to compare the second voltage signal and the third voltage signal after filtering to restore the standard BMC signal from the original BMC signal. The accuracy and anti-interference capability of BMC signal reception are improved, while the problems of complex circuit implementation and high parameter selection requirements caused by the use of DC blocking capacitors are avoided.

[0017] Optionally, after obtaining the target BMC signal, the method further includes: decoding the target BMC signal to obtain original data bits.

[0018] By adopting the above technical solution, although the extracted target BMC signal has been filtered and compared, it is still in an encoded form and needs to be further decoded to be restored to the original original data bits. Through decoding, the target BMC signal can be converted back to the original data bits, realizing data recovery and restoration, which is crucial for subsequent data processing, analysis and application. The target BMC signal is decoded to obtain the original data bits, ensuring that the target BMC signal obtained from the receiving end can be accurately restored to the original transmission data, improving the reliability and accuracy of signal transmission.

[0019] Optionally, the target BMC signal is decoded to obtain original data bits, including: detecting the width value of each pulse in the target BMC signal in turn to obtain multiple pulse width values; when the i-th pulse width value is within a preset width range, storing the i-th pulse width value in the target buffer area, wherein the i-th pulse width value is any one of the multiple pulse width values, and i is a positive integer greater than or equal to 1; when the number of pulse width values ​​in the target buffer area is greater than or equal to a preset value, performing software decoding on the data in the target buffer area until a preset condition is met to obtain the original data bits, wherein the preset condition is used to indicate that the transmission of a frame of BMC has been completed.

[0020] By adopting the above technical solution, in the target BMC signal, the width of each pulse often carries important information, which is crucial to the decoding process. However, due to the noise, interference or signal attenuation that may exist during the signal transmission process, it is also particularly important to accurately detect the width value of each pulse; however, not all detected pulse width values ​​represent valid information. In practical applications, there may be abnormal pulse width values ​​caused by noise or interference. In order to avoid the influence of these abnormal values ​​on the decoding results, a mechanism is needed to filter valid data. In addition, by setting the number of pulse width values ​​in the target buffer area to be greater than or equal to the preset value, software decoding is started, that is, hardware transmission and software decoding are carried out in parallel, the purpose of decoding while transmitting can be achieved, and the efficiency of decoding the target BMC signal is improved.

[0021] Optionally, when the ith pulse width value is within a preset width range, the ith pulse width value is stored in a target cache area, including: when the ith pulse width value is within the preset width range, determining whether the value of a current cache flag is 1; when it is determined that the value of the cache flag is 1, storing the ith pulse width value in a first cache; when it is determined that the value of the cache flag is 0, storing the ith pulse width value in a second cache, wherein the value of the cache flag is incremented by 1 when determining that each frame of BMC transmission ends.

[0022] By adopting the above technical solution, different cache areas are distinguished by cache flags, which can ensure that the data of each data frame is correctly stored in the specified location. This helps to improve the accuracy of data frame management and makes subsequent decoding processing more efficient. By dynamically allocating two caches and switching storage locations according to the status of the cache flags, it helps to use cache resources more flexibly and improve system efficiency; through data diversion and possible parallel processing, data processing efficiency can be significantly improved. The alternating use of two caches can reduce processing delays caused by waiting for the cache to be free, while improving the throughput of the system; this technical solution can greatly improve software decoding efficiency by adopting a dual-cache parallel coding method.

[0023] In a third aspect of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the program, any of the above method steps is implemented.

[0024] In a fourth aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores instructions, and when the instructions are executed, any of the above method steps is performed.

[0025] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages:

[0026] 1. After the signal to be processed is subjected to the first low-pass filter, DC bias and the second low-pass filter, and the second voltage signal is compared with the third voltage signal, the edge signal of the BMC waveform can be obtained, which eliminates the influence of the common mode voltage, improves the accuracy and anti-interference ability of the BMC signal reception, and avoids the problems of complex circuit implementation and high parameter selection requirements caused by the use of DC blocking capacitors;

[0027] 2. Through the setting of the fifth resistor and the sixth resistor, a positive feedback loop is formed between the in-phase input terminal and the output terminal of the comparator. This design realizes the function of the hysteresis comparator, effectively reduces the misjudgment caused by signal fluctuations, can effectively restore the EMC signal, and improves the accuracy of BMC signal reception;

[0028] 3. By dynamically allocating two caches and switching the storage location according to the status of the cache flag, it helps to use cache resources more flexibly and improve system efficiency; by adopting a dual-cache parallel encoding method, the software decoding efficiency can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a framework diagram of a signal receiving device provided in an embodiment of the present application;

[0030] Figure 2 is a circuit diagram of a BMC receiver provided in an embodiment of the present application;

[0031] Figure 3 is a simulation example diagram of a BMC receiver provided in an embodiment of the present application;

[0032] Figure 4 is a flow chart of a signal processing method provided by an embodiment of the present application;

[0033] Figure 5 It is a schematic diagram of a double-buffered parallel software decoding process provided by an embodiment of the present application;

[0034] Figure 6 It is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application.

[0035] Description of reference numerals:

[0036] A first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a comparator U1, a first capacitor C1, a second capacitor C2, a direct current voltage source DC; an electronic device 600, a processor 601, a communication bus 602, a user interface 603, a network interface 604, and a memory 605. DETAILED DESCRIPTION

[0037] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0038] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0039] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0040] The following is combined with Figure 1-5 The embodiments of the present application are described in detail.

[0041] The present application provides a signal receiving device, referring to Figure 1 , Figure 1 is a framework diagram of a signal receiving device provided in an embodiment of the present application, the system comprising: a first low-pass filter, a second low-pass filter, a DC bias module and a comparator, wherein:

[0042] The input end of the first low-pass filter is electrically connected to the target pin, and the first low-pass filter is used to filter the signal to be processed to obtain a first voltage signal, wherein the target pin is used to represent the CC pin of the USB Type-C interface of the receiving end, and the signal to be processed is transmitted to the receiving end through the target pin;

[0043] The output end of the first low-pass filter is electrically connected to a DC bias module, and the DC bias module is used to superimpose a DC bias on the first voltage signal to obtain a second voltage signal;

[0044] The DC bias module is also electrically connected to the input end of the second low-pass filter, and the second low-pass filter is used to filter the second voltage signal to obtain a third voltage signal, wherein the time constant of the second low-pass filter is greater than the time constant of the first low-pass filter;

[0045] The output end of the first low-pass filter is electrically connected to the non-inverting input end of the comparator, and the output end of the second low-pass filter is electrically connected to the inverting input end of the comparator. The comparator is used to compare the second voltage signal and the third voltage signal to obtain a target BMC signal, wherein the target BMC signal is a standard BMC signal included in the signal to be processed.

[0046] In the above embodiment, the second voltage signal is a voltage signal obtained after the signal to be processed is processed by the first low-pass filter and superimposed with a DC bias, and the third voltage signal is a voltage signal obtained after the second voltage signal is processed by the second low-pass filter; the signals at the in-phase terminal and the inverting terminal (or can be called the positive and negative terminals) of the comparator are both taken from the original BMC signal itself, which is equivalent to canceling out their common voltage components, including power line voltage drop, interference and noise, etc. That is, the signal to be processed can be understood as the original BMC signal, which may contain power supply interference, noise and positive and negative DC bias, etc. After the signal to be processed is processed by the first low-pass filter, DC bias and the second low-pass filter, and the second voltage signal and the third voltage signal are compared, the edge signal of the BMC waveform can be obtained, eliminating the influence of the common mode voltage. The comparator detects the signal state by comparing the voltage difference between the outputs of the two filters, which can improve the detection accuracy of the BMC signal and ensure that the signal can be accurately decoded even in a harsh electromagnetic environment; the comparator acts as an edge detector to compare the second voltage signal and the third voltage signal after filtering to restore the standard BMC signal from the original BMC signal. The standard BMC signal refers to a normal BMC square wave signal. The accuracy and anti-interference ability of BMC signal reception are improved, while avoiding the problems of complex circuit implementation and high parameter selection requirements caused by the use of DC blocking capacitors. The signal receiving device can effectively filter out low-frequency interference in the signal to be processed, and at the same time, the DC bias module superimposes the DC bias to solve the DC offset problem caused by the voltage drop on the power line or the ground line. The different time constant settings of the first low-pass filter and the second low-pass filter enable the device to adapt to different needs in terms of signal response speed, improve the accuracy of BMC signal reception, and effectively avoid signal distortion and reception errors. In the embodiment of the present application, a DC bias module is used to superimpose a DC bias on the first voltage signal output by the first low-pass filter, so that the DC offset of the BMC signal caused by reasons such as wire impedance and current change can be effectively eliminated, thereby ensuring the stability of the signal in subsequent processing; a two-stage low-pass filter design is adopted, wherein the first low-pass filter preliminarily filters out high-frequency noise, and the second low-pass filter (with a larger time constant) further filters out low-frequency interference; a comparator is used to compare the second voltage signal after filtering and DC bias processing with the third voltage signal, wherein the second voltage signal and the third voltage signal are both taken from the original BMC signal (i.e., the aforementioned signal to be processed), and the comparison between the two can offset the common voltage components, including power line voltage drop, interference and noise, etc., and can fully suppress various interference sources such as switching power supply interference and USB 2.0 communication noise, thereby improving signal quality, and then directly extracting a standard BMC signal, thereby avoiding the problem of complex circuit adjustment of threshold voltage due to signal attenuation in traditional methods, simplifying circuit design, and improving the accuracy and reliability of signal reception.

[0047] In an optional embodiment, the first low-pass filter includes a first resistor R1 and a first capacitor C1, the DC bias module includes a second resistor R2, a third resistor R3 and a DC voltage source DC, and the second low-pass filter includes a fourth resistor R4 and a second capacitor C2, wherein the first end of the first resistor R1 is electrically connected to the target pin, and the second end of the first resistor R1 is electrically connected to the ground end through the first capacitor C1; the first end of the second resistor R2 is electrically connected to the positive pole of the DC voltage source DC, the second end of the second resistor R2 is electrically connected to the ground end through the third resistor R3, and the second end of the second resistor R2 is also electrically connected to the second end of the first resistor R1; the first end of the fourth resistor R4 is electrically connected to the second end of the second resistor R2, and the second end of the fourth resistor R4 is electrically connected to the ground end through the second capacitor C2; the second end of the second resistor R2 is electrically connected to the in-phase input end of the comparator U1, and the second end of the fourth resistor R4 is electrically connected to the inverting input end of the comparator U1.

[0048] In the above embodiment, the first low-pass filter includes a first resistor R1 and a first capacitor C1, which are used to filter the signal to be processed to obtain a first voltage signal; the DC bias module includes a second resistor R2, a third resistor R3 and a DC voltage source DC, which are used to superimpose a DC bias on the first voltage signal to obtain a second voltage signal; the second low-pass filter includes a fourth resistor R4 and a second capacitor C2, which are used to filter the second voltage signal to obtain a third voltage signal. This scheme realizes accurate filtering and DC bias superposition of the signal to be processed through a specific circuit, ensuring that the subsequent comparator can accurately obtain the target BMC signal. The first low-pass filter can effectively filter out high-frequency noise in the signal to be processed while retaining the effective components of the signal; the DC bias module superimposes an appropriate DC bias to compensate for the DC offset in the signal to be processed; the second low-pass filter further filters out low-frequency interference in the second voltage signal to obtain a relatively pure third voltage signal; the comparator compares the second voltage signal and the third voltage signal to separate a clean target BMC signal. Specifically, the low-pass filter composed of the first resistor R1 and the first capacitor C1 effectively suppresses high-frequency noise; the DC bias module composed of the second resistor R2, the third resistor R3 and the DC voltage source DC ensures that the DC offset of the signal is effectively compensated during transmission; the low-pass filter composed of the fourth resistor R4 and the second capacitor C2 further improves the purity of the signal. Reasonable selection of the values ​​of the resistor and capacitor accurately controls the cutoff frequency of the low-pass filter and effectively filters out high-frequency noise; at the same time, the DC bias module stably provides the required bias voltage, eliminates the DC offset of the BMC signal, and optimizes the performance of signal processing; the design of the two-stage low-pass filter, combined with the effect of DC bias, not only filters out high-frequency and low-frequency noise, but also reduces signal distortion, significantly improves the quality of the BMC signal, and enables the receiving end to more accurately restore the standard BMC signal from the original BMC signal. Since the second voltage signal and the third voltage signal are directly derived from the original BMC signal after preliminary filtering and DC bias processing, the common voltage components (including part of the interference signal) in the two are offset by the comparator, which effectively suppresses multiple interference sources and further improves the accuracy and reliability of signal reception. By comparing the second voltage signal and the third voltage signal, the comparator can accurately identify and extract the standard BMC signal, avoiding the problem of complex circuit adjustment of threshold voltage due to signal attenuation or distortion in traditional methods, simplifying the signal processing process, and improving the efficiency and accuracy of signal extraction.

[0049] In an optional embodiment, if Figure 2As shown, the above-mentioned signal receiving device also includes a fifth resistor R5 and a sixth resistor R6, wherein the second end of the second resistor R2 is electrically connected to the in-phase input terminal of the comparator U1 through the fifth resistor R5, the fifth resistor R5 is connected between the second end of the second resistor R2 and the in-phase input terminal of the comparator U1, and the sixth resistor R6 is connected between the in-phase input terminal of the comparator U1 and the output terminal of the comparator U1.

[0050] In the above embodiment, the signal receiving device adds a fifth resistor R5 and a sixth resistor R6, the fifth resistor R5 is connected between the second end of the second resistor R2 and the in-phase input end of the comparator U1, and the sixth resistor R6 is connected between the in-phase input end of the comparator U1 and the output end of the comparator U1; the fifth resistor R5 and the sixth resistor R6 play a role of hysteresis comparison, and the BMC signal can be effectively restored through the hysteresis comparison of the comparator U1. Through the fifth resistor R5 and the sixth resistor R6, the threshold of the comparator can be adjusted more flexibly, so that it can detect the logical state of the BMC signal more accurately, which is very useful for maintaining the correct identification of the signal under different working conditions. Through the setting of the fifth resistor R5 and the sixth resistor R6, the hysteresis comparison function is realized, thereby effectively improving the restoration accuracy and stability of the BMC signal. Through the ingenious configuration of the fifth resistor R5 and the sixth resistor R6, a positive feedback loop is formed between the in-phase input terminal and the output terminal of the comparator U1. This design realizes the function of the hysteresis comparator. The hysteresis comparator can set different thresholds, namely positive thresholds and negative thresholds, during the rise and fall of the signal. Only when the input signal exceeds the higher positive threshold, the output will jump from a low level to a high level; similarly, only when the input signal drops below the lower negative threshold, the output will jump from a high level back to a low level; this hysteresis effect effectively reduces the misjudgment caused by signal fluctuations and improves the accuracy of EMC signal reception. Since the hysteresis comparator has a certain tolerance for signal fluctuations, it can more accurately restore the state of the original signal, especially for those signals with blurred edges or susceptible to interference (such as BMC signals), which helps to reduce system errors caused by signal misjudgment and improve the reliability and performance of the overall system. By introducing the hysteresis comparison mechanism, the signal receiving device has a stronger resistance to noise and electromagnetic interference in the external environment, and can ensure stable transmission and accurate processing of signals even in relatively harsh working environments. During signal transmission, the received signal may fluctuate due to noise, electromagnetic interference, etc., resulting in unclear or unstable signal edges. Due to signal fluctuations, the comparator in the related art may frequently switch output states near the critical point of the signal, which may cause the signal to be interpreted or processed incorrectly. For signals that require high-fidelity restoration, such as BMC signals, the methods in the related art may not be able to accurately capture the true state of the signal, thereby affecting the overall performance of the system. Optional, Figure 2The fifth resistor R5 and the sixth resistor R6 may not be added, and adding the fifth resistor R5 and the sixth resistor R6 is a preferred technical solution.

[0051] In an optional embodiment, the time constant of the first low-pass filter is 200 ns, and the time constant of the second low-pass filter is 300 ns.

[0052] In the above embodiment, the time constant of the second low-pass filter is greater than that of the first low-pass filter, which means that it reacts slower to changes in the signal and can further smooth the signal. Since the BMC signal itself is a rapidly changing pulse signal, the second low-pass filter will not significantly affect the basic shape of the signal, but it will further remove low-frequency noises below its cutoff frequency. The result of this is that the main characteristics of the BMC signal are retained while eliminating the remaining low-frequency noise; the function of the comparator is to determine the state of the signal based on the set threshold. One input end of the comparator is connected to the output of the first low-pass filter, and the other input end is connected to the output of the second low-pass filter. Since the second low-pass filter has a larger time constant, its output will be smoother than the first low-pass filter, so it can be used as a reference signal for the comparator. By comparing these two signals, the logical state of the BMC signal, i.e., 0 or 1, can be accurately restored. The embodiment of the present application takes the time constants of the first low-pass filter and the second low-pass filter as 200ns and 300ns respectively as an example. In practical applications, they can also be set to other values ​​as needed. Since the first low-pass filter and the second low-pass filter have different time constants, their processing results for the signal will also be different. By comparing the outputs of these two filters, the state of the signal can be detected more accurately, and high detection accuracy can be maintained even in the presence of noise interference. In some communication protocols, such as USB PD (Power Delivery), the transmission characteristics of the signal are known, so filters with specific time constants can be designed for these protocols. This ensures that the signal receiving device can meet the requirements of the protocol and show good performance in practical applications.

[0053] In an optional embodiment, the signal receiving device further includes a digital decoding module, wherein an input end of the digital decoding module is electrically connected to an output end of the comparator, and the digital decoding module is used to decode the target BMC signal to obtain original data bits.

[0054] In the above embodiments, in the process of signal reception, especially for digital signals such as BMC, the received signals are often modulated or encoded and cannot be directly used for data processing or communication. Therefore, a special decoding module is required to convert the received signals into original data bits for subsequent processing and application; the digital decoding module can quickly and accurately decode the received BMC signals, convert the modulated or encoded signals into original data bits, and provide a reliable data source for subsequent data processing and application. The received signal may be affected by noise and other factors during the transmission process, resulting in signal distortion. The digital decoding module is not only responsible for decoding, but also can check the integrity of the data by means of checksums, so as to ensure that the received data bits are accurate. The design of the digital decoding module usually follows certain communication standards or protocols to ensure that the signal receiving device is compatible with other devices and exchanges data according to established rules. The introduction of the digital decoding module enables the signal receiving device to process the received signals more efficiently, improving the overall performance and response speed of the system. The digital decoding module is integrated into the signal receiving device. Since the decoding module can be upgraded or replaced independently, it is also convenient for system maintenance and upgrading, which not only simplifies the system structure, but also improves the scalability and flexibility of the system. The digital decoding module decodes the received target BMC signal to obtain the original data bits, thereby improving the accuracy and efficiency of signal processing.

[0055] It should be noted that the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.

[0056] The embodiment of the present application provides a BMC signal receiving circuit for USB PD communication, which may also be called a BMC receiver. Figure 2 is a circuit diagram of a BMC receiver provided in an embodiment of the present application, such as Figure 2 As shown, the circuit of the BMC receiver consists of two low-pass filters (LPF) and a comparator U1 (or edge detector). Among them, the first resistor R1 and the first capacitor C1 form the first LPF (corresponding to the aforementioned first low-pass filter), and the fourth resistor R4 and the second capacitor C2 form the second LPF (corresponding to the aforementioned second low-pass filter). Their time constants (τ) are 200ns and 300ns respectively. The BMC_IN signal (which may contain interference, noise, DC offset, etc., corresponding to the aforementioned signal to be processed) passes through the first LPF to filter out high-frequency noise, and then enters the positive terminal of the comparator U1 after superimposing the DC bias through the second resistor R2 and the third resistor R3. Figure 2The DC voltage source DC, the second resistor R2 and the third resistor R3 form a DC bias circuit, and at the same time, after phase shifting through the second LPF, it enters the negative end of the comparator U1, and the BMC signal can be restored after hysteresis comparison without adding additional circuits. It can effectively solve the BMC signal offset and interference under different power supply voltages and different load currents.

[0057] Figure 3 is a simulation example diagram of a BMC receiver provided in an embodiment of the present application, such as Figure 3 As shown, Figure 3 The four simulation waveforms represent bmc_in, comp_p, comp_n and comp_out respectively. The waveform in the bmc_in label column shows the original BMC signal (i.e. the above-mentioned BMC_IN signal, corresponding to the above-mentioned signal to be processed), which is superimposed with high-frequency interference signals and positive and negative DC biases with lower frequency fluctuations, where the maximum DC drift reaches about plus or minus 0.5V. comp_p is a first-order low-pass filter signal (corresponding to the above-mentioned second voltage signal), and comp_n is a second-order low-pass filter signal (corresponding to the above-mentioned third voltage signal). After hysteresis comparison, the BMC standard signal shown in the comp_out column (corresponding to the above-mentioned target BMC signal) is generated, and then it can enter the MCU or other digital decoding units (corresponding to the above-mentioned digital decoding module).

[0058] The present application also provides a signal processing method, which is applied to the signal receiving device of any of the above embodiments. Figure 4 : is a flow chart of a signal processing method provided in an embodiment of the present application, the process includes:

[0059] Step S401, receiving a signal to be processed, wherein the signal to be processed is transmitted to a receiving end through a target pin;

[0060] Step S402, the signal to be processed is processed as follows to obtain a target BMC signal: the signal to be processed is filtered by a first low-pass filter to obtain a first voltage signal; a DC bias module is used to superimpose a DC bias on the first voltage signal to obtain a second voltage signal; the second voltage signal is filtered by a second low-pass filter to obtain a third voltage signal; the second voltage signal and the third voltage signal are compared by a comparator to obtain a target BMC signal, wherein the target BMC signal is a standard BMC signal contained in the signal to be processed.

[0061] In the above embodiment, the received signal to be processed can be effectively filtered and processed to improve the purity of the signal. The signal to be processed can be understood as the original BMC signal, which may contain power supply interference, noise, positive and negative DC bias, etc. Specifically, the signal to be processed is initially filtered by the first low-pass filter to obtain a first voltage signal, and then the DC bias module is used to superimpose the DC bias to form a second voltage signal, and then further filtered by the second low-pass filter with a larger time constant to obtain a third voltage signal. Finally, the second voltage signal and the third voltage signal are compared by a comparator, because the second voltage signal and the third voltage signal are both taken from the original BMC signal itself, and the comparator is equivalent to canceling their common voltage components, including power line voltage drop, interference and noise, so as to accurately extract the standard BMC signal from the signal to be processed. The comparator detects the signal state by comparing the voltage difference output by the two filters, which can improve the detection accuracy of the BMC signal and ensure that the signal can be accurately decoded even in a harsh electromagnetic environment; the comparator acts as an edge detector to compare the second voltage signal and the third voltage signal after filtering to restore the standard BMC signal from the original BMC signal. The accuracy and anti-interference ability of BMC signal reception are improved, while avoiding the problems of complex circuit implementation and high parameter selection requirements caused by the use of DC blocking capacitors. The signal receiving device can effectively filter out low-frequency interference in the signal to be processed, and at the same time, the DC bias module superimposes the DC bias to solve the DC offset problem caused by the voltage drop on the power line or ground line. The different time constant settings of the first low-pass filter and the second low-pass filter enable the device to adapt to different needs in terms of signal response speed, improve the accuracy of BMC signal reception, and effectively avoid signal distortion and reception errors. In the embodiment of the present application, a DC bias module is used to superimpose a DC bias on the first voltage signal output by the first low-pass filter, so that the DC offset of the BMC signal caused by reasons such as wire impedance and current change can be effectively eliminated, thereby ensuring the stability of the signal in subsequent processing; a two-stage low-pass filter design is adopted, wherein the first low-pass filter preliminarily filters out high-frequency noise, and the second low-pass filter (with a larger time constant) further filters out low-frequency interference; a comparator is used to compare the second voltage signal after filtering and DC bias processing with the third voltage signal, wherein the second voltage signal and the third voltage signal are both taken from the original BMC signal (i.e., the aforementioned signal to be processed), and the comparison between the two can offset the common voltage components, including power line voltage drop, interference and noise, etc., and can fully suppress various interference sources such as switching power supply interference and USB 2.0 communication noise, thereby improving signal quality, and then directly extracting a standard BMC signal, thereby avoiding the problem of complex circuit adjustment of threshold voltage due to signal attenuation in traditional methods, simplifying circuit design, and improving the accuracy and reliability of signal reception.

[0062] In an optional embodiment, after obtaining the target BMC signal, the method further includes: decoding the target BMC signal to obtain original data bits.

[0063] In the above embodiment, because the BMC signal is often encoded or modulated during the transmission process to adapt to the channel characteristics or improve the transmission efficiency, the decoding process is a necessary link for signal reception and processing. The goal of the decoding process is to convert the encoded or modulated signal back to the original data bit. In this process, the accuracy and integrity of the data need to be ensured. Although the extracted target BMC signal has been filtered and compared, it is still in an encoded form and needs to be further decoded to be restored to the original original data bit. Through the decoding process, the target BMC signal can be converted back to the original data bit, realizing the recovery and restoration of the data, which is crucial for subsequent data processing, analysis and application. During the signal transmission process, due to various interference factors, the received signal may deviate from the transmitted signal. The decoding process not only recovers the data, but also ensures that the decoded data bits are consistent with the data at the transmitting end. The decoding process usually includes a series of precise algorithms and verification mechanisms to ensure the accuracy and reliability of the decoding results; since the BMC signal follows a specific communication protocol or standard, the decoding process needs to be compatible with these protocols or standards. This method enhances the compatibility and adaptability of the system to different types of signals by implementing a decoding algorithm related to the BMC signal. The target BMC signal is decoded to obtain the original data bits, ensuring that the target BMC signal obtained from the receiving end can be accurately restored to the original transmission data, thereby improving the reliability and accuracy of signal transmission.

[0064] In an optional embodiment, the target BMC signal is decoded to obtain original data bits, including: sequentially detecting the width value of each pulse in the target BMC signal to obtain multiple pulse width values; when the i-th pulse width value is within a preset width range, storing the i-th pulse width value in a target buffer, wherein the i-th pulse width value is any one of the multiple pulse width values, and i is a positive integer greater than or equal to 1; when the number of pulse width values ​​in the target buffer is greater than or equal to a preset value, software decoding is performed on the data in the target buffer until a preset condition is met to obtain the original data bits, wherein the preset condition is used to indicate that a frame of BMC transmission has been completed.

[0065] In the above embodiment, in the target BMC signal, the width of each pulse often carries important information, which is crucial for the decoding process. However, due to the problems such as noise, interference or signal attenuation that may exist during the signal transmission process, it is also particularly important to accurately detect the width value of each pulse; however, not all detected pulse width values ​​represent valid information. In practical applications, there may be abnormal pulse width values ​​caused by noise or interference. In order to avoid the influence of these abnormal values ​​on the decoding results, a mechanism is needed to filter valid data. By detecting each pulse width in the BMC signal in turn and comparing it with the preset width range, it can be ensured that only those pulses that meet the expected width will be recorded, which helps to exclude abnormal pulse widths caused by noise and improve the accuracy of data recovery. By setting the preset width range and only storing the pulse width values ​​that meet the conditions in the target buffer area, the screening of valid data is achieved. In addition, by setting the number of pulse width values ​​in the target buffer area to meet the condition that is greater than or equal to the preset value, software decoding is started, that is, hardware transmission and software decoding are carried out in parallel, the purpose of decoding while transmitting can be achieved, and the efficiency of decoding the target BMC signal can be improved. Storing qualified pulse width values ​​in the target buffer instead of decoding them immediately can avoid the computational burden that may be caused by instant decoding in the data stream. When the data in the buffer reaches a certain amount, decoding processing is performed uniformly to improve processing efficiency. By setting preset conditions to determine whether a frame of data is decoded, the integrity of the decoding process can be ensured. Only when the decoded data meets the preset conditions, indicating that a frame of data transmission has been completed, will the decoding be considered successful, thereby ensuring the integrity of the data frame. The embodiment of the present application detects the width value of each pulse in the target BMC signal in turn, and stores it in the target buffer when the pulse width value is within a preset width range. When the number of pulse width values ​​stored in the target buffer reaches a preset value, the cached data is software decoded until the preset condition for the completion of a frame of BMC transmission is met, thereby accurately obtaining the original data bits. This scheme effectively improves the accuracy and efficiency of decoding the target BMC signal.

[0066] In an optional embodiment, when the ith pulse width value is within a preset width range, the ith pulse width value is stored in a target cache area, including: when the ith pulse width value is within the preset width range, determining whether the value of the current cache flag is 1; when it is determined that the value of the cache flag is 1, storing the ith pulse width value in a first cache; when it is determined that the value of the cache flag is 0, storing the ith pulse width value in a second cache, wherein the value of the cache flag is incremented by 1 when determining that each frame of BMC transmission ends.

[0067] In the above embodiment, when continuously receiving and processing BMC signals, if all data are stored in the same cache, data processing bottlenecks may occur, especially in high-speed transmission or complex signal environments. In addition, in order to improve data processing efficiency, it is sometimes necessary to process different batches of data in parallel. By introducing two caches (a first cache and a second cache), parallel processing of data is achieved. In BMC signals or other similar frame structure signals, it is crucial to clarify the start and end of each frame, which helps the decoder to correctly identify and process each frame of data to avoid data confusion or loss. By adding 1 to the cache flag bit, it is updated at the end of each frame of BMC transmission, thereby effectively managing the frame boundary. By distinguishing different cache areas by the cache flag bit, it can be ensured that the data of each data frame is correctly stored in the specified location. This helps to improve the accuracy of data frame management and make subsequent decoding processing more efficient. Whenever a frame of BMC transmission ends, the value of the cache flag bit is added by 1, which ensures that the data of the next frame will be stored in another cache area. This mechanism helps to achieve synchronization between data frames and ensure that data of different frames will not be confused during decoding. By dynamically allocating two caches and switching the storage location according to the status of the cache flag, it is helpful to use cache resources more flexibly and improve system efficiency; through data diversion and possible parallel processing, the data processing efficiency can be significantly improved, and the alternating use of the two caches can reduce the processing delay caused by waiting for the cache to be free, while improving the system throughput; this embodiment can greatly improve the software decoding efficiency by adopting a dual-cache parallel encoding method.

[0068] The embodiment of the present application also provides a method for decoding a BMC signal. The software decoding part adopts a double-buffered parallel decoding method to greatly improve the software decoding efficiency. The overall steps are as follows:

[0069] 1. The hardware is initialized and the first edge of the BMC signal is detected;

[0070] 2. Enable double edge capture of timer pulse width;

[0071] 3. Detect the pulse width value. If the pulse width exceeds the lower limit, it is interference. If it exceeds the lower limit, it means the current frame transmission is over.

[0072] 4. According to the buffer queue, the data is stored in the buffer;

[0073] 5. When there are more than 32 data in the buffer, decoding starts. At this time, hardware transmission and software decoding are performed in parallel, that is, decoding is performed while transmitting;

[0074] 6. Detection of the EOP signal or timeout signal indicates that the transmission of a BMC frame has been completed;

[0075] 7. Decoding completed.

[0076] Figure 5 This is a schematic diagram of the double-buffered parallel software decoding process provided by the embodiment of the present application. Figure 5 To explain the process:

[0077] S501, hardware initialization;

[0078] S502, start edge detection;

[0079] S503, determining whether it is the first falling edge, that is, detecting the first edge of the BMC signal;

[0080] S504, when the judgment result of step S503 is yes, perform pulse width double edge capture;

[0081] When the judgment result of the above step S503 is no, return to step S503;

[0082] S505, performing pulse width validity detection, i.e. determining whether the pulse width is valid;

[0083] S506, when the determination result of the above step S505 is no, determining whether the pulse width is too narrow;

[0084] S507, when it is determined that the pulse width is too narrow, the pulse width is discarded and the process goes to step S504;

[0085] S508, when it is determined that the pulse width is not too narrow, determining whether the pulse width has exceeded the time limit;

[0086] S509, when the judgment result of the above step S508 is yes, set the frame transmission end flag, for example, set the frame transmission end flag position to 1;

[0087] When the judgment result of the above step S508 is no, proceed to step S507;

[0088] S510, cache Cnt++, that is, cache flag bit Cnt to perform Cnt++ operation;

[0089] S511, when the determination result of the above step S505 is yes, determine whether the cache flag Cnt is equal to 1;

[0090] S512, when the judgment result of the above step S511 is yes, the value of the pulse width is stored in cache 1;

[0091] S513, when the judgment result of the above step S511 is no, the value of the pulse width is stored in the cache 2;

[0092] S514, obtaining buffer data, the buffer including cache 1 and cache 2;

[0093] S515, determining whether the buffer data is greater than 32 (or other values, corresponding to the aforementioned preset value);

[0094] S516, when the judgment result of step S515 is yes, start decoding;

[0095] When the judgment result of step S515 is no, return to step S504;

[0096] S517, determining whether the frame end flag satisfies a condition, that is, determining whether the frame ends according to the frame end flag bit, for example, determining whether the frame end flag bit is 1;

[0097] S518, when it is determined that the frame ends, it means that the decoding is completed and the data is valid;

[0098] S519, when the determination result of step S517 is no, further determining whether an EOP is detected, where the EOP is a signal used to identify the end of a data packet;

[0099] When the judgment result of the above step S519 is yes, proceed to step S518;

[0100] S520, when the judgment result of the above step S519 is no, determine whether the buffer has been decoded; if it has been decoded, return to step S504, if it has not been decoded, enter step S516 to continue decoding.

[0101] Compared with the related art, the embodiments of the present application have at least the following technical effects: 1) BMC signal offset can be accurately detected at different power levels without being affected by DC offset and high current load step; 2) The circuit is simple to implement, with few components and strong scalability. It can be easily implemented in both integrated circuit and discrete component applications.

[0102] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0103] The present application also provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed, any one of the method steps described above is executed.

[0104] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0105] The present application also discloses an electronic device. Figure 6 As shown, Figure 6 The electronic device 600 may include: at least one processor 601 , at least one network interface 604 , a user interface 603 , a memory 605 , and at least one communication bus 602 .

[0106] The communication bus 602 is used to realize the connection and communication between these components.

[0107] The user interface 603 may include a display screen (Display) and a camera (Camera). The optional user interface 603 may also include a standard wired interface and a wireless interface.

[0108] The network interface 604 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0109] Among them, the processor 601 may include one or more processing cores. The processor 601 uses various interfaces and lines to connect various parts of the entire electronic device (such as a server), and executes various functions of the server and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 605, and calling data stored in the memory 605. Optionally, the processor 601 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 601 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 601, and it can be implemented separately through a chip.

[0110] Among them, the memory 605 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 605 includes a non-transitory computer-readable storage medium. The memory 605 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 605 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 605 may optionally also be at least one storage device located away from the aforementioned processor 601. Refer to Figure 6 , the memory 605 as a computer storage medium may include an operating system, a network communication module, a user interface module and an application program of a signal processing method.

[0111] exist Figure 6 In the electronic device 600 shown, the user interface 603 is mainly used to provide an input interface for the user and obtain the data input by the user; and the processor 601 can be used to call an application program of a signal processing method stored in the memory 605, and when executed by one or more processors 601, the electronic device 600 executes one or more of the methods described in the above embodiments. It should be noted that for the aforementioned method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required for the present application.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0114] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0115] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0116] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, mobile hard drives, magnetic disks or optical disks.

[0117] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification and the truth of practice, those skilled in the art will easily think of other embodiments of the present disclosure.

[0118] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.

Claims

1. A signal receiving device, characterized in that: include: A first low pass filter, a second low pass filter, a DC bias module and a comparator, wherein, The input end of the first low-pass filter is electrically connected to the target pin, and the first low-pass filter is used to filter the signal to be processed to obtain a first voltage signal, wherein the target pin is used to represent the CC pin of the USB Type-C interface of the receiving end, and the signal to be processed is transmitted to the receiving end through the target pin; The output end of the first low-pass filter is electrically connected to the DC bias module, and the DC bias module is used to superimpose a DC bias on the first voltage signal to obtain a second voltage signal; The DC bias module is also electrically connected to the input end of the second low-pass filter, and the second low-pass filter is used to filter the second voltage signal to obtain a third voltage signal, wherein the time constant of the second low-pass filter is greater than the time constant of the first low-pass filter; The output end of the first low-pass filter is electrically connected to the non-inverting input end of the comparator, and the output end of the second low-pass filter is electrically connected to the inverting input end of the comparator. The comparator is used to compare the second voltage signal and the third voltage signal to obtain a target BMC signal, wherein the target BMC signal is a standard BMC signal included in the signal to be processed; The signal receiving device further comprises a digital decoding module, wherein an input end of the digital decoding module is electrically connected to an output end of the comparator, and the digital decoding module is used to decode the target BMC signal to obtain original data bits; The digital decoding module is used to decode the target BMC signal to obtain the original data bits in the following manner: decoding the target BMC signal to obtain the original data bits, including: sequentially detecting the width value of each pulse in the target BMC signal to obtain multiple pulse width values; when the i-th pulse width value is within a preset width range, storing the i-th pulse width value in a target buffer area, wherein the i-th pulse width value is any one of the multiple pulse width values, and i is a positive integer greater than or equal to 1; when the number of pulse width values ​​in the target buffer area is greater than or equal to a preset value, software decoding is performed on the data in the target buffer area until a preset condition is met to obtain the original data bits, wherein the preset condition is used to indicate that a frame of BMC transmission has been completed.

2. The signal receiving device according to claim 1, characterized in that: The first low-pass filter includes a first resistor and a first capacitor, the DC bias module includes a second resistor, a third resistor and a DC voltage source, and the second low-pass filter includes a fourth resistor and a second capacitor, wherein: A first end of the first resistor is electrically connected to the target pin, and a second end of the first resistor is electrically connected to a ground terminal through the first capacitor; The first end of the second resistor is electrically connected to the positive electrode of the DC voltage source, the second end of the second resistor is electrically connected to the ground terminal through the third resistor, and the second end of the second resistor is also electrically connected to the second end of the first resistor; The first end of the fourth resistor is electrically connected to the second end of the second resistor, and the second end of the fourth resistor is electrically connected to the ground terminal through the second capacitor; The second end of the second resistor is electrically connected to the non-inverting input terminal of the comparator, and the second end of the fourth resistor is electrically connected to the inverting input terminal of the comparator.

3. The signal receiving device according to claim 2, characterized in that: The signal receiving device also includes a fifth resistor and a sixth resistor, wherein the second end of the second resistor is electrically connected to the non-inverting input terminal of the comparator through the fifth resistor, the fifth resistor is connected between the second end of the second resistor and the non-inverting input terminal of the comparator, and the sixth resistor is connected between the non-inverting input terminal of the comparator and the output terminal of the comparator.

4. The signal receiving device according to claim 2, characterized in that: The time constant of the first low-pass filter is 200 ns, and the time constant of the second low-pass filter is 300 ns.

5. A signal processing method, characterized in that: The signal receiving device according to any one of claims 1 to 4 comprises: receiving a signal to be processed, wherein the signal to be processed is transmitted to the receiving end through the target pin; The signal to be processed is processed as follows to obtain a target BMC signal: the signal to be processed is filtered by the first low-pass filter to obtain a first voltage signal; a DC bias is superimposed on the first voltage signal by the DC bias module to obtain a second voltage signal; the second voltage signal is filtered by the second low-pass filter to obtain a third voltage signal; the second voltage signal and the third voltage signal are compared by the comparator to obtain the target BMC signal, wherein the target BMC signal is a standard BMC signal contained in the signal to be processed; After obtaining the target BMC signal, the method further includes: decoding the target BMC signal to obtain original data bits; The target BMC signal is decoded to obtain original data bits, including: sequentially detecting the width value of each pulse in the target BMC signal to obtain multiple pulse width values; when the i-th pulse width value is within a preset width range, storing the i-th pulse width value in a target buffer area, wherein the i-th pulse width value is any one of the multiple pulse width values, and i is a positive integer greater than or equal to 1; when the number of pulse width values ​​in the target buffer area is greater than or equal to a preset value, software decoding is performed on the data in the target buffer area until a preset condition is met to obtain the original data bits, wherein the preset condition is used to indicate that a frame of BMC transmission has been completed.

6. The method according to claim 5, characterized in that When the i-th pulse width value is within a preset width range, storing the i-th pulse width value in a target buffer area includes: When the i-th pulse width value is within a preset width range, determining whether the value of the current cache flag bit is 1; When it is determined that the value of the cache flag is 1, storing the i-th pulse width value in the first cache; When it is determined that the value of the cache flag is 0, the i-th pulse width value is stored in the second cache, wherein the value of the cache flag is incremented by 1 when it is determined that each frame of BMC transmission ends.

7. An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the program, the method according to any one of claims 5 to 6 is implemented.

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