A method and system for remote time correction of intelligent chip based on neural network

Abstract

This invention discloses a method and system for remote time correction of intelligent chips based on neural networks, relating to the field of intelligent chip time correction technology. The method includes the following steps: the intelligent chip periodically collects deviation data between its local clock and a reference clock, transmits it via a network to an edge computing device for deviation data preprocessing; trains a deep neural network model for clock deviation, deploys it to the edge computing device, receives the preprocessed clock deviation data in real time, and performs time correction inference; the edge computing device generates a time correction command based on the correction result of the deep neural network model and sends it to the intelligent chip; a cloud management platform monitors the time synchronization status of each intelligent chip in real time, detecting anomalies and faults. This invention solves the problem of low accuracy in remote time correction of intelligent chips, providing an efficient and reliable solution for time synchronization correction of intelligent chips.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent chip time correction, and in particular to a neural network-based intelligent chip remote time correction method and system. Background Art

[0002] With the rapid development of science and technology, smart chips play an increasingly important role in modern society. From smart homes to industrial automation to high-precision scientific experiments, smart chips have been widely used for their high efficiency, accuracy, and reliability. However, due to environmental factors, equipment aging, electromagnetic interference and other reasons, smart chips often have time deviations during long-term operation, which is a problem that cannot be ignored for many application scenarios that rely on time accuracy.

[0003] Traditional time correction methods, such as using an external clock source for synchronization or regular manual correction, are not only costly but also difficult to achieve high precision requirements. Especially in remote environments, time correction for smart chips faces many challenges. Therefore, studying an efficient, accurate, and remote time correction method for smart chips has important practical significance and application value.

[0004] In recent years, the rapid development of neural network technology has provided new ideas for the time correction of smart chips. Neural networks have strong learning ability and adaptability. They can extract complex laws and features hidden in data through training and learning of large amounts of data, thereby achieving accurate prediction and inference of unknown data. Applying neural network technology to the time correction of smart chips can not only achieve high-precision correction, but also remote automatic correction, greatly improving the efficiency and accuracy of correction.

[0005] For example, the existing Chinese patent with authorization announcement number CN1 13985959B discloses a method, device and storage medium for correcting the time difference between switch capacitor array chips, including using FPGA to fan out multiple phase-consistent clock signals at the same time, and inputting the multiple clock signals into the corresponding switch capacitor array chips respectively; analog sampling of the received clock signal by each switch capacitor array chip, and obtaining a digital clock signal after analog-to-digital conversion; using FPGA to calculate the digital clock signal online to obtain the timing of each switch capacitor array chip, and then obtain the correction coefficient of each switch capacitor array, and correct the timing of the corresponding switch capacitor array chip based on the correction coefficient. Although FPGA can fan out multiple phase-consistent clock signals at the same time, in actual applications, the signal may have different signal arrival times during transmission due to different line lengths, signal reflections, impedance mismatches, etc.; signal reflections and impedance mismatches will affect the quality and phase consistency of the signal. To this end, the present invention provides a remote time correction method and system for intelligent chips based on neural networks. Summary of the invention

[0006] The purpose of the present invention is to provide a method and system for remote time correction of an intelligent chip based on a neural network to solve the existing problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solution: a method for remote time correction of an intelligent chip based on a neural network, comprising the following steps:

[0008] S1. The smart chip regularly collects the deviation data between the local clock and the reference clock, and transmits it to the edge computing device through the network for deviation data preprocessing;

[0009] S2. Train the clock deviation deep neural network model, use the historical clock deviation data as model training data, and learn the laws and correction methods of clock deviation;

[0010] S3, deploying the clock deviation deep neural network model to the edge computing device, receiving the preprocessed clock deviation data in real time, and performing time correction reasoning;

[0011] S4. The edge computing device generates a time correction instruction according to the correction result of the clock deviation deep neural network model and sends it to the smart chip;

[0012] S5. The cloud management platform monitors the time synchronization status of each smart chip in real time and detects anomalies and faults.

[0013] A further improvement of the present invention is that the deviation data between the local clock and the reference clock is recorded by the smart chip as the timestamp of the current local clock. _local, the smart chip obtains the corresponding timestamp t_ref from the reference clock source, calculates the difference between the two timestamps as the clock deviation data Δt=t_ref-t_local, packages the clock deviation data and related device identifiers into a data packet, and transmits it to the edge computing device.

[0014] The present invention is further improved in that the deviation data preprocessing includes using the IQR rule to identify outliers and then removing noise through a Kalman filter, followed by standardization. The IQR rule is based on the interquartile range. If the clock deviation is less than Q1-1.5×(Q3-Q1), it is regarded as an outlier, where Q1 is the first quartile and Q3 is the third quartile. The outlier is removed to obtain the second clock deviation data X2 t Substitute the data in the second clock deviation data into the following formula X norm =((X2 t -ave(X2 t )) / stu(X2 t )) to obtain the third clock deviation data, where ave(X2 t ) represents the mean value of the data in the second clock deviation data, stu(X2 t ) represents the standard deviation of the data in the second clock deviation data.

[0015] A further improvement of the present invention is that the specific construction process of the clock deviation deep neural network model includes:

[0016] S21, randomly extracting a subsample of the third clock deviation data to obtain a deviation subsample data set (td31, td32, ..., td3 B ), where td3 B represents the Bth clock deviation data in the deviation sub-sample data set, where B represents the number of data in the deviation sub-sample data set;

[0017] S22. Calculate the first-order momentum of the deviation subsample data Among them, θ represents the bias correction term, itr represents the number of iterations, and θ itr-1 represents the bias correction term after the itr-1th update, β1 represents the exponential decay rate of the first-order momentum, β1∈[0,1), F(td3 i ,θ itr-1 ) means that at the itr-1th iteration, the bias correction term is θ itr-1 When the clock deviation td3 i The objective function value of , j represents the jth element of the model;

[0018] S23, calculate the second-order momentum using the exponential decay average of the average value of the squared gradient of each deviation sub-sample data in the first-order momentum β2 represents the exponential decay rate of the second-order momentum, β2∈[0,1);

[0019] S24. Update deviation correction item ε represents a positive number, η represents the set model learning rate, and the function sqrt() represents the square root function;

[0020] S25. Repeat step S24. When the performance of the validation set no longer improves, stop training.

[0021] A further improvement of the present invention is that the time correction instruction is sent to the smart chip. After receiving the correction instruction, the smart chip adjusts the local clock to synchronize it with the reference clock. The smart chip then updates its internal state and feeds back the corrected time information to the edge computing device and returns it to the clock deviation deep neural network model.

[0022] The smart chip updates its internal state by parsing the update tasks in the instruction, wherein the update tasks include a time correction value, a correction frequency, and a correction period. Each update task has a unique ID, a deadline, an expected execution time, and an initial priority is assigned to each task. When the smart chip receives the update instruction, the ratio of the remaining deadline to the expected execution time of all tasks of the update instruction is calculated as the task deadline factor, and the product of each task deadline factor and the initial priority of each task is calculated as the priority update value of each task. The internal state of the smart chip is updated in descending order according to the priority update value of each task.

[0023] The present invention is further improved in that the time synchronization state is achieved by using an intelligent chip to compare the corrected time information with a reference clock, including a signal jitter index and a signal stability index, specifically including:

[0024] S51, the signal jitter index is calculated by collecting a time deviation data set within a time T with a time interval t as the standard, and the signal jitter index calculation formula is: Indicates Sampling point intelligent chip time, Indicates The time of the reference clock of each sampling point;

[0025] S52. The signal stability index is evaluated by observing the change of time deviation over time, and the calculation formula is:

[0026] S53, calculating the time synchronization state bias tssb=δ1×JitterSD-δ2×StaSD, where δ1 represents the weight of the signal jitter index, and δ2 represents the weight of the signal stability index;

[0027] S54. Set the time synchronization state deviation threshold Ttssb. When the tssb≥Ttssb, the platform will trigger an alarm notification and notify the administrator via email or SMS.

[0028] On the other hand, the present invention provides a smart chip remote time correction system based on a neural network, comprising:

[0029] The device layer includes embedded devices and edge computing devices; the embedded devices include smart chips with local clock and data processing capabilities; the edge computing devices are deployed at the edge of the network and are responsible for preliminary data processing and time correction; the data analysis layer is used to be deployed on edge computing devices or the cloud, set up a clock deviation deep neural network model, provide a global time benchmark, complex analysis and management functions; the network communication layer includes Wi-Fi, 5G, and wired networks to realize data transmission between devices.

[0030] A further improvement of the present invention is that the data analysis layer includes a data acquisition and preprocessing module, a neural network time correction module, a time synchronization and correction module and a system monitoring and management module; the data acquisition and preprocessing module is used to periodically collect the deviation data between the local clock and the reference clock, and perform deviation data preprocessing after transmitting it to the edge computing device through the network; the neural network time correction module is used to train the clock deviation deep neural network model, use the historical clock deviation data as the model training data, and learn the law and correction method of the clock deviation; the time synchronization and correction module is used to deploy the clock deviation deep neural network model to the edge computing device, receive the preprocessed clock deviation data in real time, and perform time correction reasoning; the edge computing device generates a time correction instruction based on the correction result of the clock deviation deep neural network model, and sends it to the smart chip; the system monitoring and management module is used to monitor the time synchronization status of each smart chip in real time and detect anomalies and faults.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The present invention collects clock deviation data regularly through the smart chip, and transmits it to the edge computing device after preprocessing for training the deep neural network model. Using historical data, the model can learn the law of clock deviation, and perform time correction reasoning based on it, generate correction instructions and send them back to the smart chip to achieve accurate time synchronization. It combines neural network and deep learning technology, effectively improves the accuracy and efficiency of remote time correction of smart chips, and provides an efficient and reliable solution for time synchronization correction of smart chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1This is a flow chart of a method for remote time correction of an intelligent chip based on a neural network according to the present invention;

[0034] Figure 2 A flowchart of building a clock deviation deep neural network model for a neural network-based intelligent chip remote time correction method of the present invention;

[0035] Figure 3 This is a time synchronization state flow chart of a neural network-based intelligent chip remote time correction method of the present invention;

[0036] Figure 4 This is a framework diagram of a neural network-based intelligent chip remote time correction system of the present invention. DETAILED DESCRIPTION

[0037] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. The embodiments of the present invention and the technical features in the embodiments may be combined with each other unless there is a conflict.

[0038] The term "and / or" is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0039] Example 1

[0040] Figure 1 A flowchart of a method for remote time correction of an intelligent chip based on a neural network disclosed in this embodiment is shown, and the steps are as follows:

[0041] S1. The smart chip regularly collects the deviation data between the local clock and the reference clock, and transmits it to the edge computing device through the network for deviation data preprocessing;

[0042] The deviation data between the local clock and the reference clock is recorded by the smart chip as the timestamp t_local of the current local clock. The smart chip obtains the corresponding timestamp t_ref from the reference clock source, calculates the difference between the two timestamps as the clock deviation data Δt=t_ref-t_local, and packages the clock deviation data and related device identifiers into a data packet for transmission to the edge computing device.

[0043] The deviation data preprocessing includes using the IQR rule to identify outliers and then removing noise through a Kalman filter, followed by standardization. The IQR rule is based on the interquartile range. If the clock deviation is less than Q1-1.5×(Q3-Q1), it is considered an outlier, where Q1 is the first quartile and Q3 is the third quartile. The outlier is removed to obtain the second clock deviation data X2 t Substitute the data in the second clock deviation data into the following formula X norm =((X2 t -ave(X2 t )) / stu(X2 t )) to obtain the third clock deviation data, where ave(X2 t ) represents the mean value of the data in the second clock deviation data, stu(X2 t ) represents the standard deviation of the data in the second clock deviation data.

[0044] S2. Train the clock deviation deep neural network model, use the historical clock deviation data as model training data, and learn the laws and correction methods of clock deviation; Figure 2 The present invention shows a flowchart of building a clock deviation deep neural network model for a neural network-based intelligent chip remote time correction method;

[0045] The specific construction process of the clock deviation deep neural network model includes:

[0046] S21, randomly extracting a subsample of the third clock deviation data to obtain a deviation subsample data set (td31, td32, ..., td3 B ), where td3 B represents the Bth clock deviation data in the deviation sub-sample data set, where B represents the number of data in the deviation sub-sample data set;

[0047] S22. Calculate the first-order momentum of the deviation subsample data Among them, θ represents the bias correction term, itr represents the number of iterations, and θ itr-1 represents the bias correction term after the itr-1th update, β1 represents the exponential decay rate of the first-order momentum, β1∈[0,1), F(td3 i ,θ itr-1 ) means that at the itr-1th iteration, the bias correction term is θ itr-1 When the clock deviation td3 i The objective function value of , j represents the jth element of the model;

[0048] S23, calculate the second-order momentum using the exponential decay average of the average value of the squared gradient of each deviation sub-sample data in the first-order momentum β2 represents the exponential decay rate of the second-order momentum, β2∈[0,1);

[0049] S24. Update deviation correction item ε represents a positive number, η represents the set model learning rate, and the function sqrt() represents the square root function;

[0050] S25. Repeat step S24. When the performance of the validation set no longer improves, stop training.

[0051] S3, deploying the clock deviation deep neural network model to the edge computing device, receiving the preprocessed clock deviation data in real time, and performing time correction reasoning;

[0052] S4. The edge computing device generates a time correction instruction according to the correction result of the clock deviation deep neural network model and sends it to the smart chip;

[0053] The time correction instruction is sent to the smart chip. After receiving the correction instruction, the smart chip adjusts the local clock to synchronize it with the reference clock. The smart chip then updates its internal state and feeds back the corrected time information to the edge computing device and returns it to the clock deviation deep neural network model.

[0054] S5. The cloud management platform monitors the time synchronization status of each smart chip in real time, detects anomalies and faults, Figure 3 The present invention shows a time synchronization state flow chart of a remote time correction method of an intelligent chip based on a neural network;

[0055] The time synchronization status is achieved by comparing the corrected time information with the reference clock using an intelligent chip, including a signal jitter index and a signal stability index, specifically including:

[0056] S51, the signal jitter index is calculated by collecting a time deviation data set within a time T with a time interval t as the standard, and the signal jitter index calculation formula is: Indicates Sampling point intelligent chip time, Indicates The time of the reference clock of each sampling point;

[0057] S52. The signal stability index is evaluated by observing the change of time deviation over time, and the calculation formula is:

[0058] S53, calculating the time synchronization state bias tssb=δ1×JitterSD-δ2×StaSD, where δ1 represents the weight of the signal jitter index, and δ2 represents the weight of the signal stability index;

[0059] S54. Set the time synchronization state deviation threshold Ttssb. When the tssb≥Ttssb, the platform will trigger an alarm notification and notify the administrator via email or SMS.

[0060] The threshold and weight may be set by default according to the present invention, or may be set by an operator.

[0061] Example 2

[0062] Figure 4 The framework diagram of a smart chip remote time correction system based on a neural network of the present invention is shown. Based on the same inventive concept as that of Example 1, the present invention provides a smart chip remote time correction system based on a neural network, including:

[0063] The device layer includes embedded devices and edge computing devices; the embedded devices include smart chips with local clock and data processing capabilities; the edge computing devices are deployed at the edge of the network and are responsible for preliminary data processing and time correction; the data analysis layer is used to be deployed on edge computing devices or the cloud, set up a clock deviation deep neural network model, provide a global time benchmark, complex analysis and management functions; the network communication layer includes Wi-Fi, 5G, and wired networks to realize data transmission between devices.

[0064] The data analysis layer includes a data acquisition and preprocessing module, a neural network time correction module, a time synchronization and correction module and a system monitoring and management module; the data acquisition and preprocessing module is used to periodically collect the deviation data between the local clock and the reference clock, and transmit it to the edge computing device through the network for deviation data preprocessing; the neural network time correction module is used to train the clock deviation deep neural network model, use the historical clock deviation data as the model training data, and learn the law and correction method of the clock deviation; the time synchronization and correction module is used to deploy the clock deviation deep neural network model to the edge computing device, receive the preprocessed clock deviation data in real time, and perform time correction reasoning; the edge computing device generates a time correction instruction based on the correction result of the clock deviation deep neural network model, and sends it to the smart chip; the system monitoring and management module is used to monitor the time synchronization status of each smart chip in real time and detect anomalies and faults.

[0065] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0066] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0067] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0068] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0069] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A remote time correction method for an intelligent chip based on a neural network, characterized in that: The following steps are involved: S1. The smart chip regularly collects the deviation data between the local clock and the reference clock, and transmits it to the edge computing device through the network for deviation data preprocessing; S2. Train the clock deviation deep neural network model, use the historical clock deviation data as model training data, and learn the laws and correction methods of clock deviation; S3, deploying the clock deviation deep neural network model to the edge computing device, receiving the preprocessed clock deviation data in real time, and performing time correction reasoning; S4. The edge computing device generates a time correction instruction according to the correction result of the clock deviation deep neural network model and sends it to the smart chip; S5. The cloud management platform monitors the time synchronization status of each smart chip in real time and detects anomalies and failures; The deviation data between the local clock and the reference clock is recorded by the smart chip as the timestamp t_local of the current local clock. The smart chip obtains the corresponding timestamp t_ref from the reference clock source, calculates the difference between the two timestamps as the clock deviation data Δt=t_ref-t_local, and packages the clock deviation data and related device identifiers into a data packet, which is transmitted to the edge computing device; The deviation data preprocessing includes using the IQR rule to identify outliers and then removing noise through a Kalman filter, followed by standardization. The IQR rule is based on the interquartile range. If the clock deviation is less than Q1-1.5×(Q3-Q1), it is considered an outlier, where Q1 is the first quartile and Q3 is the third quartile. The outlier is removed to obtain the second clock deviation data X2 t Substitute the data in the second clock deviation data into the following formula X norm =((X2 t -ave(X2 t )) / stu(X2 t )) to obtain the third clock deviation data, where ave(X2 t ) represents the mean value of the data in the second clock deviation data, stu(X2 t ) represents the standard deviation of the data in the second clock deviation data.

2. The method for remote time correction of an intelligent chip based on a neural network according to claim 1, characterized in that: The specific construction process of the clock deviation deep neural network model includes: S21, randomly extracting a subsample of the third clock deviation data to obtain a deviation subsample data set (td31, td32, ..., td3 B ), where td3 B represents the Bth clock deviation data in the deviation sub-sample data set, where B represents the number of data in the deviation sub-sample data set; S22. Calculate the first-order momentum of the deviation subsample data Among them, θ represents the bias correction term, itr represents the number of iterations, and θ itr-1 represents the bias correction term after the itr-1th update, β1 represents the exponential decay rate of the first-order momentum, β1∈[0,1), F(td3 i ,θ itr-1 ) means that at the itr-1th iteration, the bias correction term is θ itr-1 When the clock deviation td3 i The objective function value of , j represents the jth element of the model; S23, calculate the second-order momentum using the exponential decay average of the average value of the squared gradient of each deviation sub-sample data in the first-order momentum β2 represents the exponential decay rate of the second-order momentum, β2∈[0,1); S24. Update deviation correction item ε represents a positive number, η represents the set model learning rate, and the function sqrt() represents the square root function; S25. Repeat step S24. When the performance of the validation set no longer improves, stop training.

3. The method for remote time correction of an intelligent chip based on a neural network according to claim 2 is characterized in that: The time correction instruction is sent to the smart chip. After receiving the correction instruction, the smart chip adjusts the local clock to synchronize it with the reference clock. The smart chip then updates its internal state and feeds back the corrected time information to the edge computing device and returns it to the clock deviation deep neural network model.

4. The method for remote time correction of an intelligent chip based on a neural network according to claim 3 is characterized in that: The smart chip updates its internal state by parsing the update tasks in the instruction, wherein the update tasks include a time correction value, a correction frequency, and a correction period. Each update task has a unique ID, a deadline, an expected execution time, and an initial priority is assigned to each task. When the smart chip receives the update instruction, the ratio of the remaining deadline to the expected execution time of all tasks of the update instruction is calculated as the task deadline factor, and the product of each task deadline factor and the initial priority of each task is calculated as the priority update value of each task. The internal state of the smart chip is updated in descending order according to the priority update value of each task.

5. The method for remote time correction of an intelligent chip based on a neural network according to claim 4 is characterized in that: The time synchronization status is achieved by comparing the corrected time information with the reference clock using an intelligent chip, including a signal jitter index and a signal stability index, specifically including: S51, the signal jitter index is calculated by collecting a time deviation data set within a time T with a time interval t as the standard, and the signal jitter index calculation formula is: Indicates Sampling point intelligent chip time, Indicates The time of the reference clock of each sampling point; S52. The signal stability index is evaluated by observing the change of time deviation over time, and the calculation formula is: S53, calculating the time synchronization state bias tssb=δ1×JitterSD-δ2×StaSD, where δ1 represents the weight of the signal jitter index, and δ2 represents the weight of the signal stability index; S54. Set the time synchronization state deviation threshold Ttssb. When the tssb≥Ttssb, the platform will trigger an alarm notification and notify the administrator via email or SMS.

6. A neural network-based smart chip remote time correction system, used to execute a neural network-based smart chip remote time correction method as claimed in any one of claims 1 to 5, characterized in that: include: The device layer, including embedded devices and edge computing devices; The embedded device includes an intelligent chip with local clock and data processing capabilities; The edge computing device is deployed at the edge of the network and is responsible for preliminary data processing and time correction; The data analysis layer is used to deploy on edge computing devices or in the cloud to set up a clock deviation deep neural network model, provide a global time reference, complex analysis and management functions; The network communication layer, including Wi-Fi, 5G, and wired networks, enables data transmission between devices.

7. The neural network-based intelligent chip remote time correction system according to claim 6, characterized in that: The data analysis layer includes a data acquisition and preprocessing module, a neural network time correction module, a time synchronization and correction module, and a system monitoring and management module; The data acquisition and preprocessing module is used to periodically acquire deviation data between the local clock and the reference clock, and transmit the deviation data to the edge computing device through the network for preprocessing; The neural network time correction module is used to train a clock deviation deep neural network model, using historical clock deviation data as model training data to learn the laws and correction methods of clock deviation; The time synchronization and correction module is used to deploy the clock deviation deep neural network model to the edge computing device, receive the preprocessed clock deviation data in real time, and perform time correction reasoning; The edge computing device generates a time correction instruction according to the correction result of the clock deviation deep neural network model and sends it to the smart chip; The system monitoring and management module is used to monitor the time synchronization status of each smart chip in real time and detect anomalies and failures.

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