CMOS instruction execution circuit for L2 cache of RISC-V processor

Abstract

The present invention relates to the field of processor technology, and in particular to a CM0 instruction execution circuit for a secondary cache of a RISC-V processor, comprising: a CM0 instruction execution monitoring module, used for receiving CM0 instructions from a secondary cache core of a RISC-V processor; a competition logic module, used for judging the competition between a request for CM0 instructions to enter a mainstream pipeline and an instruction currently being executed by the mainstream pipeline, and placing CM0 instructions without competition into a consistency maintenance logic module; a consistency maintenance logic module, used for judging the cache consistency of an action executed by a CM0 instruction in the mainstream pipeline, and placing CM0 instructions that do not violate cache consistency into a bus request queue module; and a bus request queue module, used for placing CM0 instructions into a bus request queue of the mainstream pipeline to execute the CM0 instructions. The present invention reduces the impact of CM0 instruction execution on processor performance.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a CMOS instruction execution circuit for a secondary cache of a RISC-V processor. Background Art

[0002] In order to balance the cost and performance requirements of hardware implementation, modern processor systems usually divide cache into cache levels such as first cache and secondary cache (also known as level 2 cache or L2C). The first cache is closest to the processor core and is faster and more expensive. The second cache is slightly slower but has a larger capacity and may be shared by multiple processor cores. Therefore, the second cache is also responsible for maintaining data consistency between the first caches and contention arbitration between different requests.

[0003] After the advent of the RISC-V instruction system, the second-level cache is responsible for executing some unique instructions, including the CMO (cache maintenance operation) instruction set that complies with the RISC-V standard. The CMO instruction is used to maintain the state and data consistency of the target cache line from the perspective of each processor core. Generally, in addition to the programmer who actively inserts CMO instructions into the program, operating systems such as Linux will also add these instructions during the software compilation process. Therefore, when implementing related circuits in the second-level cache, not only the correctness of the instruction execution must be guaranteed, but also the impact of these instructions on the normal program running performance must be considered, which is a difficult point in the processor logic design. In related technologies, when the second-level cache processes CMO instructions, a larger circuit logic design is often required, and such a design will inevitably affect the power consumption and execution complexity of the processor. Summary of the invention

[0004] The present invention aims to solve the problems of complexity and difficulty in controlling execution power consumption when the existing processor secondary cache processes a CM0 instruction set.

[0005] In order to solve the above technical problems, the present invention provides a CM0 instruction execution circuit for a secondary cache of a RISC-V processor, the CM0 instruction execution circuit comprising:

[0006] A CM0 instruction execution monitoring module, used for receiving a CM0 instruction from a secondary cache core of a RISC-V processor, wherein the CM0 instruction execution monitoring module is initialized to a standby state and switches between the standby state and a processing state according to an execution process of the CM0 instruction;

[0007] A competition logic module, used to judge the competition between the request of the CM0 instruction to enter the mainstream pipeline and the instruction currently being executed by the mainstream pipeline, and put the CM0 instruction without competition into the consistency maintenance logic module;

[0008] A consistency maintenance logic module, used for determining the cache consistency of the action executed by the CM0 instruction in the main pipeline, and placing the CM0 instruction that does not violate the cache consistency into a bus request queue module;

[0009] The bus request queue module is used to put the CM0 instruction into the bus request queue of the main pipeline to execute the CM0 instruction.

[0010] Furthermore, the CM0 instruction execution monitoring module is also used for:

[0011] When the CMO instruction is obtained, it is determined whether the running state of the CMO instruction execution monitoring module itself is the standby state, and whether the CMO instruction is the first instruction sorted in the request queue of the secondary cache core of the RISC-V processor. If so, the running state of the CMO instruction execution monitoring module itself is set to the processing state, and the instruction information of the CMO instruction is saved.

[0012] Furthermore, the bus request queue module is also used for:

[0013] After the CM0 instruction is placed into the bus request queue, the CM0 instruction execution monitoring module is notified to set its own operating state to the standby state.

[0014] Furthermore, the instruction information of the CM0 instruction includes an instruction address, and the CM0 instruction execution monitoring module is further used for:

[0015] When the running state of the CMO instruction execution monitoring module itself is the processing state, and the instruction address of the received new CMO instruction is the same as the instruction address saved by the CMO instruction execution monitoring module, the new CMO instruction is returned to the request queue of the secondary cache core of the RISC-V processor.

[0016] Furthermore, the same determination of instruction addresses of different CM0 instructions is implemented based on the address of the cache line.

[0017] Furthermore, the cache consistency detection of the consistency maintenance logic module is implemented based on the mesi protocol field of the cache line.

[0018] Furthermore, if the CMO instruction is a cbo.clean request, and there is old data of the target instruction address corresponding to the CMO instruction in the secondary cache of the RISC-V processor, the bus request queue module is further used to:

[0019] The old data is written into the bus request queue, the old data is marked by the CM0 instruction execution monitoring module, and any CM0 instruction is prohibited from reading the old data, and then the CM0 instruction is put into the bus request queue.

[0020] Furthermore, if the CMO instruction is a cbo.flush request, and there is old data of the target instruction address corresponding to the CMO instruction in the secondary cache of the RISC-V processor, the bus request queue module is further used to:

[0021] The old data is written into the bus request queue, and the cache line corresponding to the CM0 instruction is deleted from the tag record of the secondary cache of the RISC-V processor. After that, the CM0 instruction is placed into the bus request queue.

[0022] Furthermore, if the CMO instruction is a cbo.invalid request, the bus request queue module is further configured to:

[0023] Regardless of whether there is old data corresponding to the target instruction address in the secondary cache of the RISC-V processor for the CM0 instruction, the old data and the cache line corresponding to the CM0 instruction will be deleted from the tag record of the secondary cache of the RISC-V processor.

[0024] The beneficial effect achieved by the present invention is that a CMO instruction execution circuit for the secondary cache of a RISC-V processor is proposed, which is provided with a CMO instruction execution monitoring module. The module in the execution circuit will detect and borrow the existing related control logic of the main pipeline during the period when the CMO instruction is executed by the secondary cache. Therefore, during the period when the CMO instruction is executed by the secondary cache, the normal execution of other instructions by the main pipeline will not be affected. At the same time, only fewer hardware resources are needed to implement it, thereby controlling the actual circuit area and power consumption of the processor brought by the execution circuit, and greatly reducing the impact of the CMO instruction execution on the processor pipeline performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a logic schematic diagram of a CM0 instruction execution circuit for a secondary cache of a RISC-V processor provided by an embodiment of the present invention;

[0026] Figure 2 It is an execution diagram of the CM0 instruction execution circuit for the secondary cache of a RISC-V processor proposed in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] Please refer to Figure 1 , Figure 1 1 is a logic diagram of a CM0 instruction execution circuit for a secondary cache of a RISC-V processor provided in an embodiment of the present invention. RISC-V is an open source instruction set architecture proposed based on the principle of a reduced instruction set, which has the advantages of simplified instructions and low power consumption. The CM0 instruction execution circuit 100 includes:

[0029] A CMO instruction execution monitoring module 101 (CMO Monitor), configured to receive a CMO instruction from a secondary cache core of a RISC-V processor, wherein the CMO instruction execution monitoring module is initialized to a standby state and switches between the standby state and a processing state (busy) according to an execution process of the CMO instruction;

[0030] The competition logic module 102 is used to judge the competition between the request of the CM0 instruction to enter the mainstream pipeline and the instruction currently being executed by the mainstream pipeline, and put the CM0 instruction without competition into the consistency maintenance logic module 103;

[0031] A consistency maintenance logic module 103, used to determine the cache consistency of the action executed by the CM0 instruction in the main pipeline, and put the CM0 instruction that does not violate the cache consistency into the bus request queue module 104;

[0032] The bus request queue module 104 is used to put the CM0 instruction into the bus request queue of the main pipeline to execute the CM0 instruction.

[0033] Furthermore, the CM0 instruction execution monitoring module 101 is also used for:

[0034] When the CMO instruction is obtained, it is determined whether the running state of the CMO instruction execution monitoring module 101 itself is the standby state, and whether the CMO instruction is the first instruction sorted in the request queue of the secondary cache core of the RISC-V processor. If so, the running state of the CMO instruction execution monitoring module 101 itself is set to the processing state, and the instruction information of the CMO instruction is saved.

[0035] It can be understood that in an actual processor circuit, in order to realize data processing and storage, the CM0 instruction execution monitoring module 101 includes a state machine for controlling the CM0 instruction execution process, and a register group for storing information such as the CM0 instruction address and type.

[0036] Furthermore, the bus request queue module 104 is also used for:

[0037] After the CM0 instruction is placed into the bus request queue, the CM0 instruction execution monitoring module 101 is notified to set its own operating state to the standby state.

[0038] It should be noted that since the RISC-V standard CMO instructions all carry addresses and are instructions executed for a specific cache line, the CMO instruction execution monitoring module 101 will save information such as the address of the CMO instruction that has obtained the current execution permission. If other non-CMO instructions entering the mainstream pipeline during the execution of the CMO instruction are inconsistent with the instruction address currently saved by the CMO instruction execution monitoring module 101, memory access can still be performed normally.

[0039] Furthermore, the instruction information of the CM0 instruction includes an instruction address, and the CM0 instruction execution monitoring module is further used for:

[0040] When the running state of the CMO instruction execution monitoring module itself is the processing state, and the instruction address of the received new CMO instruction is the same as the instruction address saved by the CMO instruction execution monitoring module, the new CMO instruction is returned to the request queue of the secondary cache core of the RISC-V processor.

[0041] Furthermore, the same determination of instruction addresses of different CM0 instructions is implemented based on the address of the cache line.

[0042] Furthermore, the cache consistency detection of the consistency maintenance logic module 103 is implemented based on the mesi protocol field of the cache line. Mesi is a commonly used cache consistency maintenance protocol, where m / e / s / i respectively represent the status of the cache line at the current memory level, where m (modified) means that the cache line is exclusive and the data has been modified; e (exclusive) means that the cache line is exclusive and the data has not been modified; s (shared) means that the cache line is shared, and no processor should have the authority to rewrite the cache line; i (invalidated) means that the cache line is invalid at this memory level.

[0043] Cacheline coherency maintenance determines whether a cache line is still valid by judging the mesi information of the cache line. At the same time, it ensures that the status and data of any cache line are consistent from the perspective of all processors by judging and maintaining the mesi information of the processor core.

[0044] Specifically, after the memory access request obtains the cache line information stored in the secondary cache Tag ram, the operation (tag compare) to be performed by the request of the CM0 instruction is determined according to information such as the request type and the cache line status.

[0045] Based on the functions implemented by the above modules, the execution diagram of the CM0 instruction execution circuit for the secondary cache of the RISC-V processor proposed in the embodiment of the present invention is as follows: Figure 2 shown.

[0046] Furthermore, if the CMO instruction is a cbo.clean request, and there is old data (dirty data) corresponding to the target instruction address of the CMO instruction in the secondary cache of the RISC-V processor, the bus request queue module 104 is further used to:

[0047] The old data is written into the bus request queue, the old data is marked by the CM0 instruction execution monitoring module, and any CM0 instruction is prohibited from reading the old data, and then the CM0 instruction is put into the bus request queue.

[0048] Furthermore, if the CMO instruction is a cbo.flush request, and there is old data corresponding to the target instruction address of the CMO instruction in the secondary cache of the RISC-V processor, the bus request queue module 104 is further used to:

[0049] The old data is written into the bus request queue, and the cache line corresponding to the CM0 instruction is deleted from the tag record of the secondary cache of the RISC-V processor. After that, the CM0 instruction is placed into the bus request queue.

[0050] Furthermore, if the CMO instruction is a cbo.invalid request, the bus request queue module 104 is further configured to:

[0051] Regardless of whether there is old data corresponding to the target instruction address in the secondary cache of the RISC-V processor for the CM0 instruction, the old data and the cache line corresponding to the CM0 instruction will be deleted from the tag record of the secondary cache of the RISC-V processor.

[0052] It should be noted that even if the secondary cache is not used as LLC (last level cache), the execution circuit designed in the embodiment of the present invention can complete the consistency maintenance internally before the CMO instruction is processed by the LLC, and notify the processor core to release the instruction fence caused by the CMO instruction; therefore, even if the next cache level needs a longer time to process the CMO instruction issued by the secondary cache, as long as the secondary cache has completed the consistency maintenance of the cache line related to the instruction, the processor system can continue to run subsequent instructions, thereby maximizing the system performance.

[0053] Compared with the prior art, since the CMO instruction of the RISC-V standard stipulates that the processor core cannot submit other updated instructions before the current CMO instruction is completed, the technical solution provided by the embodiment of the present invention only needs the CMO instruction to complete the consistency maintenance operation at the secondary cache level, and then the processor core can be notified based on the CMO instruction execution monitoring module 101 and the bus request queue module 104 that the current CMO instruction can be submitted and completed, without waiting for the current instruction to be further sent to the next memory level for operation, thereby greatly reducing the impact of CMO instruction execution on system performance.

[0054] The beneficial effect achieved by the present invention is that a CMO instruction execution circuit for the secondary cache of a RISC-V processor is proposed, which is provided with a CMO instruction execution monitoring module. The module in the execution circuit will detect and borrow the existing related control logic of the main pipeline during the period when the CMO instruction is executed by the secondary cache. Therefore, during the period when the CMO instruction is executed by the secondary cache, the normal execution of other instructions by the main pipeline will not be affected. At the same time, only fewer hardware resources are needed to implement it, thereby controlling the actual circuit area and power consumption of the processor brought by the execution circuit, and greatly reducing the impact of the CMO instruction execution on the processor pipeline performance.

[0055] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0056] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A CMOS instruction execution circuit for a RISC-V processor secondary cache, characterized in that: The CMOS instruction execution circuit comprises: A CM0 instruction execution monitoring module, used for receiving a CM0 instruction from a secondary cache core of a RISC-V processor, wherein the CM0 instruction execution monitoring module is initialized to a standby state and switches between the standby state and a processing state according to an execution process of the CM0 instruction; A competition logic module, used to judge the competition between the request of the CM0 instruction to enter the mainstream pipeline and the instruction currently being executed by the mainstream pipeline, and put the CM0 instruction without competition into the consistency maintenance logic module; A consistency maintenance logic module, used for determining the cache consistency of the action executed by the CM0 instruction in the main pipeline, and placing the CM0 instruction that does not violate the cache consistency into a bus request queue module; The bus request queue module is used to put the CM0 instruction into the bus request queue of the main pipeline to execute the CM0 instruction.

2. The CM0 instruction execution circuit for the secondary cache of a RISC-V processor according to claim 1, characterized in that: The CMO instruction execution monitoring module is also used for: When the CMO instruction is obtained, it is determined whether the running state of the CMO instruction execution monitoring module itself is the standby state, and whether the CMO instruction is the first instruction sorted in the request queue of the secondary cache core of the RISC-V processor. If so, the running state of the CMO instruction execution monitoring module itself is set to the processing state, and the instruction information of the CMO instruction is saved.

3. The CM0 instruction execution circuit for the secondary cache of a RISC-V processor according to claim 2, characterized in that: The bus request queue module is also used for: After the CM0 instruction is placed into the bus request queue, the CM0 instruction execution monitoring module is notified to set its own operating state to the standby state.

4. The CM0 instruction execution circuit for the secondary cache of a RISC-V processor according to claim 2, characterized in that: The instruction information of the CM0 instruction includes an instruction address, and the CM0 instruction execution monitoring module is further used for: When the running state of the CMO instruction execution monitoring module itself is the processing state, and the instruction address of the received new CMO instruction is the same as the instruction address saved by the CMO instruction execution monitoring module, the new CMO instruction is returned to the request queue of the secondary cache core of the RISC-V processor.

5. The CM0 instruction execution circuit for the secondary cache of a RISC-V processor according to claim 4, characterized in that: The same determination of instruction addresses of different CM0 instructions is implemented based on the address of the cache line.

6. The CM0 instruction execution circuit for the secondary cache of a RISC-V processor according to claim 5, characterized in that: The cache consistency detection of the consistency maintenance logic module is implemented based on the mesi protocol field of the cache line.

7. The CM0 instruction execution circuit for the secondary cache of a RISC-V processor according to claim 1, characterized in that: If the CMO instruction is a cbo.clean request, and there is old data corresponding to the target instruction address of the CMO instruction in the secondary cache of the RISC-V processor, the bus request queue module is further used to: The old data is written into the bus request queue, the old data is marked by the CM0 instruction execution monitoring module, and any CM0 instruction is prohibited from reading the old data, and then the CM0 instruction is put into the bus request queue.

8. The CM0 instruction execution circuit for the L2 cache of a RISC-V processor according to claim 1, characterized in that: If the CMO instruction is a cbo.flush request, and there is old data corresponding to the target instruction address of the CMO instruction in the secondary cache of the RISC-V processor, the bus request queue module is further used to: The old data is written into the bus request queue, and the cache line corresponding to the CM0 instruction is deleted from the tag record of the secondary cache of the RISC-V processor. After that, the CM0 instruction is placed into the bus request queue.

9. The CM0 instruction execution circuit for the secondary cache of a RISC-V processor according to claim 1, characterized in that: If the CMO instruction is a cbo.invalid request, the bus request queue module is further configured to: Regardless of whether there is old data corresponding to the target instruction address in the secondary cache of the RISC-V processor for the CM0 instruction, the old data and the cache line corresponding to the CM0 instruction will be deleted from the tag record of the secondary cache of the RISC-V processor.

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