Multi-core processor architecture based on hardware physical partitioning, vehicle and control system thereof, and interrupt processing method

Abstract

The present invention relates to the field of computers and discloses a multi-core processor architecture based on hardware physical segmentation, a vehicle and its control system, and an interrupt processing method. The multi-core processor physically isolates independent cores from one or more main cores by attaching them to different buses. The independent cores are configured with a dedicated first input / output unit and an interrupt signal line for connecting to an external emergency interrupt source. In response to an interrupt request sent by the emergency interrupt source, the independent core executes an interrupt program and outputs a corresponding interrupt instruction through the first input / output unit. The independent core does not process interrupt requests from ordinary interrupt sources. In response to an interrupt request sent by an ordinary interrupt source, the system interrupt processing unit controls the main core to execute the interrupt program and output the corresponding interrupt instruction through the second input / output unit. The independent core directly receives interrupt signals from external interrupt sources to handle time-critical or mission-critical interrupt events, thereby resolving delay issues and ensuring the real-time performance of the system.

Description

Technical Field

[0001] The present invention relates to the field of multi-core processors, and in particular to a multi-core processor architecture based on hardware physical partitioning, a vehicle and its control system, and an interrupt processing method. Background Art

[0002] In applications such as industrial control and autonomous driving, processors must handle time-critical or mission-critical interrupts in the shortest possible time to meet real-time response requirements. Due to increasingly stringent real-time requirements, multi-core processors have become a mainstream trend in computer processor design. A multi-core processor integrates two or more independent cores within a single physical processor. These cores can simultaneously execute different tasks, thereby improving computer performance.

[0003] Currently, the architecture of multi-core processors is Figure 1 As shown in the operating system environment, all resources are managed by the operating system. When an interruption occurs, the operating system needs to perform task switching and resource scheduling, which is done by Figure 1 The system interrupt processing unit in the system completes task switching and resource scheduling.

[0004] However, current multi-core processors face the following major problems when handling time-critical or mission-critical interrupt events: First, because all resources are centrally managed by the operating system, when an interrupt occurs, the operating system needs to perform task switching and resource scheduling, which often leads to processing delays, affecting the real-time performance of the system and failing to meet the system's real-time requirements; second, if the processor needs to be upgraded to meet the needs of handling emergency events, this will increase the cost of the equipment.

[0005] The disclosure of the above background technology content is only used to assist in understanding the concept and technical solution of this application. It does not necessarily belong to the prior art of this application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of this application, the above background technology should not be used to evaluate the novelty and creativity of this application. Summary of the Invention

[0006] The purpose of the present invention is to provide an improved multi-core processor architecture that uses hardware physical segmentation to isolate independent cores from other processor cores, ensuring that the independent cores meet the real-time requirements of the hardware.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A multi-core processor architecture based on hardware physical partitioning, the multi-core processor comprising an independent core, one or more master cores, a first input / output unit, a second input / output unit, and a system interrupt processing unit, wherein the independent core is connected to the first input / output unit via a first internal bus, and the master core is connected to the second input / output unit and the system interrupt processing unit via a second internal bus different from the first internal bus;

[0009] The system interrupt processing unit is configured to be connected to an external common interrupt source;

[0010] The independent core is configured with a dedicated interrupt signal line, which is configured to be connected to an external emergency interrupt source;

[0011] In response to an interrupt request sent by the emergency interrupt source, the independent core executes an interrupt program and outputs a corresponding interrupt instruction through the first input and output unit;

[0012] The independent core does not process the interrupt request of the common interrupt source. In response to the interrupt request sent by the common interrupt source, the main core executes the interrupt program and outputs the corresponding interrupt instruction through the second input and output unit.

[0013] Further, based on any one of the above technical solutions or a combination of multiple technical solutions, the multi-core processor further includes a shared cache, which is connected to at least the first internal bus;

[0014] The independent core is itself configured with an intra-core interrupt processing unit. If the intra-core interrupt processing unit analyzes the interrupt request of the emergency interrupt source to include an emergency interrupt task and a non-emergency interrupt task, the intra-core interrupt processing unit completes the emergency interrupt task and stores the non-emergency interrupt task in the shared cache;

[0015] The shared cache transmits the non-urgent interrupt task to the system interrupt processing unit via an inter-core interrupt signal line, and then the main core completes the non-urgent interrupt task.

[0016] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the shared cache is also connected to the second internal bus to realize data exchange between the independent core and the main core, and / or realize data exchange between multiple main cores.

[0017] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the multi-core processor further includes a main memory controller configured to control a data channel between the core of the processor and the memory;

[0018] There is one main memory controller, which is electrically connected to the first internal bus and the second internal bus;

[0019] Alternatively, there are two main memory controllers, one of which is electrically connected to the first internal bus, and the other is electrically connected to the second internal bus.

[0020] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the architecture also includes an independent core BIOS and a main core BIOS, which are electrically connected to the main memory controller of the multi-core processor through a system bus, wherein the independent core BIOS corresponds to the independent core, and the main core BIOS corresponds to the main core.

[0021] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the architecture also includes an independent core memory and a main core memory, which is electrically connected to the main memory controller of the multi-core processor through a system bus, wherein the independent core memory corresponds to the independent core, and the main core memory corresponds to the main core.

[0022] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the architecture also includes a shared memory, which is electrically connected to the main memory controller of the multi-core processor through a system bus, and the shared memory is configured to be accessed by the independent core and the main core.

[0023] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the number of the independent cores is multiple, the number of the first internal buses and the first input and output units is multiple, and the independent cores, the first internal buses, and the first input and output units are arranged in a one-to-one correspondence.

[0024] According to another aspect of the present invention, a vehicle control system is provided, comprising a detection module, an emergency interrupt source, a normal interrupt source, a braking module, a prompt module, and the multi-core processor architecture described above, wherein the detection module is configured to detect vehicle environmental information and / or vehicle operating information; when the detection module detects that a preset emergency braking condition is satisfied, the emergency interrupt source sends an emergency interrupt request to an independent core of the multi-core processor, and the independent core then sends a braking instruction to the braking module via its corresponding first input / output unit;

[0025] When the detection module detects that the preset normal interrupt condition is met, the normal interrupt source sends a normal interrupt request to the system interrupt processing unit of the multi-core processor, and then the main core of the multi-core processor sends instructions to the braking module and / or prompt module through its corresponding second input and output unit.

[0026] According to yet another aspect of the present invention, a vehicle is provided, characterized by comprising the vehicle control system as described above.

[0027] According to another aspect of the present invention, there is provided an interrupt processing method, comprising the following steps:

[0028] Pre-dividing the cores of the multi-core processor into independent cores and main cores, physically isolating the independent cores from the main core, and configuring exclusive interrupt signal lines for the independent cores;

[0029] Connecting an emergency interrupt source outside the processor to the dedicated interrupt signal line, and connecting a common interrupt source outside the processor to the system interrupt processing unit of the multi-core processor;

[0030] If the emergency interrupt source issues an interrupt request, the independent core executes an interrupt program;

[0031] If the common interrupt source issues an interrupt request, the system interrupt processing unit controls the main core to execute the interrupt program.

[0032] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the interrupt processing method provided by the present invention also includes:

[0033] Preset shared cache;

[0034] If the independent core analyzes that the interrupt request of the emergency interrupt source includes an emergency interrupt task and a non-emergency interrupt task, the independent core completes the emergency interrupt task and stores the non-emergency interrupt task in the shared cache;

[0035] The shared cache transmits the non-urgent interrupt task to the system interrupt processing unit via an inter-core interrupt signal line, and then the system interrupt processing unit controls the main core to complete the non-urgent interrupt task.

[0036] Furthermore, based on any one of the above technical solutions or a combination of multiple technical solutions, the system interrupt processing unit controls the main core to execute the interrupt program, including:

[0037] The system interrupt processing unit generates a plurality of interrupt tasks according to the interrupt request of the common interrupt source;

[0038] The system interrupt processing unit distributes the plurality of interrupt tasks to a plurality of main cores.

[0039] The beneficial effects brought about by the technical solution provided by the present invention are as follows:

[0040] a. Physically isolate one core (an independent core) from the other cores. The independent core directly receives interrupt signals from external interrupt sources to handle time-critical or mission-critical interrupt events, resolve latency issues, and ensure the system's hard real-time performance.

[0041] b multi-core processor architecture of the present invention is applicable to Linux systems and Linux-derived real-time OS systems, and may also be applicable to Windows systems with more stringent resource requirements;

[0042] c. Compared to the increased equipment costs caused by upgrading the processor to meet the real-time requirements of handling emergency events, the present invention only requires adding an internal processor bus and an input and output unit dedicated to an independent core, which can better achieve hard real-time performance at a lower cost.

[0043] d. The independent core receives interrupt signals from emergency interrupt sources through a dedicated interrupt signal line. When handling emergency interrupt events, it is not subject to system scheduling and management, which improves the efficiency of handling emergency interrupt events;

[0044] e. The independent core and the main core are located on the same chip, and the internal bus of the processors of both parties is connected by a shared cache, which can shorten the delay of exchanging information and ensure hard real-time. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic diagram of the architecture of a current multi-core processor;

[0047] Figure 2 A schematic diagram of the architecture of a multi-core processor with physical hardware partitioning provided by an exemplary embodiment of the present invention;

[0048] Figure 3 A schematic diagram of a memory configuration structure of a multi-core processor provided as an exemplary embodiment of the present invention;

[0049] Figure 4 A schematic structural diagram of a vehicle control system provided by an exemplary embodiment of the present invention;

[0050] Figure 5 A flowchart of an interrupt processing method provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] The present invention aims to provide a new, improved multi-core processor architecture capable of achieving hard real-time performance. This architecture physically isolates one core (hereinafter referred to as an independent core) from the other cores (hereinafter referred to as the main core). The independent core directly receives interrupt signals from external interrupt sources to handle time-critical or mission-critical interrupt events, thereby resolving latency issues and ensuring the system's real-time performance. The terms "independent core" and "main core" are used only to distinguish between different processor internal buses and the corresponding task execution processes. The present invention does not specify whether the internal structures of the independent core and the main core differ. This physical isolation ensures that the isolated independent core is not affected by other main cores when handling critical events, thereby ensuring hard real-time performance.

[0054] In one embodiment of the present invention, a multi-core processor architecture based on hardware physical partitioning is provided, which includes a multi-core processor and does not exclude the possibility of also including processor peripheral structures, such as memory, etc. Figure 2 As shown, the multi-core processor includes an independent core, one or more main cores, a first input and output unit, a second input and output unit, and a system interrupt processing unit, wherein the independent core is connected to the first input and output unit via a first internal bus, and the main core is connected to the second input and output unit and the system interrupt processing unit via a second internal bus different from the first internal bus;

[0055] Whether it is an independent core or a main core, it is equipped with an interrupt processing unit to handle interrupt tasks:

[0056] The system interrupt processing unit is configured to be connected to an external common interrupt source;

[0057] The independent core is configured with an exclusive interrupt signal line, which is configured to be connected to an external emergency interrupt source. The urgency of the interrupt request of the emergency interrupt source in this embodiment is higher than that of the interrupt request of the ordinary interrupt source; providing an exclusive interrupt signal line enables faster response to external emergency events.

[0058] In response to an interrupt request sent by the emergency interrupt source, the independent core executes an interrupt program and outputs a corresponding interrupt instruction through the first input and output unit;

[0059] The independent core does not process the interrupt request of the common interrupt source. In response to the interrupt request sent by the common interrupt source, the system interrupt processing unit can receive the interrupt request of the common interrupt source through various I / O expansion buses (such as ISA, EISA, MCA, VL, PCI, etc.), and then distribute the interrupt task to each main core through the second internal bus. The main core executes the interrupt program and outputs the corresponding interrupt instruction through the second input and output unit.

[0060] In this embodiment, the independent core and the main core do not share the bus inside the processor, so that the independent core and the main core are physically isolated, that is, the hardware physical segmentation of the multi-core processor is completed. By isolating the independent core from the main core, and the independent core is directly connected to the external emergency interrupt source, it can focus on processing interrupt events caused by time critical or mission critical, without being disturbed by the processor's internal interrupt processing unit, including the main core and the system interrupt processing unit, which causes delays in the emergency interrupt event processing process. It can be seen that when the independent core processes the interrupt request sent by the emergency interrupt source, it is not subject to system scheduling and management, which improves the efficiency of processing emergency interrupt events, and the independent core has absolute control over the necessary resources when processing the interrupt. The independent core executes a simple idle task and interrupt program, or runs Linux or other operating systems, which can realize the design architecture of the multi-core processor without increasing the design complexity and cost.

[0061] The multi-core processor of this embodiment adopts deep physical segmentation, so that the multi-core processor architecture here is applicable to Linux systems and Linux-derived real-time OS systems, and can also be applied to Windows systems with stricter resource requirements.

[0062] like Figure 2 As shown, the multi-core processor further includes a shared cache, which is connected to at least the first internal bus;

[0063] The independent core is itself configured with an intra-core interrupt processing unit. If the intra-core interrupt processing unit analyzes the interrupt request of the emergency interrupt source to include an emergency interrupt task and a non-emergency interrupt task, the intra-core interrupt processing unit completes the emergency interrupt task and stores the non-emergency interrupt task in the shared cache;

[0064] The shared cache transmits the non-urgent interrupt task to the system interrupt processing unit via an inter-core interrupt signal line, and then the main core completes the non-urgent interrupt task.

[0065] That is to say, although the interrupt signals sent by the external emergency interrupt source include time critical or mission critical interrupt signals, they may also include interrupt signals that are not time critical or mission critical. In this case, if the shared cache and inter-core interrupt signal lines are not set, the independent core can handle the interrupt events caused by non-time critical and non-mission critical at the same time; in this embodiment with shared cache and inter-core interrupt signal lines, after the independent core handles the interrupt events caused by time critical or mission critical, the remaining non-urgent interrupt signals can be stored in the shared cache, and then sent to the system interrupt processing unit using the inter-core interrupt signal line, which will analyze and process them and finally allocate them to the main core to handle these non-urgent interrupt events.

[0066] Figure 2 The single number of independent cores and two main cores (main core 1 and main core 2) shown are for illustration only. On the one hand, the number of main cores can be single or expanded to three or even more, and all main cores can share the processor's internal bus, the second input and output unit, and the system interrupt processing unit; on the other hand, the number of independent cores can also be expanded. While expanding the independent cores, their exclusive internal buses and input and output units are configured one by one, so that each independent core does not share the processor's internal bus with other cores and can transmit signals through its exclusive input and output unit.

[0067] Further implementations such as Figure 2 As shown, the shared cache is also connected to the second internal bus to enable data exchange between the independent core and the master core, and / or between multiple master cores. That is, the master core can store data to the shared cache via the second internal bus, and can also retrieve data from the shared cache via the second internal bus. In addition to storing remaining non-urgent interrupt signals in the shared cache as mentioned above, the independent core can also use the shared cache to temporarily store state.

[0068] Figure 3 The multi-core processor architecture in FIG shows the memory arrangement around the multi-core processor. The multi-core processor and the memory are communicatively connected via a system bus. Correspondingly, the multi-core processor also includes a main memory controller configured to control the data channel between the processor cores and the memory.

[0069] You can Figure 3 As shown, there is one main memory controller, which is electrically connected to the first internal bus and the second internal bus at the same time, that is, the independent core and the main core share the main memory controller, which is a relatively cost-saving approach;

[0070] The present invention is not limited to the implementation of a single main memory controller. In another embodiment, there are two main memory controllers (not shown), one of which is electrically connected to the first internal bus, and the other is electrically connected to the second internal bus.

[0071] See also Figure 3 The BIOS (Basic Input Output System) in the memory includes an independent core BIOS and a main core BIOS, which are electrically connected to the main memory controller of the multi-core processor via a system bus. The independent core BIOS corresponds to the independent core, and the main core BIOS corresponds to the main core. The independent core has a dedicated BIOS, which ensures its operational independence and is not affected by other main cores. This embodiment is not limited to the use of UEFI BIOS, and a legacy BIOS may also be used.

[0072] Continue to see Figure 3 The memory further includes an independent core memory, a main core memory, and a shared memory, which is electrically connected to the main memory controller of the multi-core processor via a system bus. The independent core memory corresponds to the independent core, the main core memory corresponds to the main core, and the shared memory is configured to be accessible by both the independent core and the main core. When the amount of information to be exchanged between the independent core and the main core is small, a shared cache can be used to implement the data exchange. However, when the amount of information is large, the shared cache cannot meet the requirement, and in this case, the shared memory can be used to implement the data exchange.

[0073] One embodiment of the present invention provides a vehicle control system, such as Figure 4As shown, taking a car as an example, the car control system includes a detection module, an emergency interrupt source, a normal interrupt source, a braking module, a prompt module, and the multi-core processor architecture as described above (the entire contents of the multi-core processor architecture embodiment are incorporated into this control system embodiment by reference). The detection module is configured to detect vehicle environmental information and / or vehicle operation information. When the detection module detects that a preset emergency braking condition is met, the emergency interrupt source sends an emergency interrupt request to an independent core of the multi-core processor, and the independent core then sends a braking instruction to the braking module through its corresponding first input and output unit.

[0074] When the detection module detects that the preset normal interrupt condition is met, the normal interrupt source sends a normal interrupt request to the system interrupt processing unit of the multi-core processor, and then the main core of the multi-core processor sends instructions to the braking module and / or prompt module through its corresponding second input and output unit.

[0075] In a specific embodiment, if the detection module detects that an obstacle in front of the vehicle requires emergency braking, it sends an emergency interrupt signal to the independent core through the emergency interrupt source. The independent core processes the emergency interrupt event, generates a braking instruction and sends it to the vehicle's braking module through the first input and output unit. The remaining non-emergency interrupt signals are sent to the system interrupt processing unit through the shared cache and the inter-core interrupt signal line, such as turning on the double flash lights to alert the vehicle behind, or turning on the high beam to avoid pedestrians in front in advance. This interrupt time is allocated by the system interrupt processing unit to the corresponding main core for processing.

[0076] If the detection module detects that the vehicle is operating in reverse mode, it sends an interrupt signal to the system interrupt processing unit through a common interrupt source. The system interrupt processing unit processes this interrupt signal and then assigns the task of starting the reversing image to main core 1 and the task of driving the vehicle in reverse to main core 2. During the reversing process, if the detection module detects a situation requiring emergency obstacle avoidance, it sends an emergency interrupt signal to the independent core through the emergency interrupt source. Since the independent core has a single function, it can handle emergency interrupt events without delay, ensuring vehicle safety.

[0077] The above vehicle control system can be applied to the main bodies of various types of vehicles, such as cars, trains, subways, ships, airplanes (including drones), forklifts, excavators and other engineering vehicles.

[0078] The multi-core processor architecture of this embodiment can be widely used in fields such as industrial control and autonomous driving. In the industrial control field, the independent core of the present invention can handle time-critical events in real time, improving production efficiency; in the field of autonomous driving, the independent core of the present invention can quickly respond to emergencies and ensure driving safety. Furthermore, because the independent core of the present invention can meet the needs of emergency handling without requiring a processor upgrade, it can effectively save equipment costs and has a large market demand.

[0079] The embodiment of the present invention further provides an interrupt processing method, such as Figure 5 As shown, the interrupt processing method includes the following steps:

[0080] Pre-dividing the cores of the multi-core processor into independent cores and main cores, physically isolating the independent cores from the main core, and configuring exclusive interrupt signal lines for the independent cores;

[0081] Connecting an emergency interrupt source outside the processor to the dedicated interrupt signal line, and connecting a common interrupt source outside the processor to the system interrupt processing unit of the multi-core processor;

[0082] If the emergency interrupt source issues an interrupt request, the independent core executes an interrupt program;

[0083] If the common interrupt source issues an interrupt request, the system interrupt processing unit controls the main core to execute the interrupt program; specifically, the system interrupt processing unit generates multiple interrupt tasks according to the interrupt request of the common interrupt source; the system interrupt processing unit distributes the multiple interrupt tasks to multiple main cores.

[0084] Furthermore, the interrupt handling method provided by the present invention further includes:

[0085] Preset shared cache;

[0086] If the independent core analyzes that the interrupt request of the emergency interrupt source includes an emergency interrupt task and a non-emergency interrupt task, the independent core completes the emergency interrupt task and stores the non-emergency interrupt task in the shared cache;

[0087] The shared cache transmits the non-urgent interrupt task to the system interrupt processing unit via an inter-core interrupt signal line, and then the system interrupt processing unit controls the main core to complete the non-urgent interrupt task.

[0088] The interrupt handling method provided in this embodiment belongs to the same inventive concept as the multi-core processor architecture based on hardware physical partitioning in the above-mentioned embodiment. The entire content of the multi-core processor architecture embodiment is incorporated into the present interrupt handling method embodiment by full reference and will not be repeated here.

[0089] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0090] The above is only a specific implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A multi-core processor architecture based on hardware physical partitioning, characterized in that: The multi-core processor includes an independent core, a plurality of main cores, a first input and output unit, a second input and output unit, and a system interrupt processing unit, wherein the independent core is connected to the first input and output unit via a first internal bus, and the main core is connected to the second input and output unit and the system interrupt processing unit via a second internal bus different from the first internal bus; The system interrupt processing unit is configured to be connected to an external common interrupt source; The system interrupt processing unit is not connected to the first internal bus; The independent core is configured with a dedicated interrupt signal line, which is configured to be connected to an external emergency interrupt source; In response to an interrupt request sent by the emergency interrupt source, the independent core executes an interrupt program and outputs a corresponding interrupt instruction to a brake module outside the multi-core processor architecture through the first input and output unit; The independent core does not process the interrupt request of the common interrupt source. In response to the interrupt request sent by the common interrupt source, the system interrupt processing unit generates an interrupt task according to the interrupt request of the common interrupt source and assigns it to the main core, and then the main core executes the interrupt program and outputs the corresponding interrupt instruction through the second input and output unit; The multi-core processor further includes a shared cache connected to the first internal bus; the independent core is configured with an intra-core interrupt processing unit. If the intra-core interrupt processing unit analyzes the interrupt request of the emergency interrupt source to include an emergency interrupt task and a non-emergency interrupt task, the intra-core interrupt processing unit completes the emergency interrupt task and stores the non-emergency interrupt task in the shared cache; the shared cache transmits the non-emergency interrupt task to the system interrupt processing unit via an inter-core interrupt signal line, and the main core then completes the non-emergency interrupt task. The independent core and the main core do not share the bus inside the processor. By isolating the independent core from the main core and directly connecting the independent core to an external emergency interrupt source, the independent core is not interfered with by the processor's internal components, including the main core and the system interrupt processing unit, which may cause delays in the processing of emergency interrupt events. When processing the interrupt request sent by the emergency interrupt source, the independent core is not subject to system scheduling and management.

2. The multi-core processor architecture according to claim 1, wherein: The multi-core processor further includes a main memory controller configured to control a data channel between the cores of the processor and the memory; There is one main memory controller, which is electrically connected to the first internal bus and the second internal bus; Alternatively, there are two main memory controllers, one of which is electrically connected to the first internal bus, and the other is electrically connected to the second internal bus.

3. The multi-core processor architecture according to claim 2, wherein: The architecture further includes an independent core BIOS and a main core BIOS, which are electrically connected to the main memory controller of the multi-core processor via a system bus, wherein the independent core BIOS corresponds to the independent core, and the main core BIOS corresponds to the main core.

4. The multi-core processor architecture according to claim 2, wherein: The architecture further includes an independent core memory and a main core memory, which are electrically connected to the main memory controller of the multi-core processor via a system bus, wherein the independent core memory corresponds to the independent core, and the main core memory corresponds to the main core.

5. The multi-core processor architecture according to claim 2, wherein: The architecture further includes a shared memory electrically connected to a main memory controller of the multi-core processor via a system bus, wherein the shared memory is configured to be accessed by the independent cores and the main core.

6. The multi-core processor architecture according to any one of claims 1 to 5, characterized in that: There are multiple independent cores, multiple first internal buses and multiple first input and output units, and the independent cores, first internal buses, and first input and output units are arranged in a one-to-one correspondence.

7. A vehicle control system, characterized in that: The multi-core processor architecture comprises a detection module, an emergency interrupt source, a normal interrupt source, a braking module, a prompt module, and the multi-core processor architecture according to any one of claims 1 to 6, wherein the detection module is configured to detect vehicle environment information and / or vehicle operation information; when the detection module detects that a preset emergency braking condition is met, the emergency interrupt source sends an emergency interrupt request to an independent core of the multi-core processor architecture, and the independent core then sends a braking instruction to the braking module through its corresponding first input and output unit; When the detection module detects that the preset normal interrupt condition is met, the normal interrupt source sends a normal interrupt request to the system interrupt processing unit of the multi-core processor architecture, and then the main core of the multi-core processor architecture sends instructions to the braking module and / or prompt module through its corresponding second input and output unit.

8. A means of transport, characterized in that: Comprising the vehicle control system as claimed in claim 7.

9. An interrupt handling method based on a multi-core processor architecture according to any one of claims 1 to 6, characterized in that: The following steps are involved: Pre-dividing the cores of the multi-core processor into independent cores and main cores, physically isolating the independent cores from the main core, and configuring exclusive interrupt signal lines for the independent cores; Connecting an emergency interrupt source outside the processor to the dedicated interrupt signal line, and connecting a common interrupt source outside the processor to the system interrupt processing unit of the multi-core processor architecture; If the emergency interrupt source issues an interrupt request, the independent core executes an interrupt program; If the common interrupt source issues an interrupt request, the system interrupt processing unit controls the main core to execute the interrupt program.

10. The interrupt processing method according to claim 9, characterized in that: Also includes: Preset shared cache; If the independent core analyzes that the interrupt request of the emergency interrupt source includes an emergency interrupt task and a non-emergency interrupt task, the independent core completes the emergency interrupt task and stores the non-emergency interrupt task in the shared cache; The shared cache transmits the non-urgent interrupt task to the system interrupt processing unit via an inter-core interrupt signal line, and then the system interrupt processing unit controls the main core to complete the non-urgent interrupt task.

11. The interrupt processing method according to claim 9, wherein: The system interrupt processing unit controls the main core to execute the interrupt program, including: The system interrupt processing unit generates a plurality of interrupt tasks according to the interrupt request of the common interrupt source; The system interrupt processing unit distributes the plurality of interrupt tasks to a plurality of main cores.

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