An enhanced lateral trench gate gallium oxide MOS device and its preparation method

Abstract

The present invention discloses an enhanced lateral trench gate gallium oxide MOS device and a preparation method thereof, which relates to the field of semiconductor technology. From bottom to top, an Fe-doped semi-insulating substrate, an unintentionally doped UID layer and a Si-doped track layer are sequentially arranged; both sides of the Si-doped track layer are arranged with n+ source regions, and the upper part of the n+ source region is arranged with source metal and drain metal; the bottom of the Si-doped track layer is arranged with a p-type channel control region, and the gate dielectric groove, insulating dielectric and gate metal located on the surface of the Si-doped track layer are arranged directly above the p-type channel control region. By adopting a lateral trench gate structure, the control ability of the gate is significantly improved, the substrate leakage of the device is reduced, and the electrical stability and energy efficiency of the device are improved. The p-type channel control region is constructed below the Si-doped track layer, which further reduces the on-resistance caused by the trench gate structure and increases the on-state current.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an enhanced lateral trench gate gallium oxide MOS device and a preparation method thereof. Background Art

[0002] In today's power electronics market, gallium oxide (GaN) materials have become the preferred material for manufacturing high-efficiency power devices due to their excellent electrical properties, such as high electron mobility and wide bandgap. Traditional GaN MOS devices usually adopt a vertical structure in which the current flows perpendicular to the substrate. However, devices with this structure face some difficulties in manufacturing and integration, especially in high-voltage applications. In addition, the gate control capability of traditional GaN MOS devices is limited, which makes it impossible to effectively adjust the switching characteristics of the device, thereby limiting its performance in high-frequency and high-efficiency applications.

[0003] Disadvantages of existing technology:

[0004] Limited gate control capability: The gate control capability of traditional GaN MOS devices is insufficient, which affects the switching speed and efficiency of the device.

[0005] Substrate leakage problem: During high voltage operation, substrate leakage, which is common in traditional GaN MOS devices, increases power losses and reduces the energy efficiency of the overall device.

[0006] Manufacturing complexity: Vertically structured devices are more complex to manufacture and integrate than horizontally structured devices, increasing production costs and technical challenges.

[0007] High on-resistance: Due to the limitation of the gate control layer, the on-resistance of traditional devices is relatively high, which limits their performance in high-current applications. Summary of the invention

[0008] In view of the deficiencies in the prior art, the present invention provides an enhanced lateral trench gate gallium oxide MOS device and a method for preparing the same to solve the problems raised in the above background technology.

[0009] To achieve the above object, the present invention provides the following technical solution: an enhanced lateral trench gate gallium oxide MOS device, comprising an Fe-doped semi-insulating substrate, the Fe-doped semi-insulating substrate is located at the bottom of the device, an unintentionally doped UID layer is arranged above the Fe-doped semi-insulating substrate, and a Si-doped track layer is arranged above the unintentionally doped UID layer;

[0010] Both sides of the Si-doped track layer are provided with n+ source regions, a source metal is provided above the n+ source region on one side of the Si-doped track layer, and a drain metal is provided above the n+ source region on the other side of the Si-doped track layer;

[0011] A p-type channel control region is arranged at the bottom of the Si-doped track layer, a gate dielectric groove is arranged directly above the p-type channel control region and is located on the surface of the Si-doped track layer, an insulating medium is arranged on the inner surface of the gate dielectric groove and the upper surface of the Si-doped track layer, and a gate metal is arranged inside the gate dielectric groove.

[0012] To further optimize the technical solution, the thickness of the Fe-doped semi-insulating substrate is 2 μm, the thickness of the unintentionally doped UID layer is 300 nm, the thickness of the p-type channel control region is 50 nm, the thickness of the Si-doped track layer is 300 nm, the thickness of the n+ source region is 250 nm, the thickness of the insulating medium at the bottom of the inner surface of the gate dielectric groove is 30 nm, and the thickness of the insulating medium on the inner wall of the gate dielectric groove is 20 nm.

[0013] Further optimizing the technical solution, the doping concentration of the unintentionally doped UID layer is 2×10 17 cm -3 The doping concentration of the p-type channel control region is 8×10 17 cm -3 The doping concentration of the Si-doped orbital layer is 1×10 17 cm -3 The doping concentration of the n+ source region is 8×10 17 cm -3 .

[0014] To further optimize the technical solution, the n+ source region, the source metal and the drain metal all adopt a Ti-Au double-layer metal structure, the gate metal is a Ni material, and the insulating medium is an aluminum oxide material.

[0015] To further optimize the technical solution, the p-type doping in the p-type channel control region and the Si doping in the Si-doped track layer form a pn junction to constitute a space charge region of the device.

[0016] A method for preparing an enhanced lateral trench gate gallium oxide MOS device is prepared based on the above-mentioned enhanced lateral trench gate gallium oxide MOS device, comprising the following steps:

[0017] S1, growing an unintentionally doped UID layer on an Fe-doped semi-insulating substrate by hydride vapor phase epitaxy;

[0018] S2, epitaxially growing a Si-doped track layer on the unintentionally doped UID layer by MOCVD;

[0019] S3, depositing a barrier layer on the Si-doped track layer, etching a through hole in the p-type channel control region, and implanting Mg ions into the Si-doped track layer, with an ion implantation energy of 85-100 keV;

[0020] S4, removing the barrier layer formed in step S3, depositing a new barrier layer on the Si-doped track layer, etching a through hole in the n+ source region, and implanting Si ions into the Si-doped track layer, with an ion implantation energy of 10-85kev;

[0021] S5, etching source metal and drain metal through holes on the barrier layer in step S4, and using magnetron sputtering along the through holes, in an argon atmosphere, high voltage produces glow discharge on the argon gas, which hits the Ti metal target material, causing it to splash and deposit on the upper surface of the device. The sputtering time is 5 minutes. After 5 minutes, the Ti metal target material is replaced with an Au metal target material, and the sputtering time is 1 minute;

[0022] S6, removing the barrier layer in step S4, re-depositing a new barrier layer on the source metal and the drain metal, etching out the insulating dielectric region, gasifying the aluminum metal organic matter at 1200° C., and then introducing the metal organic matter into the square gallium oxide material reaction chamber together with carrier gas and oxygen to cause a chemical reaction, and the reaction product is deposited on the upper surface of the device to form an aluminum oxide film;

[0023] S7, removing the barrier layer in step S4, re-depositing a new barrier layer, etching a through hole in the trench gate area, etching the insulating dielectric and gallium oxide to form a trench gate structure, first etching the insulating dielectric along the through hole, and after etching the insulating dielectric, etching gallium oxide along the gate through hole to form a gate dielectric groove, and depositing insulating dielectric aluminum oxide in the trench gate structure;

[0024] S8, removing the barrier layer in step S7, depositing a new barrier layer, etching out a gate metal region, and depositing gate metal.

[0025] The technical solution is further optimized. In step S1, the growth conditions are 900°C, the molar fraction of GaCl is 0.5; the intake speed of O2 is 0.03m / s; the molar fraction of O2 is 0.5; the intake speed of the separation gas N2 is 2.8m / s; and the distance between the Fe-doped semi-insulating substrate and the nozzle is 15cm.

[0026] To further optimize the technical solution, in step S2, under the growth condition of 860° C., triethylgallium is used as the organic source, high-purity oxygen is used as the oxygen source as the reaction source, SiH4 is used as the doped Si source, and high-purity argon is used as the carrier gas for the organic source and the doping gas.

[0027] To further optimize the technical solution, in step S7, the insulating medium is etched by wet etching, using a mixed solution of hydrogen peroxide and nitric acid, the hydrogen peroxide solution has a hydrogen peroxide content of 30%, the nitric acid solution has a content of 45%, and the ratio of the hydrogen peroxide solution to the nitric acid mixed solution is 3:4.

[0028] To further optimize the technical solution, in step S7, gallium oxide is etched by dry etching, the radio frequency power is 600 W, the chamber pressure is 1.5 Pa, the etching gas is sulfur hexafluoride and argon, and the flow ratio is 2:1.

[0029] Compared with the prior art, the present invention provides an enhanced lateral trench gate gallium oxide MOS device and a preparation method thereof, which has the following beneficial effects:

[0030] The enhanced lateral trench gate gallium oxide MOS device and its preparation method, by adopting a lateral trench gate structure, significantly improve the control capability of the gate, achieve higher switching speed and lower on-resistance; the Fe-doped semi-insulating substrate significantly reduces the substrate leakage of the device, and improves the electrical stability and energy efficiency of the device; the device structure simplifies the manufacturing process and reduces production costs, and by constructing a p-type channel control region under the Si-doped track layer, the on-resistance caused by the trench gate structure is further reduced, and the on-state current is increased, making the device more suitable for high current and high frequency application scenarios, thereby providing a more efficient and high-performance power electronic device solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic cross-sectional view of an enhanced lateral trench gate gallium oxide MOS device proposed by the present invention;

[0032] Figure 2 A schematic cross-sectional view of a device in step S1 of a method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed in the present invention;

[0033] Figure 3 A schematic cross-sectional view of a device in step S2 of a method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed in the present invention;

[0034] Figure 4 A schematic cross-sectional view of a device in step S3 of a method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed in the present invention;

[0035] Figure 5 A schematic cross-sectional view of a device in step S4 of a method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed in the present invention;

[0036] Figure 6A schematic cross-sectional view of a device in step S5 of a method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed in the present invention;

[0037] Figure 7 A schematic cross-sectional view of a device in step S6 of a method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed in the present invention;

[0038] Figure 8 A schematic cross-sectional view of a device in step S7 of a method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed in the present invention;

[0039] Fig. 9 The device cross-sectional diagram of step S8 in the method for preparing an enhanced lateral trench gate gallium oxide MOS device proposed by the present invention.

[0040] In the figure: 1. Fe-doped semi-insulating substrate; 2. Unintentionally doped UID layer; 3. Si-doped track layer; 4. n+ source region; 5. Source metal; 6. Drain metal; 7. P-type channel control region; 8. Insulating dielectric; 9. Gate metal. DETAILED DESCRIPTION

[0041] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Embodiment 1:

[0042] See also Figure 1 , an enhanced lateral trench gate gallium oxide MOS device, comprising an Fe-doped semi-insulating substrate 1, wherein the Fe-doped semi-insulating substrate 1 is located at the bottom of the device, an unintentionally doped UID layer 2 is arranged above the Fe-doped semi-insulating substrate 1, and a Si-doped track layer 3 is arranged above the unintentionally doped UID layer 2.

[0043] The Si-doped track layer 3 is provided with n+ source regions 4 on both sides, a source metal 5 is provided above the n+ source region 4 on one side of the Si-doped track layer 3 , and a drain metal 6 is provided above the n+ source region 4 on the other side of the Si-doped track layer 3 .

[0044] A p-type channel control region 7 is provided at the bottom of the Si-doped track layer 3, a gate dielectric groove is provided directly above the p-type channel control region 7 and is located on the surface of the Si-doped track layer 3, an insulating medium 8 is provided on the inner surface of the gate dielectric groove and the upper surface of the Si-doped track layer 3, and a gate metal 9 is provided inside the gate dielectric groove.

[0045] In this embodiment, the Fe-doped semi-insulating substrate 1 of the device is to achieve the support of the device to complete the subsequent process and reduce the substrate leakage of the device. The unintentionally doped UID layer 2 of the device is a buffer layer for the device substrate and structure, which prevents the defects of the device substrate from being introduced into the Si-doped track layer 3. The Si-doped track layer 3 is the gate-controlled conductive structure of the device, and its doping concentration is a compromise between the withstand voltage capability and the on-resistance. The n+ source region 4 is to form a low-resistance ohmic contact with the source metal 5 and the drain metal 6 and reduce the low resistance of the device from the source (and drain) to the device gate-controlled conductive channel, thereby reducing the overall on-resistance of the device.

[0046] Among them, the thickness of the Fe-doped semi-insulating substrate 1 is 2μm, the thickness of the unintentionally doped UID layer 2 is 300nm, the thickness of the p-type channel control region 7 is 50nm, the thickness of the Si-doped track layer 3 is 300nm, the thickness of the n+ source region 4 is 250nm, the thickness of the insulating medium 8 at the bottom of the inner surface of the gate dielectric groove is 30nm, and the thickness of the insulating medium 8 on the inner wall of the gate dielectric groove is 20nm.

[0047] The doping concentration of the unintentionally doped UID layer 2 is 2×10 17 cm -3 The doping concentration of the p-type channel control region 7 is 8×10 17 cm -3 The doping concentration of the Si-doped orbital layer 3 is 1×10 17 cm -3 The doping concentration of the n+ source region 4 is 8×10 17 cm -3 .

[0048] The device adopts a trench gate structure to form an enhanced device structure by thinning the conductive channel of the device, so that the device gate can realize the device shutdown when no voltage is applied, but this will make the conductive channel thickness of the device tens of nm, increase the on-resistance of the device, and affect the device characteristics. At the same time, based on the trench gate, a p-type channel control region 7 is constructed at the bottom of the Si-doped track layer 3 just below the gate. The p-type doping in this region and the Si-doped n-type region form a pn junction to construct a space charge region. There are no movable carriers in the space charge region and it cannot conduct electricity. Therefore, when no voltage is applied to the device gate, the device is turned off and cannot conduct electricity. When a positive voltage is applied to the device gate, the space charge region is compressed, widening the conductive channel of the device, reducing the on-resistance of the device caused by the trench gate, thereby increasing the on-state current of the device and reducing the on-resistance of the device.

[0049] In this embodiment, the n+ source region 4, source metal 5 and drain metal 6 all adopt a Ti-Au double-layer metal structure. This is because the work function difference between Ti metal and gallium oxide is small, and it is easier to form an ohmic contact. Au is used to perform anti-oxidation treatment on the surface of the device. The gate metal 9 is selected to improve the high temperature resistance of the device gate.

[0050] In this embodiment, the gate metal 9 is made of Ni material, and the insulating medium 8 is made of aluminum oxide material.

[0051] In this embodiment, the p-type doping in the p-type channel control region 7 and the Si doping in the Si-doped track layer 3 form a pn junction, constituting a space charge region of the device. Embodiment 2:

[0052] A method for preparing an enhanced lateral trench gate gallium oxide MOS device is prepared based on the enhanced lateral trench gate gallium oxide MOS device described in Embodiment 1, comprising the following steps:

[0053] S1, such as Figure 2 As shown, a non-intentionally doped UID layer 2 is grown on a Fe-doped semi-insulating substrate 1 by using a hydride vapor phase epitaxy method;

[0054] The growth conditions are 900°C, the molar fraction of GaCl is 0.5; the gas inlet velocity of O2 is 0.03 m / s; the molar fraction of O2 is 0.5; the gas inlet velocity of the separation gas N2 is 2.8 m / s; the distance between the Fe-doped semi-insulating substrate 1 and the nozzle is 15 cm;

[0055] S2, such as Figure 3 As shown, a Si-doped track layer 3 is epitaxially grown on the unintentionally doped UID layer 2 by MOCVD method;

[0056] Under the growth condition of 860°C, triethylgallium (TEGa) was used as the organic source, high-purity oxygen (6N) was used as the oxygen source as the reaction source, SiH4 was used as the doping Si source, and high-purity argon (6N) was used as the carrier gas for the organic source and the doping gas;

[0057] S3, such as Figure 4 As shown, a barrier layer is deposited on the Si-doped track layer 3, a through hole of the p-type channel control region 7 is etched, and Mg ions are implanted into the Si-doped track layer 3, and the ion implantation energy is 85-100kev;

[0058] S4, such as Figure 5 As shown, the barrier layer formed in step S3 is removed, a new barrier layer is deposited on the Si-doped track layer 3, a through hole of the n+ source region 4 is etched, and Si ions are implanted into the Si-doped track layer 3, and the ion implantation energy is 10-85kev;

[0059] S5, such as Figure 6 As shown, on the barrier layer in step S4, source metal 5 and drain metal 6 through holes are etched, and magnetron sputtering is used along the through holes. In an argon atmosphere, high voltage (1000V-1200V) generates glow discharge on the argon gas, which impacts the Ti metal target material, causing it to splash and deposit on the upper surface of the device. The sputtering time is 5 minutes. After 5 minutes, the Ti metal target material is replaced with an Au metal target material, and the sputtering time is 1 minute.

[0060] S6, such as Figure 7 As shown, the barrier layer in step S4 is removed, a new barrier layer is re-deposited on the source metal 5 and the drain metal 6, and the insulating dielectric 8 region is etched out. The metal organic matter of aluminum is gasified at 1200° C. (in order to increase the deposition rate of aluminum oxide), and then introduced into the square gallium oxide material reaction chamber together with a carrier gas (generally argon gas) and oxygen (the ratio of the metal organic matter of aluminum to oxygen is 1:1), a chemical reaction occurs, and the reaction product is deposited on the upper surface of the device to form an aluminum oxide film;

[0061] S7, such as Figure 8 As shown, the barrier layer in step S4 is removed, a new barrier layer is re-deposited, a through hole in the trench gate area is etched, the insulating dielectric 8 and gallium oxide are etched to form a trench gate structure, the insulating dielectric 8 is first etched along the through hole, and the insulating dielectric 8 is etched by wet etching, using a mixed solution of hydrogen peroxide and nitric acid, the hydrogen peroxide content of the hydrogen peroxide solution is 30%, the content of the nitric acid solution is 45%, and the ratio of the hydrogen peroxide solution to the nitric acid mixed solution is 3:4; after etching the insulating dielectric 8, gallium oxide is etched along the gate through hole to form a gate dielectric groove, and the etching of gallium oxide is dry etching, the radio frequency power is 600W, the chamber pressure is 1.5Pa, the etching gas is sulfur hexafluoride and argon, and the flow ratio is 2:1; the insulating dielectric 8 aluminum oxide is deposited in the trench gate structure, and the deposition process is consistent with step S6, and the temperature is 800°C, which is to ensure the deposition quality;

[0062] S8, such as Fig. 9 As shown, the barrier layer in step S7 is removed, a new barrier layer is deposited, the gate metal 9 region is etched out, and the gate metal 9 is deposited.

[0063] The beneficial effects of the present invention are:

[0064] The enhanced lateral trench gate gallium oxide MOS device and its preparation method, by adopting a lateral trench gate structure, significantly improve the control capability of the gate, achieve higher switching speed and lower on-resistance; the Fe-doped semi-insulating substrate significantly reduces the substrate leakage of the device, and improves the electrical stability and energy efficiency of the device; the device structure simplifies the manufacturing process and reduces production costs, and by constructing a p-type channel control region under the Si-doped track layer, the on-resistance caused by the trench gate structure is further reduced, and the on-state current is increased, making the device more suitable for high current and high frequency application scenarios, thereby providing a more efficient and high-performance power electronic device solution.

[0065] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0066] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An enhanced lateral trench gate gallium oxide MOS device, characterized in that: It comprises an Fe-doped semi-insulating substrate, wherein the Fe-doped semi-insulating substrate is located at the bottom of the device, an unintentionally doped UID layer is arranged above the Fe-doped semi-insulating substrate, and a Si-doped track layer is arranged above the unintentionally doped UID layer; Both sides of the Si-doped track layer are provided with n+ source regions, a source metal is provided above the n+ source region on one side of the Si-doped track layer, and a drain metal is provided above the n+ source region on the other side of the Si-doped track layer; A p-type channel control region is provided at the bottom of the Si-doped track layer, a gate dielectric groove is provided directly above the p-type channel control region and is located on the surface of the Si-doped track layer, an insulating dielectric is provided on the inner surface of the gate dielectric groove and the upper surface of the Si-doped track layer, and a gate metal is provided inside the gate dielectric groove; The n+ source region, source metal and drain metal all adopt a Ti-Au double-layer metal structure, the gate metal is Ni material, and the insulating medium is aluminum oxide material; The p-type doping in the p-type channel control region and the Si doping in the Si-doped track layer form a pn junction to constitute a space charge region of the device; The thickness of the Fe-doped semi-insulating substrate is 2 μm, the thickness of the unintentionally doped UID layer is 300 nm, the thickness of the p-type channel control region is 50 nm, the thickness of the Si-doped track layer is 300 nm, the thickness of the n+ source region is 250 nm, the thickness of the insulating medium at the bottom of the inner surface of the gate dielectric groove is 30 nm, and the thickness of the insulating medium on the inner wall of the gate dielectric groove is 20 nm; The doping concentration of the unintentionally doped UID layer is 2×10 17 cm -3 The doping concentration of the p-type channel control region is 8×10 17 cm -3 The doping concentration of the Si-doped orbital layer is 1×10 17 cm -3 The doping concentration of the n+ source region is 8×10 17 cm -3 .

2. A method for preparing an enhanced lateral trench gate gallium oxide MOS device, based on the enhanced lateral trench gate gallium oxide MOS device according to claim 1, characterized in that: The following steps are involved: S1, growing an unintentionally doped UID layer on an Fe-doped semi-insulating substrate by hydride vapor phase epitaxy; S2, epitaxially growing a Si-doped track layer on the unintentionally doped UID layer by MOCVD; S3, depositing a barrier layer on the Si-doped track layer, etching a through hole in the p-type channel control region, and implanting Mg ions into the Si-doped track layer, with an ion implantation energy of 85-100 keV; S4, removing the barrier layer formed in step S3, depositing a new barrier layer on the Si-doped track layer, etching a through hole in the n+ source region, and implanting Si ions into the Si-doped track layer, with an ion implantation energy of 10-85kev; S5, etching source metal and drain metal through holes on the barrier layer in step S4, and using magnetron sputtering along the through holes, in an argon atmosphere, high voltage produces glow discharge on the argon gas, which hits the Ti metal target material, causing it to splash and deposit on the upper surface of the device. The sputtering time is 5 minutes. After 5 minutes, the Ti metal target material is replaced with an Au metal target material, and the sputtering time is 1 minute; S6, removing the barrier layer in step S4, re-depositing a new barrier layer on the source metal and the drain metal, etching out the insulating dielectric region, gasifying the aluminum metal organic matter at 1200° C., and then introducing the metal organic matter into the square gallium oxide material reaction chamber together with carrier gas and oxygen to cause a chemical reaction, and the reaction product is deposited on the upper surface of the device to form an aluminum oxide film; S7, removing the barrier layer in step S6, re-depositing a new barrier layer, etching a through hole in the trench gate area, etching the insulating dielectric and gallium oxide to form a trench gate structure, first etching the insulating dielectric along the through hole, and after etching the insulating dielectric, etching gallium oxide along the gate through hole to form a gate dielectric groove, and depositing insulating dielectric aluminum oxide in the trench gate structure; S8, removing the barrier layer in step S7, depositing a new barrier layer, etching out a gate metal region, and depositing gate metal.

3. The method for preparing an enhanced lateral trench gate gallium oxide MOS device according to claim 2, characterized in that: In step S1, the growth conditions are 900° C., the molar fraction of GaCl is 0.5; the intake speed of O2 is 0.03 m / s; the molar fraction of O2 is 0.5; the intake speed of the separation gas N2 is 2.8 m / s; and the distance between the Fe-doped semi-insulating substrate and the nozzle is 15 cm.

4. The method for preparing an enhanced lateral trench gate gallium oxide MOS device according to claim 2, characterized in that: In the step S2, under the growth condition of 860° C., triethylgallium is used as the organic source, high-purity oxygen is used as the oxygen source as the reaction source, SiH4 is used as the doped Si source, and high-purity argon is used as the carrier gas for the organic source and the doping gas.

5. The method for preparing an enhanced lateral trench gate gallium oxide MOS device according to claim 2, characterized in that: In the step S7, the insulating medium is etched by wet etching, using a mixed solution of hydrogen peroxide and nitric acid, the hydrogen peroxide solution has a hydrogen peroxide content of 30%, the nitric acid solution has a content of 45%, and the ratio of the hydrogen peroxide solution to the nitric acid mixed solution is 3:

4.

6. The method for preparing an enhanced lateral trench gate gallium oxide MOS device according to claim 2, characterized in that: In the step S7, gallium oxide is etched by dry etching, the radio frequency power is 600 W, the chamber pressure is 1.5 Pa, the etching gas is sulfur hexafluoride and argon, and the flow ratio is 2:1.

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