Mask and method for forming the same
By adjusting the light shading rate of the marking area on the mask plate, the problem of blurring the bit pattern in semiconductor device manufacturing is solved, and a clear bit pattern is formed on a small-sized process platform is realized, and the manufacturing cost of the mask plate is reduced.
Patent Information
- Application Number
- CN202411415184.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-03-21
- Estimated Expiration
- 2044-10-11
AI Technical Summary
During the manufacturing process of semiconductor devices, the alignment patterns caused by the alignment marks laid on the mask plate become increasingly blurred during the lithography process, especially on small-sized process platforms such as 55nm, 40nm and 28nm. How to form clear alignment patterns is an urgent problem to be solved.
A mask plate is provided, including a transparent substrate and a mask pattern layer, including a chip region for forming a device structure and a marker region for forming a counter-bit pattern. The light shielding rate of the marking area is determined based on the line width of its layout pattern. When the line width is less than the threshold, the light shielding rate is greater than 0 and less than 1, thereby reducing the influence of diffracted light, improving contrast, and ensuring the clarity of the bit pattern.
By adjusting the light shading rate of the marking area, reducing the influence of diffraction light, and improving the contrast of the counter-bit patterns on the photoresist, thus forming a clear counter-bit patterns on the semiconductor substrate, solving the problem of blurring counter-bit patterns on small-sized process platforms and saving the manufacturing cost of the mask plate.
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Figure CN118915377B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a mask and a method for forming the mask. Background Art
[0002] In the process of integrated circuit manufacturing, in order to ensure the quality of semiconductor devices, the overlay accuracy between different film layers needs to be guaranteed. Therefore, a mask with an overlay mark is required to form an overlay pattern with a film layer on the semiconductor substrate for subsequent film layers to align. As the process requirements of semiconductor devices become higher and higher, the line width of the layout pattern on the mask is getting smaller and smaller, and the holes exposed by the mask on the photoresist during the photolithography process are becoming more and more blurred, and then the overlay pattern formed by the overlay mark set on the mask is also becoming more and more blurred, such as the 55nm, 40nm and 28nm process platforms. How to form a clear overlay pattern on the semiconductor substrate based on the overlay mark has become an urgent problem to be solved. Summary of the invention
[0003] In view of the above problems, the purpose of the present application is to provide a mask and a method for forming the same, so as to ensure that a clear alignment pattern can be formed on a semiconductor substrate based on the alignment marks on the mask.
[0004] According to a first aspect of the present invention, there is provided a mask, comprising:
[0005] Transparent substrate;
[0006] A mask pattern layer, located on the surface of the transparent substrate, including a chip area for forming a device structure and a mark area arranged outside the chip area for forming an alignment pattern;
[0007] The shading rate of the marking area is determined according to the line width of the pattern laid out in the marking area, and the shading rate of the marking area is greater than 0 and less than 1 when the line width of the pattern laid out in the marking area is less than a threshold.
[0008] Optionally, when the line width of the layout pattern of the marking area is not less than the threshold, the shading rate of the marking area is equal to 1.
[0009] Optionally, when the line width of the layout pattern of the marking area is smaller than the threshold, the mask pattern layer includes a first mask layer and the layout pattern of the marking area is formed through the first mask layer;
[0010] When the line width of the layout pattern of the marking area is not less than the threshold, the mask pattern layer includes a second mask layer and the layout pattern of the marking area is formed by the second mask layer;
[0011] The light shielding rate of the first mask layer is greater than 0 and less than 1, and the light shielding rate of the second mask layer is equal to 1.
[0012] Optionally, a line width of a layout pattern of the chip region is smaller than the threshold value, and the layout pattern of the chip region is formed by the first mask layer.
[0013] Optionally, the marking area forms an alignment pattern through an alignment mark located therein, and a boundary of the marking area does not overlap with a boundary of the alignment mark.
[0014] Optionally, the size of the marking area is 2um-4um larger than the size of the alignment mark.
[0015] Optionally, the mask includes a plurality of chip areas.
[0016] Optionally, a cutting street area exists between adjacent chip areas on the mask, and the marking area is located in the cutting street area.
[0017] According to a second aspect of the present invention, there is provided a method for forming a mask, comprising:
[0018] Providing a transparent substrate;
[0019] Forming a mask pattern layer on the surface of the transparent substrate, wherein the mask pattern layer includes a chip area for forming a device structure and a mark area for forming an alignment pattern arranged outside the chip area;
[0020] The shading rate of the marking area is determined according to the line width of the pattern laid out in the marking area, and the shading rate of the marking area is greater than 0 and less than 1 when the line width of the pattern laid out in the marking area is less than a threshold.
[0021] Optionally, a mask pattern layer is formed on the surface of the transparent substrate based on the layout design drawing;
[0022] The marking area forms an alignment pattern through an alignment mark located therein;
[0023] The mark area is determined on the layout design drawing by an auxiliary frame, and the size of the auxiliary frame is larger than the size of the alignment mark.
[0024] The unexpected technical effects of this application are:
[0025] According to the mask plate of the embodiment of the present application, it includes a transparent substrate and a mask pattern layer located on the surface of the transparent substrate, the mask pattern layer includes a chip area for forming a device structure and a mark area arranged outside the chip area for forming an alignment pattern, wherein the shading rate of the mark area is determined according to the line width of the pattern laid out in the mark area, and when the line width of the pattern laid out in the mark area is less than a threshold, the shading rate of the mark area is greater than 0 and less than 1, so that the stronger diffraction light energy occurring at the edge of the layout pattern with a smaller line width in the mark area can be offset by the light transmitted through the mark area, thereby reducing the proximity effect and improving the contrast of the spatial image exposed by the mark area on the photoresist, so that a clear alignment pattern can be formed on the semiconductor substrate based on the alignment mark in the mark area.
[0026] Further, according to the mask of the embodiment of the present application, when the line width of the layout pattern of the marking area is less than a threshold value, the mask pattern layer includes a first mask layer and the marking area forms the layout pattern through the first mask layer; when the line width of the layout pattern of the marking area is not less than the threshold value, the mask pattern layer includes a second mask layer and the marking area forms the layout pattern through the second mask layer, wherein the shading rate of the first mask layer is greater than 0 and less than 1, and the shading rate of the second mask layer is equal to 1, thereby flexibly changing the mask pattern layer to ensure that when the line width of the layout pattern of the marking area is reduced, a clear alignment pattern can be formed on the semiconductor substrate based on the alignment mark in the marking area, and there is no need to use the first mask layer to re-manufacture the mask for the marking area with a smaller line width of the layout pattern, which is beneficial to saving the mask cost in the semiconductor device manufacturing process.
[0027] Furthermore, the mask according to the embodiment of the present application includes a plurality of chip areas, so that a plurality of device structures can be exposed simultaneously in one exposure unit executed based on the mask, thereby saving exposure time. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:
[0029] Figure 1 A schematic cross-sectional view of a semiconductor device is shown;
[0030] Figure 2 A schematic diagram showing a method of forming an alignment pattern on a substrate based on a mask in the related art;
[0031] Figure 3 A schematic top view of a mask provided according to an embodiment of the present application is shown;
[0032] Figure 4 A schematic diagram showing a mask provided according to an embodiment of the present application forming an alignment pattern on a substrate;
[0033] Figure 5 A schematic diagram showing another mask provided according to an embodiment of the present application forming an alignment pattern on a substrate;
[0034] Figure 6 A flow chart of a method for forming a mask according to another embodiment of the present application is shown.
[0035] Explanation of the reference numerals: 100-semiconductor device; 101-semiconductor layer; 102-shallow trench structure; 103-source region; 104-drain region; 105-gate dielectric layer; 106-gate conductor; 107-interlayer dielectric layer; 111-connection channel; 112-connection channel; 121-wiring; 122-wiring; 11-transparent substrate; 12-mask pattern layer; 13-photoresist; 14-substrate; 15-alignment pattern; 16-wiring structure; 21-transparent substrate; 22-mask pattern layer; 22a-chip area; 22b-marking area; 22x-alignment mark; 221-first mask layer; 222-second mask layer; 23-photoresist; 24-substrate; 25-alignment pattern; 26-device structure; 27-alignment pattern. DETAILED DESCRIPTION
[0036] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.
[0037] This application may be presented in a variety of forms, some examples of which are described below.
[0038] Figure 1 A schematic cross-sectional view of a semiconductor device is shown. The semiconductor device 100 is, for example, a MOSFET (i.e., a metal oxide semiconductor field effect transistor), but is not limited thereto. In a preferred embodiment, the semiconductor device is, for example, an N-type MOSFET. For the sake of clarity, the interconnection structure and the main structure of the semiconductor device 100 are separated and shown in the figure along the vertical direction.
[0039] like Figure 1As shown, the semiconductor device 100 includes a semiconductor layer 101 and a shallow trench structure 102 located in the semiconductor layer 101. The semiconductor layer 101 can be composed of any one selected from a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. For example, for an N-type MOSFET, the semiconductor layer 101 is P-type doped; for a P-type MOSFET, the semiconductor layer 101 is N-type doped. The shallow trench structure 102 extends downward from the surface of the semiconductor layer 101 to form an isolation structure surrounding the active area of the semiconductor device 100, which is used to separate the semiconductor device 100 from adjacent semiconductor devices. The shallow trench structure 102 can be composed of any one selected from silicon oxide, silicon nitride, and silicon oxynitride.
[0040] Furthermore, the semiconductor device 100 includes a source region 103 and a drain region 104 located in the semiconductor layer 101, and a gate stack located above the semiconductor layer 101. The source region 103 and the drain region 104 are doped regions in the semiconductor layer 101. For example, for an N-type MOSFET, the source region 103 and the drain region 104 are N-type doped; for a P-type MOSFET, the source region 103 and the drain region 104 are P-type doped. The gate stack of the semiconductor device 100 includes a gate dielectric layer 105 and a gate conductor 106, and the gate dielectric layer 105 is sandwiched between the semiconductor layer 101 and the gate conductor 106. The gate dielectric layer 105 is, for example, composed of silicon oxide, and the gate conductor 106 is, for example, composed of doped polysilicon.
[0041] Further, the semiconductor device 100 includes an interlayer dielectric layer 107 located above the gate stack and the source region 103 and the drain region 104, and an interconnection structure connected to the gate stack and the source region 103 and the drain region 104. The interlayer dielectric layer 107 is composed of, for example, silicon oxide, and is used to isolate the active region of the semiconductor device 100 from the wiring layer. The interconnection structure of the semiconductor device 100 includes connection channels 111 and 112 that penetrate the interlayer dielectric layer 107, and a wiring layer located above the interlayer dielectric layer 107. For example, the wiring layer includes a wiring 121 connected to the connection channel 111 and a wiring 122 connected to the connection channel 112. The connection channels 111 and 112 and the wirings 121 and 122 can be composed of metal, such as copper, aluminum, etc.
[0042] The manufacturing process of the semiconductor device 100 includes a front-end process and a back-end process, wherein the front-end process includes thin film deposition, ion implantation and patterning, and is mainly used to form the source region 103, the drain region 104 and the gate stack of the semiconductor device 100; the back-end process includes thin film deposition and patterning, and is mainly used to form the interconnection structure of the semiconductor device 100, including the connection channels 111 and 112 and the wirings 121 and 122 of the semiconductor device 100. In order to ensure the quality of the semiconductor device 100, the source region 103 and the gate stack formed by the front-end process must be aligned with the channels 111 and 112 formed by the back-end process, and the channels 111 and 112 formed by the back-end process must also be aligned with the wirings 121 and 122 formed by the back-end process, so a mask with an alignment mark is required to form an alignment pattern on the semiconductor layer 101 through a patterning process for alignment of the film layer subsequently formed on the semiconductor layer 101.
[0043] Figure 2 The figure shows a schematic diagram of a mask plate based on the related art forming an alignment pattern in a semiconductor layer such as a substrate. Figure 2 A photoresist 13 is formed on the surface of a substrate 14. In the photolithography step, the photoresist 13 is exposed and developed based on a mask plate including a transparent substrate 11 and a mask pattern layer 12. Since the mask pattern layer 12 is laid out into a pattern by setting a light-transmitting area and a light-shielding area, the portion of the photoresist 13 corresponding to the light-transmitting area of the mask pattern layer 12 is removed and the remaining portion is retained, so that the photoresist 13 is patterned corresponding to the mask pattern layer 12. After that, an etching step is performed based on the patterned photoresist 13 to form an alignment pattern 15 corresponding to the light-transmitting area of the mask pattern layer 12 in the substrate 14.
[0044] As the process requirements of the semiconductor device 100 become higher and higher, the line width of the pattern laid out on the mask becomes smaller and smaller. The exposure wavelength of the existing process makes the holes exposed by the mask on the photoresist 13 in the photolithography process more and more blurred, and then the alignment pattern 15 formed on the substrate 14 corresponding to the alignment mark set on the mask also becomes more and more blurred. For example, Figure 2 The line width of the pattern laid out in the middle mask pattern layer 12 is smaller than the threshold value, and the strong diffraction light generated at the edge of the light-shielding area of the mask pattern layer 12 causes the portion of the photoresist 13 corresponding to the light-shielding area in the mask pattern layer 12 to be exposed, so that there is a connection structure 16 between the alignment patterns 15, and the alignment patterns 15 are no longer clear due to blurred edges. The above threshold value is a value related to the wavelength of light used for exposure during the photolithography process. If the line width of the pattern laid out in the mask pattern layer 12 is not smaller than the threshold value, there will be no connection structure 16 between the alignment patterns 15.
[0045] Therefore, how to form a clear alignment pattern based on the alignment mark on the mask has become an urgent problem to be solved in today's small-size process platforms such as 55nm, 40nm and 28nm. In view of this, an embodiment of the present application provides a mask.
[0046] Figure 3 FIG. 1 is a schematic diagram of the structure of the mask provided in the embodiment of the present application, referring to FIG. Figure 3 The mask plate includes a transparent substrate 21 and a mask pattern layer 22 located on the surface of the transparent substrate 21. The material of the transparent substrate 21 is, for example, quartz. The mask pattern layer 22 includes a chip area 22a for forming a device structure and a mark area 22b for forming an alignment pattern arranged outside the chip area 22a, wherein the light shielding rate of the mark area 22b is determined according to the line width of the pattern laid out by the mark area 22b, and the light shielding rate of the mark area 22b is greater than 0 and less than 1 when the line width of the pattern laid out by the mark area 22b is less than a threshold.
[0047] It should be understood that Figure 3 The chip area 22a is indicated by a rectangular frame, and the mark area 22b is indicated by a square frame. This is only for distinguishing two different areas of the mask pattern layer 22, and does not limit the shapes of the chip area 22a and the mark area 22b in this embodiment.
[0048] It should be noted that the mask pattern layer 22 is usually hollowed out in part to form a light-transmitting area corresponding to the hollowed-out area and the remaining area where the material is set. Therefore, the light shielding rate of the marking area 22b is greater than 0 and less than 1, which means that the light shielding rate of the material set in the marking area 22b is greater than 0 and less than 1, that is, different from Figure 2 The shading rate of the shading area of the mask pattern layer 12 in the mask plate shown is 100%. The mask plate provided in the embodiment of the present application sets the shading rate of the shading area in the mark area 22b to be greater than 0 and less than 1, so that the stronger diffraction light energy occurring at the edge of the layout pattern with a smaller line width in the mark area 22b can be offset by the light transmitted by the material set in the mark area 22b, thereby reducing the proximity effect and improving the contrast of the spatial image exposed by the mark area 22b on the photoresist, so that the part of the light-transmitting area corresponding to the mark area 22b on the photoresist is removed and the part of the shading area corresponding to the mark area 22b is completely retained, so that the alignment mark formed by the layout pattern of the mask pattern layer 22 can be accurately replicated on the photoresist, and then a clear alignment pattern is formed on the semiconductor layer based on the alignment mark in the mark area 22b.
[0049] In some examples, the mask can be Figure 3 As shown, multiple chip regions 22a are included, so that multiple device structures can be exposed simultaneously in one exposure unit based on the mask, thereby saving exposure time. Figure 3As shown, there is a cutting road area between adjacent chip areas 22a of the mask. After the semiconductor device is formed based on the mask, the cutting road area corresponds to the cutting road between the chips. The above-mentioned mark area 22b can be located in the cutting road area, thereby ensuring that the alignment pattern formed by the alignment mark in the mark area 22b does not affect the function of the formed chip.
[0050] The above-mentioned mark area 22b forms an alignment pattern through the alignment mark located therein, and the boundary of the mark area 22b may not overlap with the boundary of the alignment mark, so that it can be ensured that the light shielding area forming the alignment mark is completely located in the mark area 22b and has a light shielding rate greater than 0 and less than 1, thereby ensuring that the alignment mark can form a clear alignment pattern on the semiconductor layer. Exemplarily, the size of the mark area 22b is 2um-4um larger than the size of the alignment mark to ensure that the boundary of the mark area 22b does not overlap with the boundary of the alignment mark. Figure 3 The size of the dotted rectangular frame that inscribes the pre-designed alignment mark 22x can be identified as the size of the alignment mark 22x, and the solid rectangular frame that frames the dotted rectangular frame can be used as a pre-designed auxiliary frame to occupy the position on the mask plate and determine the mark area 22b indicated by the arrow, so that after the alignment mark 22x is formed on the mask plate, the size of the mark area 22b can be larger than the size of the alignment mark 22x.
[0051] Furthermore, in the mask provided in the embodiment of the present application, when the line width of the pattern laid out in the marking area 22b is not less than the threshold value, the light shielding rate of the marking area 22b is equal to 1. In the case where the mask pattern layer 22 is hollowed out by part of the area to form a light-transmitting area corresponding to the hollowed-out area and the remaining area where the material is set, the light shielding rate of the marking area 22b is equal to 1 here, which means that the light shielding rate of the material set in the marking area 22b is equal to 1, that is, the mask pattern layer 22 flexibly adjusts the material used in different marking areas 22b based on the line width of the pattern laid out in different marking areas 22b.
[0052] Figure 4 The figure shows a schematic diagram of a mask provided in an embodiment of the present application forming an alignment pattern on a semiconductor layer such as a substrate, where one side of the dotted line is a chip area included in the mask and the other side of the dotted line is a marking area included in the mask. Figure 4A photoresist 23 is formed on the surface of a substrate 24. In the photolithography step, the photoresist 23 is exposed and developed based on a mask plate including a transparent substrate 21 and a mask pattern layer 22. Since the mask pattern layer 22 lays out the pattern by setting a light-transmitting area and a light-shielding area, the portion of the photoresist 23 corresponding to the light-transmitting area of the mask pattern layer 22 is removed and the remaining portion is retained, so that the photoresist 23 is patterned corresponding to the mask pattern layer 22. Then, an etching step is performed based on the patterned photoresist 23 to form an alignment pattern 25 corresponding to the light-transmitting area of the mark area in the mask pattern layer 22 and a device structure 26 corresponding to the light-transmitting area of the chip area in the mask pattern layer 22 in the substrate 24.
[0053] Figure 4 The middle mask pattern layer 22 includes a first mask layer 221 and a second mask layer 222, the light shielding rate of the first mask layer 221 is greater than 0 and less than 1, and the light shielding rate of the second mask layer 222 is equal to 1. It should be noted that the first mask layer 221 and the second mask layer 222 can also be hollowed out in some areas to form a light-transmitting area corresponding to the hollowed-out area and the remaining areas where the material is set, so the light shielding rate of the first mask layer 221 is greater than 0 and less than 1, which means that the light shielding rate of the material set in the first mask layer 221 is greater than 0 and less than 1, and the light shielding rate of the second mask layer 222 is equal to 1, which means that the light shielding rate of the material set in the second mask layer 222 is equal to 1, and the material set in the second mask layer 222 is, for example, an opaque metal film layer.
[0054] Reference Figure 4 , the line width of the pattern laid out in the mark area in the mask is less than the threshold value, and the pattern is laid out in the mark area through the hollow area formed by the first mask layer 221, so that the alignment patterns 25 formed in the substrate 24 are no longer connected, that is, the alignment patterns 25 are clearer. In addition, Figure 4 In the example shown, the line width of the pattern laid out in the chip area is also smaller than the threshold value. The chip area is similar to the marking area and is also laid out through the hollow area formed by the first mask layer 221 , so the device structures 26 formed in the substrate 24 are not connected.
[0055] Figure 5 The figure shows another mask provided in an embodiment of the present application, which forms an alignment pattern on a semiconductor layer such as a substrate. Similarly, the dotted line side is the chip area included in the mask, and the other side of the dotted line is the mark area included in the mask. Figure 5A photoresist 23 is formed on the surface of a substrate 24. In the photolithography step, the photoresist 23 is exposed and developed based on a mask plate including a transparent substrate 21 and a mask pattern layer 22. Since the mask pattern layer 22 lays out the pattern by setting a light-transmitting area and a light-shielding area, the portion of the photoresist 23 corresponding to the light-transmitting area of the mask pattern layer 22 is removed and the remaining portion is retained, so that the photoresist 23 is patterned corresponding to the mask pattern layer 22. Then, an etching step is performed based on the patterned photoresist 23 to form an alignment pattern 27 corresponding to the light-transmitting area of the mark area in the mask pattern layer 22 and a device structure 26 corresponding to the light-transmitting area of the chip area in the mask pattern layer 22 in the substrate 24.
[0056] Compared to Figure 4 The mask shown, Figure 5 The line width of the layout pattern of the chip area in the mask is also smaller than the threshold value, so the chip area still forms the layout pattern through the first mask layer 221, so that the device structure 26 formed in the substrate 24 corresponding to the light-transmitting area of the chip area in the mask pattern layer 22 also has no connection problem. Figure 4 The masks shown differ in that Figure 5 The marking area in the mask plate shown in the figure is formed into the layout pattern through the second mask layer 222, but due to Figure 5 The line width of the layout pattern of the marking area in the mask is not less than the threshold value, so the alignment pattern 27 formed in the substrate 24 corresponding to the light-transmitting area of the marking area in the mask pattern layer 22 also does not have the problem of connection. Figure 5 In the mask shown in the figure, the chip area is formed into a layout pattern through the first mask layer 221, and the marking area is formed into a layout pattern through the second mask layer 222, so that the marking area is no longer Figure 4 As shown, the same mask layer is used as in the chip area to form the layout pattern.
[0057] It should be noted that Figure 5 When the marking area in the mask plate is laid out by the second mask layer 222, the edge of the marking area adjacent to the chip area may be formed by the first mask layer 221 because there is a chip area around the marking area where the line width of the laid out pattern is smaller than the threshold.
[0058] Combination Figure 4 and Figure 5When the line width of the layout pattern of the marking area is less than the threshold, the marking area forms the layout pattern through the first mask layer 221; when the line width of the layout pattern of the marking area is not less than the threshold, the marking area forms the layout pattern through the second mask layer 222. Therefore, if the mask plate includes multiple marking areas and the line width of the layout pattern of some of the marking areas is less than the threshold, the mask plate can ensure that when the line width of the layout pattern of the marking area is reduced to below the threshold, a clear alignment pattern 25 can be formed on the semiconductor substrate 24 based on the alignment mark in the marking area by flexibly changing the mask pattern layer 22. There is no need to use the first mask layer 221 to re-manufacture the mask plate for the marking area with a smaller line width of the layout pattern. Therefore, by setting the mask pattern layer 22 as a dynamic film layer, the mask plate cost in the semiconductor device manufacturing process can be saved.
[0059] It should be noted that the shading rate of the above-mentioned first mask layer 221 is greater than 0 and less than 1, which can be achieved by adopting a grid structure in the area where the material is set in the first mask layer 221, so the cost is relatively high. In this way, when the line width of the layout pattern in the marking area is not less than the threshold, the marking area forms the layout pattern through the second mask layer 222, which is beneficial to save the manufacturing cost of the mask.
[0060] Corresponding to the mask provided in the above embodiment, another embodiment of the present application provides a method for forming a mask. Figure 6 FIG. 1 is a flow chart of a method for forming a mask provided in an embodiment of the present application, referring to FIG. Figure 6 , the forming method comprises:
[0061] Step S110, providing a transparent substrate;
[0062] Step S120, forming a mask pattern layer on the surface of the transparent substrate, the mask pattern layer including a chip area for forming a device structure and a mark area outside the chip area for forming an alignment pattern, wherein a shading rate of the mark area is determined according to a line width of a pattern laid out in the mark area and the shading rate of the mark area is greater than 0 and less than 1 when the line width of the pattern laid out in the mark area is less than a threshold value.
[0063] Furthermore, in step S120, a mask pattern layer is formed on the surface of the transparent substrate. If the shading rate of the mark area included in the mask pattern layer is not less than a threshold value, the shading rate of the mark area is equal to 1.
[0064] Further, step S120 is to form a mask pattern layer on the surface of the transparent substrate based on the layout design drawing, and the mark area is determined by the auxiliary frame occupying the layout design drawing, and the size of the auxiliary frame is larger than the size of the alignment mark, so as to ensure that the light shielding area forming the alignment mark in the mask pattern layer is completely located in the mark area and has a light shielding rate greater than 0 and less than 1. Specifically, the mark area can be determined by the auxiliary frame participating in the Boolean logic operation and occupying the cutting road area designed in the layout design drawing, and then the alignment mark is designed in the auxiliary frame according to the coordinates of the auxiliary frame on the layout design drawing, and it is ensured that the boundary of the alignment mark and the boundary of the auxiliary frame do not overlap, so that the layout design drawing used in step S120 is formed.
[0065] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.
Claims
1. A mask, comprising: Transparent substrate; A mask pattern layer, located on the surface of the transparent substrate, including a chip area for forming a device structure and a mark area arranged outside the chip area for forming an alignment pattern; The shading rate of the marking area is determined according to the line width of the graphics laid out in the marking area. When the line width of the graphics laid out in the marking area is less than a threshold, the material set in the marking area achieves a shading rate greater than 0 and less than 1 by adopting a grid structure.
2. The mask according to claim 1, wherein: When the line width of the layout pattern of the marking area is not less than the threshold, the shading rate of the marking area is equal to 1.
3. The mask according to claim 2, wherein: When the line width of the layout pattern of the marking area is smaller than the threshold, the mask pattern layer includes a first mask layer and the layout pattern of the marking area is formed by the first mask layer; When the line width of the layout pattern of the marking area is not less than the threshold, the mask pattern layer includes a second mask layer and the layout pattern of the marking area is formed by the second mask layer; The light shielding rate of the first mask layer is greater than 0 and less than 1, and the light shielding rate of the second mask layer is equal to 1.
4. The mask according to claim 3, wherein: The line width of the layout pattern of the chip area is smaller than the threshold value, and the layout pattern of the chip area is formed through the first mask layer.
5. The mask according to claim 1, wherein: The marking area forms an alignment pattern through an alignment mark located therein, and the boundary of the marking area does not overlap with the boundary of the alignment mark.
6. The mask according to claim 5, wherein: The size of the marking area is 2um-4um larger than the size of the alignment mark.
7. The mask according to claim 1, wherein: The mask plate includes a plurality of chip areas.
8. The mask according to claim 7, wherein: The mask has a cutting street area between adjacent chip areas, and the mark area is located in the cutting street area.
9. A method for forming a mask, comprising: Providing a transparent substrate; Forming a mask pattern layer on the surface of the transparent substrate, wherein the mask pattern layer includes a chip area for forming a device structure and a mark area for forming an alignment pattern arranged outside the chip area; The shading rate of the marking area is determined according to the line width of the graphics laid out in the marking area. When the line width of the graphics laid out in the marking area is less than a threshold, the material set in the marking area achieves a shading rate greater than 0 and less than 1 by adopting a grid structure.
10. The method for forming a mask according to claim 9, wherein: forming a mask pattern layer on the surface of the transparent substrate based on the layout design drawing; The marking area forms an alignment pattern through an alignment mark located therein; The mark area is determined on the layout design drawing by an auxiliary frame, and the size of the auxiliary frame is larger than the size of the alignment mark.
Citation Information
Patent Citations
Photomask, method of producing photomask, and method of making pattern using photomask
CN1373861A