Data synchronization control method, device, storage medium and electronic device based on FPGA

Abstract

The present disclosure relates to the field of oscilloscope technology, and in particular to a data synchronization control method, device, storage medium and electronic device based on FPGA. The method is applied to an FPGA parallel sampling system, including: obtaining a control command signal set of multiple acquisition boards; synchronously processing the control command signal set based on a target processing board to obtain a synchronization signal package; synchronously sampling multiple acquisition boards based on the synchronization signal package to obtain sampling data; performing data processing on the waveform data in the sampling data to obtain multi-core pre-stored data; and synchronously storing or synchronously reading the multi-core pre-stored data based on the synchronization signal package and the external memory of the FPGA parallel sampling system. In this way, through synchronous control, the problems of data confusion and failure caused by asynchronization in the storage and reading process in the prior art are solved, and the demand for high-speed and large-capacity data storage is met.

Description

Technical Field

[0001] The present disclosure relates to the technical field of oscilloscopes, and in particular to a data synchronization control method, device, storage medium and electronic device based on FPGA. Background Art

[0002] In the context of the development of oscilloscope technology, in the face of the sharp increase in sampling rate and data storage depth requirements, modern oscilloscope sampling systems generally adopt the "multi-ADC (Analog-to-Digital Converter) + multi-FPGA (Field-Programmable Gate Array)" architecture design. The core of this architecture is to integrate multiple ADCs in parallel to improve the parallel efficiency of data acquisition, and then use multiple FPGAs to process these high-speed, high-precision analog-to-digital conversion data in parallel to achieve fast data caching and efficient processing.

[0003] Given the huge amount of data acquisition and the strict requirements on processing speed, this design poses severe challenges to the oscilloscope's storage system, especially highlighting the urgent need for high-performance, large-capacity storage solutions. Summary of the invention

[0004] The main purpose of the present disclosure is to provide a data synchronization control method, device, storage medium and electronic device based on FPGA. To achieve the above purpose, the present disclosure proposes a data synchronization control method based on FPGA, comprising:

[0005] Acquire a control command signal set of multiple acquisition boards, wherein the control command signal set includes a reset command signal, a read command signal, and a write command signal;

[0006] Performing synchronous processing on the control command signal set based on the target processing board to obtain a synchronous signal packet, wherein the synchronous signal packet includes a synchronous reset signal, a synchronous write signal and a synchronous read signal;

[0007] Performing synchronous sampling on multiple acquisition boards based on the synchronous signal packet to obtain sampling data;

[0008] Processing the waveform data in the sampled data to obtain multi-core pre-stored data after data processing;

[0009] Based on the synchronization signal package and the external memory of the FPGA parallel sampling system, a synchronous storage operation or a synchronous reading operation is performed on the multi-core pre-stored data.

[0010] Optionally, the target processing board performs synchronization processing on the control command signal set to obtain a synchronization signal packet, including:

[0011] sending the control command signal set to a target processing board;

[0012] Based on the synchronization control module of the target processing board, multiple reset command signals in the control command signal set are captured and processed along the falling edges to obtain a reset start flag; and

[0013] Capturing rising edge processing on a plurality of reset signals included in the control command signal set to obtain a reset end flag;

[0014] The reset start flag and the reset end flag are logically ANDed to obtain target synchronous reset signals corresponding to multiple reset command signals, so as to generate multiple synchronous reset signals through the target synchronous reset signal and send them to multiple acquisition boards for synchronous reset.

[0015] Optionally, before performing synchronous sampling on multiple acquisition boards based on the synchronous signal package to obtain sampled data, the method further includes:

[0016] In response to the synchronous reset signal, generating a first internal synchronous reset signal and a second internal synchronous reset signal according to the synchronous reset signal;

[0017] The first internal synchronous reset signal is sent to the sub-processing modules corresponding to the plurality of acquisition boards, so that the sub-processing modules are reset according to the first internal synchronous reset signal; wherein the sub-processing modules include a write data and bit width conversion module, an address generation module, an FSM state machine control module, and a read data and bit width conversion module; and

[0018] The second internal synchronous reset signal is sent to the MIG processing modules corresponding to the multiple MIG cores in the external memory, so that the multiple MIG cores are reset according to the second internal synchronous reset signal based on the MIG processing modules.

[0019] Optionally, resetting the multiple MIG cores based on the MIG processing module according to the second internal synchronous reset signal includes:

[0020] In response to the second internal synchronous reset signal, the plurality of MIG cores generate a write cache reset signal;

[0021] Obtaining the write cache reset signal and counting at the same time;

[0022] When a pre-designed value is reached, the write cache reset signal is released to synchronously reset multiple MIG cores.

[0023] Optionally, before the external memory based on the synchronization signal package and the FPGA parallel sampling system performs a synchronous storage operation or a synchronous reading operation on the multi-core pre-stored data, it also includes:

[0024] Performing asynchronous FIFO construction on the multiple MIG cores in the external memory to obtain the constructed multiple MIG cores;

[0025] Based on the built multiple MIG cores, the multi-core pre-stored data is converted across clock domains so that the multiple MIG cores share the same write enable signal at the same time;

[0026] Among them, each of the multiple MIG cores after construction includes a write asynchronous FIFO and a read asynchronous FIFO.

[0027] Optionally, performing cross-clock domain conversion on the multi-core pre-stored data based on the constructed multiple MIG cores includes:

[0028] Acquire a write operation instruction set, where the write operation instruction set is generated by the storage control module of the external memory according to the synchronous write signal, the write operation instruction set includes a write operation instruction corresponding to each MIG core in a plurality of MIG cores, and the write operation instruction includes a write address and a write command;

[0029] Based on a preset MIG core particle allocation method, the sampled data is divided into multiple sub-data streams, so that each of the multiple sub-data streams corresponds to a MIG core;

[0030] Synchronously combining the multiple write operation instructions in the write operation instruction set and the multiple sub-data streams to obtain multiple target sub-data streams;

[0031] The multiple target sub-data streams are sent to the write asynchronous FIFO corresponding to each MIG core in the multiple MIG cores, so that the multiple write asynchronous FIFOs corresponding to the multiple MIG cores share the same write enable signal at the same time.

[0032] Optionally, performing parallel data processing on the waveform data in the sampled data to obtain multi-core pre-stored data after data processing includes:

[0033] Based on the FPGA, the waveform data in the sampled data is decelerated to obtain first sampled data;

[0034] Decoding the first sampled data according to preset data stream parameters to obtain second sampled data, wherein the preset data stream parameters include the number of data channels, data bit width, and data transmission rate;

[0035] Determine target data flow parameters of the external memory, wherein the target data flow parameters include total data bit width requirements corresponding to the MIG core application layer interface;

[0036] According to the target data stream parameter, the second sampled data is converted into a bit width to obtain multi-core pre-stored data after data processing.

[0037] In addition, to achieve the above-mentioned purpose, the present disclosure further provides a data synchronization control device based on FPGA, and the data synchronization control device based on FPGA includes:

[0038] An acquisition module, used for acquiring a control command signal set of multiple acquisition boards, wherein the control command signal set includes a reset command signal, a read command signal and a write command signal;

[0039] A synchronization processing module, used for performing synchronization processing on the control command signal set based on a target processing board to obtain a synchronization signal packet, wherein the synchronization signal packet includes a synchronization reset signal, a synchronization write signal and a synchronization read signal;

[0040] A synchronous sampling module, used for performing synchronous sampling on multiple acquisition boards based on the synchronous signal packet to obtain sampling data;

[0041] A data processing module, used for processing the waveform data in the sampled data to obtain multi-core pre-stored data after data processing;

[0042] A synchronous operation module is used to perform a synchronous storage operation or a synchronous reading operation on the multi-core pre-stored data based on the synchronous signal package and the external memory of the FPGA parallel sampling system.

[0043] In addition, to achieve the above-mentioned purpose, the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and a processor executes the computer program to implement the above-mentioned FPGA-based data synchronization control method.

[0044] In addition, to achieve the above-mentioned purpose, the present disclosure also provides an electronic device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-mentioned FPGA-based data synchronization control method.

[0045] The FPGA-based data synchronization control method, device, storage medium and electronic device proposed in the embodiments of the present disclosure generate synchronization signal packets by synchronously processing the control command signal set on the target processing board, thereby eliminating the signal arrival time difference caused by cross-board transmission, ensuring that each acquisition board can perform the corresponding operation at the same time when receiving the synchronization signal, thereby achieving high-precision synchronization control. Since each acquisition board starts sampling at the same time under the drive of the synchronization signal, the collected data is consistent in time, providing a reliable data source for subsequent data processing. In this way, through synchronous control, the consistency and integrity of the data during storage or reading are ensured, and problems such as data confusion and failure caused by asynchrony are avoided. At the same time, the advantages of the FPGA parallel sampling system are utilized to improve the efficiency of data storage and reading, and meet the needs of high-speed and large-capacity data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0047] Figure 1 A schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present disclosure;

[0048] Figure 2 A schematic diagram of a flow chart of a data synchronization control method based on FPGA involved in an embodiment of the present disclosure;

[0049] Figure 3 This is a block diagram of a multi-acquisition board large-capacity deep storage synchronization control solution involved in the embodiment of the present disclosure;

[0050] Figure 4 A block diagram of a single-channel deep storage DDR3 multi-core synchronous control solution involved in the embodiment of the present disclosure;

[0051] Figure 5 This is a structural block diagram of a data synchronization control device based on FPGA involved in an embodiment of the present disclosure.

[0052] The realization of the objectives, functional features and advantages of the present disclosure will be further described in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] Reference Figure 1 , Figure 1 The figure is a schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present disclosure.

[0055] Typically, the device includes: at least one processor 301, a memory 302, and an FPGA-based data synchronization control program stored in the memory 302 and executable on the processor 301, wherein the FPGA-based data synchronization control program is configured to implement the steps of the FPGA-based data synchronization control method as described above.

[0056] The processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 301 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 301 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. The processor 301 may also include an AI (Artificial Intelligence) processor, which is used to process operations related to the FPGA-based data synchronization control method, so that the FPGA-based data synchronization control method model can be trained and learned autonomously to improve efficiency and accuracy.

[0057] The memory 302 may include one or more storage media, which may be non-transitory. The memory 302 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory storage medium in the memory 302 is used to store at least one instruction, which is used to be executed by the processor 301 to implement the FPGA-based data synchronization control method provided in the method embodiment of the present disclosure.

[0058] In some embodiments, the terminal may further optionally include: a communication interface 303 and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected via a bus or a signal line. Each peripheral device may be connected to the communication interface 303 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit 304, a display screen 305 and a power supply 306.

[0059] The communication interface 303 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 301 and the memory 302. In some embodiments, the processor 301, the memory 302, and the communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, the memory 302, and the communication interface 303 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0060] The radio frequency circuit 304 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 304 communicates with the communication network and other communication devices through electromagnetic signals. The radio frequency circuit 304 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals. Optionally, the radio frequency circuit 304 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The radio frequency circuit 304 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: a metropolitan area network, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 304 may also include circuits related to NFC (Near Field Communication), which is not limited in the present disclosure.

[0061] The display screen 305 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 305 is a touch display screen, the display screen 305 also has the ability to collect touch signals on the surface or above the surface of the display screen 305. The touch signal can be input to the processor 301 as a control signal for processing. At this time, the display screen 305 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 305 can be one, the front panel of the electronic device; in other embodiments, the display screen 305 can be at least two, respectively arranged on different surfaces of the electronic device or in a folding design; in some embodiments, the display screen 305 can be a flexible display screen, arranged on a curved surface or a folding surface of the electronic device. Even, the display screen 305 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 305 can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode).

[0062] The power supply 306 is used to power various components in the electronic device. The power supply 306 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When the power supply 306 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology. Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation of the device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0063] In addition, the embodiment of the present disclosure further proposes a storage medium, on which a data synchronization control program based on FPGA is stored, and when the data synchronization control program based on FPGA is executed by a processor, the steps of the data synchronization control method based on FPGA as described above are implemented. Therefore, it will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the storage medium embodiment involved in the present disclosure, please refer to the description of the method embodiment of the present disclosure. As an example, the program instructions can be deployed to be executed on one device, or on multiple devices located at one location, or on multiple devices distributed at multiple locations and interconnected by a communication network.

[0064] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the above-mentioned program can be stored in a storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the above-mentioned storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0065] In related technologies, the main method to realize a large-capacity storage system is to use FPGA to connect external DDR3 dynamic memory particles. This solution can effectively cache massive amounts of data, support nearly seamless data acquisition, and facilitate accurate positioning and analysis of abnormal waveform signals.

[0066] However, this method of using FPGA to connect external DDR3 dynamic memory particles faces two major challenges:

[0067] Storage synchronization problem: Since a single sub-acquisition board only supports a maximum sampling rate of 20Gsps, in order to achieve the deep storage requirement of 2Gpts storage depth at an 80GSPS sampling rate, multiple acquisition boards need to work together and stitch the data together. This requires that the large-capacity storage of each acquisition board must be strictly synchronized to ensure the accuracy of subsequent data stitching.

[0068] Internal storage control issues: Even within a single acquisition board, multiple MIGs (Memory Interface Generators, storage control cores) may cause data confusion, failure, inter-frame aliasing and other errors due to improper reset and write enable synchronization control. Therefore, it is necessary to design an optimized synchronous reset and storage control mechanism.

[0069] In response to the above challenges, the present disclosure pays special attention to the high-precision synchronization problem between multiple ADCs and FPGA boards in the data transmission path (acquisition board → processing board → PCIE board → PC end). Since each acquisition board works independently, it is critical to ensure the time consistency of data acquisition between channels. This requires not only the storage of multiple acquisition boards to be synchronized, but also the processing board must be synchronized when receiving and caching data to ensure the correct splicing of data.

[0070] To achieve this goal, it is necessary to focus on solving the acquisition synchronization and write control signal synchronization problems of multiple acquisition boards to ensure that parallel signals can be stored synchronously. At the same time, for key signals such as reset, write, and read instructions transmitted across boards, a reasonable synchronization mechanism needs to be designed to eliminate the difference in signal arrival time and ensure the synchronous operation of each acquisition board.

[0071] In addition, the processing board needs to have the ability to receive and cache multi-channel data synchronously to ensure that data from different acquisition boards can be output synchronously after reaching the processing board, providing a reliable basis for subsequent data splicing and signal processing. If data storage is not synchronized, it will cause a series of problems such as waveform confusion, state machine abnormality, data aliasing, etc., which will seriously affect data quality and system performance.

[0072] In view of this, the present disclosure provides a data synchronization control method and device based on FPGA, a storage medium and an electronic device to solve the above technical problems.

[0073] Reference Figure 2 , Figure 2 The present invention is a flowchart of a data synchronization control method based on FPGA involved in the embodiment of the present invention, comprising the following steps:

[0074] Step S11: Acquire control command signal sets of multiple acquisition boards, where the control command signal sets include a reset command signal, a read command signal, and a write command signal.

[0075] Step S12: Based on the target processing board, the control command signal set is synchronously processed to obtain a synchronous signal package, where the synchronous signal package includes a synchronous reset signal, a synchronous write signal and a synchronous read signal.

[0076] Step S13: Perform synchronous sampling on multiple acquisition boards based on the synchronous signal package to obtain sampled data.

[0077] Step S14: Process the waveform data in the sampled data to obtain multi-core pre-stored data after data processing.

[0078] Step S15: Based on the synchronization signal package and the external memory of the FPGA parallel sampling system, a synchronous storage operation or a synchronous reading operation is performed on the multi-core pre-stored data.

[0079] Through the above technical solution, the control command signal set is synchronously processed on the target processing board to generate a synchronous signal packet, eliminating the signal arrival time difference caused by cross-board transmission, ensuring that each acquisition board can perform the corresponding operation at the same time when receiving the synchronization signal, thereby achieving high-precision synchronous control. Since each acquisition board starts sampling at the same time under the drive of the synchronization signal, the collected data is consistent in time, providing a reliable data source for subsequent data processing. In this way, through synchronous control, the consistency and integrity of the data during storage or reading are ensured, avoiding problems such as data confusion and failure caused by asynchrony. At the same time, the advantages of the FPGA parallel sampling system are utilized to improve the efficiency of data storage and reading, meeting the needs of high-speed and large-capacity data storage.

[0080] In a possible manner, the FPGA parallel sampling system includes four acquisition boards, a processing board, a PCIE board and a PC end; wherein each acquisition board includes two ADCs and an FPGA board, and each FPGA is externally connected to 12 DDR3 particles.

[0081] For example, Figure 3 The present invention is a block diagram of a multi-acquisition board large-capacity deep storage synchronization control solution involved in the embodiment of the present disclosure.

[0082] like Figure 3 As shown, the FPGA parallel sampling system described in the present disclosure is a multi-channel ultra-wideband interleaved sampling system, and its physical structure includes a conditioning board, four acquisition boards (acquisition board 1, acquisition board 2, acquisition board 3, acquisition board 4), a processing board, a PCIE board and a PC end. Each acquisition board consists of two ADCs and an FPGA board, and each FPGA is connected to 12 DDR3 chips.

[0083] The conditioning board uses a specific conditioning circuit to condition the signal to ensure that the signal's amplitude, frequency and other characteristics meet the ADC sampling requirements. Preprocessing, including amplification, filtering, attenuation, etc., removes noise and interference in the signal and improves signal quality to meet the input requirements of the subsequent acquisition board.

[0084] Taking acquisition board 1 as an example, each acquisition board uses two interleaved sampling ADCs (i.e., ADC1 and ADC2) to perform high-speed, high-precision analog-to-digital conversion on the conditioned signal. Interleaved sampling technology can significantly improve the sampling rate and bandwidth of the system to meet the acquisition requirements of ultra-wideband signals. Among them, ADC1 and ADC2 convert analog signals into digital signals. FPGA1 corresponding to acquisition board 1 is responsible for controlling the sampling process of ADC1 and ADC2, converting the sampled data, and performing cross-clock domain processing based on the cross-clock domain FIFO, and then storing the data in the external DDR3 particles.

[0085] In the present disclosure, the multi-core memory between multiple acquisition boards needs to be designed synchronously to ensure the synchronization of each acquisition board during sampling, storage, etc. Through the precise control of FPGA, clock synchronization, sampling synchronization and data synchronization between multiple acquisition boards are achieved.

[0086] The processing board receives data from each acquisition board, performs further data processing and analysis, and coordinates the working status of each acquisition board to ensure the stable operation of the entire system. Specifically, the processing board can read data from each acquisition board through a high-speed interface (such as a high-speed serial bus). And based on the synchronization signals such as reset / write enable / read enable of multiple acquisition boards at the previous stage, the data is synchronously processed.

[0087] The synchronization signal package Sync_signal includes a synchronous DDR storage interface control core system reset signal (ie, Sync_mig_sys_rst), a synchronous DDR storage control user top-level reset signal (ie, Sync_ddr_ui_rst), a synchronous write signal (ie, Sync_pc_ddr_start), and a synchronous read signal (ie, Sync_pc_ddr_ren).

[0088] The PCIE board acts as a bridge for data transmission, efficiently and stably transmitting data from the processing board to the PC end. Specifically, the PCIE board uses the high-speed transmission characteristics of the PCIE bus to achieve fast data transmission. It also supports multi-channel parallel transmission to improve the bandwidth and efficiency of data transmission.

[0089] The PC serves as the control center and data storage center of the system and is responsible for receiving, storing, analyzing and displaying data.

[0090] Of course, the FPGA parallel sampling system in the present disclosure may also include external devices such as a display, a keyboard, a mouse, etc. for human-computer interaction, so as to facilitate users to monitor and operate the entire system.

[0091] Figure 4 The present invention is a block diagram of a single-channel deep storage DDR3 multi-core synchronous control solution involved in the embodiment of the present invention.

[0092] like Figure 4 As shown, the FPGA's MIG core is called to control the read and write of the DDR3 SDRAM memory. The built DDR3 storage control module (ie, DDR3_CTRL_Manage) is responsible for interacting with the MIG core to achieve the writing and reading of single waveform data.

[0093] The specific operation process is as follows:

[0094] The state machine is deployed on the DDR3 storage control module to realize the read and write control of the MIG core under the control of the state machine. The state machine has four states: initial state, waiting state, read state, and write state. When a storage command is received, the sampled data is written into the DDR3 particle, and the storage enters the waiting state after completion. When a read command is received, the data is read out from the DDR3 particle according to the read address, and the read data is transmitted to the subsequent module for processing.

[0095] In a possible manner, the control command signal set is synchronously processed based on the target processing board, and the obtained synchronization signal packet includes:

[0096] sending a control command signal set to a target processing board;

[0097] Based on the synchronous control module of the target processing board, multiple reset command signals in the control command signal set are captured and processed along the falling edge to obtain a reset start flag; and

[0098] Capturing rising edge processing on multiple reset signals included in the control command signal set to obtain a reset end flag;

[0099] The reset start flag and the reset end flag are logically processed to obtain target synchronous reset signals corresponding to multiple reset command signals, so as to generate multiple synchronous reset signals through the target synchronous reset signals and send them to multiple acquisition boards for synchronous reset.

[0100] It should be understood that during the data reading and writing process, the DDR3 storage control module of each acquisition board receives the reset and read / write start commands sent by the host computer. Since the path delays from the PC to each acquisition board are different, the arrival time of the read / write control signals is also different. Therefore, it is necessary to design the synchronization of the read / write start signals of multiple acquisition boards.

[0101] Before waveform acquisition, the acquisition system can be reset, the DDR control state machine can be reset, the previous data in the FIFO and DDR can be cleared, and the DDR3 control state machine can be reset to ensure that the subsequent acquisition storage space is clean. Otherwise, the stored waveform may be mixed with the previous residue, causing waveform confusion, or state machine disorder, or data aliasing, etc. Then, data acquisition, processing, caching, transmission, display and other operations can be carried out in a reciprocating cycle.

[0102] After each acquisition is completed, a new round of acquisition and storage can be started after synchronous reset. Generally, the user sends a reset signal to the processing board through the PC software program, and then the reset signal of the processing board is transmitted to the acquisition board through the interface, thereby resetting the cache module and processing module on the acquisition board. Since the reset signal sent by the processing board will have a path delay problem during the transmission between boards, the time it arrives at the acquisition board is different, and the time when the reset signal starts to fall will be different.

[0103] Even if it is the same acquisition board, since there are three sets of DDR3 MIG storage management control cores on the same acquisition board, the transmission delay of the reset signal to the three MIGs may be inconsistent and there will be differences. Therefore, the time when different acquisition boards start collecting waveforms and start the storage of large-capacity deep storage and DDR3 MIG cores may not be synchronized. Therefore, in order to ensure the synchronous acquisition of different acquisition boards, it should be ensured that the reset signal received by each acquisition board is valid at the same time.

[0104] In the present disclosure, each acquisition board can send the received reset and read / write command signals to the same processing board, namely the target processing board, respectively, and then send them to each acquisition board after synchronization processing by the synchronization control module of the target processing board. The synchronization signal packet sync_signal from the processing board to the acquisition board is required to be strictly equal in length and the transmission delay is controlled. In this way, the signal synchronization processing is deployed on the processing board, and the processing board uniformly sends a reset signal or a read / write control signal to the DDR3 storage control module to each acquisition board to ensure that each DDR3 storage control module receives a synchronized control command signal.

[0105] Specifically, first, multiple acquisition boards receive the reset signal sent by the software, and then each acquisition board sends the reset signal it receives to the same processing board. After receiving the multiple reset signals, the processing board captures the falling edge to obtain the reset start flag start_rst_flag, captures the rising edge to obtain the reset end flag finish_rst_flag, and then performs logical AND on the reset start flag start_rst_flag and the reset end flag finish_rst_flag to regenerate a common synchronous reset signal. Then, the synchronous reset signal generates four synchronous reset signals and sends them to the four acquisition boards on the front end for synchronous reset.

[0106] It is worth mentioning that the synchronous reset signal between the processing board and the acquisition board can use LVDS differential signal, and the length is strictly controlled. After the acquisition board receives the synchronization signal, an LVDS synchronization delay window control is performed, and the I0delay interface in the FPGA is used to strictly control the signal transmission delay to ensure that the signal transmission delay of the DDR control module of each acquisition board is consistent, thereby achieving synchronous reset.

[0107] In a possible manner, before performing synchronous sampling on multiple acquisition boards based on the synchronous signal packet to obtain sampled data, the method further includes:

[0108] In response to the synchronous reset signal, generating a first internal synchronous reset signal and a second internal synchronous reset signal according to the synchronous reset signal;

[0109] The first internal synchronous reset signal is sent to the sub-processing modules corresponding to the plurality of acquisition boards so that the sub-processing modules are reset according to the first internal synchronous reset signal; wherein the sub-processing modules include a write data and bit width conversion module, an address generation module, an FSM state machine control module, and a read data and bit width conversion module; and

[0110] The second internal synchronous reset signal is sent to the MIG processing modules corresponding to the multiple MIG cores in the external memory, so that the multiple MIG cores are reset according to the second internal synchronous reset signal based on the MIG processing modules.

[0111] For example, in the present disclosure, the system performs a reset operation at the beginning of each acquisition. The reset process of the DDR3 storage control module (ie, DDR3_CTRL_Manage) of a single acquisition board includes the following:

[0112] like Figure 4 As shown, after the DDR3 storage control module (ie, DDR3_CTRL_Manage) receives the synchronous reset signal, the synchronous DDR storage control user top-level reset signal (ie, Sync_ddr_ui_rst) is used as the reset signal of each sub-module in the module and is sent to the write data and bit width conversion module, the address generation module, the FSM state machine control module, and the read data and bit width conversion module.

[0113] The MIG processing module (mig_process) here uses a separate synchronous DDR storage interface control core system reset signal (ie, Sync_mig_sys_rst) reset signal as the system reset signal sys_rst of three MIG processing sub-modules (ie, the first MIG processing sub-module, the second MIG processing sub-module, and the third MIG processing sub-module) to reset the three MIG processing sub-modules.

[0114] After that, they start to uniformly respond to the synchronous write start signal of DDR3, serving as the write enable fifo_wen of each write w_fifo, and start to synchronously write data.

[0115] In a possible manner, resetting multiple MIG cores based on the MIG processing module according to the second internal synchronous reset signal includes:

[0116] In response to the second internal synchronous reset signal, the plurality of MIG cores generate a write cache reset signal;

[0117] Get the write cache reset signal and count at the same time;

[0118] When a pre-designed value is reached, the write cache reset signal is released to synchronously reset multiple MIG cores.

[0119] For example, Figure 4As shown, after the first MIG core, the second MIG core, and the third MIG core receive the synchronous reset signal sent by the synchronous reset module, they wait for some clocks and then generate a write cache reset signal wfifo_rst signal which is fed back to the previous write cache w_fifo. A counting register is set in front of the previous w_fifo. When the wfifo_rst signal is fed back, the reg_cnt module starts to latch the reset signal and count. When the pre-designed value N is reached, the reset signal is released to start resetting each MIG core, so that the three groups of w_fifo corresponding to the three MIG cores are reset synchronously for a period of time.

[0120] In a possible manner, data processing is performed on the waveform data in the sampled data to obtain multi-core pre-stored data after data processing, including:

[0121] Based on the FPGA, the waveform data in the sampled data is decelerated to obtain the first sampled data;

[0122] Decoding and converting the first sampled data according to preset data stream parameters to obtain second sampled data, wherein the preset data stream parameters include the number of data channels, data bit width, and data transmission rate;

[0123] Determine the target data flow parameters of the external memory, the target data flow parameters including the total data bit width requirement corresponding to the MIG core application layer interface;

[0124] According to the target data stream parameters, the second sampled data is converted into a bit width to obtain multi-core pre-stored data after data processing.

[0125] For example, after the system is reset, a cross sampling scheme of 8 10GSa / s ADC chips is used for sampling. A single acquisition board consists of two ADCs with a sampling rate of 10GSa / s and a vertical resolution of 12 bits. After the input signal is processed by the front-end signal conditioning channel, it is sent to the two ADCs for acquisition. The ADC sampling data is then transmitted to the acquisition board FPGA through high-speed reception. The FPGA receives and decodes the collected data at a reduced speed and converts it into 80 channels*12bit*250Mbps parallel data streams.

[0126] Since the present disclosure uses 12 DDR3 chips as external memory to store the sampled data, Figure 4As shown, 12 DDR3 particles are divided into the first DDR3 particle group, the second DDR3 particle group and the third DDR3 particle group, wherein the bit width of each DDR3 particle is 16 bits, the burst operation length is 8, and the data bit width is the data bit width of the particle multiplied by 8. Therefore, the total bit width of the MIG core application layer data is 12*16bit*8(BL)=1536bit, and the number of parallel paths of the corresponding sampled data is 128. In order to match the total data bit width of the MIG core application layer interface of 1536 bits, the bit width of the 80-path*12bit 80-path parallel data stream of the collected output is converted into 128-path*12bit 128-path parallel data stream.

[0127] In a possible manner, before performing a synchronous storage operation or a synchronous reading operation on multi-core pre-stored data based on the synchronous signal packet and the external memory of the FPGA parallel sampling system, the method further includes:

[0128] Asynchronous FIFOs are constructed for multiple MIG cores in an external memory to obtain multiple constructed MIG cores;

[0129] Based on the multiple MIG cores that have been built, the multi-core pre-stored data is converted across clock domains so that multiple MIG cores can share the same write enable signal at the same time;

[0130] Among them, each of the multiple MIG cores after construction includes a write asynchronous FIFO and a read asynchronous FIFO.

[0131] For example, since the clock (250MHZ) for generating write addresses and write commands and converting data bit width is different from the clock (200MHZ) of the MIG core, if the data is directly converted through the read / write address module and then written to the DDR3 SDRAM memory module through the MIG core, it is very likely to cause metastability. In order to avoid data loss caused by the occurrence of metastable states, the data of write / read address conversion needs to be transformed across clock domains before the data is written to the MIG core.

[0132] like Figure 4 As shown, the present disclosure can generate a cross-clock domain solution by using an asynchronous fifo, and build a corresponding asynchronous FIFO for each MIG core to perform cross-clock domain data processing. Since the reading and writing process of the external memory involves data cross-clock processing, two asynchronous FIFOs are built for each MIG core as a write asynchronous FIFO (w_fifo) and a read asynchronous FIFO (r_fifo). Among them, the write clock of the asynchronous FIFO is the system clock 250MHZ, and the read clock of the asynchronous FIFO is the working clock 200MHZ of the MIG core.

[0133] In a possible way, based on the multiple MIG cores after construction, the multi-core pre-stored data is converted across clock domains, including:

[0134] Acquire a write operation instruction set, where the write operation instruction set is generated by a storage control module of the external memory according to a synchronous write signal, and the write operation instruction set includes a write operation instruction corresponding to each MIG core in the multiple MIG cores, and the write operation instruction includes a write address and a write command;

[0135] Based on a preset MIG core particle allocation method, the sampled data is divided to obtain a plurality of sub-data streams, so that each of the plurality of sub-data streams corresponds to a MIG core;

[0136] Synchronously combining multiple write operation instructions and multiple sub-data streams in the write operation instruction set to obtain multiple target sub-data streams;

[0137] The multiple target sub-data streams are sent to the write asynchronous FIFO corresponding to each of the multiple MIG cores, so that the multiple write asynchronous FIFOs corresponding to the multiple MIG cores share the same write enable signal at the same time.

[0138] For example, the parallel data stream after bit width conversion can be divided into three parts according to the particle allocation method of MIG core 5-5-2, namely 640 bits, 640 bits and 256 bits respectively, and synchronized with the write operation instructions (including write address and write command) generated by the DDR3 storage control module to generate new data streams. Then it is sent to the write asynchronous FIFO of each MIG core. The bit widths of the write asynchronous FIFOs corresponding to the three MIG cores are 671 bits, 671 bits and 287 bits respectively. The three write asynchronous FIFOs share the same write enable signal at the same time, ensuring that the address data is aligned.

[0139] In the present disclosure, the sampling data is written to the external memory when the system receives a write start signal. The system sends this write signal to the state machine and the MIG processing module (i.e., mig_process), enters the write state from the idle state according to the state machine state, and starts the write process to the asynchronous FIFO.

[0140] The control state machine of the DDR3 storage control module jumps to the write state after detecting the write start command. In the write state, the write address module generates a write address and a synchronous write enable according to the write start address sent by the upper module, and transmits them to the control state machine module to generate an address signal app_addr (bit width is 28 bits), a command signal app_cmd (bit width is 3 bits) and an address valid signal.

[0141] In the process of writing sampled data to external memory, different groups of write asynchronous fifos judge whether the current MIG core is ready to accept write commands for write operations based on the feedback signals app_rdy and app_wdf_rdy output by different groups of MIG cores. The feedback signal output by the MIG core and the non-empty signal empty of the asynchronous FIFO (w_fifo) are logically ANDed and the result is used as the read enable signal of the write asynchronous fifo. When the result is "true", the write address, write command and data of the write asynchronous fifo are read out and output to the user interface of each MIG core. Each MIG core writes the data to the corresponding DDR3 particles according to the write address.

[0142] Similar to the data writing process, reading data from external memory can be done by first ensuring the synchronization of the read start signals of the multiple acquisition boards. When the read start signal is detected, the control state machine jumps to the read state. Then the read address generation module generates the read address and the synchronous read enable signal according to the read start address issued by the software and the step value 8 by accumulation. Then the read command and the read address are passed to the MIG core after writing the asynchronous fifo across the clock. The corresponding sampled data is read from the external memory through the MIG core and sent to the DDR3 storage control module, and then transmitted to the processing board after processing.

[0143] The receiving cache synchronization process of the processing board may be that the processing board receives the sampled data from multiple acquisition boards, and then performs cache, splicing and other processing. In order to achieve the correct splicing of the sampled data from multiple acquisition boards, the processing board needs to synchronously receive the acquisition data from multiple acquisition boards at the previous stage and cache them, and the cache process is controlled by digital triggering. The synchronous FIFO method can be used to achieve the synchronization of multi-channel data reception, which is not limited in the embodiments of the present disclosure.

[0144] Reference Figure 5 , Figure 5 This is a structural block diagram of a data synchronization control device based on FPGA involved in the embodiment of the present disclosure. Based on the same inventive concept as the above embodiment, the device includes:

[0145] An acquisition module 10, used to acquire a control command signal set of multiple acquisition boards, wherein the control command signal set includes a reset command signal, a read command signal, and a write command signal;

[0146] A synchronization processing module 20, configured to perform synchronization processing on the control command signal set based on a target processing board to obtain a synchronization signal packet, wherein the synchronization signal packet includes a synchronization reset signal, a synchronization write signal, and a synchronization read signal;

[0147] A synchronous sampling module 30, used for performing synchronous sampling of multiple acquisition boards based on the synchronous signal packet to obtain sampling data;

[0148] A data processing module 40 is used to process the waveform data in the sampled data to obtain multi-core pre-stored data after data processing;

[0149] The synchronous operation module 50 is used to perform a synchronous storage operation or a synchronous reading operation on the multi-core pre-stored data based on the synchronous signal package and the external memory of the FPGA parallel sampling system.

[0150] Optionally, the synchronization processing module 20 is used to:

[0151] sending the control command signal set to a target processing board;

[0152] Based on the synchronization control module of the target processing board, multiple reset command signals in the control command signal set are captured and processed along the falling edges to obtain a reset start flag; and

[0153] Capturing rising edge processing on a plurality of reset signals included in the control command signal set to obtain a reset end flag;

[0154] The reset start flag and the reset end flag are logically ANDed to obtain target synchronous reset signals corresponding to multiple reset command signals, so as to generate multiple synchronous reset signals through the target synchronous reset signal and send them to multiple acquisition boards for synchronous reset.

[0155] Optionally, the FPGA-based data synchronization control device further includes a reset module, and the reset module is used to:

[0156] Before performing synchronous sampling on multiple acquisition boards based on the synchronous signal packet to obtain sampled data, in response to the synchronous reset signal, generating a first internal synchronous reset signal and a second internal synchronous reset signal according to the synchronous reset signal;

[0157] The first internal synchronous reset signal is sent to the sub-processing modules corresponding to the plurality of acquisition boards, so that the sub-processing modules are reset according to the first internal synchronous reset signal; wherein the sub-processing modules include a write data and bit width conversion module, an address generation module, an FSM state machine control module, and a read data and bit width conversion module; and

[0158] The second internal synchronous reset signal is sent to the MIG processing modules corresponding to the multiple MIG cores in the external memory, so that the multiple MIG cores are reset according to the second internal synchronous reset signal based on the MIG processing modules.

[0159] Optionally, the reset module is used to:

[0160] In response to the second internal synchronous reset signal, the plurality of MIG cores generate a write cache reset signal;

[0161] Obtaining the write cache reset signal and counting at the same time;

[0162] When a pre-designed value is reached, the write cache reset signal is released to synchronously reset multiple MIG cores.

[0163] Optionally, the FPGA-based data synchronization control device further includes a cross-clock domain conversion module, and the cross-clock domain conversion module is used for:

[0164] Before performing a synchronous storage operation or a synchronous reading operation on the multi-core pre-stored data in the external memory based on the synchronous signal packet and the FPGA parallel sampling system, asynchronous FIFO construction is performed on the multiple MIG cores in the external memory to obtain the constructed multiple MIG cores;

[0165] Based on the built multiple MIG cores, the multi-core pre-stored data is converted across clock domains so that the multiple MIG cores share the same write enable signal at the same time;

[0166] Among them, each of the multiple MIG cores after construction includes a write asynchronous FIFO and a read asynchronous FIFO.

[0167] Optionally, the cross-clock domain transfer is used for:

[0168] Acquire a write operation instruction set, where the write operation instruction set is generated by the storage control module of the external memory according to the synchronous write signal, the write operation instruction set includes a write operation instruction corresponding to each MIG core in a plurality of MIG cores, and the write operation instruction includes a write address and a write command;

[0169] Based on a preset MIG core particle allocation method, the sampled data is divided into multiple sub-data streams, so that each of the multiple sub-data streams corresponds to a MIG core;

[0170] Synchronously combining the multiple write operation instructions in the write operation instruction set and the multiple sub-data streams to obtain multiple target sub-data streams;

[0171] The multiple target sub-data streams are sent to the write asynchronous FIFO corresponding to each MIG core in the multiple MIG cores, so that the multiple write asynchronous FIFOs corresponding to the multiple MIG cores share the same write enable signal at the same time.

[0172] Optionally, the data processing module 40 is used to:

[0173] Based on the FPGA, the waveform data in the sampled data is decelerated to obtain first sampled data;

[0174] Decoding and converting the first sampled data according to preset data stream parameters to obtain second sampled data, wherein the preset data stream parameters include the number of data channels, data bit width, and data transmission rate;

[0175] Determine target data flow parameters of the external memory, wherein the target data flow parameters include total data bit width requirements corresponding to the MIG core application layer interface;

[0176] According to the target data stream parameter, the second sampled data is converted into a bit width to obtain multi-core pre-stored data after data processing.

[0177] It should be noted that, since the steps executed by the device of this embodiment are the same as the steps of the aforementioned method embodiment, its specific implementation method and the technical effects that can be achieved can refer to the aforementioned embodiment and will not be repeated here.

[0178] In addition, in one embodiment, an embodiment of the present disclosure further provides an electronic device, which includes a processor, a memory, and a computer program stored in the memory, and the computer program implements the steps of the method in the aforementioned embodiment when executed by the processor.

[0179] In addition, in one embodiment, an embodiment of the present disclosure further provides a computer storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method in the aforementioned embodiment are implemented.

[0180] In some embodiments, the computer readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or various devices including one or any combination of the above memories. The computer may be various computing devices including intelligent terminals and servers.

[0181] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0182] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file storing other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0183] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0184] It should be noted that, in this article, the terms "include", "may include" or any other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0185] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0186] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a disk, or an optical disk), and includes a number of instructions for enabling a multimedia terminal device (which can be a mobile phone, a computer, a television receiver, or a network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0187] The above descriptions are only optional embodiments of the present disclosure, and are not intended to limit the patent scope of the present disclosure. All equivalent structural transformations made using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A data synchronization control method based on FPGA, characterized in that: Applied to FPGA parallel sampling systems, including: Acquire a control command signal set of multiple acquisition boards, wherein the control command signal set includes a reset command signal, a read command signal, and a write command signal; The control command signal set is synchronously processed based on the target processing board to obtain a synchronization signal package, wherein the synchronization signal package includes a synchronization reset signal, a synchronization write signal and a synchronization read signal; the synchronization signal package obtained by the synchronization processing of the control command signal set based on the target processing board includes: sending the control command signal set to the target processing board; based on the synchronization control module of the target processing board, capturing the falling edge processing of multiple reset command signals in the control command signal set to obtain a reset start mark; and capturing the rising edge processing of multiple reset signals included in the control command signal set to obtain a reset end mark; performing logical AND processing on the reset start mark and the reset end mark to obtain target synchronization reset signals corresponding to the multiple reset command signals, so as to generate multiple synchronization reset signals through the target synchronization reset signal and send them to multiple acquisition boards for synchronous reset; Performing synchronous sampling on multiple acquisition boards based on the synchronous signal packet to obtain sampling data; Processing the waveform data in the sampled data to obtain multi-core pre-stored data after data processing; Based on the synchronization signal package and the external memory of the FPGA parallel sampling system, a synchronous storage operation or a synchronous reading operation is performed on the multi-core pre-stored data.

2. The method according to claim 1, characterized in that Before performing synchronous sampling on multiple acquisition boards based on the synchronous signal package to obtain sampled data, the method further includes: In response to the synchronous reset signal, generating a first internal synchronous reset signal and a second internal synchronous reset signal according to the synchronous reset signal; The first internal synchronous reset signal is sent to the sub-processing modules corresponding to the plurality of acquisition boards, so that the sub-processing modules are reset according to the first internal synchronous reset signal; wherein the sub-processing modules include a write data and bit width conversion module, an address generation module, an FSM state machine control module, and a read data and bit width conversion module; and The second internal synchronous reset signal is sent to the MIG processing modules corresponding to the multiple MIG cores in the external memory, so that the multiple MIG cores are reset according to the second internal synchronous reset signal based on the MIG processing modules.

3. The method according to claim 2, characterized in that The resetting of the multiple MIG cores based on the MIG processing module according to the second internal synchronous reset signal includes: In response to the second internal synchronous reset signal, the plurality of MIG cores generate a write cache reset signal; Obtaining the write cache reset signal and counting at the same time; When a pre-designed value is reached, the write cache reset signal is released to synchronously reset multiple MIG cores.

4. The method according to claim 1, characterized in that: Before the external memory based on the synchronization signal package and the FPGA parallel sampling system performs a synchronous storage operation or a synchronous reading operation on the multi-core pre-stored data, it also includes: Performing asynchronous FIFO construction on the multiple MIG cores in the external memory to obtain the constructed multiple MIG cores; Based on the built multiple MIG cores, the multi-core pre-stored data is converted across clock domains so that the multiple MIG cores share the same write enable signal at the same time; Among them, each of the multiple MIG cores after construction includes a write asynchronous FIFO and a read asynchronous FIFO.

5. The method according to claim 4, characterized in that The method of performing cross-clock domain conversion on the multi-core pre-stored data based on the built multiple MIG cores includes: Acquire a write operation instruction set, where the write operation instruction set is generated by the storage control module of the external memory according to the synchronous write signal, the write operation instruction set includes a write operation instruction corresponding to each MIG core in a plurality of MIG cores, and the write operation instruction includes a write address and a write command; Based on a preset MIG core particle allocation method, the sampled data is divided into multiple sub-data streams, so that each of the multiple sub-data streams corresponds to a MIG core; Synchronously combining the multiple write operation instructions in the write operation instruction set and the multiple sub-data streams to obtain multiple target sub-data streams; The multiple target sub-data streams are sent to the write asynchronous FIFO corresponding to each MIG core in the multiple MIG cores, so that the multiple write asynchronous FIFOs corresponding to the multiple MIG cores share the same write enable signal at the same time.

6. The method according to claim 1, characterized in that The processing of the waveform data in the sampled data to obtain multi-core pre-stored data after the data processing includes: Based on the FPGA, the waveform data in the sampled data is decelerated to obtain first sampled data; Decoding and converting the first sampled data according to preset data stream parameters to obtain second sampled data, wherein the preset data stream parameters include the number of data channels, data bit width, and data transmission rate; Determine target data flow parameters of the external memory, wherein the target data flow parameters include total data bit width requirements corresponding to the MIG core application layer interface; According to the target data stream parameter, the second sampled data is converted into a bit width to obtain multi-core pre-stored data after data processing.

7. A data synchronization control device based on FPGA, characterized in that: Applied to FPGA parallel sampling systems, including: An acquisition module, used for acquiring a control command signal set of multiple acquisition boards, wherein the control command signal set includes a reset command signal, a read command signal and a write command signal; A synchronization processing module, used for performing synchronization processing on the control command signal set based on a target processing board to obtain a synchronization signal package, wherein the synchronization signal package includes a synchronization reset signal, a synchronization write signal and a synchronization read signal; the synchronization processing on the control command signal set based on the target processing board to obtain the synchronization signal package includes: sending the control command signal set to the target processing board; based on the synchronization control module of the target processing board, capturing a plurality of reset command signals in the control command signal set to perform a falling edge processing to obtain a reset start mark; and capturing a plurality of reset signals included in the control command signal set to perform a rising edge processing to obtain a reset end mark; performing a logic AND processing on the reset start mark and the reset end mark to obtain a target synchronization reset signal corresponding to the plurality of reset command signals, so as to generate a plurality of synchronization reset signals through the target synchronization reset signal and send them to a plurality of acquisition boards for synchronization reset; A synchronous sampling module, used for performing synchronous sampling on multiple acquisition boards based on the synchronous signal packet to obtain sampling data; A data processing module, used for processing the waveform data in the sampled data to obtain multi-core pre-stored data after data processing; A synchronous operation module is used to perform a synchronous storage operation or a synchronous reading operation on the multi-core pre-stored data based on the synchronous signal package and the external memory of the FPGA parallel sampling system.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the processor executes the computer program to implement the method according to any one of claims 1 to 6.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method according to any one of claims 1 to 6.

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