semiconductor modules

Abstract

A semiconductor module includes a conductive substrate, a plurality of first semiconductor elements, and a plurality of second semiconductor elements. The conductive substrate includes a first conductive portion electrically connected to the plurality of first semiconductor elements, and a second conductive portion electrically connected to the plurality of second semiconductor elements. The semiconductor module further includes a first input terminal, a second input terminal, and a third input terminal disposed proximate the first conductive portion. The second and third input terminals are spaced apart from each other across the first input terminal. The first input terminal is electrically connected to the first conductive portion. The polarity of the first input terminal is set to be opposite to the polarity of the second and third input terminals.

Description

[0001] This application is a divisional application; the application number of the parent application is "2021800555338" and the name of the invention is "Semiconductor Module". Technical Field

[0002] The present disclosure relates to a semiconductor module. Background Art

[0003] In the past, semiconductor modules with power switching elements such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor) were known. Such semiconductor modules are installed in all electronic devices ranging from industrial equipment to home appliances, information terminals, and automotive equipment. Patent document 1 discloses a conventional semiconductor module (power module). The semiconductor module described in patent document 1 includes a semiconductor element and a supporting substrate (ceramic substrate). The semiconductor element is, for example, an IGBT made of Si (silicon). The supporting substrate supports the semiconductor element. The supporting substrate includes an insulating substrate and conductor layers stacked on both sides of the substrate. The substrate is made of, for example, ceramic. Each conductor layer is made of, for example, Cu (copper), and a semiconductor element is bonded to one of the conductor layers.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2015-220382 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] In recent years, there has been a demand for electronic devices to be more energy-efficient, have higher performance, and be smaller in size. Consequently, there is a need for semiconductor modules mounted in electronic devices to be more efficient and smaller in size.

[0009] In view of the above, an object of the present disclosure is to provide a semiconductor module having a module structure that is preferable in terms of reducing parasitic inductance components.

[0010] Solutions to Problems

[0011] The semiconductor module disclosed herein comprises: a conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the opposite side of the main surface; a semiconductor element electrically bonded to the main surface and having a switching function; a conductive component forming a path for a main circuit current switched by the semiconductor element; a first input terminal, a second input terminal, and a third input terminal arranged on one side of a first direction perpendicular to the thickness direction relative to the conductive substrate; and an output terminal arranged on the other side of the first direction relative to the conductive substrate. The conductive substrate includes a first conductive portion and a second conductive portion, and the semiconductor element includes a plurality of first semiconductor elements electrically bonded to the first conductive portion and a plurality of second semiconductor elements electrically bonded to the second conductive portion. The second input terminal and the third input terminal are arranged on one side and the other side of a second direction perpendicular to both the thickness direction and the first direction, across the first input terminal. The first input terminal is one of a positive electrode and a negative electrode and is electrically connected to the first conductive portion. The second input terminal and the third input terminal are the other of the positive electrode and the negative electrode.

[0012] Effects of the Invention

[0013] According to the structure according to the present disclosure, it is possible to provide a module structure that is preferable in terms of reducing parasitic inductance components in a semiconductor module. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a perspective view of the semiconductor module according to the first embodiment.

[0015] Figure 2 is Figure 1 In the perspective view of FIG, the sealing resin, the resin portion, and the resin-filled portion are omitted.

[0016] Figure 3 is Figure 2 The conductive components are omitted in the stereoscopic view.

[0017] Figure 4 It is a plan view showing the semiconductor module according to the first embodiment.

[0018] Figure 5 is Figure 4 The sealing resin, the resin portion, and the resin-filled portion are shown by imaginary lines in the top view of FIG.

[0019] Figure 6 It is magnified Figure 5 , omitting the imaginary lines of the sealing resin, the resin portion, and the resin-filled portion.

[0020] Figure 7 It is magnified Figure 6 A partial enlarged view of a part of .

[0021] Figure 8 is Figure 5 A diagram showing a portion of a conductive component using imaginary lines in a top view of FIG.

[0022] Figure 9 This is a front view showing the semiconductor module according to the first embodiment.

[0023] Figure 10 It is a bottom view showing the semiconductor module according to the first embodiment.

[0024] Figure 11 It is a left side view showing the semiconductor module according to the first embodiment.

[0025] Figure 12 It is a right side view showing the semiconductor module according to the first embodiment.

[0026] Figure 13 It is along Figure 5 Cross-sectional view along line XIII-XIII.

[0027] Figure 14 It is along Figure 5 Cross-sectional view along line XIV-XIV.

[0028] Figure 15 It is magnified Figure 14 A partial enlarged view of a part of .

[0029] Figure 16 It is along Figure 5 Cross-sectional view along line XVI-XVI.

[0030] Figure 17 It is along Figure 5 Cross-sectional view along line XVII-XVII.

[0031] Figure 18 It is along Figure 5 Cross-sectional view of line XVIII-XVIII.

[0032] Figure 19 It is along Figure 5 Cross-sectional view of the XIX-XIX line.

[0033] Figure 20 This is an example of the circuit configuration of the semiconductor module according to the first embodiment.

[0034] Figure 21 It is a plan view showing one step of the method for manufacturing the semiconductor module according to the first embodiment.

[0035] Figure 22This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor module according to the first embodiment.

[0036] Figure 23 It is a plan view showing one step of the method for manufacturing the semiconductor module according to the first embodiment.

[0037] Figure 24 is a cross-sectional end view showing one step of the manufacturing method of the first embodiment, and Figure 13 The cross section shown corresponds.

[0038] Figure 25 This is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing a semiconductor module according to the first embodiment, and an enlarged cross-sectional view of Figure 13 The figure corresponds to a portion of the cross section shown.

[0039] Figure 26 This is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing a semiconductor module according to the first embodiment, and an enlarged cross-sectional view of Figure 14 The figure corresponds to a portion of the cross section shown.

[0040] Figure 27 This is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing a semiconductor module according to the first embodiment, and an enlarged cross-sectional view of Figure 14 The figure corresponds to a portion of the cross section shown.

[0041] Figure 28 This is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing a semiconductor module according to the first embodiment, and an enlarged cross-sectional view of Figure 13 The figure corresponds to a portion of the cross section shown.

[0042] Figure 29 This is an enlarged cross-sectional view of a main part showing one step of the method for manufacturing a semiconductor module according to the first embodiment, and an enlarged cross-sectional view of Figure 14 The figure corresponds to a portion of the cross section shown.

[0043] Figure 30 The semiconductor module according to the second embodiment is Figure 5 Same top view.

[0044] Figure 31 It is magnified Figure 30 , omitting the imaginary lines of the sealing resin, the resin portion, and the resin-filled portion.

[0045] Figure 32 It is magnified Figure 31 A partial enlarged view of a part of .

[0046] Figure 33A semiconductor module according to a third embodiment is Figure 5 Same top view.

[0047] Figure 34 It is along Figure 33 Cross-sectional view of line XXXIV-XXXIV. DETAILED DESCRIPTION

[0048] Hereinafter, preferred embodiments of the semiconductor module disclosed herein will be described with reference to the accompanying drawings. In the following description, identical or similar components are denoted by identical reference numerals, and duplicate descriptions will be omitted.

[0049] Figures 1 to 20 The semiconductor module A1 according to the first embodiment is shown. The semiconductor module A1 includes a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal support 5, a conductive member 6, a first conductive bonding material 71, a second conductive bonding material 72, a plurality of metal wires 731 to 735, a sealing resin 8, a resin portion 87, and a resin-filled portion 88.

[0050] Figure 1 It is a perspective view showing the semiconductor module A1. Figure 2 is Figure 1 The sealing resin 8, the resin portion 87, and the resin-filled portion 88 are omitted in the perspective view of FIG. Figure 3 is Figure 2 The conductive component 6 is omitted in the perspective view. Figure 4 It is a plan view showing the semiconductor module A1. Figure 5 is Figure 4 The sealing resin 8, the resin portion 87, and the resin-filled portion 88 are shown by imaginary lines in the plan view of FIG. Figure 6 It is magnified Figure 5 A partial enlarged view of a part of the Figure 6 In FIG. 8 , imaginary lines of the sealing resin 8 , the resin portion 87 , and the resin-filled portion 88 are omitted. Figure 7 It is magnified Figure 6 A partial enlarged view of a part of . Figure 8 is Figure 5 A diagram showing a portion of the conductive member 6 (a second conductive member 62 described later) by imaginary lines in a plan view of FIG. Figure 9 It is a front view showing the semiconductor module A1. Figure 10 It is a bottom view showing the semiconductor module A1. Figure 11 It is a left side view showing the semiconductor module A1. Figure 12 It is a right side view showing the semiconductor module A1. Figure 13 It is along Figure 5Cross-sectional view along line XIII-XIII. Figure 14 It is along Figure 5 Cross-sectional view along line XIV-XIV. Figure 15 It is magnified Figure 14 A partial enlarged view of a part of . Figure 16 It is along Figure 5 Cross-sectional view along line XVI-XVI. Figure 17 It is along Figure 5 Cross-sectional view along line XVII-XVII. Figure 18 It is along Figure 5 Cross-sectional view of line XVIII-XVIII. Figure 19 It is along Figure 5 The sectional view of the XIX-XIX line. Figure 2 、 Figure 3 、 Figure 7 、 Figure 14 、 Figure 18 , a plurality of metal wires 731 to 735 are omitted. Figure 20 This is an example of the circuit configuration of the semiconductor module A1. Figure 20 In the circuit diagram, only one of the plurality of first semiconductor elements 10A (described later) and the plurality of second semiconductor elements 10B (described later) is shown, and the other first semiconductor elements 10A and the other second semiconductor elements 10B are omitted.

[0051] For the sake of convenience, reference is made to three mutually orthogonal directions, namely, the x-direction, the y-direction, and the z-direction. The z-direction is the thickness direction of the semiconductor module A1. The x-direction is the top view of the semiconductor module A1 (see Figure 4 ) in the left and right directions. The y direction is the top view of the semiconductor module A1 (refer to Figure 4 ). One side of the x-direction is set as the x1 direction, and the other side of the x-direction is set as the x2 direction. Similarly, one side of the y-direction is set as the y1 direction, and the other side of the y-direction is set as the y2 direction, and one side of the z-direction is set as the z1 direction, and the other side of the z-direction is set as the z2 direction. In the following description, "looking down" means when observing in the z-direction. In addition, there is a case where the z1 direction is called the bottom and the z2 direction is called the top. The z-direction is an example of a "thickness direction", the x-direction is an example of a "first direction", and the y-direction is an example of a "second direction". In addition, in the following description, directions that are opposite to each other in one direction are respectively referred to as "one side" and "the other side", but the present disclosure is not limited to this. Specifically, the x2 direction is referred to as "one side of the first direction", and the x1 direction is referred to as "the other side of the first direction". Similarly, the y2 direction is referred to as "one side of the second direction", and the y1 direction is referred to as "the other side of the second direction". In addition, the z2 direction is referred to as “one side in the thickness direction”, and the z1 direction is referred to as “the other side in the thickness direction”.

[0052] The plurality of semiconductor elements 10 are the functional cores of the semiconductor module A1. The constituent material of each semiconductor element 10 is, for example, a semiconductor material mainly composed of SiC (silicon carbide). The semiconductor material is not limited to SiC, and may also be Si (silicon), GaAs (gallium arsenide) or GaN (gallium nitride). Each semiconductor element 10 has a switching function unit Q1 (see FIG. 1 ) composed of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) Figure 20 The switch function unit Q1 is not limited to a MOSFET and may also be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET), a bipolar transistor such as an IGBT, or other transistors. Each semiconductor element 10 is the same element. Each semiconductor element 10 is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0053] like Figure 15 As shown, each semiconductor element 10 has an element principal surface 101 and an element rear surface 102. In each semiconductor element 10, the element principal surface 101 and the element rear surface 102 are spaced apart in the z direction. The element principal surface 101 faces the z2 direction, and the element rear surface 102 faces the z1 direction.

[0054] The plurality of semiconductor elements 10 include a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. In this embodiment, the semiconductor module A1 includes three first semiconductor elements 10A and three second semiconductor elements 10B. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited to this structure and can be appropriately changed according to the performance required of the semiconductor module A1. Figure 8 In this example, three first semiconductor elements 10A and three second semiconductor elements 10B are provided. The number of first semiconductor elements 10A and second semiconductor elements 10B can be one, two, or four or more. The number of first semiconductor elements 10A and second semiconductor elements 10B can be the same or different. The number of first semiconductor elements 10A and second semiconductor elements 10B is determined by the current capacity handled by semiconductor module A1.

[0055] like Figure 20As shown, semiconductor module A1 is configured as a half-bridge switching circuit, for example. In this case, multiple first semiconductor elements 10A constitute the upper arm circuit of semiconductor module A1, and multiple second semiconductor elements 10B constitute the lower arm circuit. In the upper arm circuit, multiple first semiconductor elements 10A are connected in parallel with each other, while in the lower arm circuit, multiple second semiconductor elements 10B are connected in parallel with each other. Each first semiconductor element 10A and each second semiconductor element 10B are connected in series to form a bridge layer.

[0056] like Figure 8 as well as Figure 16 As shown in FIG. 1 and FIG. 2 , a plurality of first semiconductor elements 10A are mounted on the conductive substrate 2. Figure 8 In the illustrated example, a plurality of first semiconductor elements 10A are arranged in the y-direction, for example, with spacing therebetween. Each first semiconductor element 10A is conductively bonded to the conductive substrate 2 (a first conductive portion 2A, described later) via a second conductive bonding material 72. When each first semiconductor element 10A is bonded to the first conductive portion 2A, the element back surface 102 faces the first conductive portion 2A.

[0057] like Figure 8 as well as Figure 17 As shown in FIG. 1 and FIG. 2 , a plurality of second semiconductor elements 10B are mounted on the conductive substrate 2. Figure 8 In the example shown, a plurality of second semiconductor elements 10B are arranged in the y direction, for example, with intervals between them. Each second semiconductor element 10B is conductively bonded to the conductive substrate 2 (the second conductive portion 2B described later) via the second conductive bonding material 72. When each second semiconductor element 10B is bonded to the second conductive portion 2B, the element back surface 102 faces the second conductive portion 2B. Figure 8 As understood, the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap when viewed in the x-direction, but they do not necessarily overlap.

[0058] Multiple semiconductor elements 10 (multiple first semiconductor elements 10A and multiple second semiconductor elements 10B) each include a first main surface electrode 11, a second main surface electrode 12, and a back surface electrode 15. The structures of the first main surface electrode 11, the second main surface electrode 12, and the back surface electrode 15 described below are common to all semiconductor elements 10. The first main surface electrode 11 and the second main surface electrode 12 are provided on the element main surface 101. The first main surface electrode 11 and the second main surface electrode 12 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0059] The first main surface electrode 11 is, for example, a gate electrode, which inputs a drive signal (e.g., a gate voltage) for driving the semiconductor element 10. In each semiconductor element 10, the second main surface electrode 12 is, for example, a source electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers substantially the entire back surface 102 of the element. The back surface electrode 15 is, for example, plated with Ag.

[0060] If a driving signal (gate voltage) is input to the first main surface electrode 11 (gate electrode) through the above-mentioned switching function unit Q1, each semiconductor element 10 switches between the on state and the off state according to the driving signal. The action of switching between the on state and the off state is called a switching action. In the on state, current flows from the back electrode 15 (drain electrode) to the second main surface electrode 12 (source electrode), and in the off state, the current does not flow. In other words, each semiconductor element 10 performs a switching action through the switching function unit Q1. The semiconductor module A1 converts the first power supply voltage (DC voltage) input between one input terminal 41 and two input terminals 42 and 43 into a second power supply voltage (AC voltage) through the switching function unit Q1 of multiple semiconductor elements 10, and outputs the second power supply voltage from the output terminal 44. The input terminals 41 to 43 and the output terminal 44 are both power supply terminals that process power supply voltages. The input terminals 41 to 43 are first power supply terminals that input the first power supply voltage. The output terminal 44 is a second power supply terminal that outputs the second power supply voltage.

[0061] Some of the plurality of semiconductor elements 10 (in Figure 8 In the example shown, there are two) in addition to the switch function part Q1, there is also a diode function part D1 (see Figure 20 In the semiconductor module A1, one of the plurality of first semiconductor elements 10A (arranged in Figure 8 The first semiconductor element 10A closest to the y2 direction side) and one of the plurality of second semiconductor elements 10B (arranged at Figure 8 The second semiconductor element 10B on the side closest to the y1 direction) includes a diode function portion D1 in addition to the switch function portion Q1. The function and role of the diode function portion D1 are not particularly limited, and an example thereof may be a temperature detection diode. Figure 20 The diode D2 shown is, for example, a parasitic diode component of the switching function unit Q1 .

[0062] like Figure 8As shown, the semiconductor device 10 having the diode functional portion D1 has, in addition to the first main surface electrode 11, the second main surface electrode 12, and the back surface electrode 15, a third main surface electrode 13, a fourth main surface electrode 14, and a fifth main surface electrode 16. The structures of the third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16 described below are common to all semiconductor devices 10 having the diode functional portion D1. The third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16 are formed on the device main surface 101. In the semiconductor device 10 having the diode functional portion D1, the third main surface electrode 13 and the fourth main surface electrode 14 are electrically connected to the diode functional portion D1. The fifth main surface electrode 16 is, for example, a source sense electrode, through which the source current of the switch functional portion Q1 flows.

[0063] like Figure 7 As shown, each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view. Figure 7 , a first semiconductor element 10A arranged in the center of the y direction among a plurality of first semiconductor elements 10A arranged in the y direction is shown, but the other first semiconductor elements 10A also have a first side 191, a second side 192, a third side 193 and a fourth side 194. The first side 191 and the second side 192 extend in the y direction, respectively. The first side 191 is the end edge on the x2 direction side when viewed from above, and the second side 192 is the end edge on the x1 direction side when viewed from above. The third side 193 and the fourth side 194 extend in the x direction, respectively. The third side 193 is the end edge on the y2 direction side when viewed from above, and the fourth side 194 is the end edge on the y1 direction side when viewed from above. Each first semiconductor element 10A is rectangular in shape when viewed from above, so the four corners formed by the first side 191, the second side 192, the third side 193 and the fourth side 194 are approximately right angles when viewed from above. As shown Figure 7 As shown, the four corners do not overlap with the conductive member 6 (first conductive member 61 and second conductive member 62 described later) in a plan view. The lengths of the third side 193 and the fourth side 194 are greater than the lengths of the first side 191 and the second side 192.

[0064] The conductive substrate 2 is also called a lead frame. It supports multiple semiconductor elements 10. The conductive substrate 2 is bonded to the support substrate 3 via a first conductive bonding material 71. The conductive substrate 2 has a rectangular shape, for example, when viewed from above. Together with the conductive component 6, the conductive substrate 2 forms a path for the main circuit current switched by the multiple semiconductor elements 10.

[0065] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each a plate-shaped member made of metal. The metal is, for example, Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B together with the plurality of input terminals 41 to 43 and the plurality of output terminals 44 constitute a conductive path to the plurality of semiconductor elements 10. Figures 13 to 18 As shown, the first conductive portion 2A and the second conductive portion 2B are bonded to the support substrate 3 via the first conductive bonding material 71. A plurality of first semiconductor elements 10A are bonded to the first conductive portion 2A via the second conductive bonding material 72. A plurality of second semiconductor elements 10B are bonded to the second conductive portion 2B via the second conductive bonding material 72. Figure 3 、 Figure 8 、 Figure 13 as well as Figure 14 As shown, the first conductive portion 2A and the second conductive portion 2B are spaced apart in the x-direction. In the example shown in the above figure, the first conductive portion 2A is located closer to the x2 direction than the second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each rectangular in shape, for example, when viewed from above. The first conductive portion 2A and the second conductive portion 2B overlap when viewed in the x-direction. The first conductive portion 2A and the second conductive portion 2B have a dimension of, for example, 15 mm to 25 mm in the x-direction (preferably about 20 mm), a dimension of, for example, 30 mm to 40 mm in the y-direction (preferably about 35 mm), and a dimension of 1.5 mm to 3.0 mm in the z-direction (preferably about 2.0 mm).

[0066] The conductive substrate 2 has a main surface 201 and a back surface 202. Figure 13 、 Figure 14 as well as Figures 16 to 18 As shown, the main surface 201 and the back surface 202 are spaced apart in the z direction. The main surface 201 faces the z2 direction, and the back surface 202 faces the z1 direction. The main surface 201 is a surface formed by combining the upper surface of the first conductive part 2A and the upper surface of the second conductive part 2B. The back surface 202 is a surface formed by combining the lower surface of the first conductive part 2A and the lower surface of the second conductive part 2B. The back surface 202 is bonded to the support substrate 3 in a manner opposite to the support substrate 3. Figure 5 、 Figure 8 as well as Figure 13As shown, a plurality of recesses 201a are formed on the main surface 201. Each recess 201a is a portion that is recessed from the main surface 201 along the z direction. The degree of recess (depth) of each recess 201a is, for example, greater than 0 μm and less than 100 μm. Each recess 201a is formed, for example, during the molding process described later. The plurality of recesses 201a include recesses formed on the main surface 201 in the first conductive part 2A and recesses formed on the main surface 201 in the second conductive part 2B. The two recesses 201a formed on the main surface 201 of the first conductive part 2A are spaced apart in the y direction and overlap when viewed in the y direction. The two recesses 201a formed on the main surface 201 of the second conductive part 2B are spaced apart in the y direction and overlap when viewed in the y direction.

[0067] The conductive substrate 2 (each of the first conductive part 2A and the second conductive part 2B) includes a base material 21, a main surface bonding layer 22 and a back surface bonding layer 23 stacked on each other. The base material 21 is a plate-shaped component made of metal. The metal is Cu or a Cu alloy. The main surface bonding layer 22 is formed on the upper surface of the base material 21. The main surface bonding layer 22 is a surface layer on the z2 direction side of the conductive substrate 2. The upper surface of the main surface bonding layer 22 is equivalent to the main surface 201 of the conductive substrate 2. The main surface bonding layer 22 is, for example, Ag-plated. The back surface bonding layer 23 is formed on the lower surface of the base material 21. The back surface bonding layer 23 is a surface layer on the z1 direction side of the conductive substrate 2. The lower surface of the back surface bonding layer 23 is equivalent to the back surface 202 of the conductive substrate 2. The back surface bonding layer 23 is the same as the main surface bonding layer 22 and is, for example, Ag-plated.

[0068] The supporting substrate 3 supports the conductive substrate 2. The supporting substrate 3 is formed of, for example, a DBC (Direct Bonded Copper) substrate and includes an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.

[0069] The insulating layer 31 is, for example, a ceramic with excellent thermal conductivity. Examples of such ceramics include AlN (aluminum nitride). The insulating layer 31 is not limited to ceramics and may also be an insulating resin sheet. The insulating layer 31 is, for example, rectangular in plan view.

[0070] The first metal layer 32 is formed on the upper surface of the insulating layer 31 (the surface facing the z2 direction). The constituent material of the first metal layer 32 includes Cu, for example. The constituent material may also include Al instead of Cu. The first metal layer 32 includes a first portion 32A and a second portion 32B. The first portion 32A and the second portion 32B are separated in the x direction. The first portion 32A is located on the x2 direction side of the second portion 32B. The first portion 32A is bonded to the first conductive portion 2A to support the first conductive portion 2A. The second portion 32B is bonded to the second conductive portion 2B to support the second conductive portion 2B. The first portion 32A and the second portion 32B are each rectangular in shape, for example, when viewed from above.

[0071] The first bonding layer 321 is formed on the upper surface of the first metal layer 32 (each of the first portion 32A and the second portion 32B). The first bonding layer 321 is, for example, Ag plating. The first bonding layer 321 is provided to improve the bonding formed by solid phase diffusion with the first conductive bonding material 71.

[0072] The second metal layer 33 is formed on the lower surface (the surface facing the z1 direction) of the insulating layer 31. The constituent material of the second metal layer 33 is the same as that of the first metal layer 32. Figure 10 In the illustrated example, the lower surface of the second metal layer 33 (bottom surface 302 described later) is exposed from the sealing resin 8. This lower surface may be covered by the sealing resin 8 instead of being exposed from the sealing resin 8. In a plan view, the second metal layer 33 overlaps both the first portion 32A and the second portion 32B.

[0073] like Figures 13 to 18 As shown, the support substrate 3 has a support surface 301 and a bottom surface 302. The support surface 301 and the bottom surface 302 are spaced apart in the z direction. The support surface 301 faces the z2 direction, and the bottom surface 302 faces the z1 direction. Figure 10 As shown, the bottom surface 302 is exposed from the sealing resin 8. The support surface 301 is the upper surface of the first bonding layer 321, and is a surface formed by combining the upper surface of the first part 32A and the upper surface of the second part 32B. The support surface 301 is opposite to the conductive substrate 2 and is bonded to the conductive substrate 2. The bottom surface 302 is the lower surface of the second metal layer 33. On the bottom surface 302, a heat dissipation component (such as a heat sink) not shown in the figure can be installed. The dimension of the support substrate 3 in the z direction (the distance along the z direction from the support surface 301 to the bottom surface 302) is, for example, 0.7 mm to 2.0 mm.

[0074] The plurality of input terminals 41 to 43 and the plurality of output terminals 44 are each formed of a plate-shaped metal plate. The constituent material of the metal plate is, for example, Cu or a Cu alloy. Figures 1 to 5 、 Figure 8 as well as Figure 10 In the illustrated example, the semiconductor module A1 includes three input terminals 41 to 43 and two output terminals 44 .

[0075] A power supply voltage is applied between the three input terminals 41 to 43. In this embodiment, the input terminal 41 is the positive pole (P terminal), and the two input terminals 42 and 43 are the negative poles (N terminals). Alternatively, the input terminal 41 can be the negative pole (N terminal) and the two input terminals 42 and 43 can be the positive pole (P terminal). In this case, it is sufficient to change the wiring inside the package appropriately by changing the polarity of the terminals to make them consistent. The three input terminals 41 to 43 and the two output terminals 44 each include a portion covered by the sealing resin 8 and a portion exposed from the resin side of the sealing resin 8.

[0076] like Figure 14 As shown in FIG, the input terminal 41 is formed integrally with the first conductive portion 2A. Unlike this structure, the input terminal 41 is separated from the first conductive portion 2A, or it can be conductively connected to the first conductive portion 2A. Figure 8 As shown in FIG. 1 , input terminal 41 is located on the x2 side relative to the plurality of first semiconductor elements 10A and first conductive portion 2A (conductive substrate 2 ). Input terminal 41 is electrically connected to first conductive portion 2A and, via first conductive portion 2A, to back surface electrode 15 (drain electrode) of each first semiconductor element 10A. Input terminal 41 is an example of a "first input terminal."

[0077] The input terminal 41 has an input side joint surface 411 and an input side side surface 412. The input side joint surface 411 faces the z2 direction and extends to the x2 direction. The input side side surface 412 is located at the periphery of the input side joint surface 411 when viewed in the z direction, and faces a direction intersecting the input side joint surface 411. In this embodiment, the input side side surface 412 includes a front end surface 413 and a pair of side surfaces 414. The front end surface 413 is located at the x2 side end of the input terminal 41 and faces the x2 direction. The pair of side surfaces 414 are located at both ends of the y direction of the input terminal 41 and face the y1 direction and the y2 direction. On the input side side surface 412, at least one of the front end surface 413 and the pair of side surfaces 414 has an input side processing mark. The input side processing mark is formed by the cutting process of the lead frame described later.

[0078] like Figure 8 As shown, the two input terminals 42 and 43 are spaced apart from the first conductive portion 2A. The two input terminals 42 and 43 are respectively connected to the second conductive component 62. Figure 8As shown in FIG. 1 , the two input terminals 42 and 43 are located on the x2 side relative to the plurality of first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2 ). The two input terminals 42 and 43 are each electrically conductive to the second conductive member 62 and, via the second conductive member 62, to the second main surface electrode 12 (source electrode) of each second semiconductor element 10B. Input terminal 42 is an example of a "second input terminal," and input terminal 43 is an example of a "third input terminal."

[0079] The input terminals 42 and 43 have input-side bonding surfaces 421 and 431 and input-side side surfaces 422 and 432. The input-side bonding surfaces 421 and 431 face the z2 direction and extend toward the x2 direction. The input-side side surfaces 422 and 432 are located at the periphery of the input-side bonding surfaces 421 and 431 when viewed in the z direction, and face in a direction intersecting the input-side bonding surfaces 421 and 431. In this embodiment, the input-side side surface 422 includes a front end surface 423 and a pair of side surfaces 424. The front end surface 423 is located at the x2-direction end of the input terminal 42 and faces the x2 direction. The pair of side surfaces 424 are located at both ends of the input terminal 42 in the y direction and face the y1 and y2 directions. On the input-side side surface 422, at least one of the front end surface 423 and the pair of side surfaces 424 has an input-side processing mark. This input-side processing mark is formed by the cut process of the lead frame described later. The input-side side surface 432 includes a front face 433 and a pair of side faces 434. The front face 433 is located at the x2-direction end of the input terminal 43 and faces the x2 direction. The pair of side faces 434 are located at both ends of the input terminal 43 in the y-direction and face the y1 and y2 directions. On the input-side side surface 432, at least one of the front face 433 and the pair of side faces 434 has an input-side processing mark. This input-side processing mark is formed by the cross-sectioning process of the lead frame, which will be described later.

[0080] like Figures 1 to 5 、 Figure 8 as well as Figure 10 As shown in FIG. 1 , three input terminals 41 to 43 protrude from the encapsulation resin 8 in the x2 direction in semiconductor module A1. Input terminals 41 to 43 are spaced apart from one another. Input terminals 42 and 43 are located on opposite sides of input terminal 41 in the y direction. Input terminal 42 is located on the y2 side of input terminal 41, while input terminal 43 is located on the y1 side of input terminal 41. The three input terminals 41 to 43 overlap when viewed in the y direction.

[0081] As from Figure 8 as well as Figure 14 As can be understood, the two output terminals 44 are formed integrally with the second conductive portion 2B. Unlike this structure, the output terminal 44 is separated from the second conductive portion 2B, or can be conductively connected to the second conductive portion 2B. Figure 8 As shown in FIG. 1 , two output terminals 44 are located on the x1 side relative to the plurality of second semiconductor elements 10B and the second conductive portion 2B (conductive substrate 2 ). Each output terminal 44 is electrically connected to the second conductive portion 2B and, via the second conductive portion 2B, to the back surface electrode 15 (drain electrode) of each second semiconductor element 10B. These two output terminals 44 are examples of a "first output terminal" and a "second output terminal," respectively.

[0082] The output terminal 44 has an output side joint surface 441 and an output side side surface 442. The output side joint surface 441 faces the z2 direction and extends to the x1 direction. The output side side surface 442 is located at the periphery of the output side joint surface 441 when viewed in the z direction, and faces a direction intersecting the output side joint surface 441. In this embodiment, the output side side surface 442 includes a front end surface 443 and a pair of side surfaces 444. The front end surface 443 is located at the x1 side end of the output terminal 44 and faces the x1 direction. The pair of side surfaces 444 are located at the y ends of the output terminal 44 and face the y1 and y2 directions. In the output side side surface 442, at least one of the front end surface 443 and the pair of side surfaces 444 has an output side processing mark. The output side processing mark is formed by the cutting process of the lead frame described later. In addition, the number of output terminals 44 is not limited to two, and for example, it can be one or more than three. For example, when there is only one output terminal 44 , it is desirable to connect it to the center portion of the second conductive portion 2B in the y direction.

[0083] The plurality of control terminals 45 are pin-shaped terminals used to control each semiconductor element 10. The plurality of control terminals 45 include a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D. The plurality of first control terminals 46A to 46E are used to control each first semiconductor element 10A. The plurality of second control terminals 47A to 47D are used to control each second semiconductor element 10B.

[0084] The plurality of first control terminals 46A to 46E are arranged at intervals in the y direction. Figure 8 as well as Figure 14 As shown in FIG. 1 and FIG. 2 , each of the first control terminals 46A to 46E is supported on the first conductive portion 2A via a control terminal support 5 (a first support portion 5A described later). Figure 5 as well as Figure 8 As shown, in the x-direction, each of the first control terminals 46A to 46E is located between the plurality of first semiconductor elements 10A and the three input terminals 41 to 43 .

[0085] The first control terminal 46A is a terminal (gate terminal) for inputting a drive signal to the plurality of first semiconductor elements 10A. A drive signal (eg, a gate voltage) for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A.

[0086] The first control terminal 46B is a terminal (source sense terminal) for detecting source signals of the plurality of first semiconductor elements 10A. The first control terminal 46B detects the voltage (voltage corresponding to the source current) applied to each second main surface electrode 12 (source electrode) of the plurality of first semiconductor elements 10A.

[0087] The first control terminal 46C and the first control terminal 46D are terminals electrically connected to the diode function portion D1. The first control terminal 46C is electrically connected to the third main surface electrode 13 of the first semiconductor element 10A having the diode function portion D1, and the first control terminal 46D is electrically connected to the fourth main surface electrode 14 of the first semiconductor element 10A having the diode function portion D1.

[0088] The first control terminal 46E is a terminal (drain sense terminal) for detecting drain signals of the plurality of first semiconductor elements 10A. The first control terminal 46E detects the voltage (voltage corresponding to the drain current) applied to each back electrode 15 (drain electrode) of the plurality of first semiconductor elements 10A.

[0089] The plurality of second control terminals 47A to 47D are arranged at intervals in the y direction. Figure 5 as well as Figure 18 As shown in FIG. 1 and FIG. 2 , each of the second control terminals 47A to 47D is supported on the second conductive portion 2B via a control terminal support 5 (a second support portion 5B described later). Figure 5 as well as Figure 8 As shown, in the x-direction, each of the second control terminals 47A to 47D is located between the plurality of second semiconductor elements 10B and the two output terminals 44 .

[0090] Each of the plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) includes a bracket 451 and a metal pin 452 .

[0091] The bracket 451 is made of conductive material. Figure 15As shown, the bracket 451 is bonded to the control terminal support 5 (the first metal layer 52 described later) via a conductive bonding material 459. The bracket 451 includes a cylindrical portion, an upper flange portion, and a lower flange portion. The upper flange portion is connected to the upper portion of the cylindrical portion, and the lower flange portion is connected to the lower portion of the cylindrical portion. A metal pin 452 is inserted through at least the upper flange portion and the cylindrical portion of the bracket 451. The upper surface of the upper flange portion is exposed from the sealing resin 8 (the second protrusion 852 described later) and is covered by the resin portion 87.

[0092] The metal pin 452 is a rod-shaped member extending in the z direction. The metal pin 452 is supported by being pressed into the bracket 451. The metal pin 452 is electrically connected to the control terminal support 5 (the first metal layer 52 described later) at least via the bracket 451. Figure 15 As shown in the example, when the lower end (end on the z1 direction side) of the metal pin 452 contacts the conductive bonding material 459 in the insertion hole of the bracket 451 , the metal pin 452 is electrically connected to the control terminal support 5 via the conductive bonding material 459 .

[0093] The control terminal support 5 supports the plurality of control terminals 45 . The control terminal support 5 is interposed between the main surface 201 (conductive substrate 2 ) and the plurality of control terminals 45 .

[0094] The control terminal support body 5 includes a first support portion 5A and a second support portion 5B. The first support portion 5A is disposed on the first conductive portion 2A of the conductive substrate 2 and supports a plurality of first control terminals 46A to 46E among the plurality of control terminals 45. Figure 15 As shown, the first support portion 5A is bonded to the first conductive portion 2A via a bonding material 59. The bonding material 59 can be either conductive or insulating, and for example, solder is used. The second support portion 5B is disposed on the second conductive portion 2B of the conductive substrate 2 and supports the second control terminals 47A to 47D of the plurality of control terminals 45. The second support portion 5B is bonded to the second conductive portion 2B via the bonding material 59.

[0095] The control terminal support body 5 (each of the first support portion 5A and the second support portion 5B) is formed of, for example, a DBC substrate and includes an insulating layer 51, a first metal layer 52, and a second metal layer 53 stacked on top of each other.

[0096] The insulating layer 51 is made of, for example, ceramics and has, for example, a rectangular shape in a plan view.

[0097] like Figure 15 As shown in FIG. 1 , the first metal layer 52 is formed on the upper surface of the insulating layer 51. Each control terminal 45 is vertically arranged on the first metal layer 52. The first metal layer 52 is, for example, Cu or a Cu alloy. Figure 8As shown in FIG. 5 , the first metal layer 52 includes a first portion 521, a second portion 522, a third portion 523, a fourth portion 524, and a fifth portion 525. The first portion 521, the second portion 522, the third portion 523, the fourth portion 524, and the fifth portion 525 are spaced apart and insulated from each other.

[0098] The first portion 521 is bonded to a plurality of metal wires 731 and is electrically connected to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 via each metal wire 731. Figure 8 As shown, the first control terminal 46A is engaged with the first portion 521 of the first support portion 5A, and the second control terminal 47A is engaged with the first portion 521 of the second support portion 5B.

[0099] The second portion 522 is bonded to a plurality of metal wires 732 and is electrically connected to the second main surface electrode 12 (source electrode) of each semiconductor element 10 via each metal wire 732. Figure 8 As shown, the first control terminal 46B is engaged with the second portion 522 of the first support portion 5A, and the second control terminal 47B is engaged with the second portion 522 of the second support portion 5B.

[0100] The third portion 523 is bonded to the metal wire 733 and is electrically connected to the third main surface electrode 13 of the semiconductor element 10 having the diode function portion D1 via the metal wire 733. Figure 8 As shown, the first control terminal 46C is engaged with the third portion 523 of the first support portion 5A, and the second control terminal 47C is engaged with the third portion 523 of the second support portion 5B.

[0101] The fourth portion 524 is bonded to the metal wire 734 and is electrically connected to the fourth main surface electrode 14 of the semiconductor element 10 having the diode function portion D1 via the metal wire 734. Figure 8 As shown, the first control terminal 46D is engaged with the fourth portion 524 of the first support portion 5A, and the second control terminal 47D is engaged with the fourth portion 524 of the second support portion 5B.

[0102] The fifth portion 525 of the first supporting portion 5A is connected to the metal wire 735 and is electrically connected to the first conductive portion 2A via the metal wire 735. The fifth portion 525 of the second supporting portion 5B is not electrically connected to other structural parts. Figure 8 As shown, the first control terminal 46E is engaged with the fifth portion 525 of the first support portion 5A.

[0103] like Figure 15 As shown in FIG. 1 , the second metal layer 53 is formed on the lower surface of the insulating layer 51. Figure 15 As shown, the second metal layer 53 of the first support portion 5A is bonded to the first conductive portion 2A via a bonding material 59 .

[0104] The second metal layer 53 of the second supporting portion 5B is bonded to the second conductive portion 2B via a bonding material 59 .

[0105] The conductive component 6, together with the conductive substrate 2, forms a path for the main circuit current switched by the plurality of semiconductor elements 10. The conductive component 6 is spaced apart from the main surface 201 (conductive substrate 2) in the z2 direction and overlaps with the main surface 201 when viewed from above. In the present embodiment, the conductive component 6 is formed of a metal plate. The metal is, for example, Cu or a Cu alloy. Specifically, the conductive component 6 is a bent metal plate. Not limited to this, the conductive component 6 may also be formed of a metal foil. In the present embodiment, the conductive component 6 includes a plurality of first conductive components 61 and a second conductive component 62. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current is a current having a path between the input terminal 41 and the output terminal 44. The second main circuit current is a current having a path between the output terminal 44 and the input terminals 42 and 43.

[0106] The plurality of first conductive members 61 are respectively bonded to the second main surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 2B, thereby electrically connecting the second main surface electrode 12 of each first semiconductor element 10A to the second conductive portion 2B. Figure 8 ), and each first conductive component 61 and the second conductive portion 2B are bonded via a conductive bonding material 69. The conductive bonding material 69 is, for example, solder, metal paste, or sintered metal. Figure 8 As shown, each first conductive member 61 is in a strip shape extending in the x-direction in a plan view.

[0107] In this embodiment, if Figure 6 As shown in FIG. 1 , each first conductive component 61 has an opening 61h formed in the rectangular portion connecting each first semiconductor element 10A to the second conductive portion 2B. The opening 61h is preferably formed in the center of the rectangle when viewed from above, and is, for example, a through-hole extending in the z-direction. When a fluid resin material is injected to form the encapsulating resin, the opening 61h is formed near each first conductive component 61 to facilitate the flow of the resin material between the upper side (z2 direction) and the lower side (z1 direction). The planar shape of the opening 61h can be a perfect circle, an ellipse, a rectangle, or other shapes. The shape of the first conductive component 61 is not limited to this configuration; for example, the opening 61h may not be formed.

[0108] In this embodiment, three first conductive members 61 are provided to correspond to the number of first semiconductor elements 10A. As a modification, a single first conductive member 61 common to the plurality of first semiconductor elements 10A may be used regardless of the number of the plurality of first semiconductor elements 10A.

[0109] The second conductive member 62 provides electrical connection between the second main surface electrode 12 of each second semiconductor element 10B and each input terminal 42, 43. The maximum dimension of the second conductive member 62 in the x-direction is, for example, 25 mm to 40 mm (preferably about 32 mm), and the maximum dimension in the y-direction is, for example, 30 mm to 45 mm (preferably about 38 mm). Figure 6 As shown, the second conductive member 62 includes a first wiring portion 621 , a second wiring portion 622 , a third wiring portion 623 and a fourth wiring portion 624 .

[0110] The first wiring portion 621 is connected to the input terminal 42. The first wiring portion 621 and the input terminal 42 are bonded together by a conductive bonding material 69. The first wiring portion 621 is a strip-shaped portion extending in the x-direction in a plan view.

[0111] The second wiring portion 622 is connected to the input terminal 43. The second wiring portion 622 and the input terminal 43 are bonded together using a conductive bonding material 69. The second wiring portion 622 is a strip-shaped portion extending in the x-direction when viewed from above. The first wiring portion 621 and the second wiring portion 622 are spaced apart in the y-direction and arranged substantially parallel to each other. The second wiring portion 622 is located in the y1 direction relative to the first wiring portion 621.

[0112] The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622. The third wiring portion 623 is a strip-shaped portion extending in the y direction when viewed from above. Figure 6 As can be understood, the third wiring portion 623 overlaps with the plurality of second semiconductor elements 10B in a plan view. Figure 17 As shown in FIG. 1 , the third wiring portion 623 is connected to each second semiconductor element 10B. The third wiring portion 623 has a plurality of concave regions 623a. Figure 17 As shown, each concave region 623a protrudes further in the z1 direction than other parts of the third wiring portion 623. Each concave region 623a in the third wiring portion 623 is bonded to each second semiconductor element 10B. Each concave region 623a in the third wiring portion 623 is bonded to the second main surface electrode 12 (see FIG. Figure 8 ) are joined via a conductive bonding material 69.

[0113] The fourth wiring section 624 is connected to both the first wiring section 621 and the second wiring section 622. In addition, the fourth wiring section 624 is connected to the third wiring section 623. The fourth wiring section 624 is located closer to the x2 direction than the third wiring section 623. Figure 6 As can be understood, the fourth wiring portion 624 overlaps with the plurality of first semiconductor elements 10A in a plan view. The fourth wiring portion 624 includes a first strip-shaped portion 625 and a plurality of second strip-shaped portions 626.

[0114] The first strip portion 625 is spaced apart from the third wiring portion 623 in the x direction and is a strip-shaped portion of the fourth wiring portion 624 when viewed from above. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622. The first strip portion 625 overlaps with the plurality of first semiconductor elements 10A when viewed from above. The first strip portion 625 has a plurality of convex regions 625a. Figure 16 As shown, each convex region 625a protrudes further in the z2 direction than other parts of the first strip portion 625. Figure 6 As shown in FIG. 1 , each convex region 625a overlaps with each first semiconductor element 10A in a plan view. Figure 16 As shown, the first strip portion 625 has a plurality of convex regions 625a, so that each first semiconductor element 10A has a region that is bonded to each first conductive member 61. This prevents the first strip portion 625 from contacting each first conductive member 61.

[0115] Multiple second strips 626 are connected to the first strip 625 and the third wiring section 623, respectively. Each second strip 626 is strip-shaped, extending in the x-direction when viewed from above. The multiple second strips 626 are spaced apart in the y-direction and arranged substantially parallel to each other. When viewed from above, one end of each of the multiple second strips 626 is connected between two adjacent first semiconductor elements 10A in the y-direction of the first strip 625, and the other end is connected between two adjacent second semiconductor elements 10B in the y-direction of the third wiring section 623.

[0116] The first strip portion 625 has a first end edge 627 and a second end edge 628. Figure 7 As shown, the first end edge 627 is located closer to the x1 direction than the first side 191 in a plan view, and extends at least from the third side 193 to the fourth side 194 in the y direction. Therefore, in a plan view, the two corners 171 and 172 on the x2 side of each first semiconductor element 10A do not overlap with the second conductive component 62. These two corners are the angle 171 formed by the first side 191 and the third side 193, and the angle 172 formed by the first side 191 and the fourth side 194. Therefore, in each first semiconductor element 10A, in a plan view (specifically, in the Figure 7When observing as shown in FIG. 1 and FIG. 2 , the same applies to the following. ), a portion of each of the two sides sandwiching the corners 171 and 172 can be seen. Figure 7 As shown, the second edge 628 is located closer to the x2 direction than the second side 192 in a plan view and extends from at least the third side 193 to 194 in the y direction. Consequently, in a plan view, the two corners 173 and 174 on the x1 side of each first semiconductor element 10A do not overlap with the second conductive member 62. These two corners are the angle 173 formed by the second side 192 and the third side 193, and the angle 174 formed by the second side 192 and the fourth side 194. Therefore, in each first semiconductor element 10A, a portion of each of the two sides sandwiching these corners 173 and 174 is visible in a plan view.

[0117] At each of the corners 171, 172, 173, and 174, the two sides sandwiching the corners 171, 172, 173, and 174 need only be visible when viewed from above, with a length exceeding 0 μm and not exceeding 200 μm. Furthermore, the length of the visible portion of the two sides sandwiching each corner 171, 172, 173, and 174 when viewed from above is preferably between 5 μm and 150 μm. If the visible portion of the two sides sandwiching each corner 171, 172, 173, and 174 is at least 2 μm, the corner of the first semiconductor element 10A can be detected. If the visible portion of the two sides is at least 5 μm, the corner of the first semiconductor element 10A can be reliably detected. However, if the visible portion of the two sides exceeds 200 μm, the bonding area between the first conductive member 61 and the first semiconductor element 10A becomes unnecessarily small, which is not preferred. If the upper limit of the length of the visible portion of the two sides is 150 μm or less, it is possible to avoid the bonding area between the first conductive member 61 and the first semiconductor element 10A from becoming too small, which is preferable.

[0118] like Figure 6 As shown, the conductive component 6 (the first conductive component 61 and the second conductive component 62) has a first portion 601. The first portion 601 is a region that overlaps with the semiconductor element 10 (either the plurality of first semiconductor elements 10A or the plurality of second semiconductor elements 10B) when viewed from above. In the second conductive component 62, a portion of the fourth wiring portion 624 (the region that overlaps with the plurality of first semiconductor elements 10A when viewed from above) and a portion of the third wiring portion 623 (the region that overlaps with the plurality of second semiconductor elements 10B when viewed from above) constitute the first portion 601.

[0119] like Figure 6 、 Figure 8As shown, the main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A (the first semiconductor element 10A having the diode functional portion D1) are arranged along the y-direction at the end portion of the first semiconductor element 10A on the x2-direction side. In a plan view, the first conductive component 61 and the second conductive component 62 do not overlap with any of the main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A, nor with any of the x2-direction corners 171 and 172. Furthermore, in a plan view, the first conductive component 61 and the second conductive component 62 do not overlap with at least one of the corners 173 and 174 on the x1-direction side (the side opposite the side where the main surface electrodes are arranged) of the first semiconductor element 10A. Consequently, at least three of the four corners 171, 172, 173, and 174 of the semiconductor element 10A are visible in a plan view. Thus, when the semiconductor element 10A, the first conductive member 61, and the second conductive member 62 are mounted on the conductive substrate 2, it is possible to perform an automated visual inspection to verify that the semiconductor element 10A is correctly mounted. When viewed from above, all four corners 171, 172, 173, and 174 of the semiconductor element 10A are visible. Furthermore, the principal surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A described above are examples of "one-side principal surface electrodes."

[0120] In addition, if Figure 6 As shown, each second semiconductor element 10B is also rectangular in plan view, similar to the first semiconductor element 10A, and has four corners 181, 182, 183, and 184 corresponding to the four corners 171, 172, 173, and 174 of the first semiconductor element 10A. The relationship between the four corners 171, 172, 173, and 174 of each first semiconductor element 10A and the first conductive member 61 and the second conductive member 62 in plan view is also similar to the relationship between the four corners 181, 182, 183, and 184 of each second semiconductor element 10B and the second conductive member 62 in plan view.

[0121] like Figure 5 As shown, the second conductive component 62 includes a first portion 62A and a second portion 62B. The first portion 62A overlaps with the main surface 201 of the conductive substrate 2 (the main surface 201 of the first conductive portion 2A or the second conductive portion 2B) when viewed from above, and does not overlap with any of the plurality of semiconductor elements 10 when viewed from above. The second portion 62B overlaps with the main surface 201 when viewed from above, and overlaps with any of the plurality of semiconductor elements 10 when viewed from above. Figure 5 In the figure, the first portion 62A is marked with a right rising hatching, and the second portion 62B is marked with a right descending hatching. The first portion 62A has an opening 63. Figure 5 as well as Figure 13As shown in FIG. 1 , the opening 63 is a portion that has been partially removed when viewed from above. In this embodiment, the opening 63 overlaps with the main surface 201 of the first conductive portion 2A (conductive substrate 2) when viewed from above, and is located so as not to overlap with the plurality of semiconductor elements 10 when viewed from above. The opening 63 is, for example, a through-hole extending in the z-direction. The opening 63 includes a portion formed in the first wiring portion 621 and a portion formed in the second wiring portion 622. The opening 63 is located near at least two of the four corners of the conductive substrate 2 when viewed from above, for example, on the x2 side of each of the first wiring portion 621 and the second wiring portion 622. The planar shape of the opening 63 is not limited and can be a hole as in this embodiment, or a notch, unlike this embodiment. The opening 63 can also be produced, for example, by electroforming. In this case, the second conductive component 62 has an opening 63 formed by a portion where no metal is electrodeposited, rather than an opening 63 formed by a portion that has been removed.

[0122] In the second conductive member 62, an opening 625h is formed in a rectangular portion that overlaps with each first semiconductor element 10A in a plan view. In this embodiment, the opening 625h is preferably formed so as to overlap with the center portion of each first semiconductor element 10A in a plan view. The opening 625h is, for example, a through hole formed in each convex region 625a of the first strip portion 625 (fourth wiring portion 624) (see FIG. Figure 6 When the first conductive member 61 and the first semiconductor element 10A are bonded together, the opening 625h is used to optically confirm the bonding condition from above.

[0123] The second conductive component 62 has an opening 623h formed in a rectangular portion that overlaps with each second semiconductor element 10B in a plan view. In this embodiment, the opening 623h is preferably formed so as to overlap the center portion of the second semiconductor element 10B in a plan view. The opening 623h is, for example, a through-hole formed in each concave region 623a of the third wiring portion 623. The opening 623h is used to position the second conductive component 62 relative to the conductive substrate 2. The planar shape of the two openings 623h and 625h can be a perfect circle, an ellipse, a rectangle, or other shapes.

[0124] The shape of the second conductive member 62 is not limited to this configuration and may not include the fourth wiring portion 624. However, in order to reduce the inductance value generated by the current flowing through the second conductive member 62, it is preferable to provide the fourth wiring portion 624 in the second conductive member 62.

[0125] The first conductive bonding material 71 is interposed between the conductive substrate 2 and the support substrate 3 to electrically connect the conductive substrate 2 and the support substrate 3. The first conductive bonding material 71 includes a portion that electrically connects the first conductive portion 2A to the first portion 32A and a portion that electrically connects the second conductive portion 2B to the second portion 32B. Figure 15 As shown, the first conductive bonding material 71 includes a first base layer 711 , a first layer 712 , and a second layer 713 stacked on top of each other.

[0126] like Figure 15 As shown, the side surface of the first conductive bonding material 71 and the side surface of the first metal layer 32 as the uppermost layer of the support substrate 3 are most preferably on the same surface. Preferably, the side surface of the first metal layer 32 is located slightly inside the side surface of the first conductive bonding material 71 when viewed from above. That is, when viewed from above, the side surface of the first metal layer 32 is bonded in a manner that does not extend further outward than the side surface of the first conductive bonding material 71. In the case where the side surface of the first metal layer 32 extends further outward than the side surface of the first conductive bonding material 71 when viewed from above, the surface distance between the first metal layer 32 and the second metal layer 33 becomes smaller, so it is not preferred. In addition, when viewed from above, the side surface of the first metal layer 32 is arranged further outward than the side surface of the base material 21 possessed by the conductive substrate 2.

[0127] The first base layer 711 is made of metal, such as Al or an Al alloy. The first base layer 711 is a sheet material. Al (aluminum), which is a constituent material of the first base layer 711, has a Young's modulus of 70.3 GPa.

[0128] The first layer 712 is formed on the upper surface of the first base layer 711. The first layer 712 is between the first base layer 711 and the conductive substrate 2 (each of the first conductive part 2A and the second conductive part 2B). The first layer 712 is, for example, Ag-plated. The first layer 712 is bonded to the back bonding layers 23 of the first conductive part 2A and the second conductive part 2B, for example, by solid-phase diffusion of metal. That is, the first layer 712 is bonded to the back bonding layers 23 of the first conductive part 2A and the second conductive part 2B by solid-phase diffusion bonding. Thus, the first layer 712 is bonded to the back bonding layers 23 in a state where they are directly in contact with each other at the bonding interface. In addition, in the present disclosure, "A and B are bonded by solid-phase diffusion bonding" means that, as a result of implementing solid-phase diffusion bonding, A and B are fixed to each other in a state where they are directly in contact with each other at the bonding interface, and it can be said that a solid-phase diffusion bonding layer is formed by A and B. When solid-phase diffusion bonding is implemented under ideal conditions, there is a case where the bonding interface does not exist clearly due to the diffusion of metal elements. On the other hand, when an intermediary such as an oxide film exists on the surface layers of A and B, or when a void exists between A and B, these intermediaries or voids may exist at the bonding interface.

[0129] The second layer 713 is formed on the lower surface of the first base layer 711. The second layer 713 is between the first base layer 711 and the supporting substrate 3 (each of the first part 32A and the second part 32B). The second layer 713 is, for example, Ag-plated. The second layer 713 is bonded to the first bonding layer 321 formed on the first part 32A and the second part 32B, respectively, by, for example, solid-phase diffusion of metal. That is, the second layer 713 and the first bonding layer 321 are bonded by solid-phase diffusion bonding, so as to be bonded in a state of direct contact with each other at the bonding interface. The Young's modulus of Ag (silver) plating, which is the constituent material of the first layer 712 and the second layer 713, is 82.7 GPa.

[0130] In the first conductive bonding material 71, the constituent materials of the first base layer 711 and the constituent materials of the first layer 712 and the second layer 713 are the same as those described above. Therefore, the Young's modulus of the first base layer 711 is smaller than the Young's modulus of the first layer 712 and the second layer 713. The thickness (z-direction dimension) of the first base layer 711 is greater than the thickness of each of the first layer 712 and the second layer 713.

[0131] In the first conductive bonding material 71, no Ag plating is formed on the end face of the first base layer 711, which is Al or an Al alloy, and the end face of the first base layer 711 is exposed. However, Ag plating may be formed on the end face of the first base layer 711. From the perspective of reducing the manufacturing cost of the first conductive bonding material 71, it is preferred to form Ag plating on both sides of a large-area sheet and then produce the first conductive bonding material 71 by cutting the sheet with Ag plating. From this perspective, it is preferred not to form Ag plating on the end face of the first base layer 711.

[0132] The second conductive bonding material 72 is interposed between the conductive substrate 2 and each semiconductor element 10, and makes the conductive substrate 2 and each semiconductor element 10 conductively bonded. The second conductive bonding material 72 has a portion that makes each first semiconductor element 10A conductively bonded to the first conductive portion 2A and a portion that makes each second semiconductor element 10B conductively bonded to the second conductive portion 2B. Figure 15 As shown, the second conductive bonding material 72 includes a second base layer 721 , a third layer 722 , and a fourth layer 723 stacked on top of each other.

[0133] The second base layer 721 is made of metal, such as Al or Al alloy, and is a sheet material.

[0134] The third layer 722 is formed on the upper surface of the second base layer 721. The third layer 722 is interposed between the second base layer 721 and each semiconductor element 10. The third layer 722 is, for example, Ag-plated. The third layer 722 is bonded to the back electrode 15 of each semiconductor element 10, for example, by solid-phase diffusion of the metal. In other words, the third layer 722 and the back electrode 15 are bonded by solid-phase diffusion bonding, directly contacting each other at the bonding interface.

[0135] The fourth layer 723 is formed on the lower surface of the second base layer 721. The fourth layer 723 is interposed between the second base layer 721 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The fourth layer 723 is, for example, plated with Ag. The fourth layer 723 is bonded to the respective main surface bonding layers 22 of the first conductive portion 2A and the second conductive portion 2B, for example, by solid-phase diffusion of the metal. In other words, the fourth layer 723 is bonded to the respective main surface bonding layers 22 by solid-phase diffusion bonding, so that they are directly in contact with each other at the bonding interface.

[0136] In the second conductive bonding material 72, the constituent materials of the second base layer 721 and the constituent materials of the third layer 722 and the fourth layer 723 are the same as those described above. Therefore, the Young's modulus of the second base layer 721 is smaller than the Young's modulus of the third layer 722 and the fourth layer 723. The thickness (z-direction dimension) of the second base layer 721 is greater than the thickness of each of the third layer 722 and the fourth layer 723.

[0137] In the second conductive bonding material 72, no Ag plating is formed on the end faces of the second base layer 721, which is Al or an Al alloy, and the end faces of the second base layer 721 are exposed. However, Ag plating may be formed on the end faces of the second base layer 721. From the perspective of reducing the manufacturing cost of the second conductive bonding material 72, it is preferred to form Ag plating on both sides of a sheet of an area of ​​​​a certain size and then produce the second conductive bonding material 72 by cutting the sheet with Ag plating. From this perspective, it is preferred that no Ag plating is formed on the end faces of the second base layer 721.

[0138] The plurality of metal wires 731 to 735 each provide electrical conduction between two mutually spaced locations. The plurality of metal wires 731 to 735 are, for example, bonding wires. The constituent material of the plurality of metal wires 731 to 735 includes, for example, Au (gold), Al, or Cu.

[0139] like Figure 8 As shown, a plurality of metal wires 731 are respectively bonded to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 and the first portion 521 (first metal layer 52) of each control terminal support 5 to make them conductive. Figure 8As shown, the plurality of metal wires 731 include a plurality of first metal wires 731a and a plurality of second metal wires 731b. The plurality of first metal wires 731a are respectively connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A and the first portion 521 (first metal layer 52) of the first support portion 5A. Thus, the first control terminal 46A is electrically connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first metal wire 731a. The plurality of second metal wires 731b are respectively connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B and the first portion 521 (first metal layer 52) of the second support portion 5B. Thus, the second control terminal 47A is electrically connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second metal wire 731b.

[0140] like Figure 8 As shown, a plurality of metal wires 732 are bonded to the second main surface electrode 12 (source electrode) of each semiconductor element 10 and the second portion 522 (first metal layer 52) of each control terminal support 5, respectively, to provide electrical continuity between them. However, in each semiconductor element 10 having a diode function portion D1, each metal wire 732 is bonded to the fifth main surface electrode 16 (source sense electrode) instead of the second main surface electrode 12 (source electrode).

[0141] like Figure 8 As shown, a plurality of metal wires 733 are bonded to the third main surface electrode 13 of each semiconductor element 10 having the diode function portion D1 and the third portion 523 (first metal layer 52 ) of each control terminal support 5 , respectively, to establish electrical conduction therebetween.

[0142] like Figure 8 As shown, a plurality of metal wires 734 are bonded to the fourth main surface electrode 14 of each semiconductor element 10 having the diode function portion D1 and the fourth portion 524 (first metal layer 52 ) of each control terminal support 5 , thereby establishing electrical conduction therebetween.

[0143] like Figure 8 As shown, the metal wire 735 is bonded to the main surface 201 of the first conductive portion 2A (conductive substrate 2 ) and the fifth portion 525 (first metal layer 52 ) of the first support portion 5A (control terminal support 5 ), thereby establishing electrical continuity between them.

[0144] The sealing resin 8 covers the plurality of semiconductor elements 10, the conductive substrate 2, the support substrate 3 (excluding the bottom surface 302), portions of the plurality of input terminals 41 to 43, portions of the plurality of output terminals 44, portions of the plurality of control terminals 45, the control terminal support 5, the conductive component 6, and the plurality of metal wires 731 to 735. The sealing resin 8 is made of, for example, a black epoxy resin. The sealing resin 8 is formed, for example, by molding as described later. The dimensions of the sealing resin 8 in the x-direction are, for example, approximately 35 mm to 60 mm, in the y-direction are, for example, approximately 35 mm to 50 mm, and in the z-direction are, for example, approximately 4 mm to 15 mm. The above dimensions are the sizes of the largest portions along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831 to 834.

[0145] like Figure 9 、 Figure 11 as well as Figure 12 As shown in FIG. 1 , the resin main surface 81 and the resin back surface 82 are spaced apart in the z direction. The resin main surface 81 faces the z2 direction, and the resin back surface 82 faces the z1 direction. A plurality of control terminals 45 (a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D) protrude from the resin main surface 81. Figure 10 As shown, the resin back surface 82 is a frame-shaped structure that surrounds the bottom surface 302 of the support substrate 3 (the lower surface of the second metal layer 33) when viewed from above. The bottom surface 302 of the support substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82. The plurality of resin side surfaces 831 to 834 are connected to both the resin main surface 81 and the resin back surface 82, and are sandwiched between them in the z direction. Figure 4 As shown in FIG. 8 , the resin side surface 831 and the resin side surface 832 are spaced apart in the x direction. The resin side surface 831 faces the x1 direction, and the resin side surface 832 faces the x2 direction. Two output terminals 44 protrude from the resin side surface 831, and three input terminals 41 to 43 protrude from the resin side surface 832. Figure 4 As shown in FIG. 8 , the resin side surface 833 and the resin side surface 834 are spaced apart in the y direction. The resin side surface 833 faces the y1 direction, and the resin side surface 834 faces the y2 direction.

[0146] like Figure 4 As shown, multiple recesses 832a are formed in the resin side surface 832. Each recess 832a is recessed in the x-direction when viewed from above. The multiple recesses 832a include a portion formed between input terminals 41 and 42, and a portion formed between input terminals 41 and 43, when viewed from above. The multiple recesses 832a are provided to increase the creepage distance between input terminals 41 and 42 along the resin side surface 832, as well as the creepage distance between input terminals 41 and 43 along the resin side surface 832.

[0147] like Figure 13 as well as Figure 14 As shown in FIG. 1 and FIG. 2 , the sealing resin 8 includes a plurality of first protrusions 851 , a plurality of second protrusions 852 , and a resin cavity 86 .

[0148] Multiple first protrusions 851 protrude from the resin main surface 81 in the z-direction. The multiple first protrusions 851 are arranged near the four corners of the sealing resin 8 when viewed from above. A first protruding end surface 851a is formed at the tip (end in the z2 direction) of each first protrusion 851. Each first protruding end surface 851a of the multiple first protrusions 851 is approximately parallel to the resin main surface 81 and lies on the same plane (x-y plane). Each first protrusion 851 has, for example, a hollow-bottomed truncated cone shape. In a device utilizing power generated by the semiconductor module A1, when the semiconductor module A1 is mounted on a control circuit board or the like included in the device, the multiple first protrusions 851 serve as spacers. Each of the multiple first protrusions 851 has a recessed portion 851b and an inner wall surface 851c formed in the recessed portion 851b. Each first protrusion 851 can be cylindrical in shape, preferably cylindrical. The shape of the recess 851b is preferably cylindrical, and the inner wall surface 851c is a single perfect circle in a plan view. Each first protrusion 851 is an example of a "protrusion", and each first protrusion end surface 851a is an example of a "protrusion end surface".

[0149] The semiconductor module A1 may be mechanically fixed to a control circuit board or the like by screwing or other methods. In this case, the inner wall surface 851c of the recessed portion 851b in the plurality of first protrusions 851 may be formed with a screw thread. Alternatively, an embedded nut may be embedded in the recessed portion 851b in the plurality of first protrusions 851.

[0150] like Figure 14 As shown in FIG. 1 , multiple second protrusions 852 protrude from the resin main surface 81 in the z-direction. The multiple second protrusions 852 overlap the multiple control terminals 45 when viewed from above. The metal pins 452 of the multiple control terminals 45 protrude from each second protrusion 852. A portion of the bracket 451 (the upper surface of the upper flange) is exposed from the upper end surface of each second protrusion 852. Each second protrusion 852 is truncated conical in shape. A resin portion 87 is disposed on each second protrusion 852.

[0151] like Figure 13As shown, resin void 86 extends from resin principal surface 81 in the z-direction through recess 201a formed in principal surface 201 of conductive substrate 2. Resin void 86 is formed in a tapered shape with its cross-sectional area decreasing as it moves toward the z-direction from resin principal surface 81 in recess 201a. The resin void edge 861 of resin void 86, which contacts principal surface 201, and the recess edge 201b of recess 201a, which contacts principal surface 201, coincide with each other. Resin void 86 is formed during the molding process described later and is the portion where sealing resin 8 is not formed during this molding process.

[0152] The resin portion 87 is provided on the second protrusion 852 of the sealing resin 8. The resin portion 87 covers a portion of the bracket 451 (the upper surface of the upper flange portion) and a portion of the metal pin 452 that are exposed from the sealing resin 8 in each control terminal 45. The resin portion 87 is made of, for example, epoxy resin, similar to the sealing resin 8, but may also be made of a material different from the sealing resin 8.

[0153] The resin filling portion 88 fills the resin gap 86 so as to fill the resin gap 86. The resin filling portion 88 is made of, for example, epoxy resin like the sealing resin 8, but may be made of a material different from that of the sealing resin 8.

[0154] Below, refer to Figures 21 to 29 A method for manufacturing the semiconductor module A1 will be described. Figure 21 It is a plan view showing one step of the method for manufacturing the semiconductor module A1. Figure 22 It is a schematic cross-sectional view showing one step of a method for manufacturing the semiconductor module A1. Figure 23 It is a plan view showing one step of the method for manufacturing the semiconductor module A1. Figure 24 This is a cutaway end view showing one step of a method for manufacturing the semiconductor module A1. Figure 24 and Figure 13 The cross section shown corresponds. Figure 25 as well as Figure 28 This is an enlarged cross-sectional view of a main part of a process of the manufacturing method of the semiconductor module A1, and an enlarged cross-sectional view of the main part of the semiconductor module A1 Figure 13 The figure corresponds to a portion of the cross section shown. Figure 26 、 Figure 27 as well as Figure 29 This is an enlarged cross-sectional view of a main part of a process of the manufacturing method of the semiconductor module A1, and an enlarged cross-sectional view of the main part of the semiconductor module A1 Figure 14 The figure corresponds to a portion of the cross section shown.

[0155] First, prepare a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, and a plurality of output terminals 44. The structures of the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are as described above. In the stage of preparing the above components, the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are prepared separately and are not bonded to each other. In addition, as Figure 21 As shown in FIG. 1 , the conductive substrate 2, the plurality of input terminals 41 to 43, and the plurality of output terminals 44 are connected to each other and are formed of, for example, the same lead frame. Figure 21 As shown, no recess 201 a is formed on the main surface 201 of the conductive substrate 2 .

[0156] Then, if Figure 22 As shown, the conductive substrate 2 is placed on the support substrate 3 via the first conductive bonding material 71, and each semiconductor element 10 is placed on the conductive substrate 2 via the second conductive bonding material 72. Then, the lower surface of the support substrate 3 and the upper surface of each semiconductor element 10 are clamped (see Figure 22 The semiconductor elements 10 are bonded to the conductive substrate 2 by solid-phase diffusion, and the conductive substrate 2 is bonded to the support substrate 3 by solid-phase diffusion. Specifically, the first bonding layer 321 (support substrate 3) on the first metal layer 32 and the second layer 713 (first conductive bonding material 71), the first layer 712 (first conductive bonding material 71) and the back bonding layer 23 (conductive substrate 2), the fourth layer 723 (second conductive bonding material 72) and the main surface bonding layer 22 (conductive substrate 2), and the third layer 722 (second conductive bonding material 72) and the back electrode 15 of each semiconductor element 10 are bonded to each other by solid-phase diffusion. Under the conditions of solid-phase diffusion, the heating temperature during bonding can be in the range of 200°C to 350°C, and the pressure applied during bonding (the above-mentioned clamping force) can be in the range of 1 MPa to 100 MPa. Solid-phase diffusion is assumed to be carried out in the atmosphere, but it can also be carried out in a vacuum. Thus, the conductive substrate 2 is bonded to the support substrate 3 via the first conductive bonding material 71, and each semiconductor element 10 is bonded to the conductive substrate 2 via the second conductive bonding material 72. Furthermore, the bonding between the conductive substrate 2 and the support substrate 3 and the bonding between the conductive substrate 2 and each semiconductor element 10 can be performed separately rather than simultaneously. However, in order to improve manufacturing efficiency, it is preferable to perform them simultaneously.

[0157] like Figure 16 as well as Figure 17 As shown, when each semiconductor element 10 is placed on the conductive substrate 2 with the second conductive bonding material 72 interposed therebetween, a separate second conductive bonding material 72 corresponding to each semiconductor element 10 is arranged. Figure 16 The three semiconductor elements 10 shown share a common corresponding second conductive bonding material 72 .

[0158] Then, if Figure 23 As shown, the control terminal supports 5 are bonded, the holders 451 of the control terminals 45 are bonded, the wires 731 to 735 are wire-bonded, the first conductive members 61 are bonded, and the second conductive member 62 is bonded. The order of the above-mentioned processes is not limited.

[0159] Next, the sealing resin 8 is formed. The sealing resin 8 is formed by, for example, molding. Figure 24 As shown, the metal mold 91 used in the molding is provided with a pressing pin 911 as a pressing component. The front end of the pressing pin 911 is in contact with the main surface 201 of the conductive substrate 2. At this time, the pressing force of the pressing pin 911 on the main surface 201 is used to form a recessed portion 201a on the main surface 201. The degree of depression (depth) of the recessed portion 201a is changed by the size of the pressing force, etc. In addition, the pressing pin 911 in contact with the main surface 201 in the first conductive part 2A is inserted into the opening 63 of the second conductive part 62. Then, a fluid resin material is injected into the cavity space 919 of the metal mold 91 through the resin flow path and the resin injection port (both omitted in the figure). The fluid resin material after injection is solidified to form a sealing resin 8. As shown Figure 25 as well as Figure 26 As shown in FIG. 8 , the formed sealing resin 8 has the first protrusion 851, the second protrusion 852, and the resin void 86. Figure 25 As shown, the resin cavity portion edge 861 in contact with the main surface 201 in the resin cavity portion 86 and the recess portion edge 201b in contact with the main surface 201 in the recess portion 201a are aligned with each other. Figure 26 As shown, the upper surface of the bracket 451 is exposed from the second protrusion 852 and is flush with the upper surface of the second protrusion 852. Figure 24 as well as Figure 25 As can be understood, the resin void 86 is formed by using a non-fluid resin material filled with a pressing pin 911. Alternatively, the pressing pin 911 may be a movable pin. In this case, the pressing pin 911 is preferably disposed in a hole formed in the mold 91 and elastically supported. The pressing member is not limited to a pin; a block-shaped pressing member may also be used.

[0160] Next, the metal mold 91 is opened to remove the lead frame including the conductive substrate 2 and the molded body including the sealing resin 8. The sealing resin 8 is then separated from the resin solidified in the resin flow path and the resin injection port. In this process, resin separation marks are formed on the resin side surface 831 on the x1 side of the sealing resin 8 at any of the following positions. The first position is Figure 1 In the resin side surface 831 shown, at two positions near the two ends in the y direction, or at least one of the corners at the two ends. In the case where resin separation marks are formed at the corners at both ends, resin separation marks are formed on the surface formed at the corner (the portion chamfered into a C shape when viewed from above). The above-mentioned inclined surface is included in the resin side surface 831 on the x1 side of the sealing resin 8. The second position is Figure 1 The resin side surface 831 shown is between the two output terminals 44. These resin separation lines correspond to the positions of the resin injection ports of the metal mold 91 and are formed by separating the sealing resin 8 from the resin solidified in the resin injection ports. To prevent uneven resin spread, the resin is preferably injected from the center in the y direction. In this case, a resin separation line is formed between the two output terminals 44.

[0161] Then, if Figure 27 As shown, the metal pins 452 of the plurality of control terminals 45 are pressed into the respective brackets 451. Specifically, the cylindrical portion (see Figure 26 ) are inserted while applying insertion pressure. Thus, each bracket 451 and each metal pin 452 are mechanically fixed and electrically connected. For example, soldering can also be used to electrically connect each bracket 451 and each metal pin 452. Then, as shown in FIG. Figure 28 as well as Figure 29 As shown in FIG. 8 , a resin portion 87 and a resin-filled portion 88 are formed. The resin portion 87 and the resin-filled portion 88 are formed by potting, for example.

[0162] Next, the lead frame is cut as needed to separate the plurality of input terminals 41 to 43 and the output terminal 44. Figure 21 The input terminals 41 to 43 and the output terminal 44 shown in the figure can be cut by using a metal mold or the like to cut the vicinity of the connection between each terminal and the outer frame of the lead frame (in the vicinity of the connection between each terminal and the outer frame of the lead frame). Figure 21 Here, the input terminals 41 to 43 are respectively provided with front end surfaces 413, 423, and 433 as processing marks on the input side. The output terminal 44 is provided with a front end surface 443 as a processing mark on the output side. In the case of a tie rod in the lead frame that connects the terminals adjacent in the y direction in the y direction, the tie rod can also be cut using a metal mold or the like. In this case, processing marks are formed on both sides of each terminal facing the y direction. By going through the above steps, a Figures 1 to 20 The semiconductor module A1 is shown.

[0163] The semiconductor module A1 is mounted on a control circuit board, etc. Here, each metal pin 452 is inserted into a pinhole of the circuit board on which the semiconductor module A1 is mounted and connects to a terminal surrounding the pinhole. The input terminals 41, 42, and 43, respectively, have input-side bonding surfaces 411, 421, and 431 facing one side in the z-direction (the z2 direction). Each output terminal 44 has an output-side bonding surface 441 facing one side in the z-direction (the z2 direction). The input-side bonding surfaces 411, 421, and 431 and the output-side bonding surface 441 are connected to the terminals of the circuit board on which the semiconductor module A1 is mounted, for example, using solder.

[0164] The following describes the path of current from the input terminal 41 to the output terminal 44 in the semiconductor module A1 of this embodiment. A first main circuit current flows through the path comprising the input terminal 41, the first conductive portion 2A, each first semiconductor element 10A, the first conductive component 61, the second conductive portion 2B, and each output terminal 44. The first main circuit current flows in the x-direction between the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 2B via each first conductive component 61. In the second conductive portion 2B, the first main circuit current flows in the x-direction and in a direction slightly inclined therefrom, between the portion bonded to each first conductive component 61 and each output terminal 44.

[0165] The following describes the path of the current from the output terminal 44 to the input terminals 42 and 43. The second main circuit current flows through the path comprising the output terminal 44, the second conductive portion 2B, each second semiconductor element 10B, the second conductive component 62, the input terminals 42 and 43. This path includes the second conductive component 62, and the second main circuit current flows through both the third wiring portion 623 extending in the y-direction and the first wiring portion 621 and the second wiring portion 622 connected to both ends of the third wiring portion 623 and extending in the x2 direction. Furthermore, the second main circuit current flows through the first wiring portion 621 and the second wiring portion 622, using two second strip-shaped portions 626 extending in the x-direction between the first wiring portion 621 and the second wiring portion 622, and a first strip-shaped portion 625 extending in the y-direction between the first wiring portion 621 and the second wiring portion 622 as the path.

[0166] A second main circuit current flows between the input terminals 42 and 43 and the second main surface electrodes 12 of each second semiconductor element 10B via the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, the two second strip portions 626, and the first strip portion 625 included in each second conductive member 62. The second main circuit current flows in the x-direction through the first wiring portion 621, the second wiring portion 622, and the two second strip portions 626. The direction of flow of the first main circuit current is opposite to the direction of flow of the second main circuit current.

[0167] The direction in which the first main circuit current flows in the first conductive member 61 and the direction in which the second main circuit current flows in the first wiring portion 621 , the second wiring portion 622 , and the two second strip portions 626 included in the second conductive member 62 are both in the x direction.

[0168] The functions and effects of the semiconductor module A1 are as follows.

[0169] Semiconductor module A1 includes a conductive substrate 2, multiple input terminals 41 to 43, an output terminal 44, and a conductive component 6. The conductive substrate 2 includes a first conductive portion 2A bonded to multiple first semiconductor elements 10A and a second conductive portion 2B bonded to multiple second semiconductor elements 10B. Input terminal 41 is connected to first conductive portion 2A and electrically connects to multiple first semiconductor elements 10A via first conductive portion 2A. Input terminals 42 and 43 are electrically connect to multiple second semiconductor elements 10B via second conductive component 62 (conductive component 6). Output terminal 44 is connected to second conductive portion 2B and electrically connects to multiple second semiconductor elements 10B via second conductive portion 2B. Conductive component 6 includes a first conductive component 61 that electrically connects each first semiconductor element 10A to second conductive portion 2B, and a second conductive component 62 that electrically connects each second semiconductor element 10B to input terminals 42 and 43. Multiple input terminals 41-43 are arranged on the x2 side relative to the conductive substrate 2, and output terminal 44 is arranged in the x1 direction relative to the conductive substrate 2. Furthermore, the two input terminals 42 and 43 are arranged on opposite sides of each other in the y direction, with input terminal 41 sandwiched between them. In a semiconductor module with a structure different from semiconductor module A1, if input terminal 43 is not included and input terminals 41 and 42 are arranged side by side in the y direction, there is a possibility that the path of the current flowing from input terminal 41 through each first semiconductor element 10A to output terminal 44 may deviate, and the path of the current flowing from output terminal 44 through each second semiconductor element 10B to each input terminal 42 may deviate. Therefore, semiconductor module A1 includes two input terminals 42 and 43. By sandwiching input terminal 41 between these two input terminals 42 and 43, variations in the path of current flowing from input terminal 41 through each first semiconductor element 10A to output terminal 44 can be reduced. Variations in the path of current flowing from output terminal 44 through each second semiconductor element 10B to input terminals 42 and 43 can also be reduced. This reduces the parasitic inductance component of semiconductor module A1. In other words, semiconductor module A1 has a package structure that is ideal for reducing parasitic inductance components.

[0170] In the semiconductor module A1, the upper arm current path and the lower arm current path overlap in a plan view. The upper arm current path is a path for current flowing from the input terminal 41 to the output terminal 44 via the first conductive portion 2A, each first semiconductor element 10A, each first conductive member 61, and the second conductive portion 2B. In this embodiment, Figure 5 As can be understood, the lower arm current path is a path of current flowing from the output terminal 44 to the input terminal 42 via each second semiconductor element 10B and the second conductive member 62. Figure 5As can be understood, from the x1 side to the x2 side. According to this structure, the magnetic field generated by the current along the upper arm current path and the magnetic field generated by the current along the lower arm current path cancel each other out, thereby reducing the parasitic inductance component. In particular, in semiconductor module A1, by forming the conductive component 6 (each of the plurality of first conductive components 61 and the second conductive component 62) from a metal plate, it is possible to appropriately ensure the area where the upper arm current path and the lower arm current path overlap when viewed from above. In other words, semiconductor module A1 has a preferred packaging structure in terms of reducing parasitic inductance components.

[0171] In semiconductor module A1, the second conductive member 62, which forms the lower arm current path, includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43, which are located on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps with the plurality of first semiconductor elements 10A when viewed from above. The second conductive member 62, which includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624, is arranged spaced apart from the main surface 201 (conductive substrate 2) in the z direction and overlaps a wide area of ​​the main surface 201 when viewed from above. This structure can appropriately reduce variations in the path of the current flowing from the output terminal 44 to the input terminals 42 and 43 via the second semiconductor elements 10B, and is suitable for reducing parasitic inductance components.

[0172] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x-direction. This configuration prevents the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) on which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged from increasing in size in the y-direction, thereby miniaturizing the semiconductor module A1.

[0173] The fourth wiring portion 624 of the second conductive member 62 includes a first strip-shaped portion 625 and multiple second strip-shaped portions 626. The first strip-shaped portion 625 connects to both the first and second wiring portions 621 and 622, extending in the y-direction and overlapping with the multiple first semiconductor elements 10A when viewed from above. The multiple second strip-shaped portions 626 connect to the first strip-shaped portion 625 and the third wiring portion 623, respectively, and are strip-shaped and extend in the x-direction when viewed from above. The multiple second strip-shaped portions 626 are spaced apart in the y-direction and arranged substantially parallel to each other. When viewed from above, one end of each of the multiple second strip-shaped portions 626 connects between two adjacent first semiconductor elements 10A in the y-direction of the first strip-shaped portion 625, and the other end connects between two adjacent second semiconductor elements 10B in the y-direction of the third wiring portion 623. This structure allows the fourth wiring portion 624 (second conductive member 62) to have a larger size when viewed from above. This is more preferable in terms of reducing parasitic inductance components.

[0174] The first strip-shaped portion 625 has multiple convex regions 625a that protrude further in the z2 direction than other portions. Each convex region 625a overlaps with each first semiconductor element 10A in a plan view. The configuration of the first strip-shaped portion 625 having multiple convex regions 625a prevents the first strip-shaped portion 625 from inadvertently contacting the first conductive member 61 bonded to the first semiconductor element 10A.

[0175] The third wiring portion 623 has multiple concave regions 623a that protrude further in the z1 direction than other portions. Each concave region 623a is bonded to one of the plurality of second semiconductor elements 10B. This structure allows for proper electrical connection between the third wiring portion 623 (second conductive member 62) and the plurality of second semiconductor elements 10B, while also ensuring a large size for the third wiring portion 623 (second conductive member 62) when viewed from above.

[0176] In addition to the conductive member 6 (first conductive member 61 and second conductive member 62) having the aforementioned structure, semiconductor module A1 also includes a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D for controlling the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are arranged to extend in the z-direction on the main surface 201 of the conductive substrate 2. This structure of semiconductor module A1 allows for a reduction in size when viewed from above, and is therefore suitable for achieving both a reduced parasitic inductance component and a reduced size when viewed from above.

[0177] The plurality of first control terminals 46A to 46E are supported by the first conductive portion 2A and are arranged on the x2 side relative to the plurality of first semiconductor elements 10A. The plurality of second control terminals 47A to 47D are supported by the second conductive portion 2B and are arranged on the x1 side relative to the plurality of second semiconductor elements 10B. The plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are arranged at intervals in the y direction. Thus, the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are appropriately arranged in regions corresponding to the plurality of first semiconductor elements 10A constituting the upper arm circuit and the plurality of second semiconductor elements 10B constituting the lower arm circuit. The semiconductor module A1 of this structure is more preferred in terms of achieving miniaturization while reducing parasitic inductance components.

[0178] The first semiconductor element 10A and the second semiconductor element 10B each have a first main surface electrode 11 (gate electrode) oriented in the z2 direction. The first control terminal 46A is connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first metal wire 731a. The second control terminal 47A is connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second metal wire 731b. This allows the drive signal for driving the first semiconductor element 10A (second semiconductor element 10B) having a switching function to be appropriately input to the first main surface electrode 11 via the first control terminal 46A (second control terminal 47A) and the first metal wire 731a (second metal wire 731b).

[0179] When semiconductor module A1 is mounted on a circuit board, each metal pin 452 is inserted into a pinhole in the circuit board on which semiconductor module A1 is mounted and connects to the terminals surrounding the pinhole. Input terminals 41, 42, and 43, respectively, have input-side bonding surfaces 411, 421, and 431 facing one side in the z-direction (z2 direction). Each output terminal 44 has an output-side bonding surface 441 facing one side in the z-direction (z2 direction). Input-side bonding surfaces 411, 421, and 431 and output-side bonding surface 441 are connected to the terminals of the circuit board on which semiconductor module A1 is mounted, for example, using solder. This structure allows the power circuit board, to which input terminals 41 to 43 and output terminal 44 are connected, and the control circuit board, to which each metal pin 452 is connected, to be separated in the z-direction. This arrangement firstly increases the flexibility in the placement of signal terminals in semiconductor module A1. Secondly, it increases the flexibility in routing and length of signal wiring in semiconductor module A1. Third, when using the semiconductor module A1, the user's freedom in arranging the circuit board is improved.

[0180] In semiconductor module A1, each control terminal 45 protrudes from the resin main surface 81 and extends in the z-direction. In structures different from semiconductor module A1, each control terminal 45 may be arranged to extend along a plane perpendicular to the z-direction (the x-y plane). This structure has limitations on miniaturization when viewed from above. Therefore, by arranging each control terminal 45 to extend in the z-direction, as in semiconductor module A1, semiconductor module A1 can be miniaturized when viewed from above. In other words, semiconductor module A1 constitutes a preferred package structure for achieving miniaturization when viewed from above.

[0181] In the semiconductor module A1 of this embodiment, a control terminal support 5 is interposed between each control terminal 45 and the main surface 201 (conductive substrate 2). The control terminal support 5 includes an insulating layer 51, and each control terminal 45 is supported on the conductive substrate 2 via the control terminal support 5. This structure, including the control terminal support 5, ensures insulation from the conductive substrate 2 while also properly supporting the control terminals 45 on the conductive substrate 2.

[0182] The control terminal support 5 is a laminated structure comprising an insulating layer 51, a first metal layer 52, and a second metal layer 53 stacked one on another. The control terminal 45 is bonded to the first metal layer 52 formed on the upper surface of the control terminal support 5 via a conductive bonding material 459. This structure allows the use of an existing laminated structure (e.g., a DBC substrate) as the control terminal support 5, and allows the control terminal 45 to be conductively bonded to the control terminal support 5 (first metal layer 52).

[0183] The semiconductor element 10 has an element main surface 101 facing the z2 direction and an element back surface 102 facing the z1 direction. A first main surface electrode 11 (gate electrode) is arranged on the element main surface 101. The first main surface electrode 11 of each semiconductor element 10 is connected to the first metal layer 52 (first portion 521) by a conductive metal wire 731. This allows the drive signal for driving the semiconductor element 10 having a switching function to be appropriately input to the first main surface electrode 11 via the control terminal 45, the first metal layer 52, and the metal wire 731.

[0184] Each control terminal 45 includes a bracket 451 and a metal pin 452. The bracket 451 is made of a conductive material and is configured to include a cylindrical portion. The metal pin 452 is a rod-shaped member extending in the z direction and is pressed into the bracket 451. In addition, a portion of the bracket 451 (the upper surface of the upper end flange portion) is exposed from the sealing resin 8. According to this structure, through the formation of the sealing resin 8 (molding), the bracket 451 is covered with the sealing resin 8 except for a portion (the upper end surface), and the upper end surface of the bracket 451 is exposed from the sealing resin 8. Thus, the metal pin 452 can be inserted into the bracket 451 after the sealing resin 8 is formed. Therefore, according to the structure in which the control terminal 45 includes the above-mentioned bracket 451 and the metal pin 452, it is possible to avoid the metal mold 91 used in the molding from becoming complicated, which is suitable for efficiently manufacturing the semiconductor module A1.

[0185] The semiconductor module A1 of this embodiment includes a resin portion 87 bonded to the encapsulating resin 8. The resin portion 87 covers the portion of the bracket 451 (the upper surface of the upper flange) and the portion of the metal pin 452 that is exposed from the encapsulating resin 8. This structure prevents foreign matter from entering the connection between the bracket 451 and the metal pin 452. The semiconductor module A1 having the above structure is preferred in terms of improved durability and reliability.

[0186] The sealing resin 8 has a plurality of second protrusions 852 protruding from the resin main surface 81. The plurality of second protrusions 852 surround the plurality of control terminals 45 in a plan view. Each metal pin 452 of the plurality of control terminals 45 protrudes from each second protrusion 852. A resin portion 87 is disposed on each second protrusion 852. This configuration increases the creepage distance along the resin main surface 81 between adjacent control terminals 45. This is advantageous in terms of increasing the withstand voltage of adjacent control terminals 45.

[0187] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B spaced apart from each other in the x-direction. The first conductive portion 2A is located further in the x2 direction than the second conductive portion 2B. The plurality of semiconductor elements 10 include a first semiconductor element 10A bonded to the first conductive portion 2A and a second semiconductor element 10B bonded to the second conductive portion 2B. The plurality of control terminals 45 include first control terminals 46A to 46E and second control terminals 47A to 47D. The first control terminals 46A to 46E are supported by the first conductive portion 2A and located in the x-direction between the first semiconductor element 10A and the input terminals 41 and 42, etc. The second control terminals 47A to 47D are located in the x-direction between the second semiconductor element 10B and the output terminal 44. With this configuration, the plurality of control terminals 45 (the first control terminals 46A to 46E and the second control terminals 47A to 47D) are appropriately arranged in regions corresponding to the first semiconductor element 10A constituting the upper arm circuit and the second semiconductor element 10B constituting the lower arm circuit, respectively. This structure is more preferable in terms of achieving miniaturization of the semiconductor module A1.

[0188] The sealing resin 8 has a plurality of first protrusions 851 protruding from the resin main surface 81. A first protruding end surface 851a is formed at the front end of each first protrusion 851. Each first protruding end surface 851a of the plurality of first protrusions 851 is substantially parallel to the resin main surface 81 and lies on the same plane (x-y plane). According to this structure, in a device that utilizes power generated by the semiconductor module A1, a predetermined gap can be ensured between the surface of the control circuit substrate on which the semiconductor module A1 is mounted and the resin main surface 81. Thus, even if various functional components are mounted on the surface of the control circuit substrate opposite to the semiconductor module A1, inadvertent contact between the functional components and the sealing resin 8 can be avoided.

[0189] Semiconductor module A1 includes a conductive substrate 2 to which semiconductor elements 10 are bonded. This structure allows heat generated by energizing each semiconductor element 10 to be transferred to the conductive substrate 2, and the heat transferred from each semiconductor element 10 is diffused within the conductive substrate 2. Therefore, semiconductor module A1 has a preferred packaging structure for improving heat dissipation from each semiconductor element 10.

[0190] In the semiconductor module A1, the conductive substrate 2 and the support substrate 3 are bonded via a first conductive bonding material 71. The first conductive bonding material 71 includes a first layer 712 and a second layer 713. The first layer 712 is bonded to the conductive substrate 2 by solid-phase diffusion of metal, so as to be bonded in a state where they are directly in contact with each other at the bonding interface. The second layer 713 is bonded to the support substrate 3 by solid-phase diffusion of metal, so as to be bonded in a state where they are directly in contact with each other at the bonding interface. According to this structure, the bonding strength between the conductive substrate 2 and the support substrate 3 can be improved compared to the case where the conductive substrate 2 and the support substrate 3 are bonded by a bonding material such as solder. Therefore, the semiconductor module A1 is constituted as a preferred packaging structure in terms of suppressing peeling of the conductive substrate 2 and the support substrate 3.

[0191] In the semiconductor module A1, each semiconductor element 10 is bonded to the conductive substrate 2 via a second conductive bonding material 72. The second conductive bonding material 72 includes a third layer 722 and a fourth layer 723. The third layer 722 is bonded to each semiconductor element 10 (back electrode 15) by solid-phase diffusion of metal, so as to be bonded in a state where they are directly in contact with each other at the bonding interface. The fourth layer 723 is bonded to the conductive substrate 2 by solid-phase diffusion of metal, so as to be bonded in a state where they are directly in contact with each other at the bonding interface. According to this structure, the bonding strength between each semiconductor element 10 and the conductive substrate 2 can be improved compared to the case where each semiconductor element 10 and the conductive substrate 2 are bonded by a bonding material such as solder. Therefore, the semiconductor module A1 is constituted as a preferred packaging structure in terms of suppressing peeling between each semiconductor element 10 and the conductive substrate 2.

[0192] In the semiconductor module A1 of this embodiment, the Young's modulus of the first base layer 711 in the first conductive bonding material 71 is lower than the Young's modulus of the materials constituting the first layer 712 and the second layer 713. This structure allows the first conductive bonding material 71 to be bonded to the conductive substrate 2 and the support substrate 3 via solid-phase diffusion, while the relatively soft first base layer 711 can alleviate stress and smoothen the bond boundary. This allows for a more secure bond between the first layer 712 and the conductive substrate 2, and between the second layer 713 and the support substrate 3, via solid-phase diffusion.

[0193] Furthermore, in this embodiment, the thickness of the first base layer 711 is greater than the thickness of each of the first layer 712 and the second layer 713. Consequently, when solid-phase diffusion bonding is employed, the pressing force acting on the boundary between the first layer 712 and the conductive substrate 2 (back bonding layer 23), and on the boundary between the second layer 713 and the supporting substrate 3 (first bonding layer 321), becomes more uniform. Consequently, the first layer 712 and the conductive substrate 2, and the second layer 713 and the supporting substrate 3, can each achieve a more secure conductive bond.

[0194] The first layer 712 and the second layer 713 are each made of a material containing silver. This structure suppresses oxidation of the first layer 712 and the second layer 713 during solid-phase diffusion bonding using the first conductive bonding material 71, enabling excellent solid-phase diffusion bonding. Furthermore, the back bonding layer 23 and the first bonding layer 321, which are bonded to the first layer 712 and the second layer 713, also contain silver, enabling even better solid-phase diffusion bonding.

[0195] In this embodiment, the Young's modulus of the second base layer 721 in the second conductive bonding material 72 is smaller than the Young's modulus of the materials constituting the third layer 722 and the fourth layer 723. With this structure, when the second conductive bonding material 72 is bonded to the semiconductor element 10 (back electrode 15) and the conductive substrate 2 via solid-phase diffusion, the relatively soft second base layer 721 can alleviate stress and smooth the bonding boundary. As a result, the third layer 722 and the semiconductor element 10 (back electrode 15), and the fourth layer 723 and the conductive substrate 2, are more firmly bonded via solid-phase diffusion.

[0196] Furthermore, in this embodiment, the thickness of the second base layer 721 is greater than the thickness of each of the third layer 722 and the fourth layer 723. Consequently, during solid-phase diffusion bonding, the pressing force acting on the boundary between the third layer 722 and the semiconductor element 10 (back electrode 15), and on the boundary between the fourth layer 723 and the conductive substrate 2 (main surface bonding layer 22), becomes more uniform. Consequently, the third layer 722 and the semiconductor element 10 (back electrode 15), and the fourth layer 723 and the conductive substrate 2, respectively, can achieve a more robust conductive bond.

[0197] The third layer 722 and the fourth layer 723 are each composed of silver. This structure suppresses oxidation of the third and fourth layers 722, 723 during solid-phase diffusion bonding using the second conductive bonding material 72, enabling excellent solid-phase diffusion bonding. Furthermore, the back electrode 15 and the main surface bonding layer 22, which are bonded to the third and fourth layers 722, 723, also contain silver, enabling even better solid-phase diffusion bonding.

[0198] The first conductive bonding material 71 has a structure in which a first layer 712 and a second layer 713, which are Ag-plated layers, are laminated on the surfaces (both sides) of a first base layer 711 made of a sheet material containing Al. Furthermore, the second conductive bonding material 72 also has a structure in which a third layer 722 and a fourth layer 723, which are Ag-plated layers, are laminated on the surfaces (both sides) of a second base layer 721 made of a sheet material containing Al. This structure makes it easy to prepare the first conductive bonding material 71 and the second conductive bonding material 72.

[0199] In semiconductor module A1, openings 63 are formed in the second conductive member 62. Openings 63 overlap with the main surface 201 (conductive substrate 2) when viewed from above, but do not overlap with the semiconductor elements 10 when viewed from above. This structure allows pressing pins 911 provided on the mold 91 to be inserted through openings 63 during the molding process (the process of forming the encapsulating resin 8) in the manufacturing process of semiconductor module A1. This allows pressing pins 911 to press the conductive substrate 2 without interfering with the second conductive member 62, thereby suppressing warping of the support substrate 3 to which the conductive substrate 2 is bonded. This warping can occur, for example, by positioning the outer sides of the support substrate 3 in the y-direction above its center in the y-direction. If this occurs in the support substrate 3, there is a concern that the bonding strength between the conductive substrate 2 and the support substrate 3 may be reduced. Furthermore, during molding, resin leakage may cause a portion of the encapsulating resin 8 to form on the bottom surface 302, potentially leading to poor bonding of heat dissipation components (such as heat sinks) bonded to the bottom surface 302. Therefore, the semiconductor module A1 is a preferred packaging structure in terms of improving the bonding strength between the conductive substrate 2 and the support substrate 3 by suppressing warping of the support substrate 3, and is also a preferred packaging structure in terms of suppressing leakage of the sealing resin 8 to undesirable locations.

[0200] The conductive substrate 2 includes a first conductive portion 2A bonded to a plurality of first semiconductor elements 10A, and a second conductive portion 2B bonded to a plurality of second semiconductor elements 10B. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x-direction, with the first conductive portion 2A positioned closer to the second conductive portion 2B in the x2 direction. A second conductive member 62 connects the plurality of second semiconductor elements 10B and the input terminals 42 and 43. An opening 63 provided in the second conductive member 62 overlaps the main surface 201 of the first conductive portion 2A in a plan view. This structure allows for a large plan view dimension of the second conductive member 62, while preventing interference with the encapsulating resin 8 during molding. Furthermore, the conductive substrate 2 can be pressed by the pressing pins 911 provided on the mold 91. Furthermore, by increasing the plan view dimension of the second conductive member 62, the parasitic resistance component of the second conductive member 62 (conductive member 6) that forms the path for the main circuit current can be suppressed.

[0201] The second conductive component 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to the input terminals 42 and 43, which are arranged on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The opening 63 is formed in each of the first wiring portion 621 and the second wiring portion 622 at a position close to the x2 direction. Thus, the opening 63 is located near the two outer corners of the conductive substrate 2 (first conductive portion 2A) in the y direction when viewed from above. Therefore, the opening 63 is located near the two outer corners of the support substrate 3 that supports the conductive substrate 2 (first conductive portion 2A) in the y direction when viewed from above. This structure ensures a relatively large size for the second conductive member 62 in a plan view. Furthermore, during the formation of the sealing resin 8 (during molding), the pressing pins 911 provided on the metal mold 91 can be inserted through the openings 63 to press the conductive substrate 2 (first conductive portion 2A) near the outer corners in the y direction. As described above, warping of the support substrate 3 to which the conductive substrate 2 is bonded occurs when the outer corners in the y direction of the support substrate 3 are positioned above the center in the y direction. This structure effectively suppresses warping of the support substrate 3 during molding.

[0202] In this embodiment, the conductive member 6 (the first conductive member 61 and the second conductive member 62) is formed from a metal plate. This facilitates forming the opening 63 in the second conductive member 62. Furthermore, the conductive member 6 (the first conductive member 61 and the second conductive member 62) formed from a metal plate can be easily adapted to various shapes and sizes, and by ensuring sufficient bonding area with other parts, the reliability of the bonding with other parts can be improved.

[0203] Recesses 201a are formed in the main surface 201 of the conductive substrate 2 (first conductive portion 2A) at locations overlapping with the openings 63 when viewed from above. Each recess 201a is a trace of the pressing force applied to the main surface 201 by the pressing pins 911 during molding. In this embodiment, the arrangement of the second conductive member 62 and the openings 63 formed therein is carefully considered. This allows for the pressing pins 911 to press the appropriate locations of the conductive substrate 2 (first conductive portion 2A) while avoiding interference with functional elements such as the semiconductor device 10 during molding.

[0204] A resin void portion 86 is formed in the sealing resin 8, extending from the resin main surface 81 through the recess 201a. The resin void portion 86 is tapered, and its cross-sectional area decreases as it moves from the resin main surface 81 toward the recess 201a. This resin void portion 86 is formed during molding (when the sealing resin 8 is formed). After molding, the surface of the recess 201a in the main surface 201 of the conductive substrate 2 is exposed from the sealing resin 8. In addition, in this embodiment, a resin filling portion 88 is filled in the resin void portion 86 in such a manner as to fill the resin void portion 86. According to this structure, it is possible to prevent foreign matter (including moisture) from intruding into the recess 201a exposed from the sealing resin 8. The semiconductor module A1 having the above structure is preferred in terms of improving durability and reliability.

[0205] In this embodiment, each opening 63 formed in the second conductive member 62 (conductive member 6) is a through-hole extending in the z-direction. This configuration reduces the current path bias caused by the openings 63 in the second conductive member 62 (conductive member 6), which forms the path for the main circuit current.

[0206] Semiconductor module A1 includes a conductive component 6. The conductive component 6 forms a path for the main circuit current switched by each semiconductor element 10. The conductive component 6 includes first conductive components 61 connected to each first semiconductor element 10A and second conductive components 62 connected to each second semiconductor element 10B. The conductive component 6 (each first conductive component 61 and each second conductive component 62) is formed from a metal plate. The main circuit current may sometimes reach a relatively large value. In such cases, it is preferable to reduce the power consumption of semiconductor module A1 by suppressing the parasitic resistance component in the conductive component 6, which serves as the path for the main circuit current. Therefore, in semiconductor module A1, as described above, the conductive component 6 is formed from a metal plate rather than a bonding wire, thereby suppressing the parasitic resistance component in the conductive component 6. In other words, semiconductor module A1 has a package structure that is preferable for achieving the suppression of parasitic resistance components.

[0207] In the semiconductor module A1, each first semiconductor element 10A is rectangular in plan view, and the four corners of the first semiconductor element 10A do not overlap with the second conductive member 62 in plan view. According to this structure, in the manufacturing process of the semiconductor module A1, before the step of forming the sealing resin 8, it is possible to perform a visual inspection to see whether each first semiconductor element 10A is properly bonded. In other words, the semiconductor module A1 can be inspected during the manufacturing process (for example, Figure 23The appearance inspection of the bonding state of each first semiconductor element 10A is performed (in the state shown), so it can be determined whether each first semiconductor element 10A is properly bonded. For example, the distances of the four corners of the first semiconductor element 10A are measured by a laser distance measurement method. If the difference in the measured distances of the four corners is small, it can be determined that the first semiconductor element 10A is properly bonded. Therefore, the semiconductor module A1 can be subjected to appearance inspection in the middle of manufacturing, and thus constitutes a preferred packaging structure in terms of achieving improved reliability. In addition, when performing the appearance inspection, it is sufficient to confirm that at least three of the four corners of the first semiconductor element 10A when viewed from above, so it is sufficient to constitute the three corners so as not to overlap with the second conductive component 62. In addition, as Figure 5 As shown, in each second semiconductor element 10B, the four corners of each second semiconductor element 10B do not overlap with the second conductive member 62 when viewed from above. Therefore, in the manufacturing process of the semiconductor module A1, before the step of forming the sealing resin 8, it is possible to perform a visual inspection to determine whether each second semiconductor element 10B is properly bonded. The visual inspection may also be an automatic visual inspection using imaging and image processing.

[0208] The second conductive component 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to the input terminals 42 and 43, which are located on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. The fourth wiring portion 624 is located on the x2 side relative to the third wiring portion 623 and overlaps with the plurality of first semiconductor elements 10A in a plan view. The second conductive member 62, which includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624, overlaps a wide area of ​​the main surface 201 in a plan view and has a relatively large size in a plan view. Increasing the size of the second conductive member 62 in a plan view is thus more preferable in terms of suppressing the parasitic resistance component of the second conductive member 62 (conductive member 6) that forms the path of the main circuit current.

[0209] Each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 when viewed from above. The first side 191 and the second side 192 each extend in the y-direction. The first side 191 is the end edge on the x2 side when viewed from above, and the second side 192 is the end edge on the x1 side when viewed from above. The third side 193 and the fourth side 194 each extend in the x-direction. The third side 193 is the end edge on the y2 side when viewed from above, and the fourth side 194 is the end edge on the y1 side when viewed from above. Each first semiconductor element 10A has a rectangular shape when viewed from above, and the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are approximately right angles when viewed from above. Meanwhile, the fourth wiring portion 624 (first strip-shaped portion 625) of the second conductive member 62 has a first end edge 627 and a second end edge 628. The first edge 627 is the edge of the fourth wiring portion 624 located in the x2 direction and is located closer to the x1 direction than the first side 191 in a plan view. The first edge 627 also extends in the y direction from at least the third side 193 to the fourth side 194. Thus, in a plan view, neither of the two corners 171 and 172 on the x2 side of each first semiconductor element 10A overlaps with the second conductive member 62. The second edge 628 is the edge of the fourth wiring portion 624 (first strip-shaped portion 625) located in the x1 direction and is located closer to the x2 direction than the second side 192 in a plan view. The second edge 628 also extends in the y direction from at least the third side 193 to the fourth side 194. Thus, in a plan view, neither of the two corners 173 and 174 on the x1 side of each first semiconductor element 10A overlaps with the second conductive member 62. In this structure, by ensuring an area in the fourth wiring portion 624 that overlaps with each first semiconductor element 10A in a plan view, the size of the second conductive member 62 in a plan view is increased, and the four corners of the first semiconductor element 10A in a plan view do not overlap with the second conductive member 62. Therefore, the parasitic resistance component of the second conductive member 62 (conductive member 6) can be effectively suppressed, and the bonding state of each first semiconductor element 10A can be visually inspected during the manufacture of the semiconductor module A1.

[0210] The fourth wiring portion 624 (first strip-shaped portion 625) has multiple convex regions 625a that protrude further in the z2 direction than other portions. Each convex region 625a overlaps with each first semiconductor element 10A in a plan view. The configuration of the fourth wiring portion 624 having multiple convex regions 625a prevents inadvertent contact between the fourth wiring portion 624 and the first conductive member 61 bonded to the first semiconductor element 10A.

[0211] The third wiring portion 623 has multiple concave regions 623a that protrude further in the z1 direction than other portions. Each concave region 623a is bonded to one of the plurality of second semiconductor elements 10B. This structure allows for proper electrical connection between the third wiring portion 623 (second conductive member 62) and the plurality of second semiconductor elements 10B, while also ensuring a large size for the third wiring portion 623 (second conductive member 62) when viewed from above.

[0212] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x-direction. This configuration prevents the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) on which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged from increasing in size in the y-direction, thereby miniaturizing the semiconductor module A1.

[0213] Semiconductor module A1 includes a conductive substrate 2, two input terminals 41 and 42 (or two input terminals 41 and 43), an output terminal 44, and a conductive component 6. The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B arranged in the x-direction when viewed from above. A plurality of first semiconductor elements 10A are electrically bonded to the first conductive portion 2A. Furthermore, a plurality of second semiconductor elements 10B are electrically bonded to the second conductive portion 2B. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are spaced apart in the y-direction. The two input terminals 41 and 42 (or the two input terminals 41 and 43) are located in the x2 direction relative to the first conductive portion 2A. Input terminal 41 is a positive electrode and is connected to the first conductive portion 2A. Input terminal 42 (or input terminal 43) is a negative electrode. Output terminal 44 is located in the x1 direction relative to the second conductive portion 2B. The conductive member 6 includes a first conductive member 61 connected to the plurality of first semiconductor elements 10A and the second conductive portion 2B, and a second conductive member 62 connected to the plurality of second semiconductor elements 10B and the input terminal 42 (or the input terminal 43). According to this structure, the path of the main circuit current switched by the plurality of semiconductor elements 10 (the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B) is along the x-direction in a plan view and is configured to be the symmetric axis of the semiconductor module A1 in the planar structure (see Figure 5The auxiliary line L1 of the circuit ( L1 ) extends along the y-direction when viewed from above. That is, the axis of symmetry is orthogonal to the path of the main circuit current. As a result, the difference in the current paths to the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B in the main circuit current input from the two input terminals 41 and 42 (or the two input terminals 41 and 43) and output from the output terminal 44 can be reduced. In other words, variations in the parasitic inductance components and current within the semiconductor module A1 can be suppressed. Therefore, the semiconductor module A1 constitutes a preferred packaging structure for achieving equalization of the parasitic inductance components in the path of the main circuit current and equalization of the current amount flowing to each semiconductor element 10.

[0214] Each first semiconductor element 10A is spaced apart from each second semiconductor element 10B in the x-direction. Each first semiconductor element 10A and each second semiconductor element 10B are arranged in the y-direction. Therefore, the direction in which each semiconductor element 10 is arranged is perpendicular to the direction in which the first main circuit current or the second main circuit current flows. Consequently, when multiple switching elements are connected in parallel for use as in this embodiment, any differences in the length of the current path for the first main circuit current between the three first semiconductor elements 10A can be minimized. This also reduces the parasitic resistance component in the conductive component 6, which serves as the path for the main circuit current.

[0215] The area where the first main circuit current flows and the area where the second main circuit current flows are configured to overlap when viewed from above. That is, to allow the second main circuit current to flow, the second conductive component 62 connecting the output terminal 44 and the first input terminal 42, which serves as the negative terminal, and the second input terminal 43 is arranged above the area where the first main circuit current flows (the first conductive portion 2A, the first conductive portion 61, and the second conductive portion 2B). The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows. Therefore, through this configuration, the magnetic field generated by the first main circuit current and the magnetic field generated by the second main circuit current can be offset, thereby reducing the inductance.

[0216] The semiconductor module A1 of this embodiment includes two input terminals 42 and 43. These input terminals 42 and 43 are both negative electrodes and sandwich the input terminal 41 in the y-direction. Furthermore, a second conductive member 62 is connected to both input terminals 42 and 43. This configuration further reduces variations in the paths of current flowing from the output terminal 44 through the second semiconductor elements 10B and the second conductive member 62 to the input terminals 42 and 43.

[0217] In semiconductor module A1, the second conductive member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are connected to input terminals 42 and 43, respectively, which are located on opposite sides of the input terminal 41 in the y direction, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622, extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is located on the x2 side relative to the third wiring portion 623 and is connected to each of the first wiring portion 621, the second wiring portion 622, and the third wiring portion 623. The second conductive component 62, which includes the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624, overlaps a wide area of ​​the main surface 201 when viewed from above, ensuring a large size when viewed from above. This structure appropriately reduces variations in the path of the current flowing from the output terminal 44 to the input terminals 42 and 43 via the second semiconductor elements 10B and the second conductive component 62. Therefore, the semiconductor module A1 of this embodiment is more advantageous in achieving equalization of the parasitic inductance components in the main circuit current path (the second conductive component 62) and equalization of the current flowing to the second semiconductor elements 10B.

[0218] The fourth wiring portion 624 connects to both the first wiring portion 621 and the second wiring portion 622, overlapping the plurality of first semiconductor elements 10A in a plan view. Furthermore, the fourth wiring portion 624 (first strip-shaped portion 625) includes a plurality of convex regions 625a that protrude further in the z2 direction than the other portions. Each convex region 625a overlaps a first semiconductor element 10A in a plan view. This structure ensures a large size for the fourth wiring portion 624 (second conductive member 62) in a plan view, while preventing the fourth wiring portion 624 from inadvertently contacting the first conductive member 61 bonded to the first semiconductor element 10A.

[0219] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x-direction. This configuration prevents the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) on which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged from increasing in size in the y-direction, thereby miniaturizing the semiconductor module A1.

[0220] Figures 30 to 32 A semiconductor module according to a second embodiment is shown. In the semiconductor module A2 of this embodiment, the structure of the second conductive member 62 is different from that of the semiconductor module A1 of the above embodiment.

[0221] In this embodiment, the area occupied by the fourth wiring portion 624 of the second conductive component 62 is different from that of the above embodiment. Specifically, the dimension of the first strip portion 625 in the x direction is larger than that of the semiconductor module A1. Figure 31 、 Figure 32 As shown, compared with the semiconductor module A1, the second end edge 628 of the first strip portion 625 is located on the x1 direction side. Figure 32 As shown, the second edge 628 is located closer to the x1 direction than the second side 192 of the first semiconductor element 10A in a plan view. Therefore, the two corners on the x1 side of each first semiconductor element 10A in a plan view overlap with the second conductive member 62 (first strip portion 625).

[0222] The semiconductor module A2 of this embodiment also achieves the same operational advantages as the semiconductor module A1 of the aforementioned embodiment. Furthermore, in the semiconductor module A2, the first strip portion 625 (second conductive member 62) of the fourth wiring portion 624 can be made larger in plan view. This is further advantageous in terms of reducing parasitic inductance components.

[0223] Figure 33 as well as Figure 34 A semiconductor module according to a third embodiment is shown. The semiconductor module A3 according to this embodiment mainly differs from the semiconductor module A1 according to the above embodiment in the structure of the second conductive member 62 .

[0224] In the semiconductor module A3, unlike the above embodiment, the second conductive member 62 does not have the opening 63. When manufacturing the semiconductor module A3, the metal mold 91 used for forming (molding) the sealing resin 8 does not have the pressing pin 911. Figure 34 As shown, no resin voids 86 are formed in the encapsulating resin 8, and no recesses 201a are formed in the main surface 201 of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B). Furthermore, since no resin voids 86 are formed in the encapsulating resin 8, the semiconductor module A3 of this embodiment also does not include the resin filling portion 88 used to fill the resin voids 86 in the above-described embodiment.

[0225] The semiconductor module A3 of the present embodiment also exhibits the same operational effects as those of the semiconductor module A1 of the above-described embodiment.

[0226] The semiconductor module of the present disclosure is not limited to the above-described embodiment, and the specific structure of each part of the semiconductor module of the present disclosure can be freely modified in various designs.

[0227] In the above embodiment, the first conductive portion 2A and the second conductive portion 2B are arranged at intervals in the x-direction, and the plurality of first semiconductor elements 10A bonded to the first conductive portion 2A and the plurality of second semiconductor elements 10B bonded to the second conductive portion 2B are arranged side by side in the y-direction. Alternatively, the first conductive portion 2A and the second conductive portion 2B may be arranged at intervals in the y-direction. In this case, the plurality of first semiconductor elements 10A bonded to the first conductive portion 2A and the plurality of second semiconductor elements 10B bonded to the second conductive portion 2B are arranged side by side in the x-direction. With this configuration, in which the input terminals 41-43 are positioned on the x2 side of the conductive substrate 2 and the output terminal 44 is positioned on the x1 side, the upper arm current path flowing from the first conductive portion 2A via the first semiconductor elements 10A and the first conductive members 61 to the second conductive portion 2B and the lower arm current path flowing from the second conductive portion 2B via the second semiconductor elements 10B to the second conductive member 62 are oriented in opposite directions along the y direction. This configuration cancels out the magnetic field generated by the current flowing along the upper arm current path and the magnetic field generated by the current flowing along the lower arm current path, thereby reducing parasitic inductance components.

[0228] In the above embodiment, the plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) are arranged so that each control terminal 45 extends along the z-direction, but the present invention is not limited thereto. For example, the plurality of control terminals 45 may be arranged so that each control terminal 45 extends along a plane perpendicular to the z-direction (the x-y plane).

[0229] The present disclosure includes the configurations described in the following supplementary notes.

[0230] Note 1.

[0231] A semiconductor module comprising:

[0232] a conductive substrate having a main surface facing one side in a thickness direction and a back surface facing a side opposite to the main surface;

[0233] a semiconductor element electrically bonded to the main surface and having a switching function;

[0234] a conducting member constituting a path for a main circuit current switched by the semiconductor element;

[0235] a first input terminal, a second input terminal, and a third input terminal arranged on one side of a first direction perpendicular to the thickness direction with respect to the conductive substrate; and

[0236] an output terminal arranged on the other side of the first direction relative to the conductive substrate,

[0237] The conductive substrate includes a first conductive portion and a second conductive portion.

[0238] The semiconductor element includes a first semiconductor element electrically connected to the first conductive portion, and a second semiconductor element electrically connected to the second conductive portion.

[0239] The second input terminal and the third input terminal are arranged on one side and the other side of a second direction perpendicular to both the thickness direction and the first direction across the first input terminal.

[0240] The first input terminal is one of the positive and negative electrodes and is electrically connected to the first conductive portion.

[0241] The second input terminal and the third input terminal are the other of the positive electrode and the negative electrode.

[0242] Note 2.

[0243] According to the semiconductor module described in Supplementary Note 1,

[0244] The first input terminal is electrically connected to the first conductive portion.

[0245] The output terminal is electrically connected to the second conductive portion.

[0246] The above-mentioned conductive components include:

[0247] a first conductive component connected to the first semiconductor element and the second conductive portion; and

[0248] The second conductive member is connected to the second semiconductor element, the second input terminal, and the third input terminal, and overlaps the first semiconductor element when viewed in the thickness direction.

[0249] Note 3.

[0250] According to the semiconductor module described in Appendix 2,

[0251] The first conductive portion and the second conductive portion are arranged on one side of the first direction and the other side of the first direction,

[0252] The second conductive component includes:

[0253] a first wiring portion connected to the second input terminal and extending in the first direction;

[0254] a second wiring portion connected to the third input terminal and extending in the first direction;

[0255] a third wiring portion connected to both the first wiring portion and the second wiring portion, extending in the second direction, and connected to the second semiconductor element; and

[0256] The fourth wiring portion is connected to both the first wiring portion and the second wiring portion, is located on one side in the first direction relative to the third wiring portion, and overlaps the first semiconductor element when viewed in the thickness direction.

[0257] Note 4.

[0258] According to the semiconductor module described in Appendix 3,

[0259] The first semiconductor element and the second semiconductor element each have a source electrode facing one side in the thickness direction and a drain electrode facing the other side in the thickness direction.

[0260] The first conductive component is connected to the source electrode of the first semiconductor element.

[0261] The first conductive portion is connected to the drain electrode of the first semiconductor element.

[0262] The third wiring portion is connected to the source electrode of the second semiconductor element.

[0263] The second conductive portion is connected to the drain electrode of the second semiconductor element.

[0264] Note 5.

[0265] According to the semiconductor module described in Appendix 4,

[0266] The first semiconductor element and the second semiconductor element overlap with each other when viewed in the first direction.

[0267] Note 6.

[0268] According to the semiconductor module described in Supplementary Note 5,

[0269] The fourth wiring portion includes a first strip-shaped portion and a second strip-shaped portion.

[0270] The first strip portion is spaced apart from the third wiring portion in the first direction, is connected to both the first wiring portion and the second wiring portion, extends in the second direction, and overlaps with the first semiconductor element when viewed in the thickness direction.

[0271] When viewed in the thickness direction, one end of the second strip-shaped portion connects between the first semiconductor elements adjacent to the first strip-shaped portion, and the other end connects between the second semiconductor elements adjacent to the third wiring portion.

[0272] Note 7.

[0273] According to the semiconductor module described in Appendix 6,

[0274] The first strip-shaped portion overlaps with the first semiconductor element when viewed in the thickness direction and has a convex region that protrudes further toward one side in the thickness direction than other portions.

[0275] Note 8.

[0276] The semiconductor module according to any one of Supplementary Notes 3 to 7,

[0277] The third wiring portion has a concave region that protrudes further toward the other side in the thickness direction than other portions.

[0278] The concave region is bonded to the second semiconductor element.

[0279] Note 9.

[0280] The semiconductor module according to any one of Supplementary Notes 3 to 8,

[0281] A first control terminal and a second control terminal for controlling the first semiconductor element and the second semiconductor element are provided,

[0282] The first control terminal and the second control terminal are respectively arranged on the main surface and extend in the thickness direction.

[0283] Note 10.

[0284] According to the semiconductor module described in Supplementary Note 9,

[0285] The first control terminal is supported by the first conductive portion and is arranged on one side of the first direction relative to the first semiconductor element.

[0286] The second control terminal is supported by the second conductive portion and is arranged on the other side of the first direction relative to the second semiconductor element.

[0287] Note 11.

[0288] According to the semiconductor module described in Supplementary Note 10,

[0289] The first semiconductor element and the second semiconductor element each have a gate electrode facing one side in the thickness direction.

[0290] The first control terminal is connected to the gate electrode of the first semiconductor element via a first conductive metal wire.

[0291] The second control terminal is connected to the gate electrode of the second semiconductor element via a second conductive metal wire.

[0292] Note 12.

[0293] The semiconductor module according to any one of Supplementary Notes 1 to 11,

[0294] The first input terminal, the second input terminal, and the third input terminal overlap with each other when viewed in the second direction.

[0295] Note 13.

[0296] The semiconductor module according to any one of Supplementary Notes 1 to 12,

[0297] The conductive member is formed of a metal plate.

[0298] Note 14.

[0299] The semiconductor module according to any one of Supplementary Notes 1 to 13,

[0300] The first input terminal, the second input terminal, and the third input terminal each include an input-side bonding surface extending toward one side in the first direction and facing one side in the thickness direction.

[0301] The output terminal includes an output-side bonding surface extending toward the other side of the first direction and facing one side of the thickness direction.

[0302] Note 15.

[0303] The semiconductor module according to any one of Supplementary Notes 1 to 14,

[0304] The first input terminal, the second input terminal, and the third input terminal each have: an input side surface located at a periphery of the input side joint surface when viewed in the thickness direction and facing a direction intersecting the input side joint surface; and an input side processing mark formed on the input side side surface.

[0305] The output terminal includes an output side surface located at the periphery of the output side joint surface when viewed in the thickness direction and facing a direction intersecting the output side joint surface; and an output side processing mark formed on the output side surface.

[0306] Note 16.

[0307] The semiconductor module according to any one of Supplementary Notes 1 to 15,

[0308] A sealing resin is further provided, the sealing resin covering at least a portion of the conductive substrate, the semiconductor element, and the conductive member.

[0309] Note 17.

[0310] The semiconductor module according to any one of Supplementary Notes 3 to 12,

[0311] a plurality of the first semiconductor elements arranged at intervals in the second direction; and

[0312] The plurality of second semiconductor elements are arranged at intervals in the second direction.

[0313] Note 18.

[0314] A semiconductor module comprising:

[0315] a conductive substrate having a main surface facing one side in a thickness direction and a back surface facing a side opposite to the main surface;

[0316] a semiconductor element electrically bonded to the main surface and having a switching function;

[0317] a conducting member constituting a path for a main circuit current switched by the semiconductor element and spaced apart from the main surface toward one side in the thickness direction;

[0318] a first input terminal, a second input terminal, and a third input terminal arranged on one side of a first direction perpendicular to the thickness direction with respect to the conductive substrate; and

[0319] an output terminal arranged on the other side of the first direction relative to the conductive substrate,

[0320] The conductive substrate includes a first conductive portion and a second conductive portion spaced apart from each other when viewed in the thickness direction.

[0321] The semiconductor element includes a plurality of first semiconductor elements electrically connected to the first conductive portion, and a plurality of second semiconductor elements electrically connected to the second conductive portion.

[0322] The second input terminal and the third input terminal are arranged on one side and the other side of a second direction perpendicular to both the thickness direction and the first direction across the first input terminal.

[0323] The first input terminal is connected to the first conductive portion.

[0324] The output terminal is connected to the second conductive portion.

[0325] The conductive component includes a first conductive component connected to the plurality of first semiconductor elements and the second conductive portion; and a second conductive component connected to the plurality of second semiconductor elements, the second input terminal, and the third input terminal, and overlapping with the first semiconductor elements when viewed in the thickness direction.

[0326] Note 19.

[0327] According to the semiconductor module described in Supplementary Note 18,

[0328] The first conductive portion and the second conductive portion are arranged on one side of the first direction and the other side of the first direction,

[0329] The plurality of first semiconductor elements and the plurality of second semiconductor elements are respectively arranged at intervals along the second direction.

[0330] The second conductive component includes:

[0331] a first wiring portion connected to the second input terminal and extending in the first direction;

[0332] a second wiring portion connected to the third input terminal and extending in the first direction;

[0333] a third wiring portion connected to both the first wiring portion and the second wiring portion, extending in the second direction, and connected to each of the plurality of second semiconductor elements; and

[0334] The fourth wiring portion is connected to both the first wiring portion and the second wiring portion, is located on one side in the first direction relative to the third wiring portion, and overlaps the plurality of first semiconductor elements when viewed in the thickness direction.

[0335] Note 20.

[0336] According to the semiconductor module described in Appendix 19,

[0337] The first semiconductor element and the second semiconductor element each have a source electrode facing one side in the thickness direction and a drain electrode facing the other side in the thickness direction.

[0338] The first conductive component is connected to the source electrode of the first semiconductor element.

[0339] The first conductive portion is connected to the drain electrode of the first semiconductor element.

[0340] The third wiring portion is connected to the source electrode of the second semiconductor element.

[0341] The second conductive portion is connected to the drain electrode of the second semiconductor element.

[0342] Note 21.

[0343] According to the semiconductor module described in Supplementary Note 20,

[0344] The plurality of first semiconductor elements and the plurality of second semiconductor elements overlap with each other when viewed in the first direction.

[0345] Note 22.

[0346] According to the semiconductor module described in Supplementary Note 21,

[0347] The fourth wiring portion includes a first strip-shaped portion and a second strip-shaped portion.

[0348] The first strip portion is spaced apart from the third wiring portion in the first direction, is connected to both the first wiring portion and the second wiring portion, extends in the second direction, and overlaps with the plurality of first semiconductor elements when viewed in the thickness direction.

[0349] When viewed in the thickness direction, one end of the second strip-shaped portion connects between the first semiconductor elements adjacent to the first strip-shaped portion, and the other end connects between the second semiconductor elements adjacent to the third wiring portion.

[0350] Note 23.

[0351] According to the semiconductor module described in Supplementary Note 22,

[0352] The first strip-shaped portion overlaps with each of the first semiconductor elements when viewed in the thickness direction, and has a plurality of convex regions that protrude further toward one side in the thickness direction than other portions.

[0353] Note 24.

[0354] The semiconductor module according to any one of Supplementary Notes 19 to 23,

[0355] The third wiring portion has a plurality of concave regions that protrude further toward the other side in the thickness direction than other portions.

[0356] Each of the concave regions is bonded to any one of the plurality of second semiconductor elements.

[0357] Note 25.

[0358] The semiconductor module according to any one of Supplementary Notes 19 to 24,

[0359] comprising a plurality of first control terminals and a plurality of second control terminals for controlling the plurality of first semiconductor elements and the plurality of second semiconductor elements,

[0360] The plurality of first control terminals and the plurality of second control terminals are respectively arranged on the main surface and extend in the thickness direction.

[0361] Note 26.

[0362] According to the semiconductor module described in Supplementary Note 25,

[0363] The plurality of first control terminals are supported by the first conductive portion and are arranged at intervals in the second direction on one side of the first direction relative to the plurality of first semiconductor elements.

[0364] The plurality of second control terminals are supported by the second conductive portion and are arranged at intervals in the second direction on the other side of the first direction relative to the plurality of second semiconductor elements.

[0365] Note 27.

[0366] According to the semiconductor module described in Supplementary Note 26,

[0367] The first semiconductor element and the second semiconductor element each have a gate electrode facing one side in the thickness direction.

[0368] The first control terminal is connected to the gate electrode of the first semiconductor element via a first conductive metal wire.

[0369] The second control terminal is connected to the gate electrode of the second semiconductor element via a second conductive metal wire.

[0370] Note 28.

[0371] The semiconductor module according to any one of Supplementary Notes 18 to 27,

[0372] The first input terminal, the second input terminal, and the third input terminal overlap with each other when viewed in the second direction.

[0373] Note 29.

[0374] The semiconductor module according to any one of Supplementary Notes 18 to 28,

[0375] The first conductive member and the second conductive member are formed of metal plates.

[0376] Explanation of symbols

[0377] A1, A2, A3—semiconductor module, 10—semiconductor element, 10A—first semiconductor element, 10B—second semiconductor element, 101—element main surface, 102—element back surface, 11—first main surface electrode (gate electrode), 12—second main surface electrode (source electrode), 13—third main surface electrode, 14—fourth main surface electrode, 15—back surface electrode (drain electrode), 16—fifth main surface electrode, 171, 172, 173, 174, 181, 182, 183, 184—corners, 191—first side, 192—second side, 193—third side, 194—fourth side, 2—conductive substrate, 2A—first conductive portion, 2B—second conductive portion, 201—main surface, 201a—recess, 2 01b—recess end edge, 202—back surface, 21—substrate, 22—main surface bonding layer, 23—back surface bonding layer, 3—support substrate, 301—support surface, 302—bottom surface, 31—insulating layer, 32—first metal layer, 32A—first portion, 32B—second portion, 321—first bonding layer, 33—second metal layer, 41—input terminal (first input terminal), 411—input side bonding surface, 412—input side side, 413—front end surface, 414—side surface, 42—input terminal (second input terminal), 421—input side bonding surface, 422—input side side, 423—front end surface, 424—side surface, 43—input terminal (third input terminal), 431—input side bonding surface, 432— Input side surface, 433—front end surface, 434—side surface, 44—output terminal, 441—output side bonding surface, 442—output side surface, 443—front end surface, 444—side surface, 45—control terminal, 451—bracket, 452—metal pin, 459—conductive bonding material, 46A, 46B, 46C, 46D, 46E—first control terminal, 47A, 47B, 47C, 47D—second control terminal, 5—control terminal support, 51—insulating layer, 52—first metal layer, 521—first part, 522—second part, 523—third part, 524—fourth part, 525—fifth part, 53—second metal layer, 59—bonding material, 6—conductive component, 601—first part , 61—first conductive component, 61h—opening, 62—second conductive component, 62A—first portion, 62B—second portion, 621—first wiring portion, 622—second wiring portion, 623—third wiring portion, 623a—concave area, 623h—opening, 624—fourth wiring portion, 625—first strip-shaped portion, 625a—convex area, 625h—opening, 626—second strip-shaped portion, 627—first end edge, 628—second end edge 63—opening, 69—conductive bonding material, 71—first conductive bonding material, 711—first base layer, 712—first layer, 713—second layer, 72—second conductive bonding material, 721—second base layer, 722—third layer, 723—fourth layer,731 — Metal wire (for connecting the gate electrode and the first metal layer), 731a — First metal wire, 731b — Second metal wire, 732, 733, 734, 735 — Metal wires, 8 — Sealing resin, 81 — Resin main surface, 82 — Resin back surface, 831, 832 — Resin side surfaces, 832a — Recessed portion, 833, 834 — Resin side surfaces, 851 — First protrusion (protrusion), 851a — First protrusion end surface (protrusion end surface), 851b — Recessed portion, 851c — Inner wall surface, 852 — Second protrusion, 86 — Resin gap, 861 — Resin gap end edge, 87 — Resin portion, 88 — Resin filling portion, 91 — Metal mold, 911 — Pressing pin.

Claims

1. A semiconductor module, characterized in that: have: a conductive substrate having a main surface facing one side in a thickness direction and a back surface facing a side opposite to the main surface; a semiconductor element electrically bonded to the main surface and having a switching function; A plurality of control terminals for controlling the semiconductor elements; a conducting member constituting a path for a main circuit current switched by the semiconductor element; a first input terminal, a second input terminal, and a third input terminal, which are arranged on one side of a first direction perpendicular to the thickness direction relative to the conductive substrate; an output terminal arranged on the other side of the first direction relative to the conductive substrate; and a sealing resin covering at least a portion of the conductive substrate, the semiconductor element, and the conductive member; The conductive substrate includes a first conductive portion and a second conductive portion. The semiconductor element includes at least one first semiconductor element electrically connected to the first conductive portion, and at least one second semiconductor element electrically connected to the second conductive portion. The plurality of control terminals include a first control terminal for controlling each of the at least one first semiconductor element and a second control terminal for controlling each of the at least one second semiconductor element. The second input terminal and the third input terminal are arranged on one side and the other side of a second direction perpendicular to both the thickness direction and the first direction across the first input terminal. The first input terminal is one of the positive and negative electrodes and is electrically connected to the first conductive portion. The second input terminal and the third input terminal are the other of the positive and negative electrodes. The sealing resin has a resin side surface facing the one side in the first direction, and the first input terminal, the second input terminal, and the third input terminal protrude from the resin side surface. On the side surface of the resin, a first recessed portion is formed between the first input terminal and the second input terminal, when viewed in the thickness direction, and is recessed toward the other side in the first direction. A second recessed portion is formed between the first input terminal and the third input terminal, when viewed in the thickness direction, and is recessed toward the other side in the first direction. The first control terminal and the second control terminal respectively protrude from the sealing resin. At least a portion of each of the first control terminal and the second control terminal protruding from the sealing resin extends in the thickness direction.

2. The semiconductor module according to claim 1, wherein Each of the at least one first semiconductor element and each of the at least one second semiconductor element has a gate electrode facing the one side in the thickness direction. The first control terminal is connected to the gate electrode of each of the at least one first semiconductor element via a conductive first metal wire. The second control terminal is connected to the gate electrode of each of the at least one second semiconductor element via a second conductive wire.

3. The semiconductor module according to claim 2, wherein: Each of the at least one first semiconductor element and each of the at least one second semiconductor element overlap with each other when viewed in the first direction.

4. The semiconductor module according to claim 2, wherein: The at least one first semiconductor element includes a plurality of first semiconductor elements. The at least one second semiconductor element includes a plurality of second semiconductor elements. The plurality of first semiconductor elements are arranged at intervals in a first orthogonal direction orthogonal to the thickness direction. The plurality of second semiconductor elements are arranged at intervals in a second orthogonal direction orthogonal to the thickness direction.

5. The semiconductor module according to claim 4, wherein The first orthogonal direction and the second orthogonal direction are respectively the second directions. The semiconductor module according to claim 4 , wherein: Each of the plurality of first semiconductor elements and each of the plurality of second semiconductor elements includes a MOSFET, and a constituent material thereof includes SiC.

7. The semiconductor module according to any one of claims 1 to 6, characterized in that The first input terminal, the second input terminal, and the third input terminal overlap with each other when viewed in the second direction.

8. The semiconductor module according to claim 1, wherein The sealing resin includes: a resin back surface facing in the same direction as the back surface in the thickness direction; a convex portion arranged at an outer edge of the resin back surface when viewed in the thickness direction; and a third concave portion adjacent to the convex portion.

9. The semiconductor module according to claim 1, wherein further comprising a first control terminal support body and a second control terminal support body, each having an insulating layer, The first conductive portion has a first main surface facing the one side in the thickness direction. The second conductive portion has a second main surface facing the one side in the thickness direction. The first control terminal support is interposed between the first main surface and the first control terminal. The second control terminal support body is interposed between the second main surface and the second control terminal.

10. The semiconductor module according to claim 9, wherein The above-mentioned first control terminal support body and the above-mentioned second control terminal support body respectively have: a first metal layer, which is stacked on the above-mentioned one side in the above-mentioned thickness direction of the above-mentioned insulating layer; and a second metal layer, which is stacked on the above-mentioned other side in the above-mentioned thickness direction of the above-mentioned insulating layer and is joined to the above-mentioned conductive substrate in a manner opposite to the above-mentioned main surface.

11. The semiconductor module according to claim 1, wherein The first control terminal and the second control terminal are respectively arranged on the main surface and extend in the thickness direction.

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