A semiconductor laser chip with a small horizontal divergence angle and a preparation method thereof

Abstract

The present invention proposes a semiconductor laser chip with a small horizontal divergence angle and a preparation method, which relates to the field of semiconductor laser chips, including a substrate layer, an n-type cladding layer, an n-type waveguide layer, an active area, a p-type waveguide layer, a p-type cladding layer, a p-type confinement layer and a p-type contact layer stacked in sequence from bottom to top, wherein the p-type confinement layer includes at least two current blocking layers and a conductive medium layer, and at least two blocking grooves that are opposite and spaced are opened on the conductive medium layer along the length direction of the laser chip, and the at least two current blocking layers are respectively arranged in the corresponding blocking grooves, and the p-type confinement layer is used to adjust the formation position of the carrier injection region formed between two adjacent current blocking layers to suppress the lateral diffusion of the current in the p-type confinement layer. The present invention is helpful to improve the output power and beam quality of the laser.

Description

Technical Field

[0001] The invention relates to the field of semiconductor laser chips, and in particular to a semiconductor laser chip with a small horizontal divergence angle and a preparation method thereof. Background Art

[0002] Semiconductor lasers have been widely and far-reachingly used in military, industrial processing, precision measurement, laser medicine, optical communications, optical storage, and laser printing due to their high conversion efficiency, small size, light weight, long life, high reliability, direct modulation, and easy integration with other semiconductor devices.

[0003] The Chinese patent application with publication number CN109167253B discloses a method for manufacturing a small divergence angle buried heterojunction DFB laser, comprising preparing an epitaxial wafer, wherein the uppermost layer of the epitaxial wafer is an InP grating, coating a photoresist on the InP grating layer, and forming a Bragg grating region on the photoresist in a partial region through a grating photomask, and the other partial region is a Bragg non-grating region, and forming a grating pattern in the Bragg grating region; sequentially growing a grating buried P-type InP layer and an intrinsic InGaAsP layer on the photoresist with the grating pattern formed; and coating a photoresist on the intrinsic InG A ridge mask is photolithographically formed on the aAsP layer through a single growth to form a ridge strip, and ridge etching is performed on both sides of each layer structure below the ridge strip in turn, so that each layer structure below the ridge strip is an overall gradually expanding structure along the etching direction; high-temperature heat treatment is performed on both gradually expanding edges of the gradually expanding structure, and a first current blocking layer and a second current blocking layer are sequentially grown on the gradually expanding edges after high-temperature heat treatment, wherein the first current blocking layer is a P-type InP layer, and the second current blocking layer is an N-type InP layer; the overall structure formed after the above steps is subjected to subsequent processes to obtain a laser. However, when the operating current is high, the laser will generate a high-order lateral mode, resulting in a larger lateral divergence angle of the device, which seriously reduces the lateral beam quality of the laser. Therefore, it is very necessary to provide a semiconductor laser chip with a small horizontal divergence angle and a preparation method to improve the output power and beam quality of the laser. Summary of the invention

[0004] In view of this, the present invention proposes a semiconductor laser chip with a small horizontal divergence angle and a preparation method. Through the special design of the current blocking layer and the conductive medium layer in the p-type confinement layer, the semiconductor laser chip can accurately control the position and shape of the carrier injection area. The current blocking layers arranged relatively and at intervals help to form a narrower effective gain area, achieving the purpose of suppressing the diffusion and aggregation effects of carriers, so as to improve the output power and beam quality of the laser.

[0005] The present invention provides a semiconductor laser chip with a small horizontal divergence angle, comprising a substrate layer, an n-type cladding layer, an n-type waveguide layer, an active region, a p-type waveguide layer, a p-type cladding layer, a p-type confinement layer and a p-type contact layer stacked in sequence from bottom to top, wherein:

[0006] The p-type limiting layer includes at least two current blocking layers and a conductive medium layer. The conductive medium layer is provided with at least two blocking grooves which are opposite to each other and spaced apart along the length direction of the laser chip. The at least two current blocking layers are respectively arranged in corresponding blocking grooves. The p-type limiting layer is used to adjust the formation position of the carrier injection region formed between two adjacent current blocking layers to suppress the lateral diffusion of the current in the p-type limiting layer.

[0007] On the basis of the above technical solution, preferably, the at least two current blocking layers are symmetrically arranged along the vertical direction of the center line of the width of the p-type confinement layer.

[0008] On the basis of the above technical solution, preferably, the thickness of the p-type waveguide layer is smaller than the thickness of the n-type waveguide layer, and the thickness of the p-type cladding layer is smaller than the thickness of the n-type cladding layer.

[0009] More preferably, the ratio of the area of ​​two adjacent current blocking layers to the carrier injection region formed between the two adjacent current blocking layers is 0.4 to 0.67, and the width of the carrier injection region is 300 μm to 500 μm.

[0010] More preferably, the current blocking layer comprises a first blocking layer and a second blocking layer stacked in sequence from bottom to top, the first blocking layer is doped with n-GaInP, and the second blocking layer is doped with n-GaAs.

[0011] More preferably, the p-type waveguide layer and the n-type waveguide layer are both doped with Al 0.18-0.22 GaAs, the thickness of the p-type waveguide layer is 150 nm, and the thickness of the n-type waveguide layer is 300 nm.

[0012] More preferably, the p-type cladding layer is doped with Al 0.6-0.8 GaAs, the n-type cladding layer is doped with Al 0.22- 0.3 GaAs, the thickness of the p-type cladding layer is 1000 nm, and the thickness of the n-type cladding layer is 2500 nm.

[0013] More preferably, the conductive medium layer, the current blocking layer and the p-type cladding layer stacked in sequence form a current-blocking reverse bias junction, and the current-blocking reverse bias junction is used to suppress lateral expansion of current in the laser chip.

[0014] More preferably, the substrate layer includes an n-type substrate and an n-type buffer layer, the n-type substrate and the n-type buffer layer both include any one of GaAs, InP, GaSb and GaN, the thickness of the n-type substrate is 450nm, and the thickness of the n-type buffer layer is 250nm.

[0015] In a second aspect of the present application, a semiconductor laser chip with a small horizontal divergence angle and a preparation method are provided. The preparation method is used to prepare a semiconductor laser chip with a small horizontal divergence angle, comprising:

[0016] Preparing an epitaxial wafer, the epitaxial wafer comprising epitaxially growing an n-type cladding layer, an n-type waveguide layer, an active region, a p-type waveguide layer, a p-type cladding layer and a p-type confinement layer in sequence on a substrate;

[0017] The epitaxial wafer is taken out from the MOCVD reaction chamber, and the p-type confinement layer located at the uppermost layer of the epitaxial wafer is etched to remove a part of the conductive dielectric layer in the p-type confinement layer to expose the current blocking layers located at both sides of the p-type confinement layer, and the area between the current blocking layers is used as the current injection area, and the current blocking layers exposed at both sides are the non-current injection area;

[0018] placing the cleaned and dried epitaxial wafer back into the MOCVD reaction chamber for a second epitaxial growth to form a p-type confinement layer and a p-type contact layer on the surface of the epitaxial wafer; and

[0019] A P-side electrode and an N-side electrode are sequentially fabricated on opposite sides of the epitaxial wafer to complete the fabrication of the semiconductor laser.

[0020] The semiconductor laser chip with a small horizontal divergence angle and the preparation method provided by the present invention have the following beneficial effects compared with the prior art:

[0021] (1) Through the special design of the current blocking layer and the conductive medium layer in the p-type confinement layer, the semiconductor laser chip can accurately control the position and shape of the carrier injection region, which helps to improve the carrier injection efficiency. At the same time, by adjusting the formation position of the carrier injection region, the lateral mode of the laser can be effectively controlled, and the quality and focusing ability of the laser beam can be improved. The current blocking layers arranged relatively and at intervals help to form a narrower effective gain region, thereby reducing the horizontal divergence angle of the laser output, improving the directivity and focusing characteristics of the laser beam, achieving the purpose of suppressing the diffusion and aggregation effects of carriers, and at the same time reducing the number of lateral modes, thereby improving the laser output power and beam quality;

[0022] (2) By precisely controlling the ratio of the current injection area to the current blocking area, a sufficiently large area is provided for current injection to ensure effective carrier transport, and this width range can usually meet the power requirements of most applications without being too large to cause additional heat generation. The area ratio of the two opposite and spaced current blocking layers to the carrier injection area is 0.4 to 0.67. By controlling the area ratio of the current blocking layer to the carrier injection area, the injection and distribution of the current can be further refined and optimized. At the same time, this area ratio makes the current blocking area much smaller than the carrier injection area, which can effectively limit the current diffusion and ensure that most of the current is confined to the predetermined injection area. At the same time, the narrower injection area helps to limit the lateral expansion of the laser mode and improve the quality and focusing ability of the laser beam, thereby achieving an optimal balance between current injection efficiency, mode control and device performance. This allows the laser to provide good beam quality and reliability while maintaining high efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 This is a schematic cross-sectional view of the semiconductor laser chip provided by the present invention.

[0025] Explanation of the reference numerals: 1, substrate layer; 2, n-type cladding layer; 3, n-type waveguide layer; 4, active region; 5, p-type waveguide layer; 6, p-type cladding layer; 7, p-type confinement layer; 71, conductive dielectric layer; 72, current blocking layer; 8, p-type contact layer. DETAILED DESCRIPTION

[0026] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate quantity restrictions, but indicate the existence of at least one. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship also changes accordingly.

[0028] refer to Figure 1 The present invention provides a semiconductor laser chip with a small horizontal divergence angle, comprising a substrate layer 1, an n-type cladding layer 2, an n-type waveguide layer 3, an active region 4, a p-type waveguide layer 5, a p-type cladding layer 6, a p-type confinement layer 7 and a p-type contact layer 8 stacked in sequence from bottom to top, wherein:

[0029] In this embodiment, the substrate layer 1 includes an n-type substrate and an n-type buffer layer, both of which include any one of GaAs, InP, GaSb and GaN, the thickness of the n-type substrate is 450nm, and the thickness of the n-type buffer layer is 250nm.

[0030] N-type semiconductor materials are prepared by adding appropriate impurities (such as silicon, antimony, germanium, etc.) so that their main carriers are free electrons. These materials have the characteristics of high electron concentration and high electron mobility, and are widely used in electronic devices and optoelectronic devices. GaAs, InP, GaSb and GaN are all important III-V compound semiconductor materials. They can be prepared into n-type structures by doping and used as substrate materials in various heterostructure devices. In the manufacturing process of heterostructure devices, the n-type buffer layer is usually located between the substrate and the device layer structure, which plays a role in alleviating the lattice mismatch between the substrate and the epitaxial layer, reducing the dislocation density, providing good crystal quality for the growth of subsequent device layers, and providing a conductive channel to reduce the parasitic resistance of the device.

[0031] In this embodiment, the thickness of the p-type waveguide layer 5 is smaller than that of the n-type waveguide layer 3, and the thickness of the p-type cladding layer 6 is smaller than that of the n-type cladding layer 2. Both the p-type waveguide layer 5 and the n-type waveguide layer 3 are doped with Al 0.18-0.22 GaAs, the thickness of the p-type waveguide layer 5 is 150nm, and the thickness of the n-type waveguide layer 3 is 300nm. The p-type cladding layer 6 is doped with Al 0.6-0.8 GaAs, n-type cladding 2 doped with Al 0.22- 0.3GaAs, the thickness of the p-type cladding layer 6 is 1000nm, and the thickness of the n-type cladding layer 2 is 2500nm.

[0032] In one example, the p-type cladding layer 6 has a high Al component. If the conventional wide-strip ridge waveguide sidewall structure is exposed for too long during the wet etching process, oxidation will occur to form defects. However, the p-GaAs layer under the current blocking layer in this solution can prevent the p-type cladding layer 6 with a high Al component from oxidizing, thereby effectively avoiding the increase of series resistance and performance deterioration.

[0033] It can be understood that the vertical epitaxial layer design is characterized by extremely asymmetric thickness and composition of the waveguide layers adjacent to the p-doped and n-doped side waveguides, cladding and active area 4 of the semiconductor laser chip. The design achieves high electro-optical conversion efficiency at high current by combining thin p-side waveguide layers and cladding with high optical confinement and mode gain. The thinning of the p-doped layer ensures low series resistance, light absorption and carrier leakage, while the high mode gain reduces Ith (threshold current) and thermal power saturation, thereby achieving high electro-optical conversion efficiency at high power output.

[0034] Thinner p-doped side waveguide layers and cladding can reduce free carrier absorption (FCA). In the p-type region, the hole concentration is high and the FCA loss is more significant. By thinning the p-doped side structure, this loss can be significantly reduced. At the same time, the thinner p-doped side structure helps to improve the carrier injection efficiency. Due to the low mobility of holes, the thinner p-doped side structure can reduce the distance that holes need to traverse, thereby improving the injection efficiency. High optical confinement means that the light mode is more concentrated in the active region 4, and by increasing the overlap of the mode with the active region 4, the mode gain is improved and the loss of light in the passive region is reduced. The mode gain can be further improved by optimizing the overlap of the optical mode with the gain region.

[0035] The p-type limiting layer 7 includes at least two current blocking layers 72 and a conductive medium layer 71. The conductive medium layer 71 is provided with at least two blocking grooves that are opposite and spaced apart along the length direction of the laser chip. At least two current blocking layers 72 are respectively arranged in corresponding blocking grooves. The p-type limiting layer 7 is used to adjust the formation position of the carrier injection region formed between two adjacent current blocking layers 72 to inhibit the lateral diffusion of current in the p-type limiting layer 7.

[0036] In this embodiment, at least two current blocking layers 72 are symmetrically arranged along the vertical direction of the width center line of the p-type confinement layer 7 .

[0037] This symmetrically designed current blocking layer 72 structure ensures uniform distribution of current in the p-type confinement layer 7, avoids excessive local current density and hot spot formation, and is conducive to forming a stable optical mode, improving the spatial mode quality of laser output, helping to achieve single-mode operation and enhance beam quality. The uniform current distribution also improves the carrier injection efficiency, reduces the threshold current, and improves the overall efficiency and photoelectric conversion efficiency. In terms of reliability, the symmetrical structure reduces the uneven distribution of stress, prolongs the device life, and improves the temperature characteristics and wavelength stability. In addition, this design can better suppress the spatial hole burning effect when operating at high power, optimize the lateral mode control, and enhance the modulation performance.

[0038] The current blocking layer 72 includes a first blocking layer and a second blocking layer stacked in sequence from bottom to top, the first blocking layer is doped with n-GaInP, and the second blocking layer is doped with n-GaAs.

[0039] In this embodiment, the conductive medium layer 71 , the current blocking layer 72 and the p-type cladding layer 6 stacked in sequence form a current-blocking reverse bias junction, which is used to suppress the lateral expansion of the current in the laser chip.

[0040] The blocking reverse bias junction formed by the conductive dielectric layer 71, the current blocking layer 72 and the p-type cladding layer 6 can effectively suppress the lateral expansion of the current, optimize the current injection control, improve the carrier injection efficiency and the overall efficiency of the laser, and improve the laser beam quality and focusing ability. Secondly, the concentrated current injection reduces the threshold current, reduces the non-radiative recombination loss, and improves the energy efficiency of the device.

[0041] It can be understood that a current-blocking reverse bias junction (PNP) is formed in the part close to the active area 4, so that the current blocking layer limits the lateral expansion of the current, wherein a thin layer of n-GaInP is designed in the N-type layer, and when wet etching is performed using a selective etching solution, the lower layer can be used as a blocking layer for high-precision etching of the upper layer, such as when etching n-GaAs in the current blocking layer, n-GaInP can be used as a blocking layer, and when etching n-GaInP, the lower p-GaAs layer can be used as a blocking layer, thereby ensuring the repeatability of subsequent processes.

[0042] In this embodiment, the ratio of the area of ​​two adjacent current blocking layers 72 to the area of ​​the carrier injection region formed between the two adjacent current blocking layers 72 is 0.4-0.67, and the width of the carrier injection region is 300 μm-500 μm.

[0043] By precisely controlling the ratio of the current injection area to the current blocking area, a sufficiently large area is provided for current injection to ensure effective carrier transport, and this width range can usually meet the power requirements of most applications without being too large to cause additional heat generation. The two opposing and spaced current blocking layers are close to the active layer, which means that the current transmission path is shorter, which can effectively reduce current diffusion and ensure that most of the current is confined to the predetermined injection area. At the same time, the narrower injection area helps to limit the lateral expansion of the laser mode and improve the quality and focusing ability of the laser beam, thereby achieving an optimized balance between current injection efficiency, mode control and device performance, which enables the laser to provide good beam quality and reliability while maintaining high efficiency.

[0044] In this embodiment, the p-type cladding layer 6 is doped with Al 0.6-0.8 GaAs, n-type cladding 2 doped with Al 0.22-0.3 GaAs, the thickness of the p-type cladding layer 6 is 1000 nm, and the thickness of the n-type cladding layer 2 is 2500 nm.

[0045] The p-type cladding layer 6 is doped with Al 0.6-0.8 GaAs, a material with a high aluminum content, has a large band gap, which helps to reduce carrier injection losses and improve the recombination efficiency of electrons and holes, thereby improving the efficiency of the laser. The n-type cladding 2 is doped with Al 0.22-0.3 GaAs, a material with a lower aluminum content, has better electron transmission properties and helps improve the current injection efficiency. The thickness of the p-type cladding 6 is 1000nm, so that the thinner p-type cladding 6 can provide sufficient laser light output surface intensity while controlling resistance and heat dissipation problems. The thickness of the n-type cladding 2 is 2500nm, so that the thicker p-type cladding 6 helps the effective injection and transmission of electrons and provides better structural support for the laser chip.

[0046] The p-type contact layer 8 reduces the mechanical flatness of the surface of the semiconductor laser chip after the secondary epitaxial growth, and the step height is roughly equivalent to the thickness of the current blocking layer (usually a total thickness of 60-80nm). It can effectively reduce the influence of the step edge strain field on the laser polarization during the semiconductor chip packaging process, thereby ensuring that the chip packaging has a wider process window. In addition, the thinner current blocking layer reduces the risk of defects in the lateral structure during the secondary epitaxial growth process.

[0047] Through the special design of the current blocking layer 72 and the conductive medium layer 71 in the p-type confinement layer 7, the semiconductor laser chip can accurately control the position and shape of the carrier injection region, which helps to improve the carrier injection efficiency. At the same time, by adjusting the formation position of the carrier injection region, the lateral mode of the laser can also be effectively controlled. The current blocking layers 72 arranged relatively and at intervals help to form a narrower effective gain region, thereby reducing the horizontal divergence angle of the laser output, improving the directionality and focusing characteristics of the laser beam, and achieving the purpose of suppressing the diffusion and aggregation effects of carriers. At the same time, it can reduce the number of lateral modes, improve the laser output power and beam quality, and design the current blocking layer in the p-type confinement layer. The current diffusion stroke of the conventional strip laser is reduced by about half, which effectively reduces the diffusion of lateral carriers.

[0048] It should be noted that the materials of the substrate layer 1, n-type cladding layer 2, n-type waveguide layer 3, active region 4, p-type waveguide layer 5, p-type cladding layer 6, p-type confinement layer 7 and p-type contact layer 8 listed above are for illustration only and are not limited to the above materials. The selected materials and thicknesses are also not limited thereto and can be flexibly changed according to experimental needs in actual experiments.

[0049] This embodiment also provides a preparation method corresponding to a semiconductor laser chip with a small horizontal divergence angle. The preparation method is used to prepare a semiconductor laser chip with a small horizontal divergence angle. The method includes:

[0050] An epitaxial wafer is prepared, wherein the epitaxial wafer comprises an n-type cladding layer 2, an n-type waveguide layer 3, an active region 4, a p-type waveguide layer 5, a p-type cladding layer 6 and a p-type confinement layer 7 epitaxially grown in sequence on a substrate.

[0051] In this step, a high-purity, high-quality GaAs (gallium arsenide) single crystal substrate is used, and the substrate is finely polished and cleaned to ensure surface flatness and cleanliness. Various metal organic sources (such as trimethylgallium, trimethylaluminum, etc.) and gaseous sources (such as arsine) are prepared. These raw materials will be used to grow III-V compound semiconductor materials of different components.

[0052] Epitaxial growth process: n-type cladding layer 2 usually uses AlGaAs material with high Al content and is doped with Si as an n-type dopant; n-type waveguide layer 3 uses AlGaAs with lower Al content and is also doped with Si, but the concentration is lower than that of the cladding, and the thickness of n-type waveguide layer 3 is controlled within the range of 100-200nm; active area 4: grows a multi-quantum well structure, which is usually composed of alternating GaAs quantum wells and AlGaAs barriers, and controls the thickness of each layer at the nanometer level, and the quantum well thickness is usually 5-10nm; the structure of p-type waveguide layer 5 is similar to that of n-type waveguide layer 3, but C or Zn is used as a p-type dopant, and the composition is asymmetric with that of n-type waveguide layer 3 to form good optical confinement; p-type cladding layer 6 uses AlGaAs with high Al content and is doped with C or Zn as a p-type dopant; p-type confinement layer 7 uses highly doped GaAs, and this layer will be partially etched in subsequent processes to form a current injection region.

[0053] The epitaxial wafer is taken out from the MOCVD reaction chamber, and the p-type confinement layer 7 located on the top layer of the epitaxial wafer is etched to etch away part of the conductive dielectric layer 71 in the p-type confinement layer 7 to expose the current blocking layers 72 located on both sides of the p-type confinement layer 7, and the area between the current blocking layers 72 is used as the current injection area, and the exposed current blocking layers 72 on both sides are the non-current injection area.

[0054] In this step, the epitaxial wafer is taken out from the MOCVD reaction chamber, and the epitaxial wafer is preliminarily cleaned to remove possible contaminants on the surface; photoresist is coated on the surface of the epitaxial wafer by spin coating, and the photoresist is exposed and developed through a mask to remove the photoresist in the exposed area (or unexposed area, depending on whether a positive or negative photoresist is used); the epitaxial wafer is etched using a chemical solution (such as a mixture of H2SO4:H2O2:H2O), while the etching time and temperature are controlled to achieve the desired depth (using in-situ monitoring technology, such as laser endpoint detection, to monitor the etching depth in real time or to achieve the desired depth by precisely controlling the etching time); after etching is completed, the etching depth is measured using a surface profiler or an atomic force microscope (AFM), and the morphology of the etched sidewalls is checked using a scanning electron microscope (SEM); after the inspection is completed, it is thoroughly cleaned with solvents such as deionized water and isopropyl alcohol, and blown dry with nitrogen or vacuum dried; ensure that the current blocking layer 72 has been properly exposed and the desired current injection area and non-current injection area are formed.

[0055] The key to this etching process is to precisely control the etching depth and morphology. The etching depth needs to be accurate to the nanometer level to ensure that only part of the conductive dielectric layer 71 in the p-type confinement layer 7 is removed without damaging the underlying structure. The sidewall morphology is also important because it affects the quality of subsequent growth and the performance of the device. The entire process needs to be carried out in a clean room environment to avoid contamination. The selection and optimization of etching parameters usually requires multiple experiments and characterizations to find the best process window.

[0056] The cleaned and dried epitaxial wafer is put back into the MOCVD reaction chamber for a second epitaxial growth to form a p-type confinement layer 7 and a p-type contact layer 8 on the surface of the epitaxial wafer.

[0057] In this step, the etched epitaxial wafer is thoroughly cleaned, usually using organic solvents (such as acetone, isopropanol) and deionized water, and surface treatment is performed, which may include mild chemical etching or plasma cleaning to remove the surface oxide layer, and finally blown dry with high-purity nitrogen; the MOCVD reaction chamber is evacuated and purged with high-purity hydrogen or nitrogen multiple times to remove possible contaminants, the MOCVD reaction chamber is heated to a suitable growth temperature, usually in the range of 600-750°C, and the surface is treated with arsine (AsH3) at high temperature to remove possible residual oxides to ensure good To form a good growth interface, trimethylgallium (TMGa) and arsine (AsH3) source gases are introduced, and at the same time, a p-type doping source, such as a carbon source (CCl4) or a zinc source (DEZn), is introduced at 700°C and a pressure of 50 torr for a growth time of 5-10 minutes; a highly doped GaAs contact layer continues to grow on the p-type confinement layer 7, and the flow of the p-type doping source is increased to obtain a higher doping concentration, and the thickness is usually controlled to be in the range of 100-200nm. Finally, the temperature is controlled to decrease in an arsine atmosphere to prevent the surface arsenic from falling off. After it drops to room temperature, the sample is taken out of the reaction chamber.

[0058] X-ray diffraction (XRD) is used to measure the thickness and composition of the newly grown layer, check the bonding quality of the newly grown layer with the original structure, and ensure that the newly grown layer covers the step structure formed by etching to form a good current limit. The key to secondary epitaxial growth is to ensure that the newly grown layer is well bonded to the original structure while maintaining a high-quality crystal structure.

[0059] The P-side electrode and the N-side electrode are sequentially fabricated on opposite sides of the epitaxial wafer to complete the fabrication of the semiconductor laser.

[0060] In this step, conventional P-side electrode metal production and N-side thinning and electrode production are carried out, and the single-die is split into strips for passivation film and optical film growth on the front and back cavity surfaces. Finally, the single-die is split into strips for packaging to produce the smallest unit of laser elements.

[0061] In one example, first follow the Figure 1 The structure shown is epitaxially grown, and the epitaxial structure grows all the way to the current blocking layer 72 (n-GaAs), and a sacrificial layer is added thereon. Then, the epitaxial wafer is taken out from the MOCVD reaction chamber, and the blocking layer is photolithographically and wet-etched to form a central current injection area, that is, the n-GaAs layer is selectively etched in the central area. Then, the cleaned and dried wafer is placed in the MOCVD reaction chamber, and the etching gas is turned on after the temperature is raised to 650-680°C, and the n-InGaP is etched in situ. After etching for a suitable time, the Ga source is turned on to grow the p-GaAs layer, with a thickness of about 600-800nm.

[0062] Then, conventional P-side electrode metal production, N-side thinning and electrode production are carried out, and the single-die is split into strips for passivation film and optical film growth on the front and back cavity surfaces. Finally, the single-die is split into strips and packaged to produce the smallest unit of laser components.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor laser chip with a small horizontal divergence angle, characterized in that: The invention comprises a substrate layer (1), an n-type cladding layer (2), an n-type waveguide layer (3), an active region (4), a p-type waveguide layer (5), a p-type cladding layer (6), a p-type confinement layer (7) and a p-type contact layer (8) which are stacked in sequence from bottom to top, wherein: The p-type limiting layer (7) comprises at least two current blocking layers (72) and a conductive medium layer (71); at least two blocking grooves which are arranged opposite to each other and at intervals are provided on the conductive medium layer (71) along the length direction of the laser chip; the at least two current blocking layers (72) are respectively arranged in corresponding blocking grooves; and the p-type limiting layer (7) is used to adjust the formation position of a carrier injection region formed between two adjacent current blocking layers (72) to suppress the lateral diffusion of current in the p-type limiting layer (7); The ratio of the area of ​​two adjacent current blocking layers (72) to the carrier injection region formed between the two adjacent current blocking layers (72) is 0.4 to 0.67, and the width of the carrier injection region is 300 μm to 500 μm.

2. The semiconductor laser chip with a small horizontal divergence angle as claimed in claim 1, characterized in that: The at least two current blocking layers (72) are symmetrically arranged along the vertical direction of the width center line of the p-type limiting layer (7).

3. The semiconductor laser chip with a small horizontal divergence angle as claimed in claim 1, characterized in that: The thickness of the p-type waveguide layer (5) is smaller than the thickness of the n-type waveguide layer (3), and the thickness of the p-type cladding layer (6) is smaller than the thickness of the n-type cladding layer (2).

4. The semiconductor laser chip with a small horizontal divergence angle as claimed in claim 1, characterized in that: The current blocking layer (72) comprises a first blocking layer and a second blocking layer stacked in sequence from bottom to top, the first blocking layer is doped with n-GaInP, and the second blocking layer is doped with n-GaAs.

5. The semiconductor laser chip with a small horizontal divergence angle as claimed in claim 1, characterized in that: The p-type waveguide layer (5) and the n-type waveguide layer (3) are both doped with Al 0.18-0.22 GaAs, the thickness of the p-type waveguide layer (5) is 150 nm, and the thickness of the n-type waveguide layer (3) is 300 nm.

6. The semiconductor laser chip with a small horizontal divergence angle as claimed in claim 1, characterized in that: The p-type cladding layer (6) is doped with Al 0.6-0.8 GaAs, the n-type cladding layer (2) is doped with Al 0.22-0.3 GaAs, the thickness of the p-type cladding layer (6) is 1000 nm, and the thickness of the n-type cladding layer (2) is 2500 nm.

7. The semiconductor laser chip with a small horizontal divergence angle as claimed in claim 4, characterized in that: The conductive medium layer (71), the current blocking layer (72) and the p-type cladding layer (6) stacked in sequence form a current-blocking reverse bias junction, and the current-blocking reverse bias junction is used to suppress the lateral expansion of the current in the laser chip.

8. The semiconductor laser chip with a small horizontal divergence angle as claimed in claim 1, characterized in that: The substrate layer (1) comprises an n-type substrate and an n-type buffer layer, wherein the n-type substrate and the n-type buffer layer both comprise any one of GaAs, InP, GaSb and GaN, the thickness of the n-type substrate is 450 nm, and the thickness of the n-type buffer layer is 250 nm.

9. A semiconductor laser chip with a small horizontal divergence angle and a preparation method thereof. The preparation method is used to prepare a semiconductor laser chip with a small horizontal divergence angle as claimed in any one of claims 1 to 8, characterized in that: include: Preparing an epitaxial wafer, the epitaxial wafer comprising epitaxially growing an n-type cladding layer (2), an n-type waveguide layer (3), an active region (4), a p-type waveguide layer (5), a p-type cladding layer (6) and a p-type confinement layer (7) in sequence on a substrate; The epitaxial wafer is taken out from the MOCVD reaction chamber, and the p-type restriction layer (7) located at the top of the epitaxial wafer is etched to remove a portion of the conductive dielectric layer (71) in the p-type restriction layer (7) to expose the current blocking layers (72) located on both sides of the p-type restriction layer (7), and the area between the current blocking layers (72) is used as a current injection area, and the current blocking layers (72) exposed on both sides are non-current injection areas; The cleaned and dried epitaxial wafer is placed back into the MOCVD reaction chamber for a second epitaxial growth to form a p-type confinement layer (7) and a p-type contact layer (8) on the surface of the epitaxial wafer; as well as A P-side electrode and an N-side electrode are sequentially fabricated on opposite sides of the epitaxial wafer to complete the fabrication of the semiconductor laser.

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