Low on-resistance semiconductor power device and method of making same

Abstract

The application relates to a preparation method of a low-conduction-resistance semiconductor power device, which comprises the following steps: etching a groove on a semiconductor substrate; depositing high-purity undoped silicon in the groove to form an intrinsic silicon epitaxial layer; depositing a germanium-silicon epitaxial layer on the intrinsic silicon epitaxial layer, with the temperature being controlled below 800 DEG C, the germanium content being controlled to be less than 20%, and the boron concentration being controlled to be less than 1E18 cm ‑3 The low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) or physical vapor deposition (PVD) method is adopted; wherein the total gas pressure in the LPCVD method is less than 200 torr. By controlling the flow rates of silane and germane gas, the proportion of germane gas in the total gas flow is less than 20%. The application solves the technical problem that the P-type semiconductor material is expanded in the traditional high-temperature epitaxial process, thereby affecting the resistance of the substrate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to a low on-resistance semiconductor power device and its fabrication method. Background Technology

[0002] The development of semiconductor power devices has consistently focused on increasing breakdown voltage and reducing on-resistance. With the introduction and development of superjunction theory, semiconductor power devices have achieved significantly lower on-resistance under the same breakdown voltage conditions, breaking through the traditional "silicon limit." Currently, the manufacturing processes for superjunction devices mainly include multiple epitaxial growth technology, deep trench etching and filling technology, and high-energy particle implantation technology.

[0003] The emergence of deep trench etching-filling technology has solved the problem of non-uniform superjunction structures formed in multiple epitaxial processes, becoming the mainstream process choice for superjunction device manufacturing. However, traditional single-stage high-temperature epitaxy processes have some problems when using deep trench etching-filling technology. During epitaxy, the high temperature causes the P-type semiconductor material to expand into the silicon on both sides of the deep trench, thus affecting the resistivity of the substrate. This phenomenon leads to unstable device performance, limiting further improvements in superjunction devices. Summary of the Invention

[0004] To address the shortcomings of related technologies, this invention provides a low on-resistance semiconductor power device and its fabrication method, solving the technical problem that the substrate resistance is affected by the expansion of P-type semiconductor materials during traditional high-temperature epitaxy processes.

[0005] In one possible implementation, a method for fabricating a low on-resistance semiconductor power device is provided, comprising the following steps: etching trenches on a semiconductor substrate; depositing high-purity undoped silicon within the trenches to form an intrinsic silicon epitaxial layer; depositing a germanium-silicon epitaxial layer on the intrinsic silicon epitaxial layer, wherein the temperature is controlled below 800°C, and the germanium content of the germanium-silicon epitaxial layer is controlled to be <20%, and the boron concentration is controlled to be <1E18 cm⁻¹. -3 The deposition method includes any one of the following: low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and physical vapor deposition (PVD); wherein the total gas pressure in the low-pressure chemical vapor deposition (LPCVD) method is less than 200 torr; wherein controlling the germanium content of the germanium-silicon epitaxial layer to <20% in the low-pressure chemical vapor deposition method includes: introducing silane (SiH4) gas and germanane (GeH4) gas into the reaction chamber and controlling the flow rate of silane gas; controlling the flow rate of germanane gas so that the proportion of germanane gas in the total gas flow rate is less than 20%; and adjusting the temperature in the reaction chamber to keep it below 800℃.

[0006] In one possible implementation, the low-pressure chemical vapor deposition method controls the boron concentration of the germanium-silicon epitaxial layer to be <1E18 cm⁻¹. -3 This includes: introducing borane (B₂H₆) gas into the reaction chamber during the deposition of the germanium-silicon epitaxial layer; and adjusting the flow rate of the borane gas to maintain the boron concentration at less than 1E¹⁸ cm⁻¹. -3 .

[0007] In one possible implementation, depositing high-purity undoped silicon in a trench to form an intrinsic silicon epitaxial layer includes: preheating the substrate surface in a reaction chamber to reach the deposition temperature; introducing high-purity silane (SiH4) gas into the reaction chamber; and adjusting the temperature in the reaction chamber to below 800°C to achieve a set thickness for the intrinsic epitaxial layer.

[0008] In one possible implementation, the total gas pressure in the low-pressure chemical vapor deposition (LPCVD) method is less than 200 torr.

[0009] In one possible implementation, the low-pressure chemical vapor deposition method controls the germanium content of the germanium-silicon epitaxial layer to be less than 20%.

[0010] In one possible implementation, a low on-resistance semiconductor power device is provided, comprising: a semiconductor substrate; a trench etched on the semiconductor substrate; a high-purity undoped intrinsic silicon epitaxial layer within the trench; and a germanium-silicon epitaxial layer within the trench, wherein the germanium-silicon epitaxial layer is deposited on the intrinsic silicon epitaxial layer; wherein the high-purity undoped intrinsic silicon epitaxial layer and the germanium-silicon epitaxial layer within the trench are prepared by a method for fabricating a low on-resistance semiconductor power device.

[0011] Based on the above technical solution, the method for fabricating low on-resistance semiconductor power devices of the present invention solves the problem in the traditional method that the P-type semiconductor material expands into the silicon on both sides of the deep trench during the epitaxial process of a single high-temperature epitaxy, thereby achieving the effect of precise control of the epitaxial morphology. This method can realize the fabrication of superjunction devices with smaller cell sizes, and the single intrinsic semiconductor epitaxy can effectively avoid the influence of deep trench sidewall defects on the epitaxial filling. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0013] Figure 1 This is a schematic diagram illustrating the fabrication process of a low on-resistivity semiconductor power device according to one embodiment.

[0014] In the picture:

[0015] 10. Intrinsic silicon epitaxial layer; 20. Germanium-silicon epitaxial layer; 30. Substrate; 40. Trench. Detailed Implementation

[0016] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0017] In the description of this invention, it should be understood that the terms "center", "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0018] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] To address the technical problem that the substrate resistance is affected by the expansion of P-type semiconductor materials during traditional high-temperature epitaxy, this application provides a low on-resistance semiconductor power device and its fabrication method.

[0021] According to a first aspect of this application, a method for fabricating a low on-resistance semiconductor power device is provided, see [link to relevant documentation]. Figure 1The process includes the following steps: etching trenches 40 on a semiconductor substrate 30; depositing high-purity undoped silicon in the trenches to form an intrinsic silicon epitaxial layer 10; depositing a germanium-silicon epitaxial layer 20 on the intrinsic silicon epitaxial layer 10, with the temperature controlled below 800°C, and controlling the germanium content of the germanium-silicon epitaxial layer to be <20% and the boron concentration to be <1E18 cm⁻¹. -3 The deposition method includes any one of the following: low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and physical vapor deposition (PVD); wherein the total gas pressure in the low-pressure chemical vapor deposition (LPCVD) method is less than 200 torr; wherein controlling the germanium content of the germanium-silicon epitaxial layer to <20% in the low-pressure chemical vapor deposition method includes: introducing silane (SiH4) gas and germanane (GeH4) gas into the reaction chamber and controlling the flow rate of silane gas; controlling the flow rate of germanane gas so that the proportion of germanane gas in the total gas flow rate is less than 20%; and adjusting the temperature in the reaction chamber to keep it below 800℃.

[0022] In the above scheme, firstly, trenches are etched on the semiconductor substrate to provide a suitable structure to accommodate the subsequently deposited material. Then, high-purity undoped silicon is deposited within the trenches to form an intrinsic silicon epitaxial layer, ensuring high purity and low defect density of the substrate. Next, a germanium-silicon epitaxial layer is deposited on the intrinsic silicon epitaxial layer. By controlling the deposition temperature below 800°C (e.g., 720°C) and adjusting the germane gas flow rate, the germanium content is kept below 20%, ensuring that the germanium-silicon epitaxial layer has the doping concentration required to achieve charge balance. A low-pressure chemical vapor deposition method is used, with the total gas pressure controlled below 200 torr, further optimizing the quality and performance of the epitaxial layer. Through a series of precisely controlled deposition steps, a semiconductor power device with low on-resistance is formed. See also... Figure 1 The three figures are schematic diagrams of the deposition of intrinsic silicon epitaxial layer 10, the deposition of germanium-silicon epitaxial layer 20, and the annealing process in the trench.

[0023] This method can reduce the on-resistance of semiconductor power devices, improve device efficiency and performance stability, and further reduce device cell size. By controlling the temperature and gas flow rate during the deposition process, high-quality germanium-silicon epitaxial layers can be obtained, ensuring excellent electrical properties.

[0024] When depositing germanium-silicon epitaxial layers, different deposition methods can be selected, such as plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or physical vapor deposition (PVD), adjusted according to specific requirements and equipment conditions. For different production environments, deposition parameters can be further optimized by adjusting the temperature and gas flow rate within the reaction chamber. Besides silane and germanane, other suitable gases can be selected as reaction source materials to achieve similar technical effects.

[0025] In one possible implementation, the low-pressure chemical vapor deposition method controls the boron concentration of the germanium-silicon epitaxial layer to be <1E18 cm⁻¹. -3 This includes: introducing borane (B₂H₆) gas into the reaction chamber during the deposition of the germanium-silicon epitaxial layer; and adjusting the flow rate of the borane gas to maintain the boron concentration at less than 1E¹⁸ cm⁻¹. -3 .

[0026] This method achieves precise control of the boron concentration in the epitaxial layer by introducing borane (B₂H₆) gas during the deposition of the germanium-silicon epitaxial layer. Boron, as a dopant, can modulate the electrical properties of semiconductor materials. By controlling the flow rate of the borane gas, the boron concentration is maintained at 1E¹⁸ cm⁻¹. -3 The following steps ensure that the conductivity of the germanium-silicon epitaxial layer meets the design requirements.

[0027] By controlling the boron concentration, the electrical properties of germanium-silicon epitaxial layers can be improved, the on-resistance of devices can be reduced, and the operating efficiency and reliability of power devices can be enhanced. Employing low-pressure chemical vapor deposition (LPCVD) makes the entire process more controllable and adaptable to large-scale production needs.

[0028] Besides using borane (B₂H₆) gas as the dopant source, other suitable dopants, such as boron trifluoride (BF₃), can be selected. By adjusting the type and flow rate of the dopant, the electrical properties of the epitaxial layer can be further optimized. Other suitable deposition methods can also be selected, such as molecular beam epitaxy (MBE) or plasma-enhanced chemical vapor deposition (PECVD), to adapt to different production environments and requirements.

[0029] In one possible implementation, depositing high-purity undoped silicon in the trench to form an intrinsic silicon epitaxial layer includes: preheating the substrate surface in the reaction chamber to reach the deposition temperature; introducing high-purity silane (SiH4) gas into the reaction chamber; and adjusting the temperature in the reaction chamber to below 800°C to achieve a set thickness for the intrinsic epitaxial layer.

[0030] In the above scheme, a high-purity intrinsic silicon epitaxial layer is formed by controlling the temperature and gas flow rate within the reaction chamber. First, preheating is performed within the reaction chamber to bring the substrate surface to a suitable deposition temperature. Then, high-purity silane (SiH4) gas is introduced into the reaction chamber, and a high-purity undoped silicon layer is formed within the trenches using chemical vapor deposition. By adjusting the temperature within the reaction chamber to below 800℃, the intrinsic epitaxial layer reaches the set thickness, effectively avoiding the influence of deep trench sidewall defects on epitaxial filling and ensuring the uniformity and high quality of the epitaxial layer.

[0031] This method can effectively control the purity and thickness of silicon epitaxial layers, improving their electrical performance and structural integrity. Preheating and temperature control reduce the introduction of impurities and lattice defects, enhancing the conductivity and reliability of power devices. Furthermore, the use of high-purity silane as the reaction source ensures high purity and low defect density in the epitaxial layer, making it suitable for manufacturing high-performance semiconductor devices.

[0032] Different heating methods, such as infrared heating or resistance heating, can be selected during preheating and deposition to suit different equipment conditions. High-purity silane (SiH4) gas can also be replaced with other high-purity silicon sources, such as dichlorosilane (SiH2Cl2) or trichlorosilane (SiHCl3), adjusted according to specific process requirements. The deposition temperature range can be appropriately adjusted based on material properties and equipment conditions to further optimize the performance of the epitaxial layer.

[0033] In one possible implementation, the total gas pressure in the low-pressure chemical vapor deposition (LPCVD) method is less than 200 torr.

[0034] For example, it could be 120 torr.

[0035] This method, by controlling the total gas pressure below 200 torr, makes the chemical vapor deposition process more stable and controllable. Under low-pressure conditions, molecular collisions of the reactive gases are reduced, and the deposition rate can be precisely controlled, which is beneficial for forming high-quality germanium-silicon epitaxial layers.

[0036] By controlling the total gas pressure below 200 torr, the uniformity and quality of germanium-silicon epitaxial layers can be further improved, defects and stress can be reduced, and the electrical performance and reliability of semiconductor devices can be enhanced. Furthermore, low-pressure conditions help reduce reaction temperature and energy consumption, increasing the economic efficiency and environmental friendliness of the process.

[0037] The total gas pressure setting can be adjusted according to specific equipment and process requirements, typically ranging from 100 torr to 200 torr. Under certain conditions, even lower pressures can be selected to optimize the deposition process. Furthermore, different deposition methods (such as PECVD, MBE, etc.) may have different gas pressure requirements, which can be adjusted according to specific needs.

[0038] In one possible implementation, the low-pressure chemical vapor deposition method controls the germanium content of the germanium-silicon epitaxial layer to be less than 20%.

[0039] This method maintains the germanium content in the germanium-silicon epitaxial layer below 20%, for example, 15%, by precisely controlling the flow rate of germanane (GeH4) gas. The specific steps include simultaneously introducing silane (SiH4) gas and germanane (GeH4) gas into the reaction chamber and adjusting the flow rate ratio of the two gases so that the proportion of germanane gas in the total gas flow rate reaches the set value.

[0040] By introducing a germanium content of less than 20%, the epitaxial temperature can be effectively reduced, preventing the P-type material from expanding outwards and ensuring that the doping concentration of the epitaxial material remains at a set value to achieve charge balance, thereby improving the conductivity and stability of the device. Optimizing the germanium content can effectively reduce the epitaxial temperature, preventing the P-type material from expanding outwards, improving the performance of semiconductor power devices, extending their lifespan, and making it suitable for the manufacture of high-performance electronic devices.

[0041] The germanium content can be adjusted within a certain range, such as 10% to 20%, to suit different application scenarios and device requirements. Other suitable compounds, such as germanium tetrafluoride (GeF4), can also be selected as the gas source for introducing germanium, and adjustments can be made according to specific process requirements. Different deposition methods (such as MBE, LPE, etc.) may have different methods for controlling the germanium content, which can be optimized according to specific circumstances.

[0042] In one possible embodiment, a low on-resistance semiconductor power device is provided, characterized in that it comprises: a semiconductor substrate 30; a trench 40 etched on the semiconductor substrate; a high-purity undoped intrinsic silicon epitaxial layer 10 within the trench; and a germanium-silicon epitaxial layer 20 within the trench, wherein the germanium-silicon epitaxial layer is deposited on the intrinsic silicon epitaxial layer; wherein the high-purity undoped intrinsic silicon epitaxial layer and the germanium-silicon epitaxial layer within the trench are prepared by the fabrication method of the low on-resistance semiconductor power device according to any of the above embodiments.

[0043] This semiconductor power device is fabricated by etching trenches on a semiconductor substrate and then sequentially depositing a high-purity undoped intrinsic silicon epitaxial layer and a germanium-silicon epitaxial layer within the trenches. These steps create a semiconductor power device with low on-resistance, optimizing its electrical performance and structural integrity.

[0044] The above-described fabrication method can significantly reduce the on-resistance of semiconductor power devices, thereby improving their operating efficiency and performance stability. Precise control of the high-purity, undoped intrinsic silicon epitaxial layer and the germanium-silicon epitaxial layer ensures high device quality and low defect density, making it suitable for manufacturing high-performance electronic devices.

[0045] This invention proposes a low-temperature germanium-silicon epitaxial growth technique. By using germanium-silicon material for secondary epitaxy at temperatures below 800°C, the low-temperature epitaxial growth ensures the metastable state of the entire epitaxial layer, eliminates dislocations in the channels, and precisely controls the epitaxial layer with good thickness / concentration uniformity in both vertical and horizontal directions, effectively preventing the expansion of P-type semiconductor material. At the same time, using germanium-silicon material instead of traditional silicon material can effectively reduce the temperature required for epitaxy, further preventing the expansion of P-type semiconductor material.

[0046] Low-temperature epitaxy is used to complete deep trench backfilling, effectively preventing P-type semiconductor material from expanding into the silicon on both sides of the deep trench. Using germanium-silicon material instead of traditional silicon material for epitaxy effectively reduces the required epitaxy temperature, further preventing P-type semiconductor material expansion. Employing a single intrinsic semiconductor epitaxy followed by a single low-temperature germanium-silicon epitaxy ensures that the P-type semiconductor material does not expand outwards, and the single intrinsic semiconductor epitaxy effectively avoids the impact of deep trench sidewall defects on epitaxial filling. Applying low-temperature epitaxy technology to semiconductor power devices completes the fabrication of superjunction structures, solving the problem of P-type semiconductor material expanding into the silicon on both sides of the deep trench during a single high-temperature epitaxy in superjunction devices, thus altering the substrate resistivity. It also solves the problem of P-type epitaxial material prematurely sealing the deep trench opening in the deep trench etching and filling technology for superjunction devices, forming a complete deep trench backfill.

[0047] The technology employs low-temperature epitaxy at 800℃ and below; uses germanium-silicon materials for epitaxy; avoids external expansion of P-type semiconductor materials without restriction, such as diborane; has no restriction on the aspect ratio of the trenches etched in the epitaxial growth front-end; has no restriction on the type of carrier wafer, with a thickness of 50um to 800um; and has no restriction on the type of device using this technology, such as semiconductor power devices.

[0048] Finally, it should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0049] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A method for fabricating a low on-resistance semiconductor power device, characterized in that, Includes the following steps: Trenches are formed by etching on a semiconductor substrate; High-purity, undoped silicon is deposited within the trench to form an intrinsic silicon epitaxial layer, including: Preheating is performed in the reaction chamber to bring the substrate surface to the deposition temperature; High-purity silane (SiH4) gas is introduced into the reaction chamber; The temperature inside the reaction chamber is adjusted to below 800℃ so that the intrinsic epitaxial layer reaches the set thickness; A germanium-silicon epitaxial layer was deposited on the intrinsic silicon epitaxial layer at a temperature controlled below 800℃. The germanium content of the germanium-silicon epitaxial layer was controlled to be <20%, and the boron concentration was controlled to be <1E18 cm⁻¹. - ³, The deposition method includes any of the following: low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and physical vapor deposition (PVD). In the low-pressure chemical vapor deposition (LPCVD) method, the total gas pressure is less than 200 torr; Among them, the low-pressure chemical vapor deposition method controls the germanium content of the germanium-silicon epitaxial layer to be <20%, including: Silane (SiH4) gas and germanane (GeH4) gas are introduced into the reaction chamber, and the flow rate of silane gas is controlled. Control the flow rate of germane gas so that the proportion of germane gas in the total gas flow rate is less than 20%; Adjust the temperature inside the reaction chamber to keep it below 800℃; Among them, the low-pressure chemical vapor deposition method controls the boron concentration of the germanium-silicon epitaxial layer to be <1E18 cm⁻¹. - ³Includes: Introducing borane (B2H6) gas into the reaction chamber during the deposition of germanium-silicon epitaxial layers; Adjust the flow rate of borane gas to maintain the boron concentration below 1E18 cm⁻¹. - ³.

2. A low on-resistance semiconductor power device, characterized in that, include; Semiconductor substrate; The trench contains a high-purity, undoped intrinsic silicon epitaxial layer; A germanium-silicon epitaxial layer is deposited on an intrinsic silicon epitaxial layer within the trench. The high-purity undoped intrinsic silicon epitaxial layer and germanium-silicon epitaxial layer in the trench are prepared by the method for preparing low on-resistivity semiconductor power devices as described in claim 1.

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