Light emitting diode and manufacturing method thereof
By simultaneously forming an insulating material mask layer during the formation of the current blocking layer of a light-emitting diode, and using a photoresist mask layer of a transparent conductive layer for patterning, the problem of complex processes in the prior art is solved, achieving the effects of simplified processes and reduced costs.
Patent Information
- Application Number
- CN202610005455.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-05
- Publication Date
- 2026-05-26
AI Technical Summary
Existing methods for manufacturing light-emitting diodes (LEDs) involve complex processes, impacting efficiency and cost.
By simultaneously forming an insulating material mask layer during the formation of the current blocking layer, and using a photoresist mask layer of the transparent conductive layer for patterning, the number of times the photoresist mask layer is used is reduced, and the transparent conductive layer, steps, and isolation trenches can be etched simultaneously.
The process was simplified, production efficiency was improved, and costs were reduced.
Smart Images
Figure CN122094249A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for manufacturing the same. Background Technology
[0002] A light-emitting diode (LED) chip is a semiconductor electronic component that emits light. As a highly efficient, environmentally friendly, and green new type of solid-state lighting source, it is being rapidly and widely used in applications such as traffic lights, automotive interior and exterior lights, urban landscape lighting, and mobile phone backlights.
[0003] In related technologies, the fabrication method of a light-emitting diode includes: preparing a photoresist mask on an epitaxial layer, then patterning the epitaxial layer to form steps, and removing the photoresist mask; preparing a new photoresist mask on the epitaxial layer, then patterning the epitaxial layer to form isolation trenches, and removing the photoresist mask; forming an insulating material layer on the epitaxial layer, then patterning it to form a current blocking layer; fabricating a transparent conductive material layer covering the epitaxial layer and the current blocking layer, then preparing a photoresist mask, and patterning the transparent conductive material layer to form a transparent conductive layer.
[0004] The above-mentioned manufacturing process involves too many steps, such as forming photoresist masks and patterning, which is complex and affects the manufacturing efficiency and cost of light-emitting diodes. Summary of the Invention
[0005] This disclosure provides a light-emitting diode (LED) and a method for manufacturing the same, which can reduce the number of manufacturing steps, improve manufacturing efficiency, and reduce costs. The technical solution is as follows: On one hand, a method for manufacturing a light-emitting diode is provided, the method comprising: Fabricate an insulating material layer covering the epitaxial layer; The insulating material layer is patterned to form a current blocking layer and an insulating material mask layer. The insulating material mask layer covers the stepped area of the epitaxial layer and exposes the isolation groove area of the epitaxial layer. Fabricate a transparent conductive material layer covering the epitaxial layer and the current blocking layer; A first photoresist mask layer is formed on the transparent conductive material layer, the first photoresist mask layer exposing the step region and the isolation trench region; Under the cover of the first photoresist mask layer, the transparent conductive material layer is patterned to obtain a transparent conductive layer; Under the cover of the first photoresist mask layer, the insulating material mask layer of the step region, the epitaxial layer, and the epitaxial layer of the isolation trench region are patterned to form steps and isolation trenches on the epitaxial layer.
[0006] Optionally, the insulating material layer used to fabricate the epitaxial layer includes: A SiO2 layer with a thickness of 750~800nm is fabricated on the epitaxial layer.
[0007] Optionally, the isolation groove region is an annular region surrounding the edge of the epitaxial layer, and the step region is an annular region located within and adjacent to the isolation groove region.
[0008] Optionally, under the cover of the first photoresist mask layer, the transparent conductive material layer is patterned to obtain a transparent conductive layer, including: The transparent conductive material layer is etched using a transparent conductive material etching solution to remove the transparent conductive material layer that is not covered by the first photoresist mask layer; The transparent conductive material layer is further etched using the transparent conductive material etching solution to etch away the edge portion of the transparent conductive material layer covered by the first photoresist mask layer, thereby obtaining the transparent conductive layer.
[0009] Optionally, the width of the edge portion of the transparent conductive material layer covered by the etched first photoresist mask layer is 3 to 4 micrometers.
[0010] Optionally, the insulating material mask layer in the stepped region, the epitaxial layer, and the epitaxial layer in the isolation trench region are patterned, including: Cl2 and BCl3 were used as etching gases to perform ICP etching on the insulating material mask layer and the epitaxial layer. The etching rate of the first photoresist mask layer is equal to the etching rate of the epitaxial layer, and the etching rate of the epitaxial layer is greater than the etching rate of the insulating material mask layer.
[0011] Optionally, the etching depth of the epitaxial layer in the step region is 1 to 1.2 micrometers, and the etching depth of the epitaxial layer in the isolation trench region is 5.5 to 6 micrometers.
[0012] Optionally, a first photoresist mask layer is formed on the transparent conductive material layer, including: A first photoresist mask layer with a thickness of 9-10 micrometers is fabricated on the transparent conductive material layer.
[0013] Optionally, the method further includes: Remove the first photoresist mask layer; A first electrode and a second electrode are fabricated, wherein the first electrode is located on the transparent conductive layer and the second electrode is located on the step; An insulating reflective layer is fabricated covering the epitaxial layer, the transparent conductive layer, the first electrode, and the second electrode; A first pad and a second pad are fabricated on the insulating reflective layer. The first pad passes through the insulating reflective layer and is electrically connected to the first electrode, and the second pad passes through the insulating reflective layer and is electrically connected to the second electrode.
[0014] On the other hand, a light-emitting diode is provided, which is manufactured using the method described in any one of the first aspects.
[0015] The beneficial effects of the technical solutions provided in this disclosure are: In this embodiment, a current blocking layer is first formed through patterning, and simultaneously, an insulating material mask layer covering the step region of the epitaxial layer is formed. Then, a transparent conductive material layer is formed through photolithography (i.e., preparation of a photoresist mask layer) and patterning. After the transparent conductive layer is prepared, the photoresist mask layer used during the transparent conductive layer preparation is used for masking. Simultaneously, the insulating material mask layer and the epitaxial layer in the step region, as well as the epitaxial layer in the isolation trench region, are patterned. Because the step region is covered by the insulating material mask layer, the final etching depth is smaller than the etching depth in the isolation trench region, thus forming a step in the step region and an isolation trench in the isolation trench region. In this fabrication process, the transparent conductive layer, steps, and isolation trenches use the same photoresist mask layer, reducing the fabrication and removal of photoresist masks by two steps. The steps and isolation trenches are formed in a single etching operation, reducing one etching process. This significantly reduces the number of steps involved in forming the photoresist mask and patterning, simplifying the process, thereby improving manufacturing efficiency and reducing costs. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart illustrating a method for manufacturing a light-emitting diode according to an embodiment of the present disclosure; Figure 2 This is a flowchart of another method for manufacturing a light-emitting diode provided in this embodiment of the present disclosure; Figure 3 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 8 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 9 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 10 This is a schematic diagram of the structure of a light-emitting diode during the manufacturing process according to an embodiment of this disclosure; Figure 11 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure.
[0018] The attached figures are labeled as follows: 10: Epitaxial layer; 101: First semiconductor layer; 102: Multiple quantum well; 103: Second semiconductor layer; 110: Step; 120: Isolation trench; 20: Current blocking layer; 30: Transparent conductive layer; 40: First electrode; 50: Second electrode; 60: Insulating reflective layer; 70: First pad; 80: Second pad; 90: Substrate; 300: Insulating material mask layer; 400: Transparent conductive material layer; 500: First photoresist mask layer. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.
[0020] Figure 1 This is a flowchart illustrating a method for manufacturing a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 1 The method includes the following steps: S11. Fabricate an insulating material layer covering the epitaxial layer.
[0021] S12. The insulating material layer is patterned to form a current blocking layer and an insulating material mask layer.
[0022] The insulating material mask layer covers the stepped region of the epitaxial layer, and the insulating material mask layer exposes the isolation groove region of the epitaxial layer.
[0023] S13. Fabricate a transparent conductive material layer covering the epitaxial layer and the current blocking layer.
[0024] S14. A first photoresist mask layer is formed on the transparent conductive material layer.
[0025] The first photoresist mask layer exposes the step region and the isolation trench region.
[0026] S15. Under the cover of the first photoresist mask layer, the transparent conductive material layer is patterned to obtain a transparent conductive layer.
[0027] S16. Under the cover of the first photoresist mask layer, the insulating material mask layer of the step region, the epitaxial layer, and the epitaxial layer of the isolation trench region are patterned to form a step and an isolation trench on the epitaxial layer.
[0028] That is, in this embodiment, the transparent conductive layer, the step, and the isolation trench use the same photoresist mask layer, reducing the fabrication and removal of the photoresist mask layer by two steps. The step and the isolation trench are formed in a single etching process, reducing one etching step.
[0029] The light-emitting diodes (LEDs) produced by the methods provided in this disclosure can be mini LEDs.
[0030] In this embodiment, a current blocking layer is first formed through patterning, and simultaneously, an insulating material mask layer covering the step region of the epitaxial layer is formed. Then, a transparent conductive material layer is formed through photolithography (i.e., preparation of a photoresist mask layer) and patterning. After the transparent conductive layer is prepared, the photoresist mask layer used during the transparent conductive layer preparation is used for masking. Simultaneously, the insulating material mask layer and the epitaxial layer in the step region, as well as the epitaxial layer in the isolation trench region, are patterned. Because the step region is covered by the insulating material mask layer, the final etching depth is smaller than the etching depth in the isolation trench region, thus forming a step in the step region and an isolation trench in the isolation trench region. In this fabrication process, the transparent conductive layer, steps, and isolation trenches use the same photoresist mask layer, reducing the fabrication and removal of photoresist masks by two steps. The steps and isolation trenches are formed in a single etching operation, reducing one etching process. This significantly reduces the number of steps involved in forming the photoresist mask and patterning, simplifying the process, thereby improving manufacturing efficiency and reducing costs.
[0031] Figure 2 This is a flowchart illustrating another method for fabricating a light-emitting diode (LED) as disclosed in this publication. See also... Figure 2 The method includes the following steps: S21. An epitaxial layer is fabricated on the substrate surface.
[0032] In the embodiments of this disclosure, the substrate can be any of the following: sapphire substrate, silicon substrate, etc. This disclosure does not limit the material of the substrate.
[0033] For example, the substrate is a sapphire substrate.
[0034] The epitaxial layer includes a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer, which are sequentially stacked on the substrate.
[0035] In this process, one of the first semiconductor layer and the second semiconductor layer is an N-type GaN layer, and the other is a P-type GaN layer.
[0036] Among them, the multiple quantum well layer can be an InGaN / GaN superlattice structure.
[0037] In one example, step S21 includes: The first step is to grow an N-type GaN layer (the first semiconductor layer) on the substrate surface.
[0038] For example, an N-type GaN layer can be grown on a substrate surface using a metal-organic chemical vapor deposition (MOCVD) device.
[0039] In the embodiments disclosed herein, semiconductor layer growth can be achieved using Veeco K465i, C4, or RB MOCVD equipment or AIXTRON metal-organic chemical vapor deposition equipment. High-purity H2 (hydrogen), high-purity N2 (nitrogen), or a mixture of high-purity H2 and high-purity N2 is used as the carrier gas; high-purity NH3 is used as the N source; trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources; trimethylindium (TMIn) is used as the indium source; silane (SiH4) is used as the N-type dopant; trimethylaluminum (TMAl) is used as the aluminum source; and magnesium pyrocene (CP2Mg) is used as the P-type dopant.
[0040] The second step is to grow a multiple quantum well (MQW) layer on the surface of the N-type GaN layer.
[0041] Among them, the multiple quantum well layer is an InGaN / GaN superlattice structure.
[0042] For example, an InGaN / GaN layer is grown on the surface of an N-type GaN layer using an MOCVD device.
[0043] The third step is to grow a P-type GaN layer (the second semiconductor layer) on the surface of the multi-quantum well layer.
[0044] For example, a P-type GaN layer is grown on the surface of an InGaN / GaN layer using an MOCVD device.
[0045] The structure of the epitaxial layer described above is only one example. In other examples, the epitaxial layer may include more film layers, such as buffer layers.
[0046] Optionally, after step S21, the method may further include: performing a surface cleaning process on the surface of the epitaxial layer.
[0047] S22. Fabricate an insulating material layer covering the epitaxial layer.
[0048] In one example, step S22 may include: A SiO2 layer with a thickness of 750~800nm is fabricated on the epitaxial layer.
[0049] For example, a SiO2 layer with a thickness of 760 or 770 nm can be fabricated on an epitaxial layer.
[0050] In this implementation, using a SiO2 layer of the aforementioned thickness can, on the one hand, meet the requirements of the current blocking layer to be formed subsequently, and on the other hand, reduce the etching depth of the area when etching the epitaxial layer, thereby forming a step of appropriate thickness.
[0051] In this embodiment of the disclosure, the insulating material layer can be fabricated using a plasma-enhanced chemical vapor deposition (PECVD) process.
[0052] S23. The insulating material layer is patterned to form a current blocking layer and an insulating material mask layer.
[0053] The insulating material mask layer covers the stepped region of the epitaxial layer, and the insulating material mask layer exposes the isolation groove region of the epitaxial layer.
[0054] In one example, step S23 may include: The first step is to form a second photoresist mask layer on the insulating material layer, the second photoresist mask layer exposing the area outside the current blocking layer and the insulating material mask layer.
[0055] In this embodiment of the disclosure, the process of fabricating the photoresist mask layer includes steps such as coating photoresist, exposure, and development.
[0056] For example, the thickness of the second photoresist mask layer can be 2 to 3 micrometers, such as 2.5 micrometers.
[0057] The second step involves patterning the insulating material layer under the cover of the second photoresist mask layer to obtain the current blocking layer and the insulating material mask layer.
[0058] The patterning process for the insulating material layer includes: etching the SiO2 layer not covered by the second photoresist mask layer using a buffered oxide etching (BOE) solution; The third step is to remove the second photoresist mask layer.
[0059] Figure 3 This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 3 As shown, the isolation groove region A is an annular region surrounding the edge of the epitaxial layer 10, and the step region B is an annular region located within and adjacent to the isolation groove region A.
[0060] A ring-shaped insulating material mask layer 300 is formed in step region B, and a current blocking layer 20 is formed within step region B.
[0061] like Figure 3 As shown, the current blocking layer 20 includes two spaced-apart finger structures.
[0062] like Figure 3 As shown, except for the step region B and the current blocking layer 20, the epitaxial layer 10 is exposed.
[0063] S24. Fabricate a transparent conductive material layer covering the epitaxial layer and the current blocking layer.
[0064] For example, the transparent conductive material layer is an indium tin oxide (ITO) layer.
[0065] In one example, step S24 may include: An ITO thin film is sputtered on the epitaxial layer using magnetron sputtering technology, covering the epitaxial layer and the current blocking layer, serving as a transparent conductive material layer.
[0066] For example, the thickness of the transparent conductive material layer is 40~60nm, such as 50nm.
[0067] Following this step, the method may further include: performing rapid thermal annealing (RTA).
[0068] S25. A first photoresist mask layer is formed on the transparent conductive material layer.
[0069] The first photoresist mask layer exposes the step region and the isolation trench region.
[0070] In one example, step S25 may include: A first photoresist mask layer with a thickness of 9-10 micrometers is fabricated on the transparent conductive material layer.
[0071] In this implementation, the photoresist mask layer of the aforementioned thickness not only plays a role in the patterning process of the transparent conductive material layer, but also protects the epitaxial layer during the subsequent etching process.
[0072] For example, the thickness of the first photoresist mask layer is 9.5 micrometers.
[0073] Figure 4 This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 4 As shown, a transparent conductive material layer 400 is first covered on the entire surface of the epitaxial layer 10, and then a first photoresist mask layer 500 is formed on the transparent conductive material layer 400.
[0074] In this embodiment of the present disclosure, the pattern of the first photoresist mask layer 500 is the same as the pattern of the upper surface of the epitaxial layer 10 after etching.
[0075] S26. Under the cover of the first photoresist mask layer, the transparent conductive material layer is patterned to obtain a transparent conductive layer.
[0076] In one example, step S26 may include: The transparent conductive material layer is etched using a transparent conductive material etching solution to remove the transparent conductive material layer that is not covered by the first photoresist mask layer; The transparent conductive material layer is further etched using the transparent conductive material etching solution to etch away the edge portion of the transparent conductive material layer covered by the first photoresist mask layer, thereby obtaining the transparent conductive layer.
[0077] In this implementation, the area of the final transparent conductive layer is smaller than the area covered by the first photoresist mask layer through the above process. This ensures that after subsequent etching steps, there is a certain distance between the transparent conductive layer and the surface edge of the P-type GaN layer, thereby avoiding leakage caused by conduction.
[0078] Among them, the etching solution for transparent conductive materials is also known as ITO etching solution.
[0079] For example, the width of the edge portion of the transparent conductive material layer covered by the etched first photoresist mask layer is 3 to 4 micrometers.
[0080] That is, after etching the steps, the distance from the edge of the transparent conductive layer to the surface edge of the P-type GaN layer is 3 to 4 micrometers.
[0081] For example, after etching the steps, the distance from the edge of the transparent conductive layer to the surface edge of the P-type GaN layer is 3.5 micrometers.
[0082] In this implementation, the aforementioned width ensures that leakage is avoided due to conduction, while also ensuring that the current spread is sufficiently good.
[0083] Figure 5 This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 5 As shown, a first photoresist mask layer 500 covers the area outside the isolation trench region A and the step region B. After etching, the transparent conductive material layer 400 forms a transparent conductive layer 30.
[0084] S27. Under the cover of the first photoresist mask layer, the insulating material mask layer of the step region, the epitaxial layer, and the epitaxial layer of the isolation trench region are patterned to form a step and an isolation trench on the epitaxial layer.
[0085] In one example, step S27 may include: Cl2 and BCl3 were used as etching gases to perform inductively coupled plasma (ICP) etching on the insulating material mask layer and the epitaxial layer. The etching rate of the first photoresist mask layer is equal to the etching rate of the epitaxial layer, and the etching rate of the epitaxial layer is greater than the etching rate of the insulating material mask layer.
[0086] For example, during the etching gas etching process, the selection ratio of GaN to photoresist is 1:1, and the selection ratio of GaN to SiO2 is 6:1.
[0087] In this implementation, the gas described above is used for ICP etching. Since the etching rate of the epitaxial layer is greater than that of the insulating material mask layer, the final etching depth in the step region is less than the depth of the isolation trench region. As a result, a shallower step (mesa) is formed in the step region of the epitaxial layer, and a deeper isolation trench (Isolation Trench, ISO) is formed in the isolation trench region.
[0088] For example, the etching depth of the epitaxial layer in the step region is 1 to 1.2 micrometers, and the etching depth of the epitaxial layer in the isolation trench region is 5.5 to 6 micrometers.
[0089] For example, the etching depth of the epitaxial layer in the step region is 1.1 micrometers, and the etching depth of the epitaxial layer in the isolation trench region is 5.8 micrometers.
[0090] In this implementation, the aforementioned depth is used such that the bottom of the isolation trench is located on the substrate, and the bottom of the step is located on the first semiconductor layer.
[0091] Since the thickness of the first photoresist mask layer is 9-10 micrometers and the etching rate of the first photoresist mask layer is equal to the etching rate of the epitaxial layer, the epitaxial layer in the area covered by the first photoresist mask layer is not etched.
[0092] Figure 6 This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 6 As shown, after the above-mentioned etched isolation trench area A exposes the substrate 90, forming an isolation trench 120, and the step area B exposes the epitaxial layer 10, forming a step 110.
[0093] S28. Remove the first photoresist mask layer.
[0094] In this embodiment of the disclosure, the photoresist mask layer can be removed using a wet photoresist removal process.
[0095] Figure 7 This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 7 As shown, the first photoresist mask layer 500 is removed, exposing the transparent conductive layer 30 and the epitaxial layer 10 surrounding the transparent conductive layer 30.
[0096] S29. Fabricate a first electrode and a second electrode, wherein the first electrode is located on the transparent conductive layer and the second electrode is located on the step.
[0097] For example, the first electrode and the second electrode are formed by a stack of multiple materials selected from Cr, Al, Ti, Ni, Pt and Au.
[0098] In one example, step S29 may include: A photoresist mask layer with a mask pattern is formed using photolithography. Electrode materials are deposited using electron beam evaporation technology; Remove the mask pattern and the electrode material above the mask pattern, leaving the electrode material in the mask pattern, to obtain the first electrode and the second electrode.
[0099] In this step, the thickness of the photoresist mask layer can be 3.5 to 4.5 micrometers, for example, 4 micrometers. The thickness of the first electrode and the second electrode can be 1.5 to 2 micrometers, for example, 1.8 micrometers.
[0100] Both the first electrode and the second electrode are strip electrodes, with two first electrodes and two second electrodes.
[0101] Figure 8This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 8 As shown, a first electrode 40 and a second electrode 50 are fabricated. The first electrode 40 is located on the current blocking layer 20, and the second electrode 50 is located within the step 110 of the epitaxial layer 10.
[0102] S30. Fabricate an insulating reflective layer covering the epitaxial layer, the transparent conductive layer, the first electrode, and the second electrode.
[0103] For example, the insulating reflective layer is a distributed Bragg reflector (DBR) layer, which may be a stack of at least one period of silicon oxide layer (e.g., SiO2) and titanium oxide layer (e.g., TiO2).
[0104] In one example, step S30 may include: Evaporated DBR film layer; A photoresist mask layer is formed on the DBR film using photolithography. ICP dry etching is performed on the DBR film layer not covered by the mask layer to form vias. The function of the vias is to allow subsequent bonding pads to pass through the connecting electrodes. Remove the photoresist mask layer to obtain the insulating reflective layer.
[0105] In this step, the thickness of the photoresist mask layer can be 9-10 micrometers, for example, 9.5 micrometers. The thickness of the insulating reflective layer can be 3-4 micrometers, for example, 3.5 micrometers.
[0106] Figure 9 This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 9 As shown, the insulating reflective layer 60 covers the epitaxial layer 10, the transparent conductive layer 30, the first electrode 40, and the second electrode 50. The insulating reflective layer 60 has through holes 601 corresponding to each of the first electrode 40 and the second electrode 50.
[0107] S31. A first pad and a second pad are formed on the insulating reflective layer.
[0108] The first pad passes through the insulating reflective layer and is electrically connected to the first electrode, and the second pad passes through the insulating reflective layer and is electrically connected to the second electrode.
[0109] For example, the first pad and the second pad are formed using a stack of Ti, Al, Ni and Au.
[0110] In one example, step S31 may include: A photoresist mask layer with a mask pattern is formed using photolithography. Electron beam evaporation technology is used to deposit pad materials; Remove the mask pattern and the pad material above the mask pattern, leaving the pad material in the mask pattern to obtain the first pad and the second pad.
[0111] In this step, the thickness of the photoresist mask layer can be 8-9 micrometers, for example, 8.5 micrometers. The thickness of the first and second pads can be 5-6 micrometers, for example, 5.5 micrometers.
[0112] Figure 10 This is a schematic diagram of the structure of a light-emitting diode (LED) during the manufacturing process according to an embodiment of this disclosure. Figure 10 As shown, the first pad 70 is electrically connected to the two first electrodes 40 through the two through holes 601 of the insulating reflective layer 60, and the second pad 80 is electrically connected to the two second electrodes 50 through the two through holes 601 of the insulating reflective layer 60.
[0113] Compared with related technologies, the above-described method for manufacturing light-emitting diodes provided in this disclosure reduces two photolithography processes, one dry etching process, and two resist removal processes, thereby shortening the manufacturing cycle of Mini LED chips and reducing chip manufacturing costs.
[0114] Figure 11 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. Figure 11 for Figure 10 For the cross-sectional view of C-C', see [link / reference]. Figure 11 The light-emitting diode includes: an epitaxial layer 10, a current blocking layer 20, and a transparent conductive layer 30.
[0115] The current blocking layer 20 is located on the surface of the epitaxial layer 10, and the transparent conductive layer 30 is located on the surface of the epitaxial layer 10 and covers the current blocking layer 20. The epitaxial layer 10 includes a step 110.
[0116] Optionally, the light-emitting diode further includes a first electrode 40 and a second electrode 50, the first electrode 40 being located on the current blocking layer 20 and the second electrode 50 being located within the step 110 of the epitaxial layer 10.
[0117] In this embodiment of the disclosure, the light-emitting diode further includes: an insulating reflective layer 60, a first pad 70, a second pad 80, and a substrate 90.
[0118] The epitaxial layer 10 is located on the substrate 90. The insulating reflective layer 60 covers the epitaxial layer 10, the transparent conductive layer 30, the first electrode 40, and the second electrode 50. The first pad 70 and the second pad 80 are located on opposite sides of the insulating reflective layer 60. The first pad 70 passes through the insulating reflective layer 60 and is electrically connected to the first electrode 40, and the second pad 80 passes through the insulating reflective layer 60 and is electrically connected to the second electrode 50.
[0119] See you again Figure 11 An isolation trench 120 is also formed on the substrate 90 surrounding the epitaxial layer 10.
[0120] In the embodiments disclosed herein, the substrate 90 can be any of the following substrates: sapphire substrate, silicon substrate, etc. The material of the substrate is not limited in this disclosure.
[0121] For example, substrate 90 is a sapphire substrate.
[0122] In this embodiment of the disclosure, the epitaxial layer 10 includes a first semiconductor layer 101, a multiple quantum well layer 102, and a second semiconductor layer 103 sequentially stacked on the substrate 90.
[0123] Among them, one of the first semiconductor layer 101 and the second semiconductor layer 103 is an N-type GaN layer and the other is a P-type GaN layer.
[0124] Among them, the multiple quantum well layer 102 can be an InGaN / GaN superlattice structure.
[0125] In this embodiment of the disclosure, the current blocking layer 20 can be a silicon compound layer, such as a SiO2 layer.
[0126] In this embodiment of the disclosure, the transparent conductive layer 30 may be an ITO layer.
[0127] In this embodiment of the disclosure, the first electrode 40 and the second electrode 50 can be multilayer electrodes formed from Cr, Al, Ti, Ni, Pt and Au.
[0128] In this embodiment of the disclosure, the insulating reflective layer 60 may be a distributed Bragg reflector (DBR) layer, which may be a stack of at least one periodic silicon oxide layer (e.g., SiO2) and titanium oxide layer (e.g., TiO2).
[0129] In this embodiment, the insulating reflective layer 60 has through holes 601 corresponding to the first electrode 40 and the second electrode 50, respectively, and the electrodes and pads are electrically connected through the through holes 601.
[0130] In this embodiment of the disclosure, the first pad 70 and the second pad 80 can be multilayer pads formed from various materials such as Ti, Al, Ni and Au.
[0131] In the embodiments disclosed herein, the epitaxial layer may include other film layers, such as a buffer layer, in addition to the first semiconductor layer, multiple quantum wells, and the second semiconductor layer.
[0132] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A method for manufacturing a light-emitting diode, characterized in that, The method includes: An insulating material layer covering the epitaxial layer (10) is fabricated; The insulating material layer is patterned to form a current blocking layer (20) and an insulating material mask layer (300). The insulating material mask layer (300) covers the step region B of the epitaxial layer (10) and exposes the isolation groove region A of the epitaxial layer (10). A transparent conductive material layer (400) is fabricated covering the epitaxial layer (10) and the current blocking layer (20). A first photoresist mask layer (500) is formed on the transparent conductive material layer (400), the first photoresist mask layer (500) exposing the step region B and the isolation trench region A; Under the cover of the first photoresist mask layer (500), the transparent conductive material layer (400) is patterned to obtain a transparent conductive layer (30). Under the cover of the first photoresist mask layer (500), the insulating material mask layer (300) of the step region B, the epitaxial layer (10) and the epitaxial layer (10) of the isolation trench region A are patterned to form a step (110) and an isolation trench (120) on the epitaxial layer (10).
2. The method according to claim 1, characterized in that, The process of fabricating the insulating material layer covering the epitaxial layer (10) includes: A SiO2 layer with a thickness of 750~800nm is formed on the epitaxial layer (10).
3. The method according to claim 1, characterized in that, The isolation groove region A is an annular region that runs around the edge of the epitaxial layer (10), and the step region B is an annular region located within the isolation groove region A and adjacent to the isolation groove region A.
4. The method according to any one of claims 1 to 3, characterized in that, Under the cover of the first photoresist mask layer (500), the transparent conductive material layer (400) is patterned to obtain a transparent conductive layer (30), comprising: The transparent conductive material layer (400) is etched using a transparent conductive material etching solution to remove the transparent conductive material layer (400) that is not covered by the first photoresist mask layer (500). The transparent conductive material layer (400) is further etched using the transparent conductive material etching solution to etch away the edge portion of the transparent conductive material layer (400) covered by the first photoresist mask layer (500) to obtain the transparent conductive layer (30).
5. The method according to claim 4, characterized in that, The width of the edge portion of the transparent conductive material layer (400) covered by the etched first photoresist mask layer (500) is 3-4 micrometers.
6. The method according to any one of claims 1 to 3, characterized in that, The insulating material mask layer (300) and the epitaxial layer (10) of the stepped region B and the epitaxial layer (10) of the isolation trench region A are patterned, including: Cl2 and BCl3 were used as etching gases to perform ICP etching on the insulating material mask layer (300) and the epitaxial layer (10); The etching rate of the first photoresist mask layer (500) is equal to the etching rate of the epitaxial layer (10), and the etching rate of the epitaxial layer (10) is greater than the etching rate of the insulating material mask layer (300).
7. The method according to claim 6, characterized in that, The etching depth of the epitaxial layer (10) in the step region B is 1~1.2 micrometers, and the etching depth of the epitaxial layer (10) in the isolation trench region A is 5.5~6 micrometers.
8. The method according to claim 7, characterized in that, Fabricating a first photoresist mask layer (500) on the transparent conductive material layer (400) includes: A first photoresist mask layer (500) with a thickness of 9 to 10 micrometers is formed on the transparent conductive material layer (400).
9. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Remove the first photoresist mask layer (500); A first electrode (40) and a second electrode (50) are fabricated, wherein the first electrode (40) is located on the transparent conductive layer (30) and the second electrode (50) is located on the step (110); An insulating reflective layer (60) is fabricated covering the epitaxial layer (10), the transparent conductive layer (30), the first electrode (40), and the second electrode (50). A first pad (70) and a second pad (80) are formed on the insulating reflective layer (60). The first pad (70) passes through the insulating reflective layer (60) and is electrically connected to the first electrode (40). The second pad (80) passes through the insulating reflective layer (60) and is electrically connected to the second electrode (50).
10. A light-emitting diode, characterized in that, The light-emitting diode is manufactured using the method described in any one of claims 1 to 9.