Fabrication methods and power devices

Abstract

This application discloses a method for fabricating a power device and a power device. The method includes: performing a first photolithography process on an original photoresist layer on a first surface of a wafer to obtain a first photoresist layer; performing a first dry etching process on the first photoresist layer and a first region based on a first pattern in the first photoresist layer to form a first trench in the first region of the wafer; performing a second photolithography process on the first photoresist layer after the first dry etching process to obtain a second photoresist layer; performing a second dry etching process on the second photoresist layer, a second region, and the first trench based on a second pattern in the second photoresist layer to obtain a second trench; and fabricating a power device based on the wafer containing the second trench. The embodiments of this application can remove the damaged layer formed by the first dry etching process on the wafer through a second dry etching process, thereby improving the performance and reliability of the power device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a method for fabricating a power device and the power device itself. Background Technology

[0002] Silicon carbide (SiC) is one of the third-generation semiconductor materials, possessing advantages such as high breakdown electric field, high thermal conductivity, and high saturated electron mobility, making it a promising candidate for power devices. Compared to silicon, SiC has a larger bandgap, higher thermal conductivity, higher electron saturation drift velocity, and a critical breakdown electric field 10 times that of silicon, making it an ideal semiconductor material for applications requiring high temperature, high frequency, high power, and radiation resistance. However, due to SiC's high hardness and strong corrosion resistance, the traditional trench fabrication methods used in silicon (Si)-based power devices are not entirely suitable for fabricating trenches in SiC-based power devices.

[0003] Currently, in the process of fabricating trench gates for silicon carbide-based power devices, a one-step dry etching process is generally used to prepare the trenches.

[0004] However, the etching power of the one-step dry etching process is relatively high, which can easily damage the silicon carbide surface in the trench, causing surface defects and thus reducing the performance and reliability of silicon carbide-based power devices. Summary of the Invention

[0005] The purpose of this application is to provide a method for fabricating a power device and a power device in general, which can solve the problem of reduced performance and reliability of power devices caused by related technologies during the trench fabrication process.

[0006] In a first aspect, embodiments of this application provide a method for fabricating a power device, the method comprising:

[0007] A first photolithography process is performed on the original photoresist layer on the first surface of the wafer to obtain a first photoresist layer; the first photoresist layer includes a first pattern that exposes a first region in the first surface.

[0008] Based on the first pattern, a dry etching process is performed on the first photoresist layer and the first region to form a first trench in the first region of the wafer.

[0009] A second photolithography process is performed on the first photoresist layer after a dry etching process to obtain a second photoresist layer; the second photoresist layer includes a second pattern that exposes the first trench and the second region; the second region is the region in the first surface that is connected to the sidewall of the first trench;

[0010] Based on the second pattern, a second dry etching process is performed on the second photoresist layer, the second region, and the first trench to obtain a second trench; the difference between the size of the second trench and the size of the first trench is greater than or equal to the thickness of the damage layer formed in the wafer by the first dry etching process; the power of the second dry etching process is less than the power of the first dry etching process.

[0011] Power devices are fabricated based on a wafer containing the second trench.

[0012] Optionally, the original photoresist layer includes positive photoresist and negative photoresist mixed in a preset ratio;

[0013] The first photolithography process, which involves performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain the first photoresist layer, includes:

[0014] The original photoresist layer on the first region is masked using a first mask, and the negative photoresist in the original photoresist layer on the third region is exposed to obtain the original photoresist layer after the first photolithography process; the third region is the region outside the first region on the first surface.

[0015] The original photoresist layer after the first photolithography process is developed to remove the unexposed original photoresist layer in the first region, thus obtaining the first photoresist layer.

[0016] Optionally, the step of performing a second photolithography process on the first photoresist layer after a first dry etching process to obtain a second photoresist layer includes:

[0017] The first photoresist layer after a first dry etching process on the fourth region is masked using a second mask, and the positive photoresist in the first photoresist layer after a first dry etching process on the second region is exposed to obtain the first photoresist layer after the second photolithography process; the fourth region is the region on the first surface other than the first region and the second region.

[0018] The first photoresist layer after the second photolithography process is developed to remove the first photoresist layer exposed on the second region, thereby obtaining the second photoresist layer.

[0019] Optionally, the preset ratio is: the positive photoresist accounts for 10% to 90% of the original photoresist layer; or, the negative photoresist accounts for 10% to 90% of the original photoresist layer.

[0020] Optionally, the original photoresist layer includes an original positive photoresist layer and an original negative photoresist layer sequentially stacked on the first surface; the first photoresist layer includes a first positive photoresist layer and a first negative photoresist layer sequentially stacked on the first surface;

[0021] The first photolithography process, which involves performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain the first photoresist layer, includes:

[0022] The original photoresist layer on the first region is masked using a first photomask, and the original negative photoresist layer on the third region is exposed to obtain the original negative photoresist layer after the first photolithography process; the third region is the region outside the first region on the first surface.

[0023] The original negative photoresist layer after the first photolithography process is developed to remove the unexposed original negative photoresist layer in the first region, thus obtaining the first negative photoresist layer.

[0024] The original photoresist layer on the third region is masked using a third mask, and the original positive photoresist layer on the first region is exposed to obtain the original positive photoresist layer after the first photolithography process.

[0025] The original positive photoresist layer after the first photolithography process is developed to remove the original positive photoresist layer exposed on the first region, thus obtaining the first positive photoresist layer.

[0026] Optionally, the first photoresist layer after a single dry etching process is a first positive photoresist layer; the step of performing a second photolithography process on the first photoresist layer after a single dry etching process to obtain a second photoresist layer includes:

[0027] The first positive photoresist layer on the fourth region is masked using a second photomask, and the first positive photoresist layer on the second region is exposed to obtain the first positive photoresist layer after the second photolithography process; the fourth region is the region on the first surface other than the first region and the second region.

[0028] The first positive photoresist layer after the second photolithography process is developed to remove the first positive photoresist layer exposed on the second region, thereby obtaining the second photoresist layer.

[0029] Optionally, the thickness of the original negative photoresist layer is equal to the depth of the first trench; the thickness of the original positive photoresist layer is greater than or equal to the difference between the depth of the second trench and the depth of the first trench.

[0030] Optionally, the step of performing a second dry etching process on the second photoresist layer, the second region, and the first trench based on the second pattern to obtain the second trench includes:

[0031] Simultaneously, the inner walls of the second region and the first groove are subjected to a second dry etching process to obtain the second groove; the inner wall includes a side wall and a bottom inner wall, and the angle between the side wall and the plane containing the first surface is 0° to 60°.

[0032] Optionally, the thickness of the original photoresist layer is 3 μm to 10 μm.

[0033] Optionally, the etching power of the first dry etching process is 200W to 2000W, and the etching power of the second dry etching process is 50W to 200W.

[0034] Optionally, the thickness of the damaged layer is from 0.03 μm to 0.3 μm.

[0035] Optionally, the thickness of the original photoresist layer is greater than or equal to the depth of the second trench.

[0036] Secondly, embodiments of this application provide a power device, which is prepared using the power device preparation method described above.

[0037] The power device fabrication method provided in this application embodiment involves performing a first dry etching process on the first photoresist layer and a first region based on a first pattern in the first photoresist layer on the first surface of a wafer to form a first trench in the first region of the wafer. Then, a second photolithography process is performed on the first photoresist layer after the first dry etching process to obtain a second photoresist layer. Based on a second pattern in the second photoresist layer, a second dry etching process is performed on the second photoresist layer, the second region, and the first trench to obtain a second trench. In this application embodiment, the power of the second dry etching process is less than the power of the first dry etching process, and the difference between the size of the second trench and the size of the first trench is greater than or equal to the thickness of the damage layer formed in the wafer during the first dry etching process. By etching the first trench using a low-power second dry etching process, the second trench is obtained. This ensures that the size of the second trench meets the size requirements of trenches in power devices while also removing the damage layer formed during the first dry etching process in the wafer, avoiding the impact of defects in the damage layer on the performance of the power device, and improving the performance and reliability of the power device. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the steps of a method for fabricating a power device according to an embodiment of this application;

[0039] Figure 2This is a schematic diagram of the wafer structure in the fabrication process of a power device provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the wafer structure in another power device fabrication process provided in this application embodiment;

[0041] Figure 4 This is a schematic diagram of the wafer structure in another power device fabrication process provided in this application embodiment;

[0042] Figure 5 This is a schematic diagram of the wafer structure in another power device fabrication process provided in this application embodiment;

[0043] Figure 6 This is a schematic diagram of a wafer structure including a second trench provided in an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0045] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0046] Method Implementation Examples

[0047] The fabrication method of the power device provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0048] Reference Figure 1 , Figure 1 A flowchart illustrating the steps of a method for fabricating a power device according to an embodiment of this application is shown, as follows: Figure 1 As shown, the method specifically includes steps S101 and S105:

[0049] Step S101: Perform a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain a first photoresist layer; the first photoresist layer includes a first pattern that exposes a first region in the first surface.

[0050] It should be noted that the power devices in the embodiments of this application may include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs). The wafer may be either silicon carbide or single-crystal silicon; in the embodiments of this invention, the power device may be a silicon carbide-based power device or a silicon-based power device, and this application does not specifically limit this.

[0051] The original photoresist layer is obtained by coating a first surface of a wafer with photoresist; wherein the first surface is any surface of the wafer, and the original photoresist layer may include at least one of positive photoresist and negative photoresist.

[0052] Understandably, photoresists can be categorized into positive and negative photoresists. The portion of positive photoresist exposed to ultraviolet light is removed during development, while the portion of negative photoresist exposed to ultraviolet light is retained after development. Specifically, positive photoresists mainly consist of resin, photosensitizer, and solvent. Under ultraviolet light irradiation, the resin undergoes a chemical reaction, and the resulting reactants react with the developer in an acid-base reaction, being removed during the development process. Negative photoresists mainly consist of polymer monomers, photosensitizer, and solvent. Under ultraviolet light irradiation, due to the action of the photosensitizer, the polymer monomers undergo a polymerization reaction, causing the soluble negative photoresist to form a three-dimensional molecular network insoluble in the developer, thus being retained during development.

[0053] In this embodiment, the first photoresist layer is obtained by performing a first photolithography process on the original photoresist layer using a mask corresponding to the first pattern; the first photolithography process includes at least one ultraviolet exposure and development process. Specifically, in step S101, the original photoresist layer can be subjected to at least one ultraviolet exposure and development process according to the type of photoresist in the original photoresist layer to obtain a first photoresist layer including the first pattern.

[0054] The first pattern in the first photoresist layer is used to expose a first region in the first surface, and the first region is the region where the first trench prepared in the wafer in step S102 is located.

[0055] Step S102: Based on the first pattern, perform a dry etching process on the first photoresist layer and the first region to form a first trench in the first region of the wafer.

[0056] It should be noted that during a dry etching process, the entire first surface of the wafer containing the first photoresist layer needs to be dry-etched. In step S102, the first photoresist layer and the wafer in the first region need to be dry-etched simultaneously, and a first trench is formed in the first region of the wafer.

[0057] Reference Figure 2 This illustration shows a schematic diagram of the wafer structure in the fabrication process of a power device according to an embodiment of this application. After step S101 and before step S102, which involves a dry etching process on the first photoresist layer and the first region, the first surface of the wafer containing the original photoresist layer is a flat surface, and the first photoresist layer includes a first pattern exposing the first region on the wafer surface. After the dry etching process on the first photoresist layer and the first region in step S102, a portion of the first photoresist layer with the same depth as the first trench is etched away, and a first trench is formed in the first region of the wafer.

[0058] It should be noted that the number of first trenches, the width of the first trenches, and the spacing between each first trench can be determined according to the design parameters of the power device, and this application embodiment does not impose specific limitations on these parameters. The width of the first trench is equal to the width of the first region, and the width of the first region can be determined based on the designed trench width in the power device and the thickness of the damage layer formed in the wafer during a single dry etching process.

[0059] Specifically, when the design width of the trench is X μm and the thickness of the damage layer is Y μm, the width of the first region (i.e. the width of the first trench) can be (X-2Y) μm; correspondingly, when the design depth of the trench is T μm, the first depth of the first trench can be (TY) μm.

[0060] Step S103: Perform a second photolithography process on the first photoresist layer after the first dry etching process to obtain a second photoresist layer; the second photoresist layer includes a second pattern that exposes the first trench and the second region; the second region is the region in the first surface that is connected to the sidewall of the first trench.

[0061] Specifically, after step S102, a second photolithography process can be performed on the first photoresist layer after the first dry etching process to obtain a second photoresist layer. The second pattern in the second photoresist layer is used to expose the first trench and the second region in the first surface that is connected to the sidewall of the first trench.

[0062] In this embodiment, the second photoresist layer is obtained by performing a second photolithography process on the first photoresist layer after a dry etching process using a mask corresponding to the second pattern; the second photolithography process includes at least one ultraviolet exposure and development process. Specifically, in step S102, depending on the type of photoresist in the first photoresist layer after a dry etching process, at least one ultraviolet exposure and development process can be performed on the first photoresist layer after a dry etching process to obtain a second photoresist layer including the second pattern.

[0063] like Figure 2 As shown, the second region is the area in the first surface that is connected to the sidewalls on both sides of the first groove; each first groove corresponds to two second regions separated by the first groove.

[0064] In the case where the trench design width is X μm and the damage layer thickness is Y μm, the width of each second region in the first surface can be Y μm.

[0065] Step S104: Based on the second pattern, perform a second dry etching process on the second photoresist layer, the second region, and the first trench to obtain the second trench.

[0066] Wherein, the difference between the size of the second trench and the size of the first trench is greater than or equal to the thickness of the damage layer formed in the wafer by the first dry etching process; the power of the second dry etching process is less than the power of the first dry etching process; for example, the power of the first dry etching process can be greater than or equal to 200 watts (W), and the power of the second dry etching process can be less than or equal to 200 watts (W). In this embodiment, the power of the second dry etching process is less than the power of the first dry etching process, and the difference between the size of the second trench and the size of the first trench is greater than or equal to the thickness of the damage layer formed in the wafer by the first dry etching process. This can remove the damage layer formed by the first dry etching process in the wafer, so that the size of the second trench meets the size requirements of the trench in the power device, while also reducing the damage caused to the wafer by the second dry etching process, thereby improving the performance and reliability of the power device.

[0067] It should be noted that the second trench prepared in step S104 is a trench that meets the design requirements for trench dimensions in power devices; refer to Figure 2 The second groove is obtained by performing a second dry etching process on the basis of the first groove. In the embodiments of this application, the size of the first groove is smaller than the size of the second groove, and the size can be the width and depth of the groove.

[0068] Specifically, when the designed width of the trench is X μm and the thickness of the damaged layer is Y μm, the width of the first trench can be (X-2Y) μm, and the width of the second region can be Y μm; the width of the second trench is equal to twice the width of the second region plus the width of the first trench, that is, the width of the second trench is X μm; correspondingly, when the designed depth of the trench is T μm, the first depth of the first trench can be (TY) μm, and the second depth of the second trench can be T μm.

[0069] It is understandable that in step S104, the width of the second dry etching process on the sidewall of the first trench is the width of the second region (i.e., the thickness of the damage layer), and the etching depth on the bottom surface of the first trench can be greater than or equal to the thickness of the damage layer.

[0070] It should be noted that during the secondary dry etching process, the entire surface of the wafer containing the second photoresist layer needs to be subjected to secondary dry etching. In step S104, the second photoresist layer, the wafer at the second region where the second pattern in the second photoresist layer is exposed, and the inner wall of the first trench need to be subjected to secondary dry etching simultaneously to obtain the second trench. It can be understood that the second trench corresponds to the first region in the first surface and the second region connected to both sides of the first region.

[0071] It should be noted that the second trench is obtained by further etching the second region in the wafer and the inner wall of the first trench through a secondary dry etching process; specifically, the inner wall of the first trench includes a sidewall and a bottom inner wall; in step S104, based on the first trench, the sidewall of the first trench is subjected to secondary dry etching to further expand the width of the first trench to the second region connected to the sidewall of the first trench, and the bottom inner wall of the first trench is subjected to secondary dry etching to further expand the depth of the first trench to the designed depth, thus obtaining the second trench.

[0072] In this embodiment, a first dry etching process is performed on the first photoresist layer and the first region, with the thickness of the etched first photoresist layer being the same as the thickness of the etched wafer. A second dry etching process is then performed on the second photoresist layer, the second region, and the first trench, with the thickness of the etched second photoresist layer also being the same as the thickness of the etched wafer. In step S102, to form the first trench in the wafer while ensuring that the first photoresist layer is not completely etched, the thickness of the original photoresist layer needs to be greater than the depth of the first trench. Furthermore, to prevent etching of the wafer outside the second region and the first trench during the second dry etching process in step S104, the thickness of the second photoresist layer also needs to be greater than or equal to the difference between the depth of the second trench and the depth of the first trench. Therefore, it can be determined that in step S101, the thickness of the original photoresist layer prepared on the first surface needs to be greater than or equal to the depth of the second trench.

[0073] It is understandable that if the thickness of the original photoresist layer is greater than or equal to the depth of the second trench, it can be guaranteed that after step S102, the thickness of the first photoresist layer after the first dry etching process is greater than or equal to the difference between the depth of the second trench and the depth of the first trench. Therefore, during the second dry etching process in step S104, the wafer surface outside the second region and the first trench will not be etched.

[0074] It should be noted that, in the embodiments of this application, the primary dry etching process and the secondary dry etching process can include, but are not limited to, dry etching methods such as magnetic neutral loop discharge (NLD) plasma etching, inductively coupled plasma (ICP) etching, and reactive ion etching (RIE). Although the process conditions of different dry etching methods vary slightly, their impact on etching power is basically the same.

[0075] For example, when the power device is a silicon carbide metal oxide semiconductor field-effect transistor (MOS transistor), the second trench is a Trench trench.

[0076] Step S105: Fabricate a power device based on the wafer containing the second trench.

[0077] In this embodiment, after obtaining a wafer containing the second trench through step S104, the photoresist residue on the wafer surface containing the second trench can be removed using methods known to those skilled in the art, and then subsequent power device processes can be carried out, such as gate oxide process, metal gate filling process, front metal contact process, terminal withstand ring process, back implantation and metal process, etc., to finally complete the entire process of power device fabrication and obtain a power device that meets the specifications. The specific process for removing the photoresist residue on the wafer surface containing the second trench and carrying out subsequent power device processes can be carried out using methods known to those skilled in the art, and will not be described in detail here.

[0078] The power device fabrication method provided in this application embodiment uses a secondary dry etching process with a power lower than that of the primary dry etching process. Furthermore, the difference between the size of the second trench and the size of the first trench is greater than or equal to the thickness of the damage layer formed in the wafer during the primary dry etching process. By using a low-power secondary dry etching process to etch the first trench, the size of the second trench meets the size requirements of the trench in the power device while removing the damage layer formed during the primary dry etching process. This avoids the impact of defects in the damage layer on the performance of the power device, improving its performance and reliability. In addition, since the damage layer formed during the primary dry etching process can be removed through a secondary dry etching process in this application embodiment, in practical applications, while avoiding the impact of defects in the damage layer on the performance of the power device, the power of the primary dry etching process can be appropriately increased to improve the efficiency of fabricating the first trench, thereby improving the efficiency of power device fabrication.

[0079] Optionally, the original photoresist layer includes positive photoresist and negative photoresist mixed in a preset ratio; step S101, which involves performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain a first photoresist layer, includes steps S1011 to S1012:

[0080] Step S1011: Use a first mask to block the original photoresist layer on the first region and expose the negative photoresist in the original photoresist layer on the third region to obtain the original photoresist layer after the first photolithography process; the third region is the region outside the first region on the first surface.

[0081] Step S1012: Develop the original photoresist layer after the first photolithography process to remove the unexposed original photoresist layer in the first region, and obtain the first photoresist layer.

[0082] In the embodiments of this application, when the original photoresist layer includes positive photoresist and negative photoresist mixed in a preset ratio, the original photoresist layer on the first surface of the wafer can be subjected to a first photolithography process through steps S1011 to S1012 to obtain a first photoresist layer.

[0083] Specifically, refer to Figure 3 This illustrates a schematic diagram of the wafer structure in the fabrication process of another power device provided in this application embodiment; as shown... Figure 3 As shown, during the first photolithography process on the original photoresist layer on the first surface of the wafer:

[0084] First, the original photoresist layer on the first region is masked using a first mask.

[0085] Then, the original photoresist layer on the third region outside the first region of the first surface is exposed to obtain the original photoresist layer after the first photolithography treatment. The exposure conditions for exposing the original photoresist layer on the third region are the same as those for exposing negative photoresist. Specifically, the original photoresist layer on the third region is exposed using an ultraviolet spectrum of 300nm to 450nm, thereby achieving the effect of exposing the negative photoresist in the original photoresist layer on the third region. This causes the components in the negative photoresist to undergo a polymerization reaction to form a three-dimensional molecular network that is insoluble in the developer. As a result, the original photoresist layer on the third region is retained during the development process in step S1012. During the development process in step S1012, the original photoresist layer on the first region that is blocked by the first mask is dissolved and removed by the developer, exposing the first region in the first surface.

[0086] It should be noted that when the original photoresist layer includes positive and negative photoresist mixed in a preset ratio, the negative photoresist in the original photoresist layer is exposed, causing the components in the negative photoresist to undergo a polymerization reaction to form a three-dimensional molecular network insoluble in the developer. The positive photoresist in this part of the original photoresist layer is fixed in the three-dimensional molecular network structure formed by the negative photoresist and is also retained in the development process of step S1012. However, the negative photoresist in the original photoresist layer that has not been exposed in the first region does not form a three-dimensional molecular network insoluble in the developer, so it is dissolved in the developer and removed in the development process of step S1012. The positive photoresist in this part of the original photoresist layer collapses during the dissolution of the negative photoresist and is dissolved and removed along with the negative photoresist, thereby exposing the first region in the first surface.

[0087] In this embodiment of the application, a suitable preset ratio needs to be determined in advance. During the process of steps S1011 to S1012, the unexposed original photoresist layer in the original photoresist layer after the first photolithography process is developed and removed, while the exposed original photoresist layer can be retained on the first surface, so as to cover the third region.

[0088] Next, the original photoresist layer after the first photolithography process is developed to remove the unexposed original photoresist layer in the first region, thus obtaining the first photoresist layer.

[0089] It is understood that the original photoresist layer after the first photolithography process includes the original photoresist layer exposed on the third region and the original photoresist layer not exposed on the first region. While the negative photoresist in the original photoresist layer exposed on the third region forms a three-dimensional molecular network that makes the photoresist layer on the third region insoluble in the developer, the negative photoresist in the original photoresist layer not exposed on the first region dissolves in the developer. The positive photoresist in this portion of the original photoresist layer collapses during the dissolution of the negative photoresist and is dissolved and removed along with it, thereby exposing the first region in the first surface, resulting in the first photoresist layer including the first pattern.

[0090] In addition, in order to achieve the development and removal of the original photoresist containing both positive and negative photoresist, the developing solution used in the development process of step S1012 can be adapted and improved. For example, a certain proportion of components that can dissolve positive photoresist can be added to the developing solution to achieve rapid removal of the unexposed original photoresist layer on the first region.

[0091] In this embodiment of the application, when the first photoresist layer is obtained through step S1012, step S102 can be performed to dry etch the first photoresist layer and the first region based on the first pattern in the first photoresist layer, thereby forming a first trench in the first region of the wafer.

[0092] Optionally, step S103, which involves performing a second photolithography process on the first photoresist layer after a single dry etching process to obtain a second photoresist layer, includes steps S1031 to S1032:

[0093] Step S1031: Use a second mask to block the first photoresist layer after the first dry etching process on the fourth region, and expose the positive photoresist in the first photoresist layer after the first dry etching process on the second region to obtain the first photoresist layer after the second photolithography process; the fourth region is the region outside the first region and the second region on the first surface.

[0094] Step S1032: Develop the first photoresist layer after the second photolithography process to remove the first photoresist layer exposed on the second region, and obtain the second photoresist layer.

[0095] In the embodiments of this application, when the original photoresist layer includes positive photoresist and negative photoresist mixed in a preset ratio, the first photoresist layer after a first dry etching process can be subjected to a second photolithography process through steps S1031 to S1032 to obtain a second photoresist layer.

[0096] Specifically, such as Figure 3 As shown, during the second photolithography process on the first photoresist layer after the first dry etching process:

[0097] First, the first photoresist layer after a dry etching process on the fourth region is masked using a second mask; wherein, the fourth region is the region outside the first and second regions in the first surface, and the fourth region and the second region constitute the third region in the first surface.

[0098] Then, the first photoresist layer after the first dry etching process on the second region is exposed to obtain the first photoresist layer after the second photolithography process.

[0099] The exposure conditions for exposing the first photoresist layer after the previous dry etching process in the second region are the same as those for exposing positive photoresist. Specifically, the first photoresist layer after the previous dry etching process in the second region is exposed using an ultraviolet spectrum of 160nm to 280nm. This exposes the positive photoresist in the first photoresist layer after the previous dry etching process in the second region, allowing the components in the positive photoresist to react under ultraviolet light to generate reactants that can undergo acid-base reactions with the developer. Consequently, the first photoresist layer exposed on the second region is dissolved and removed by the developer during the development process in step S1032, exposing the second region on the first surface. During the development process in step S1032, the first photoresist layer after the previous dry etching process on the fourth region, which is blocked by the second mask, remains on the fourth region because it is insoluble in the developer, thus covering the fourth region.

[0100] It should be noted that when the original photoresist layer includes positive and negative photoresist mixed in a preset ratio, the positive photoresist in the first photoresist layer after the first dry etching process on the second region is exposed in step S1031, so that the positive photoresist is dissolved in the developer during the development process in step S1032 and removed. Moreover, the negative photoresist in this part of the first photoresist layer collapses during the dissolution of the positive photoresist and is dissolved and removed along with the positive photoresist, thereby exposing the second region in the first surface. The first photoresist layer after the first dry etching process on the fourth region, which is blocked by the second mask, cannot be removed by the developer during the development process in step S1032 because it is not exposed to ultraviolet light. Accordingly, the negative photoresist in this part of the first photoresist layer after the first dry etching process is fixed in the positive photoresist and will also be retained during the development process in step S1032.

[0101] Then, the first photoresist layer after the second photolithography process is developed to remove the first photoresist layer exposed on the second region, thus obtaining the second photoresist layer.

[0102] It is understood that the first photoresist layer after the second photolithography process includes the first photoresist layer exposed on the second region and the first photoresist layer that has not been exposed. When the first photoresist layer exposed on the second region dissolves in the developer to expose the first region in the first surface, and the first photoresist layer that has not been exposed on the fourth region is retained, a second photoresist layer including the second pattern is obtained.

[0103] In addition, in order to achieve the development and removal of the original photoresist containing both positive and negative photoresist, the developing solution used in the development process of step S1032 can be adapted and improved. For example, a certain proportion of components that can dissolve negative photoresist can be added to the developing solution to achieve rapid removal of the first photoresist layer after exposure on the second region.

[0104] In this embodiment of the application, if the second photoresist layer is obtained through step S1032, step S104 can be performed to perform a second dry etching process on the second photoresist layer, the second region exposed in the first surface, and the first trench based on the second pattern to obtain the second trench.

[0105] Optionally, the preset ratio between positive and negative photoresist in the original photoresist layer is: positive photoresist accounts for 10% to 90% of the original photoresist layer; or, negative photoresist accounts for 10% to 90% of the original photoresist layer. It is understood that the sum of the proportions of positive and negative photoresist in the original photoresist layer is 100%.

[0106] The preset ratio can be either a volume ratio or a weight ratio, and this application embodiment does not limit this.

[0107] The power device fabrication method provided in this application embodiment includes a positive photoresist and a negative photoresist mixed in a preset ratio in the original photoresist layer. The negative photoresist in the original photoresist layer on the third region is exposed and developed to obtain a first photoresist layer. The positive photoresist in the first photoresist layer after a first dry etching process on the second region is exposed and developed to obtain a second photoresist layer. Before the first dry etching process, only one exposure and development process is required, which simplifies the process flow for fabricating the first photoresist layer and improves the efficiency of fabricating the first photoresist layer.

[0108] Optionally, the original photoresist layer includes an original positive photoresist layer and an original negative photoresist layer sequentially stacked on the first surface; the first photoresist layer includes a first positive photoresist layer and a first negative photoresist layer sequentially stacked on the first surface; step S101, which involves performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain the first photoresist layer, includes steps S1013 to S104:

[0109] Step S1013: Use a first mask to block the original photoresist layer on the first region and expose the original negative photoresist layer on the third region to obtain the original negative photoresist layer after the first photolithography process; the third region is the region outside the first region on the first surface.

[0110] Step S1014: Develop the original negative photoresist layer after the first photolithography process to remove the unexposed original negative photoresist layer in the first region, and obtain the first negative photoresist layer.

[0111] Step S1015: Use a third mask to block the original photoresist layer on the third region and expose the original positive photoresist layer on the first region to obtain the original positive photoresist layer after the first photolithography process.

[0112] Step S1016: Develop the original positive photoresist layer after the first photolithography process to remove the original positive photoresist layer exposed on the first region, and obtain the first positive photoresist layer.

[0113] Reference Figure 4 This illustrates a schematic diagram of the wafer structure in the fabrication process of another power device provided in this application embodiment; as shown... Figure 4As shown, the original photoresist layer includes an original positive photoresist layer and an original negative photoresist layer sequentially stacked on the first surface; the first photoresist layer includes a first positive photoresist layer and a first negative photoresist layer sequentially stacked on the first surface.

[0114] Specifically, in step S1013, the original photoresist layer on the first region is first masked using a first mask; then the original negative photoresist layer on the third region is exposed using an ultraviolet spectrum of 300nm to 450nm to obtain the original negative photoresist layer after the first photolithography process.

[0115] The third region is the region outside the first region on the first surface.

[0116] The original negative photoresist layer after the first photolithography process includes the original negative photoresist layer that has not been exposed in the first region, and the original negative photoresist layer that has been exposed in the third region.

[0117] In step S1014, the original negative photoresist layer after the first photolithography process is developed to remove the unexposed original negative photoresist layer on the first region, thereby obtaining the first negative photoresist layer.

[0118] Understandably, after the development process removes the unexposed original negative photoresist layer in the first region of the original negative photoresist layer after the first photolithography process, a first negative photoresist layer including a first pattern is obtained. At this time, the first pattern in the first negative photoresist layer is used to expose the original positive photoresist layer in the first region, so that the original positive photoresist layer in the first region can be exposed in step S1015.

[0119] In step S1015, the original photoresist layer on the third region is first masked using a third mask; then the original positive photoresist layer on the first region is exposed using an ultraviolet spectrum of 160nm to 280nm to obtain the original positive photoresist layer after the first photolithography process.

[0120] The original positive photoresist layer after the first photolithography process includes the original positive photoresist layer exposed on the first region and the original positive photoresist layer in the third region that has not been exposed.

[0121] In step S1016, the original positive photoresist layer after the first photolithography process is developed to remove the original positive photoresist layer exposed on the first region, thereby obtaining the first positive photoresist layer.

[0122] It is understood that after the exposure of the original positive photoresist layer on the first region of the original positive photoresist layer after the first photolithography process is removed by the development process, a first positive photoresist layer including a first pattern is obtained, and the first positive photoresist layer and the first negative photoresist layer constitute the first photoresist layer in this application. At this time, the first pattern in the first positive photoresist layer and the first negative photoresist layer is used to expose the first region in the first surface for the first trench to be prepared by a dry etching process in step S102.

[0123] Optionally, the first photoresist layer after the first dry etching process is a first positive photoresist layer; step S103, which describes performing a second photolithography process on the first photoresist layer after the first dry etching process to obtain a second photoresist layer, includes steps S1033 to S1034:

[0124] Step S1033: Use the second mask to block the first positive photoresist layer on the fourth region and expose the first positive photoresist layer on the second region to obtain the first positive photoresist layer after the second photolithography process.

[0125] Step S1034: Develop the first positive photoresist layer after the second photolithography process to remove the first positive photoresist layer exposed on the second region, and obtain the second photoresist layer.

[0126] In this embodiment of the application, the thickness of the first negative photoresist layer obtained in step S1014 is equal to the depth of the first trench obtained in step S102; it can be understood that after obtaining the first trench in step S102, the first photoresist layer after one dry etching process is the first positive photoresist layer.

[0127] Specifically, in the process of performing a second photolithography process on the first photoresist layer after a first dry etching process to obtain the second photoresist layer:

[0128] First, the first positive photoresist layer on the fourth region is masked using a second mask. The fourth region is the area outside the first and second regions on the first surface, and the fourth and second regions constitute the third region on the first surface.

[0129] Then, the first positive photoresist layer on the second region is exposed using an ultraviolet spectrum from 160 nm to 280 nm to obtain the first positive photoresist layer after the second photolithography treatment.

[0130] The first positive photoresist layer after the second photolithography process includes the first positive photoresist layer exposed on the second region and the first positive photoresist layer not exposed on the fourth region.

[0131] Next, the first positive photoresist layer after the second photolithography process is developed to remove the first positive photoresist layer exposed on the second region, thus obtaining the second photoresist layer.

[0132] Understandably, after the first positive photoresist layer exposed to the second region in the first positive photoresist layer after the second photolithography process is removed by the development process, a second photoresist layer including a second pattern is obtained. At this time, the type of photoresist in the second photoresist layer is positive photoresist; the second pattern in the first photoresist layer is used to expose the second region in the first surface for the second dry etching process in step S104 to obtain the second trench.

[0133] The power device fabrication method provided in this application provides a way to fabricate a first photoresist layer and a second photoresist layer when the original photoresist layer includes an original positive photoresist layer and an original negative photoresist layer sequentially stacked on a first surface. This improves the flexibility of fabricating the first and second photoresist layers in this application, thereby improving the feasibility of this application.

[0134] Optionally, when the original photoresist layer includes an original positive photoresist layer and an original negative photoresist layer sequentially stacked on the first surface, the thickness of the original negative photoresist layer is equal to the depth of the first trench; the thickness of the original positive photoresist layer is greater than or equal to the difference between the depth of the second trench and the depth of the first trench; thereby, it is possible to simultaneously prepare the first photoresist layer and the second photoresist layer, while avoiding etching of areas outside the second trench in the wafer, thus ensuring the surface quality of the wafer containing the second trench.

[0135] Optionally, the original photoresist layer only includes positive photoresist. Specifically, during the process of performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain the first photoresist layer:

[0136] First, the original photoresist layer on the third region is masked using a third mask, and the original photoresist layer on the first region is exposed to obtain the original photoresist layer after the first photolithography process.

[0137] Then, the original photoresist layer after the first photolithography process is developed to remove the original photoresist layer exposed on the first region, thus obtaining the first photoresist layer.

[0138] In the process of performing a second photolithography process on the first photoresist layer after a first dry etching process to obtain the second photoresist layer:

[0139] First, the first photoresist layer after the previous dry etching process in the fourth region is masked using a second mask, and the first photoresist layer after the previous dry etching process in the second region is exposed to obtain the first photoresist layer after the second photolithography process.

[0140] Then, the first photoresist layer after the second photolithography process is developed to remove the first photoresist layer exposed on the second region, thus obtaining the second photoresist layer.

[0141] Optionally, the original photoresist layer only includes negative photoresist. Specifically, during the process of performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain the first photoresist layer:

[0142] First, the original photoresist layer on the first region is masked using a first mask, and the original photoresist layer on the third region is exposed to obtain the original photoresist layer after the first photolithography process.

[0143] Then, the original photoresist layer after the first photolithography process is developed to remove the unexposed original photoresist layer in the first region, thus obtaining the first photoresist layer.

[0144] In the process of performing a second photolithography process on the first photoresist layer after a first dry etching process to obtain the second photoresist layer:

[0145] First, the first photoresist layer after the first dry etching process on the second region is masked using a fourth mask, and then the first photoresist layer after the first dry etching process on the fourth region is exposed to obtain the first photoresist layer after the second photolithography process.

[0146] Then, the first photoresist layer after the second photolithography process is developed to remove the first photoresist layer that has not been exposed on the second region, thus obtaining the second photoresist layer.

[0147] Optionally, the original photoresist layer includes either positive photoresist or negative photoresist. Specifically:

[0148] First, prior to step S101, a first raw photoresist layer is prepared on the first surface of the wafer; the thickness of the first raw photoresist layer is greater than or equal to the depth of the first trench, and the first raw photoresist layer includes either positive photoresist or negative photoresist.

[0149] Then, the first original photoresist layer on the first surface is subjected to a first photolithography process in step S101 to obtain the first photoresist layer.

[0150] Then, in step S102, based on the first pattern in the first photoresist layer, a dry etching process is performed on the first photoresist layer and the first region to form a first trench in the first region of the wafer.

[0151] Next, a second primary photoresist layer is prepared on the first surface of the wafer where the first trench is prepared; the thickness of the second primary photoresist layer is greater than or equal to the difference between the depth of the second trench and the depth of the first trench, and the second primary photoresist layer includes either positive photoresist or negative photoresist.

[0152] Then, the second original photoresist layer is subjected to a second photolithography process in step S103 to obtain the second photoresist layer;

[0153] Finally, in step S104, based on the second pattern in the second photoresist layer, a second dry etching process is performed on the second photoresist layer, the second region, and the first trench to obtain the second trench.

[0154] For example, refer to Figure 5 This illustrates a schematic diagram of the wafer structure in another power device fabrication process provided in this application embodiment; specifically:

[0155] In step S101, the original photoresist layer is as follows: Figure 5 The first raw photoresist layer shown includes a positive photoresist. In the process of performing a first photolithography process on the raw photoresist layer on a first surface of a wafer to obtain the first photoresist layer, firstly, the first raw photoresist layer on a third region is masked using a third mask, and the first raw photoresist layer on the first region is exposed to obtain the first raw photoresist layer after the first photolithography process; then, the first raw photoresist layer after the first photolithography process is developed to remove the exposed first raw photoresist layer on the first region, thus obtaining the first photoresist layer.

[0156] The first groove is obtained through a dry engraving process in step S102.

[0157] Prior to step S103, the method further includes: preparing a second primary photoresist layer on a first surface in which a first trench is formed in a wafer, wherein the second primary photoresist layer comprises positive photoresist.

[0158] In step S103, firstly, the second original photoresist layer on the fourth region is masked using the second mask, and the second original photoresist layer on the second region and the first trench is exposed to obtain the second original photoresist layer after the second photolithography process; then, the second original photoresist layer after the second photolithography process is developed to remove the exposed second original photoresist layer on the second region to obtain the second photoresist layer.

[0159] Optionally, step S104, which involves performing a second dry etching process on the second photoresist layer, the second region, and the first trench based on the second pattern to obtain the second trench, includes:

[0160] Simultaneously, the inner walls of the second region and the first groove are subjected to a second dry engraving process to obtain the second groove.

[0161] Among them, reference Figure 6 This illustration shows a schematic diagram of a wafer structure including a second trench according to an embodiment of this application; as shown Figure 6 As shown, when the inner walls of the second region and the first trench are simultaneously subjected to secondary dry etching, the corner of the upper surface of the second trench is simultaneously etched from above and inside. The etching rate is relatively fast, and a second trench with a certain slope at the opening can be obtained, which is beneficial to the subsequent gate oxide process and gate metal filling process.

[0162] In this embodiment of the application, the inner wall of the second groove includes a side wall and a bottom inner wall, and the angle θ between the side wall of the second groove and the plane where the first surface is located is 0° to 60°; for example, the angle θ between the side wall of the second groove and the plane where the first surface is located can be one of 0°, 10°, 20°, 30°, 40°, 50° and 60° or any two of them.

[0163] It is understandable that the larger the angle between the sidewall of the second trench and the plane containing the first surface, the larger the opening of the second trench, which is more conducive to subsequent gate oxide and gate metal filling processes. However, if the angle between the sidewall of the second trench and the plane containing the first surface is too large (greater than 60°), the area of ​​the wafer-source metal connection region will be reduced, which can easily lead to short circuits and power device failure.

[0164] In this embodiment, considering that the opening of the second trench is relatively small, during subsequent gate oxide and gate metal filling processes, interconnection may easily occur on both sides of the opening, forming a cavity within the second trench. This embodiment simultaneously performs a secondary dry etching process on the second region and the inner wall of the first trench, resulting in an angle of 0° to 60° between the sidewall of the second trench and the plane containing the first surface. This is beneficial for subsequent gate oxide and gate metal filling processes, improving the feasibility of this embodiment.

[0165] Optionally, the thickness of the original photoresist layer is from 3 μm to 10 μm; for example, the thickness of the original photoresist layer can be a range of one or any two of 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm and 10 μm.

[0166] Optionally, the etching power of the single dry etching process is 200W to 2000W; for example, the etching power of the single dry etching process can be a range of one or any two of 200W, 400W, 600W, 800W, 1000W, 1200W, 1400W, 1600W, 1800W and 2000W.

[0167] Optionally, the etching power of the secondary dry etching process is 50W to 200W; for example, the etching power of the secondary dry etching process can be a range of one or any two of 50W, 60W, 70W, 80W, 90W, 100W, 110W, 120W, 130W, 140W, 150W, 160W, 170W, 180W, 190W and 200W.

[0168] It should be noted that the etching power in the embodiments of this application refers to the bias current power during the dry etching process.

[0169] Optionally, the thickness of the damaged layer is from 0.03 μm to 0.3 μm; exemplaryly, the thickness of the damaged layer is a range of one or any two of the following: 0.03 μm, 0.05 μm, 0.07 μm, 0.09 μm, 0.11 μm, 0.13 μm, 0.15 μm, 0.17 μm, 0.19 μm, 0.21 μm, 0.23 μm, 0.25 μm, 0.27 μm, and 0.3 μm.

[0170] Optionally, the thickness of the original photoresist layer is greater than or equal to the depth of the second trench.

[0171] It should be noted that during the fabrication of power devices, the degree of damage to the wafer caused by the first and second dry etching processes can be measured by the surface roughness of the inner wall of the second trench in the wafer. The smaller the surface roughness and the smoother the surface, the less damage the dry etching process causes to the wafer.

[0172] As an example, in the case of a silicon carbide MOSFET as a power device, the one-step dry etching process in related technologies is as follows: First, the silicon carbide wafer is surface-cleaned, and a layer of photoresist is coated on the surface of the silicon carbide wafer; then, the photoresist layer on the surface of the silicon carbide wafer is developed and cured to obtain a patterned photolithographic coating; next, a one-step dry etching process is performed to obtain trenches; finally, the photoresist coating on the surface of the silicon carbide wafer containing the trenches is removed, and subsequent gate oxide and metal filling processes are performed. In the related technologies, the one-step dry etching uses magnetic neutral loop discharge plasma etching with a bias current power of 250W. However, in the process of fabricating a silicon carbide MOSFET using the power device fabrication method provided in this application, the bias current power of the first dry etching process is 300W, and the bias current power of the second dry etching process is 100W.

[0173] In the fabrication of silicon carbide MOSFETs using the power device fabrication method provided in this application, the root mean square (RMS) surface roughness of the inner wall of the second trench is less than 20 nm, while the RMS surface roughness of the inner wall of the trench in silicon carbide MOSFETs fabricated by related technologies is around 40 nm. Therefore, the power device fabrication method provided in this application can remove the damage layer formed by a single dry etching process on the wafer, reducing the damage caused to the wafer by the dry etching process, avoiding the impact of defects in the damage layer on the performance of the power device, and improving the performance and reliability of the power device. Furthermore, in the process of obtaining the second trench by performing a second dry etching process on the second photoresist layer, the second region, and the first trench based on the second pattern, the inner walls of the second region and the first trench are simultaneously subjected to a second dry etching process to obtain the second trench. This ensures that the angle between the sidewall of the second trench and the plane containing the first surface is 0° to 60°, increasing the opening of the second trench, which is beneficial for subsequent gate oxide processes and gate metal filling processes, thus improving the feasibility of this application.

[0174] This application also provides a power device, which is prepared by the power device preparation method described above and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0175] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0176] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for fabricating a power device, characterized in that, The method includes: A first photolithography process is performed on the original photoresist layer on the first surface of the wafer to obtain a first photoresist layer; the first photoresist layer includes a first pattern that exposes a first region in the first surface. Based on the first pattern, a dry etching process is performed on the first photoresist layer and the first region to form a first trench in the first region of the wafer. A second photolithography process is performed on the first photoresist layer after a dry etching process to obtain a second photoresist layer; the second photoresist layer includes a second pattern that exposes the first trench and the second region; the second region is the region in the first surface that is connected to the sidewall of the first trench; Based on the second pattern, a second dry etching process is performed on the second photoresist layer, the second region, and the first trench to obtain a second trench; the difference between the size of the second trench and the size of the first trench is greater than or equal to the thickness of the damage layer formed in the wafer by the first dry etching process; the power of the second dry etching process is less than the power of the first dry etching process. Power devices are fabricated based on a wafer containing the second trench.

2. The method according to claim 1, characterized in that, The original photoresist layer includes positive photoresist and negative photoresist mixed in a preset ratio; The first photolithography process, which involves performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain the first photoresist layer, includes: The original photoresist layer on the first region is masked using a first mask, and the negative photoresist in the original photoresist layer on the third region is exposed to obtain the original photoresist layer after the first photolithography process; the third region is the region outside the first region on the first surface. The original photoresist layer after the first photolithography process is developed to remove the unexposed original photoresist layer in the first region, thus obtaining the first photoresist layer.

3. The method according to claim 2, characterized in that, The process of performing a second photolithography process on the first photoresist layer after a first dry etching process to obtain a second photoresist layer includes: The first photoresist layer after a first dry etching process on the fourth region is masked using a second mask, and the positive photoresist in the first photoresist layer after a first dry etching process on the second region is exposed to obtain the first photoresist layer after the second photolithography process; the fourth region is the region on the first surface other than the first region and the second region. The first photoresist layer after the second photolithography process is developed to remove the first photoresist layer exposed on the second region, thereby obtaining the second photoresist layer.

4. The method according to claim 2, characterized in that, The preset ratio is: the positive photoresist accounts for 10% to 90% of the original photoresist layer; or, the negative photoresist accounts for 10% to 90% of the original photoresist layer.

5. The method according to claim 1, characterized in that, The original photoresist layer includes an original positive photoresist layer and an original negative photoresist layer sequentially stacked on the first surface; the first photoresist layer includes a first positive photoresist layer and a first negative photoresist layer sequentially stacked on the first surface; The first photolithography process, which involves performing a first photolithography process on the original photoresist layer on the first surface of the wafer to obtain the first photoresist layer, includes: The original photoresist layer on the first region is masked using a first photomask, and the original negative photoresist layer on the third region is exposed to obtain the original negative photoresist layer after the first photolithography process; the third region is the region outside the first region on the first surface. The original negative photoresist layer after the first photolithography process is developed to remove the unexposed original negative photoresist layer in the first region, thus obtaining the first negative photoresist layer. The original photoresist layer on the third region is masked using a third mask, and the original positive photoresist layer on the first region is exposed to obtain the original positive photoresist layer after the first photolithography process. The original positive photoresist layer after the first photolithography process is developed to remove the original positive photoresist layer exposed on the first region, thus obtaining the first positive photoresist layer.

6. The method according to claim 5, characterized in that, The first photoresist layer after a single dry etching process is a first positive photoresist layer; the second photolithography process performed on the first photoresist layer after the single dry etching process to obtain a second photoresist layer includes: The first positive photoresist layer on the fourth region is masked using a second photomask, and the first positive photoresist layer on the second region is exposed to obtain the first positive photoresist layer after the second photolithography process; the fourth region is the region on the first surface other than the first region and the second region. The first positive photoresist layer after the second photolithography process is developed to remove the first positive photoresist layer exposed on the second region, thereby obtaining the second photoresist layer.

7. The method according to claim 5, characterized in that, The thickness of the original negative photoresist layer is equal to the depth of the first trench; the thickness of the original positive photoresist layer is greater than or equal to the difference between the depth of the second trench and the depth of the first trench.

8. The method according to claim 1, characterized in that, The second trench is obtained by performing a second dry etching process on the second photoresist layer, the second region, and the first trench based on the second pattern, including: Simultaneously, the inner walls of the second region and the first groove are subjected to a second dry etching process to obtain the second groove; the inner wall includes a side wall and a bottom inner wall, and the angle between the side wall and the plane containing the first surface is 0° to 60°.

9. The method according to claim 1, characterized in that, The thickness of the original photoresist layer is 3 μm to 10 μm.

10. The method according to claim 1, characterized in that, The etching power of the first dry etching process is 200W to 2000W, and the etching power of the second dry etching process is 50W to 200W.

11. The method according to claim 1, characterized in that, The thickness of the damaged layer is 0.03 μm to 0.3 μm.

12. The method according to claim 1, characterized in that, The thickness of the original photoresist layer is greater than or equal to the depth of the second trench.

13. A power device, characterized in that, The power device is prepared by the method for preparing a power device as described in any one of claims 1 to 12.

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