Wafer fabrication methods and semiconductor structures
By using a combination method of elastic fasteners and wafer gaskets in semiconductor processes, the damage problem caused by the difference in fastening force and thermal expansion of wafers is solved, and the stable fixation and protection of thinner wafers is achieved, which improves the Processing success rate and device performance.
Patent Information
- Application Number
- CN202411418705.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2044-10-12
AI Technical Summary
In semiconductor processes, thinner wafers are prone to damage due to the fastening force exerted by the fastener, and may even fragment, and the difference in the coefficient of thermal expansion between the carrier disk and the wafer leads to position changes and frictional damage.
Using a wafer processing method including elastic fasteners and wafer gaskets, by setting a card slot and a clamping member on the carrier disk, the wafer space is fixed with the wafer to be processed to ensure that the coefficient of thermal expansion between the two is small. , reduces the impact of fastening forces on the wafer and provides additional support and protection through groove design.
It effectively reduces the risk of fragmentation of wafers during processing, improves process yield, reliability of semiconductor structure and device performance.
Smart Images
Figure CN118943072B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a wafer processing method and a semiconductor structure. Background Art
[0002] During various semiconductor processes, the wafer to be processed needs to be fixed on a carrier plate; for example, a fastener can be used to fix the wafer, and the fastener can be against the edge of the wafer and apply a fastening force to the edge of the wafer to fix the wafer. However, if the fastening force applied by the fastener to the edge of the wafer is too large, it may cause damage to the wafer or even wafer fragmentation, especially for thinner wafer sheets (for example, wafers with a thickness of less than 250 microns), the wafer sheet may not be able to withstand the damage caused by the fastening force used to fix the wafer during processing, and there may be a risk of wafer fragmentation. Summary of the invention
[0003] According to at least one embodiment of the present disclosure, a wafer processing method is provided, comprising: providing a wafer to be processed and a process machine, wherein the process machine comprises a carrier plate and an elastic fastener, the carrier plate has a slot, the elastic fastener comprises an elastic component and a clamping component, the elastic component is located on a first side of the carrier plate in a first direction, the clamping component is connected to the elastic component, and is located on a side of the carrier plate in a second direction, the first direction and the second direction intersect; placing a wafer gasket on a second side of the carrier plate opposite to the first side; placing the wafer to be processed on a side of the wafer gasket away from the carrier plate; placing the clamping component of the elastic fastener in the slot of the carrier plate, and the clamping component abuts against the side walls of the wafer gasket and the wafer to be processed, thereby fixing the wafer gasket and the wafer to be processed on the carrier plate; and performing a semiconductor process on the wafer to be processed, wherein the difference in thermal expansion coefficient between the wafer to be processed and the wafer gasket is smaller than the difference in thermal expansion coefficient between the wafer to be processed and the carrier plate.
[0004] According to the wafer processing method provided by at least one embodiment of the present disclosure, the substrate material of the wafer to be processed and the material of the wafer gasket have the same thermal expansion coefficient.
[0005] According to the wafer processing method provided by at least one embodiment of the present disclosure, the substrate material of the wafer to be processed is the same as the material of the wafer gasket.
[0006] According to the wafer processing method provided by at least one embodiment of the present disclosure, after the wafer gasket and the wafer to be processed are fixed on the carrier plate and during the semiconductor process, the orthographic projection of the wafer to be processed on a reference plane parallel to the carrier plate is located within the orthographic projection of the wafer gasket on the reference plane.
[0007] According to the wafer processing method provided by at least one embodiment of the present disclosure, in the first direction, the thickness of the wafer gasket is greater than the thickness of the wafer to be processed.
[0008] According to the wafer processing method provided by at least one embodiment of the present disclosure, the wafer gasket has a groove and includes a central portion and an edge portion surrounding the central portion, the second thickness of the edge portion is greater than the first thickness of the central portion, and the groove is defined by the inner side wall of the edge portion and the surface of the central portion.
[0009] According to the wafer processing method provided by at least one embodiment of the present disclosure, the first thickness of the central portion is greater than the thickness of the wafer to be processed.
[0010] According to the wafer processing method provided by at least one embodiment of the present disclosure, the side of the wafer gasket having the groove faces the wafer to be processed, and the wafer to be processed is placed on the edge portion of the wafer gasket and spaced apart from the center portion.
[0011] According to the wafer processing method provided by at least one embodiment of the present disclosure, the first thickness is greater than or equal to 250 microns, the depth of the groove is greater than 100 microns, and the width of the orthographic projection of the edge portion on a reference plane parallel to the carrier plate is greater than or equal to 1 millimeter.
[0012] According to the wafer processing method provided by at least one embodiment of the present disclosure, the method for forming the wafer gasket includes: providing an initial wafer gasket, the initial wafer gasket including an initial center portion and the edge portion surrounding the initial center portion; and removing a portion of the initial center portion to reduce the thickness of the initial center portion and form the center portion.
[0013] According to the wafer processing method provided by at least one embodiment of the present disclosure, the card slot of the carrier plate includes a first card slot and a second card slot, and a first depth of the first card slot in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate is greater than a second depth of the second card slot in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate.
[0014] According to the wafer processing method provided by at least one embodiment of the present disclosure, the carrier plate includes a carrier body and a plurality of protrusions, wherein the plurality of protrusions protrude from the carrier body in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate, and at least a portion of each slot is defined by a gap between two adjacent and spaced-apart protrusions among the plurality of protrusions.
[0015] According to the wafer processing method provided by at least one embodiment of the present disclosure, the carrier body has a carrier edge, the multiple protrusions are located on the side of the carrier edge away from the carrier body, and the carrier body has a depression that is concave from the carrier edge toward the center of the carrier body, the depression is connected to the gap space between two adjacent protrusions among the multiple protrusions, and together define the first card slot; the second card slot is defined by the gap between two adjacent protrusions among the multiple protrusions and the carrier edge.
[0016] According to the wafer processing method provided by at least one embodiment of the present disclosure, the carrier body includes an arc-shaped edge, the bottom of the first card slot is located on the inner side of the arc-shaped edge close to the center of the carrier body, and the bottom of the second card slot is located at the arc-shaped edge.
[0017] According to the wafer processing method provided by at least one embodiment of the present disclosure, the carrier plate includes at least two of the second card slots.
[0018] According to the wafer processing method provided by at least one embodiment of the present disclosure, the area of the carrier body in the direction parallel to the main surface of the carrier plate is smaller than the area of the wafer gasket or the wafer to be processed in the direction parallel to the main surface of the carrier plate.
[0019] According to the wafer processing method provided by at least one embodiment of the present disclosure, the clamping component of the elastic fastener includes a first clamping portion and a second clamping portion, the first clamping portion is configured to be used in conjunction with the first clamping slot, and the second clamping portion is configured to be used in conjunction with the second clamping slot; wherein before the wafer gasket and the wafer to be processed are placed on the carrier plate, the second clamping portion is placed in the second clamping slot, and the first clamping portion is removed from the first clamping slot; and after the wafer gasket and the wafer to be processed are placed on the carrier plate, the first clamping portion is placed in the first clamping slot to fix the wafer gasket and the wafer to be processed.
[0020] According to the wafer processing method provided by at least one embodiment of the present disclosure, the process machine also includes: a planetary disk located on the first side of the carrier disk; and a connecting shaft located between the planetary disk and the carrier disk, and connecting the planetary disk and the carrier disk, wherein the elastic component is connected to the connecting shaft, wherein during the semiconductor process, the carrier disk, the wafer gasket and the wafer to be processed are configured to rotate with the rotation of the planetary disk.
[0021] According to the wafer processing method provided by at least one embodiment of the present disclosure, the semiconductor process includes a deposition process.
[0022] According to the wafer processing method provided by at least one embodiment of the present disclosure, the thickness of the wafer to be processed is less than 250 microns.
[0023] According to the wafer processing method provided by at least one embodiment of the present disclosure, the wafer to be processed includes a silicon-containing material, and the material of the wafer gasket includes a silicon-containing material or sapphire.
[0024] At least one embodiment of the present disclosure provides a semiconductor structure, including: a substrate; and a material layer formed on the substrate by any of the above-mentioned wafer processing methods.
[0025] The wafer processing method of at least one embodiment of the present disclosure can avoid or significantly reduce the risk of wafer fragmentation during processing, improve process yield, and improve the reliability and device performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.
[0027] Figure 1 A schematic cross-sectional view of a process tool according to some embodiments of the present disclosure is shown.
[0028] Figure 2 A schematic plan view of a carrier plate and a clamping component in a process tool according to some embodiments of the present disclosure is shown.
[0029] Figure 3 A schematic cross-sectional view showing how a wafer to be processed and a wafer gasket are fixed on a carrier plate of a process tool for wafer processing in a wafer processing method according to some embodiments of the present disclosure.
[0030] Figure 4 A schematic cross-sectional view of an initial wafer spacer according to some embodiments of the present disclosure is shown.
[0031] Figure 5 A schematic cross-sectional view of a wafer spacer according to some embodiments of the present disclosure is shown.
[0032] Figure 6 A schematic cross-sectional view of an initial wafer according to some embodiments of the present disclosure is shown.
[0033] Figure 7 A schematic cross-sectional view of a wafer to be processed according to some embodiments of the present disclosure is shown.
[0034] Figure 8 A schematic plan view of a wafer spacer according to some embodiments of the present disclosure is shown.
[0035] Fig. 9 Schematic plan views of wafer spacers according to other embodiments of the present disclosure are shown.
[0036] Fig.10 A schematic cross-sectional view of a processed wafer according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION
[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.
[0038] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
[0039] In some process machines, elastic fasteners such as spring clips can be used to fix the wafer on the carrier plate for wafer processing. The elastic fasteners rest against the edge of the wafer and apply elastic pressure to the wafer to fix the wafer. However, if the pressure applied by the fasteners on the wafer is too large, it may cause damage to the wafer, especially for wafer slices with a thickness of less than 250 microns, there may be a risk of wafer fragmentation.
[0040] On the other hand, there may be a large difference in thermal expansion coefficient between the carrier plate and the wafer. During the semiconductor process, the carrier plate and the wafer may be affected by temperature and undergo different degrees of deformation (e.g., expansion / contraction). As a result, the relative position relationship between the carrier plate, the wafer and the elastic fastener may change. For example, the position of the elastic fastener at the edge of the wafer may shift, causing more friction between the elastic fastener and the edge of the wafer (e.g., when the elastic fastener is thinner, it will exert a force similar to a cutting force on the edge of the wafer), causing damage to the wafer and even wafer fragments.
[0041] Furthermore, in some examples, in order to ensure that the elastic fasteners can securely fix the wafer, it may not be possible to reduce damage to the wafer edge by sharing the pressure of the elastic fasteners through a carrier plate; that is, the elastic pressure of the elastic fasteners may be borne by the wafer edge, resulting in a greater risk of wafer fragmentation.
[0042] The embodiments of the present disclosure provide a wafer processing method, which can significantly reduce the risk of wafer fragmentation during processing.
[0043] For example, the wafer processing method of the embodiment of the present disclosure includes: providing a wafer to be processed and a process machine, wherein the process machine includes a carrier plate and an elastic fastener, the carrier plate has a slot, the elastic fastener includes an elastic component and a clamping component, the elastic component is located on a first side of the carrier plate in a first direction, the clamping component is connected to the elastic component and is located on a side of the carrier plate in a second direction, and the first direction and the second direction intersect; placing a wafer gasket on a second side of the carrier plate opposite to the first side; placing the wafer to be processed on a side of the wafer gasket away from the carrier plate; placing the clamping component of the elastic fastener in the slot of the carrier plate, and the clamping component abuts against the side walls of the wafer gasket and the wafer to be processed, thereby fixing the wafer gasket and the wafer to be processed on the carrier plate; and performing a semiconductor process on the wafer to be processed, wherein the difference in thermal expansion coefficient between the wafer to be processed and the wafer gasket is smaller than the difference in thermal expansion coefficient between the wafer to be processed and the carrier plate.
[0044] In the wafer processing method of the embodiment of the present disclosure, a wafer gasket is arranged between the carrier plate and the wafer to be processed, and a clamping component is pressed against the side walls of the wafer gasket and the wafer to be processed to fix the wafer gasket and the wafer to be processed, so that the wafer gasket and the wafer to be processed can jointly bear the fastening force from the clamping component, thereby reducing the fastening force borne by the wafer to be processed, thereby reducing the risk of wafer fragments. Moreover, there is a small difference in thermal expansion coefficient between the wafer to be processed and the wafer gasket, so the deformation (for example, expansion / contraction) of the wafer and the wafer gasket due to temperature changes during processing is similar or approximately the same, so that the relative position relationship between the wafer, the wafer gasket, and the elastic fastener changes little or remains approximately unchanged during wafer processing. For example, the elastic fastener may not move or move little at the side wall of the wafer, thereby avoiding or reducing friction damage to the wafer caused by displacement between the wafer and the elastic fastener, and the wafer gasket can continue to share the pressure from the elastic fastener during the semiconductor process, thereby reducing the risk of wafer fragments in the wafer to be processed, improving the process yield, and further improving the reliability and device performance of the formed semiconductor structure.
[0045] Figure 1 A schematic cross-sectional view of a process tool according to some embodiments of the present disclosure is shown. Figure 2 A schematic plan view showing a carrier plate and a clamping component in a process machine according to some embodiments of the present disclosure, and a schematic enlarged view showing a clamping slot of the carrier plate; Figure 1 The carrier plate and the clamping component of the process machine shown are, for example, Figure 2 The line I-I' is intercepted.
[0046] refer to Figure 1 In some embodiments, the process machine 150 includes a carrier plate 102 and an elastic fastener 105. The carrier plate 102 is configured to carry a wafer gasket and a wafer to be processed during wafer processing. The carrier plate 102 has a first side and a second side opposite to each other in a first direction D1, and the second side of the carrier plate 102 is, for example, used to carry a wafer. The elastic fastener 105 is configured to fix the wafer gasket and the wafer to be processed on the carrier plate 102. For example, the elastic fastener 105 may include an elastic component 105a and a clamping component 105b. The elastic component 105a is located on a first side of the carrier plate 102, and the clamping component 105b is connected to the elastic component 105a and is located on a side of the carrier plate 102 in the second direction D2.
[0047] For example, at least a portion of the holding member 105b is located on the side of the carrier plate 102 in the second direction D2. The first direction D1 and the second direction D2 intersect each other, for example, are substantially perpendicular to each other. The first direction D1 may be a direction perpendicular to the main surface of the carrier plate, the wafer pad, or the wafer, for example, the vertical direction shown in the figure; the second direction D2 may be a horizontal direction shown in the figure, and may be any horizontal direction parallel to the main surface of the carrier plate, the wafer pad, or the wafer.
[0048] like Figure 1 and Figure 2 As shown, the carrier plate 102 has a slot 12 , and the slot 12 and the holding component 105 b are configured to cooperate with each other to fix the wafer. For example, the slot 12 is used to accommodate and fix the holding component 105 b of the elastic fastener 105 .
[0049] In some embodiments, the process machine 150 further includes a planetary disk 100 and a connecting shaft 101, wherein the planetary disk 100 is located on a first side of the carrier disk 102; the connecting shaft 101 is located between the planetary disk 100 and the carrier disk 102, and connects the planetary disk 100 and the carrier disk 102. The elastic component 105a is connected to the connecting shaft 101; for example, one end of the elastic component 105a away from the clamping component 105b can be connected and fixed to the connecting shaft 101. In some embodiments, the planetary disk 100 is configured to be rotatable, and the carrier disk 102 is configured to rotate with the rotation of the planetary disk 100. In some embodiments, one or more carrier disks 102 may be provided on the planetary disk 100, and each carrier disk 102 is configured to carry a wafer gasket and a wafer to be processed for wafer processing. It should be understood that for the sake of simplicity, only a single carrier plate is shown in the cross-sectional view, but the present disclosure is not limited to this. Multiple carrier plates 102 may be provided on the planetary plate 100, and each carrier plate and the corresponding elastic fastener have a structure similar to or substantially the same as the structure shown in the figure.
[0050] Figure 3 A schematic cross-sectional view is shown of fixing a wafer to be processed and a wafer gasket on a carrier plate of a process tool for wafer processing in a wafer processing method according to some embodiments of the present disclosure.
[0051] refer to Figure 1 , Figure 2 and Figure 3In some embodiments, the wafer pad 200 is placed on the second side of the carrier plate 102, and then the wafer 300 to be processed is placed on the side of the wafer pad 200 away from the carrier plate 102; the clamping part 105b of the elastic fastener 105 is placed in the clamping groove 12 of the carrier plate 102, and the clamping part 105b is against the side walls of the wafer pad 200 and the wafer 300 to be processed, so that the wafer pad 200 and the wafer 300 to be processed are fixed on the carrier plate 102. Afterwards, the semiconductor process can be performed on the wafer 300 to be processed. For example, during the semiconductor process, the carrier plate 102, the wafer pad 200 and the wafer 300 to be processed can be configured to rotate with the rotation of the planetary disk 100, so that each area of the wafer to be processed can be processed uniformly. The wafer 300 to be processed can be or include a semiconductor wafer, for example.
[0052] like Figure 1 and Figure 3 As shown, when the wafer gasket and the wafer to be processed are not placed on the carrier plate 102, the elastic component 105a is in a contracted state or a slightly stretched state; when the wafer gasket and the wafer to be processed are placed on the carrier plate 102, and the clamping component 105b of the elastic fastener 105 is placed in the clamping groove and abuts against the wafer gasket and the wafer, the elastic component 105a is in a stretched state, so that the elastic potential energy of the elastic component 105a is converted into a fastening force (i.e., clamping force), and the wafer gasket and the wafer to be processed are fixed by the clamping component 105b.
[0053] In some embodiments, the difference in thermal expansion coefficient between the wafer to be processed and the wafer pad is smaller than the difference in thermal expansion coefficient between the wafer to be processed and the carrier plate. For example, the substrate material of the wafer to be processed and the material of the wafer pad have the same thermal expansion coefficient. For example, the substrate material of the wafer to be processed and the material of the wafer pad are the same.
[0054] In some embodiments, the wafer to be processed may include semiconductor materials, for example, silicon-containing materials, for example, its substrate includes silicon; the material of the wafer gasket may include semiconductor materials, for example, silicon-containing materials such as silicon and silicon carbide, or the material of the wafer gasket may also include sapphire.
[0055] In some embodiments, the difference in thermal expansion coefficient between the wafer 300 to be processed and the wafer gasket 200 is less than the difference in thermal expansion coefficient between the wafer 300 to be processed and the carrier plate 102. For example, the difference in thermal expansion coefficient between the wafer 300 to be processed and the wafer gasket 200 may be as small as zero, that is, the two may have approximately the same thermal expansion coefficient in some examples. For example, the substrate material of the wafer 300 to be processed and the material of the wafer gasket 200 may have a similar or approximately the same thermal expansion coefficient. For example, the substrate material of the wafer 300 to be processed may be similar to or the same as the material of the wafer gasket 200. For example, the wafer 300 to be processed may include at least a substrate, and in some embodiments may also include other material layers disposed on the substrate. For example, the substrate of the wafer 300 to be processed may include a semiconductor material, such as a silicon-containing material; for example, the wafer 300 to be processed includes a silicon substrate. For example, the material of the wafer spacer 200 may include semiconductor materials, such as silicon-containing materials; for example, the material of the wafer spacer 200 may include silicon, silicon carbide, or sapphire, etc. It should be understood that the above materials are only for illustration and the present disclosure is not limited thereto.
[0056] In some embodiments, after the wafer gasket and the wafer to be processed are fixed on the carrier plate and during the semiconductor process, the orthographic projection of the wafer to be processed on a reference plane parallel to the carrier plate is located within the orthographic projection of the wafer gasket on the reference plane.
[0057] In some embodiments, in the first direction, the thickness of the wafer spacer is greater than the thickness of the wafer to be processed.
[0058] In some embodiments, the wafer pad has a groove and includes a central portion and an edge portion surrounding the central portion, the second thickness of the edge portion is greater than the first thickness of the central portion, and the groove is defined by the inner sidewall of the edge portion and the surface of the central portion. For example, the first thickness of the central portion is greater than the thickness of the wafer to be processed.
[0059] In some embodiments, the side of the wafer pad having the groove faces the wafer to be processed, and the wafer to be processed is placed on the edge portion of the wafer pad and spaced apart from the center portion.
[0060] refer to Figure 3For example, after the wafer spacer 200 and the wafer 300 to be processed are fixed on the carrier plate 102 and during the above-mentioned semiconductor process, the orthographic projection of the wafer 300 to be processed on a reference plane parallel to the carrier plate 102 (for example, the main surface of the planetary plate 100) is located within the orthographic projection of the wafer spacer 200 on the reference plane. For example, the area of the orthographic projection of the wafer spacer 200 may be greater than or approximately equal to the area of the orthographic projection of the wafer 300 to be processed.
[0061] For example, the width W1 of the wafer spacer 200 in the direction parallel to the main surface of the carrier plate 102 is greater than or substantially equal to the width W2 of the wafer 300 to be processed in the direction parallel to the main surface of the carrier plate 102. Here, the widths of the wafer spacer 200 and the carrier plate 102 are the widths in the same direction; for example, the width of the wafer spacer 200 refers to the width between the edge thereof abutting against the clamping component 105b, and the width of the wafer 300 to be processed refers to the width between the edge thereof abutting against the clamping component 105b.
[0062] In some embodiments, in a direction perpendicular to the main surface of the susceptor 102 (eg, the first direction D1 ), the thickness of the wafer spacer 200 is greater than the thickness of the wafer 300 to be processed.
[0063] Figure 5 A schematic cross-sectional view showing a wafer spacer 200 according to some embodiments of the present disclosure; Figure 7 A schematic cross-sectional view of a wafer 300 to be processed according to some embodiments of the present disclosure is shown.
[0064] refer to Figure 3 and Figure 5 In some embodiments, the wafer gasket 200 has a groove 203 and includes a central portion 201 and an edge portion 202 surrounding the central portion 201. The central portion 201 has a first thickness t1, and the edge portion 202 has a second thickness t2, and the second thickness t2 is greater than the first thickness t1. For example, the groove 203 of the wafer gasket 200 is defined by the inner side wall of the edge portion 202 and the surface of the central portion 201. The first thickness of the central portion and the second thickness of the edge portion are both thicknesses in a direction perpendicular to the main surface of the wafer gasket (e.g., the first direction D1). The main surface of the wafer gasket refers to the surface of its main body.
[0065] In some embodiments, each region of the central portion 201 has a substantially uniform first thickness t1. For example, the cross-sectional shape of the central portion 201 may be substantially rectangular. In some embodiments, the edge portion 202 has a rounded chamfer, i.e., has an arc-shaped outer sidewall. For example, the cross-sectional shape of the edge portion 202 may be semicircular, semi-racetrack (i.e., a combination of semicircular and rectangular), or the like.
[0066] For example, the edge portion 202 has the maximum thickness at a position closest to the center portion 201 in a direction parallel to the main surface of the wafer pad (i.e., at the inner sidewall defining the groove 203), and the thickness of the edge portion 202 gradually decreases as it moves away from the center portion 201 in a direction parallel to the main surface of the wafer pad, for example, it has the minimum thickness at the edge position farthest from the center portion 201. In this article, the second thickness t2 of the edge portion 202 refers to the maximum thickness of the edge portion 202, that is, it is substantially equal to the thickness of the orthogonal projection of the edge portion 202 on a reference plane parallel to the first direction D1 in the first direction D1.
[0067] refer to Figure 7 In some embodiments, the wafer 300 to be processed has a wafer center portion 301 and a wafer edge portion 302, and the wafer edge portion 302 surrounds the wafer center portion 301 in a direction parallel to the main surface of the wafer. The wafer center portion 301 has a thickness t3, for example, a substantially uniform thickness t3 in each region thereof. For example, the cross-sectional shape of the wafer center portion 301 may be substantially rectangular. In some embodiments, the wafer edge portion 302 has an uneven thickness; for example, the wafer edge portion 302 has a maximum thickness at a position closest to the wafer center portion 301, and the thickness gradually decreases as it moves away from the wafer center portion in a direction parallel to the main surface of the wafer (for example, the second direction D2), and has a minimum thickness at an edge position farthest from the wafer center portion 301. The maximum thickness of the wafer edge portion 302 is substantially equal to the thickness of the wafer center portion 301. For example, the cross-sectional shape of the wafer edge portion 302 may be a fan-shaped or similar shape. In some embodiments, the main surface of the wafer center portion 301 may be substantially flush with the main surface of the wafer edge portion 302 in the second direction D2 .
[0068] refer to Figure 3 , Figure 5 and Figure 7 In some embodiments, the second thickness t2 of the wafer gasket 200 is greater than the thickness t3 of the wafer 300 to be processed; in some embodiments, the first thickness t1 of the wafer gasket 200 is also greater than the thickness t3 of the wafer 300 to be processed. In some embodiments, the wafer edge portion 302 (or the wafer edge portion 302 and a portion of the wafer center portion 301) of the wafer 300 to be processed contacts the edge portion 202 of the wafer gasket 200, so that the wafer gasket 200 provides support to the wafer 300 to be processed; in some embodiments, the edge portion 202 of the wafer gasket 200 and the wafer edge portion 302 overlap in the first direction D1, and in any portion of the gasket edge portion and the corresponding portion of the wafer edge portion that overlap each other, the thickness of the portion of the edge portion 202 of the wafer gasket 200 is greater than the thickness of the corresponding portion of the wafer edge portion 302.
[0069] refer to Figure 3In some embodiments, after the wafer gasket 200 and the wafer 300 to be processed are fixed on the carrier plate 102, the side of the wafer gasket 200 with the groove 203 faces the wafer 300 to be processed, and the wafer 300 to be processed is placed on the edge portion 202 of the wafer gasket 200 and is spaced apart from the center portion 201 of the wafer gasket 200. In this way, the main part or all of the wafer center portion 301 of the wafer 300 to be processed will not contact the wafer gasket 200, so that damage to the surface of the wafer to be processed due to the wafer gasket can be avoided when the wafer to be processed is installed and / or during the semiconductor process. Moreover, the provision of the groove 203 on the wafer gasket 200 can also reduce the weight of the wafer gasket, thereby reducing the overall weight borne by the planetary disk, which is beneficial to reduce the mechanical loss of the process machine.
[0070] Figure 8 and Fig. 9 A schematic plan view of a wafer spacer 200 according to some embodiments of the present disclosure is shown.
[0071] refer to Figure 8 and Fig. 9 , the edge portion 202 of the wafer pad 200 surrounds the central portion 201 in a direction parallel to the main surface of the pad. Figure 8 As shown, in some examples, the wafer spacer 200 may have a planar shape of a circular segment, for example, may be in the shape of a major arc, and may have a straight surface (ie, a chord of the arc) and an arc surface (ie, an arc of the arc). Fig. 9 As shown, in some examples, the wafer spacer 200 may have a circular planar shape and may have an arc-shaped surface. In some embodiments, the shape of the wafer spacer 200 may match the shape of the corresponding wafer to be processed, for example, they may be similar or substantially the same as each other; for example, the planar shape of the wafer to be processed may be the same as Figure 8 or Fig. 9 The positional relationship between the edge of the wafer and the center of the wafer can be similar to the positional relationship between the edge and the center of the wafer pad shown in the figure, and no further description is given here. When the plane shape of the wafer to be processed is a circular segment, select Figure 8 When the planar shape of the wafer to be processed is circular, select Fig. 9 Wafer spacer shown.
[0072] In some embodiments, the planar shape of the central portion 201 of the wafer gasket 200 is substantially the same as the overall shape of the wafer gasket, and the edge portion 202 is a corresponding ring shape. For example, the wafer gasket 200 has a first diameter d1, the central portion 201 has a second diameter d2, and the edge portion 202 has a reserved width D, where D=(d1-d2) / 2. It should be understood that when the planar shape of the wafer gasket is a circular segment (e.g., a major arc), the above diameter refers to the diameter of the circle corresponding to the shape of the wafer gasket (e.g., the circle where the arc is located).
[0073] refer to Figure 3 , Figure 5 , Figure 8 and Fig. 9 In some embodiments, the first thickness t1 of the wafer spacer 200 may be greater than or equal to 250 microns, the second thickness t2 may be greater than or equal to 350 microns, and the depth h of the groove 203 may be greater than or equal to 100 microns. In some embodiments, the first diameter d1 of the wafer spacer 200 may be set according to product requirements, for example, it may be 4 inches, 5 inches, 6 inches or 8 inches, and the reserved width D of the edge portion 202 may be greater than or equal to 1 mm.
[0074] like Figure 3 and Figure 5 As shown, in some examples, the edge portion 202 has a non-uniform width at different heights, for example, from bottom to top in the first direction D1, the width of the edge portion 202 gradually increases, and then gradually decreases. It should be understood that the reserved width D of the edge portion 202 is the maximum width of the edge portion 202 in the second direction, that is, it is equal to the width of the orthographic projection of the edge portion 202 on a reference plane parallel to the carrier disk (for example, the main surface of the planetary disk 100).
[0075] In some embodiments, the above-mentioned size setting of the wafer gasket enables the wafer gasket to provide sufficient support strength and protection for the wafer to be processed; at the same time, the groove design is beneficial to protecting the surface of the wafer to be processed from damage during the installation process and / or processing process, and is beneficial to reducing the weight of the wafer gasket, thereby reducing the mechanical loss of the process machine.
[0076] Figure 4 and Figure 5 Schematic cross-sectional views showing structures of various steps in a method of forming a wafer spacer according to some embodiments of the present disclosure.
[0077] In some embodiments, a method for forming a wafer gasket includes: providing an initial wafer gasket, wherein the initial wafer gasket includes an initial center portion and an edge portion surrounding the initial center portion; and removing a portion of the initial center portion to reduce the thickness of the initial center portion and form the center portion.
[0078] For example, refer to Figure 4 , providing an initial wafer gasket 20, the initial wafer gasket 20 includes an initial central portion 21 and an edge portion 202, the edge portion 202 surrounds the initial central portion 21 in a direction parallel to the main surface of the gasket. The cross-sectional shape of the initial wafer gasket 20 may be a racetrack shape, the initial central portion 21 is rectangular, and the edge portion 202 is semicircular or semi-racetrack shaped. The initial central portion 21 has an initial first thickness t0, and the edge portion 202 has a second thickness t2. As described above, the second thickness t2 is the maximum thickness of the edge portion 202. In this step, the initial first thickness t0 of the initial central portion 21 and the second thickness t2 of the edge portion 202 are substantially the same.
[0079] refer to Figure 4 and Figure 5 , a thinning process is performed to remove a portion of the initial central portion 21, thereby thinning the thickness of the initial central portion 21 and forming the central portion 201; for example, the thickness of the initial central portion 21 is thinned from the initial first thickness t0 to the first thickness t1 of the central portion 201. The edge portion 202 is not removed during the thinning process and is therefore not thinned. In other words, the edge portion 202 has the same second thickness t2 before and after the thinning process. In this way, a groove 203 defined by the edge portion 202 and the thinned central portion 201 is formed in the wafer gasket 200.
[0080] In some embodiments, a portion of the initial central portion 21 may be removed by photolithography and etching processes, or a portion of the initial central portion 21 may be removed by a Taiko thinning process, thereby forming a wafer spacer 200 having a groove 203 .
[0081] Figure 6 and Figure 7 A schematic cross-sectional view showing the structure of each step in a method for forming a wafer to be processed according to some embodiments of the present disclosure. For example, the method for forming a wafer to be processed includes: providing an initial wafer; and performing a thinning process on the entire initial wafer.
[0082] refer to Figure 6 For example, an initial wafer 30 is provided, and the initial wafer 30 has an initial wafer center portion 31 and an initial wafer edge portion 32. The shape of the initial wafer 30 may be similar to Figure 4 The shape of the initial wafer spacer 20 shown is generally similar. For example, the cross-sectional shape of the initial wafer 30 may be a racetrack shape as a whole, the initial wafer center portion 31 may have a rectangular cross-sectional shape, and the cross-sectional shape of the initial wafer edge portion 32 may be a semicircular shape. The initial wafer center portion 31 and the initial wafer edge portion 32 have an initial thickness t3', and it should be understood that the maximum thickness of the initial wafer edge portion 32 is the initial thickness t3'.
[0083] refer to Figure 6 and Figure 7 , a thinning process is performed on the initial wafer 30 to form a wafer 300 to be processed including a wafer center portion 301 and a wafer edge portion 302. The thinning process removes part of the initial wafer center portion 31 to form the wafer center portion 301, and removes part of the initial wafer edge portion 32 to form the wafer edge portion 302. That is, in the thinning process, both the initial wafer center portion 31 and the initial wafer edge portion 32 are thinned, for example, from an initial thickness t3' to a thickness t3. In some embodiments, the thickness t3 of the wafer 300 to be processed is below 250 microns, for example, in a range of 50 microns to 200 microns. For example, the thinning process may include a grinding process, a chemical mechanical polishing (CMP) process, etc., and may cause each area of the initial wafer 30 to be thinned.
[0084] refer to Figures 4 to 7 In some embodiments, the initial wafer spacer 20 has an initial diameter d0, and the first diameter d1 of the wafer spacer 200 is substantially the same as the initial diameter d0 of the initial wafer spacer 20. That is, the diameter of the wafer spacer 200 does not change substantially before and after the thinning process. In some embodiments, the initial wafer 30 has an initial wafer diameter d3, and the wafer 300 to be processed has a wafer diameter d4, and the wafer diameter d4 may be less than or equal to the initial wafer diameter d3. It should be understood that the diameter of each wafer or spacer is its maximum width in the second direction, that is, the width of its orthographic projection on the horizontal reference plane (for example, the width shown in the top view); from the cross-sectional view, since the edge portions of the initial wafer or initial wafer spacer have rounded chamfers, the initial wafer or initial wafer spacer may have different widths at different heights; for example, from bottom to top in the first direction, the width of the wafer or spacer gradually increases, and for example has a maximum value at about 1 / 2 of its thickness (that is, height), and then gradually decreases.
[0085] For example, in some examples, the initial wafer 30 is thinned to a thickness exceeding 1 / 2 of its initial thickness, that is, the thickness t3 of the final wafer 300 to be processed is less than 1 / 2 of the initial thickness t3' of the initial wafer 30, and the wafer diameter d4 will be smaller than the initial wafer diameter d3. In some embodiments, the initial diameter d0 of the initial wafer spacer 20, the first diameter d1 of the wafer spacer 200, and the initial wafer diameter d3 of the initial wafer 30 are substantially the same; therefore, the wafer diameter d4 of the wafer 300 to be processed may be smaller than the first diameter d1 of the wafer spacer 200.
[0086] refer to Figure 3In some embodiments, after the wafer 300 to be processed and the wafer spacer 200 are fixed on the carrier plate 102 and during the subsequent semiconductor process, the orthographic projection of the wafer 300 to be processed on a reference plane parallel to the carrier plate 102 (for example, the main surface of the planetary plate 100) is located within the orthographic projection of the wafer spacer 200 on the reference plane. For example, the wafer diameter of the wafer 300 to be processed is smaller than the first diameter of the wafer spacer 200, that is, the area of the orthographic projection of the wafer 300 to be processed is smaller than the area of the orthographic projection of the wafer spacer 200.
[0087] In some embodiments, the clamping part 105b of the elastic fastener 105 abuts against the edge of the wafer gasket 200 and the wafer 300 to be processed, and applies a fastening force (e.g., a clamping force) to the wafer gasket 200 and the wafer 300 to be processed, thereby fixing the wafer gasket 200 and the wafer 300 to be processed. For example, the abutting surface 105s of the clamping part 105b abuts against and contacts the edge of the wafer gasket 200 and the wafer 300 to be processed. The clamping force of the clamping part 105b is applied to both the wafer gasket and the wafer to be processed; that is, the wafer gasket can share the clamping force from the clamping part, thereby reducing the clamping force borne by the wafer to be processed, avoiding the side wall of the wafer from being subjected to unbearable damage due to excessive clamping force, and reducing the risk of wafer fragmentation.
[0088] In some embodiments, in the second direction D2, the size (e.g., area, width, etc.) of the wafer pad 200 may be larger than the size (e.g., area, width, etc.) of the wafer 300 to be processed, and the abutting surface 105s of the clamping component 105b may be inclined, for example, inclined toward the center of the wafer. For example, the bottom angle α of the clamping component 105b may be an acute angle; the bottom angle of the clamping component 105b is the angle between its abutting surface 105s and the reference plane along the second direction D2, for example, the angle between its abutting surface 105s and the horizontal portion connected to the elastic component 105a. In this way, most of the clamping force of the clamping component 105b is applied to the wafer pad 200, while the clamping force borne by the wafer 300 to be processed is relatively small, so that the side wall of the wafer 300 to be processed can be greatly reduced or avoided from being damaged, thereby greatly reducing the risk of wafer fragments of the wafer 300 to be processed.
[0089] In some embodiments, the card slots and the holding components of the carrier plate are used in conjunction with each other to fix the wafers and wafer pads to be processed. For example, multiple card slots and multiple holding components are arranged in a one-to-one correspondence and are configured to be used in conjunction with each other. The multiple card slots may include card slots with the same or different depths.
[0090] For example, the card slot of the carrier plate includes a first card slot and a second card slot, and a first depth of the first card slot in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate is greater than a second depth of the second card slot in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate.
[0091] In some embodiments, the carrier plate includes a carrier body and a plurality of protrusions, wherein the plurality of protrusions protrude from the carrier body in a direction parallel to a main surface of the carrier plate and perpendicular to a circumference of the carrier plate, and at least a portion of each slot is defined by a gap between two adjacent and spaced-apart protrusions among the plurality of protrusions.
[0092] For example, the carrier body has a carrier edge, the multiple protrusions are located on the side of the carrier edge away from the carrier body, and the carrier body has a depression that is concave from the carrier edge toward the center of the carrier body, the depression is connected to the gap space between two adjacent protrusions among the multiple protrusions, and together define the first slot; the second slot is defined by the gap between two adjacent protrusions among the multiple protrusions and the carrier edge.
[0093] For example, the carrying body includes an arc-shaped edge, the bottom of the first clamping groove is located on the inner side of the arc-shaped edge close to the center of the carrying body, and the bottom of the second clamping groove is located at the arc-shaped edge.
[0094] In some embodiments, the area of the carrier body in a direction parallel to the main surface of the carrier plate is smaller than the area of the wafer pad or the wafer to be processed in a direction parallel to the main surface of the carrier plate.
[0095] refer to Figure 2 and Figure 3 In some embodiments, the clamping member 105b is fixed in the clamping slot 12 of the carrier plate 102 to fix the wafer and wafer pad to be processed. Figure 2 As shown, the slot 12 of the carrier tray 102 may include a first slot 12a and a second slot 12b. The first slot 12a and the second slot 12b may have different depths.
[0096] For example, a first depth 12d1 of the first slot 12a in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate is greater than a second depth 12d2 of the second slot 12b in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate.
[0097] refer to Figure 2For example, the carrier plate 102 includes a carrier body 10 and a plurality of protrusions 11, the plurality of protrusions 11 protrude from the carrier body 10 in a direction parallel to the main surface of the carrier plate 102 and perpendicular to the circumference of the carrier plate 102, and at least part of each slot is defined by a gap between two adjacent and spaced protrusions of the plurality of protrusions 11. In this document, the circumference of the carrier plate 102 refers to the circumference of its carrier body 10, and generally refers to the extension direction of the edge of the carrier body (i.e., the carrier edge described below).
[0098] For example, the carrier body 10 has a carrier edge 10e, and a plurality of protrusions 11 are connected to the carrier body 10 and are located on a side of the carrier edge 10e away from the carrier body 10, that is, located on the outside of the carrier edge. The carrier body 10 is provided with a recess 9 at a position corresponding to the first clamping groove 12a, and the recess 9 is concave from the carrier edge 10e toward the center of the carrier body, and is spatially connected with the gap 8 between two adjacent protrusions 11 to jointly define the first clamping groove 12a. That is, the first clamping groove 12a includes the gap 8 and the recess 9. That is, the first clamping groove 12a extends into the carrier body, and its bottom is located on the inner side of the carrier edge close to the center of the carrier body.
[0099] For example, the carrier body 10 may not have a recess at a position corresponding to the second slot 12b, and the second slot 12b is defined by the gap 8 between the corresponding two adjacent protrusions 11 and the carrier edge 10e. That is, the bottom of the second slot 12b is located at the carrier edge 10e, for example, a portion of the surface of the carrier edge is exposed, and does not extend into the carrier body.
[0100] The first depth 12d1 of the first slot 12a is substantially equal to the sum of the depth of the gap 8 between two adjacent protrusions 11 and the depth of the recess 9; the second depth 12d2 of the second slot 12b is substantially equal to the depth of the gap 8 between two adjacent protrusions 11. In this article, the depths of the slots, gaps and recesses are all depths in a direction parallel to the main surface of the carrier disk and perpendicular to the circumference of the carrier disk. The depth of the gap 8 is substantially equal to the length of the corresponding protrusion 11 in a direction parallel to the main surface of the carrier disk and perpendicular to the circumference of the carrier disk, and the lengths of the plurality of protrusions 11 may be substantially the same as each other.
[0101] In other words, the plurality of protrusions 11 are disposed on the bearing edge 10e (i.e., the side wall of the bearing body); the plurality of protrusions 11 include a plurality of groups of protrusions, each group of protrusions including two protrusions disposed adjacently and spaced apart. The plurality of groups of protrusions may be substantially evenly or symmetrically distributed on various regions of the bearing edge of the bearing body. In some examples, the bearing body may be circular, circular-segmented, or similarly shaped, and the bearing edge may include an arcuate edge, or include an arcuate edge and a straight edge, but the present disclosure is not limited thereto.
[0102] The first slot 12a extends into the carrier body and overlaps with the edge of the carrier body in a direction parallel to the circumference of the carrier body. The second slot 12b does not extend into the carrier body and therefore may not overlap with the carrier body in a direction parallel to the circumference of the carrier body.
[0103] In some embodiments, the carrier plate 102 includes at least one first card slot 12a and at least one second card slot 12b, for example, it may include one first card slot 12a and two or more second card slots 12b. It should be understood that the number of card slots shown in the figure is only for illustration, and the present disclosure is not limited thereto, as long as the arrangement of the card slots and the corresponding holding components can enable the wafer pad and the wafer to be processed to be firmly fixed on the carrier plate, and the relevant arrangement can be designed and adjusted according to actual product requirements.
[0104] In some embodiments, the carrier body 10 includes a central portion and an edge portion, the edge portion surrounding the central portion, for example, Figure 2 The dotted circle in the figure schematically shows the boundary between the center part and the edge part, wherein the part inside the dotted circle is the center part, and the part outside the dotted circle is the edge part. For example, the thickness of the edge part of the carrier body 10 may be greater than the thickness of the center part, and the carrier body 10 may have a groove 103 defined by the surface of the center part away from the planetary disk and the inner side wall of the edge part. Figure 3 As shown, the groove 103 of the carrier body 10 faces the wafer gasket 200, and the edge portion of the carrier body 10 contacts the wafer gasket 200 to provide support for the wafer gasket 200 and the wafer above. The center portion 201 of the wafer gasket 200 is separated from the center portion of the carrier body 10 by the groove 103, and such a configuration can also help protect the surface of the center portion of the wafer gasket 200 from damage during the process. On the other hand, the carrier plate is provided with a groove, which can also help reduce the weight of the carrier plate, thereby reducing the overall weight borne by the planetary plate, and further helps reduce the mechanical loss of the process machine.
[0105] refer to Figure 2 and Figure 3 In some embodiments, the area of the carrier body 10 in the direction parallel to the main surface of the carrier plate is smaller than the area of the wafer pad 200 or the wafer to be processed 300 in the direction parallel to the main surface of the carrier plate. For example, setting the carrier body 10 to have a smaller area and / or setting the second card slot to extend into the carrier body can help avoid the problem of the wafer falling due to the elastic fastener not being firmly fixed due to the thermal expansion of the carrier plate during the semiconductor process, so that the wafer pad and the wafer to be processed can be firmly fixed on the carrier plate under various temperature conditions.
[0106] In some embodiments, the clamping component of the elastic fastener includes a first clamping portion and a second clamping portion, the first clamping portion is configured to be used in conjunction with the first clamping slot, and the second clamping portion is configured to be used in conjunction with the second clamping slot; wherein before the wafer gasket and the wafer to be processed are placed on the carrier plate, the second clamping portion is placed in the second clamping slot, and the first clamping portion is removed from the first clamping slot; and after the wafer gasket and the wafer to be processed are placed on the carrier plate, the first clamping portion is placed in the first clamping slot to fix the wafer gasket and the wafer to be processed.
[0107] refer to Figure 2 and Figure 3 In some embodiments, the clamping component 105b of the elastic fastener 105 includes a first clamping portion 15 and a second clamping portion 25, the first clamping portion 15 is configured to be used in conjunction with the first card slot 12a, and the second clamping portion 25 is configured to be used in conjunction with the second card slot 12b. The clamping portions are arranged in a one-to-one correspondence with the card slots. For example, in some examples, the clamping component 105b includes a first clamping portion 15 arranged corresponding to a first card slot 12a, and two second clamping portions 25 arranged corresponding to two second card slots 12b, respectively. For example, the elastic component 105a also includes a plurality of elastic portions, and the plurality of elastic portions are arranged in a one-to-one correspondence with the plurality of clamping portions, one end of each elastic portion is fixedly connected to the connecting shaft 101, and the other end is connected to the corresponding clamping portion.
[0108] For example, when the wafer 300 to be processed needs to be fixed in a process machine for semiconductor processing, before placing the wafer gasket 200 and the wafer to be processed on the carrier plate 102, the second clamping portion 25 is placed in the second clamping groove 12b, and the first clamping portion 15 is removed from the first clamping groove 12a to facilitate the placement of the wafer gasket and the wafer to be processed. Then, the wafer gasket 200 is placed on the carrier body 10 of the carrier plate 102, and the groove of the wafer gasket 200 is facing upward, that is, facing the side away from the carrier plate. For example, the wafer gasket can be taken and placed by using tweezers, a suction pen, a fingertip, etc., and the wafer gasket can be placed on the carrier plate. Next, the wafer 300 to be processed is placed on the wafer gasket 200, that is, on the side of the wafer gasket 200 away from the carrier plate; for example, the wafer 300 to be processed can be taken and placed using tweezers, a suction pen, finger gloves, etc., and the wafer 300 to be processed can be placed on the wafer gasket 200.
[0109] After the wafer gasket 200 and the wafer 300 to be processed are placed on the carrier plate 102, the first clamping portion 15 is placed in the first clamping groove 12a, so that the first clamping portion 15 and the second clamping portion 25 both abut against the wafer gasket 200 and the wafer 300 to be processed to fix the wafer gasket 200 and the wafer 300 to be processed.
[0110] After the wafer pad 200 and the wafer 300 to be processed are fixed on the carrier plate 102, a semiconductor process is performed on the wafer 300 to be processed in the process machine 150. For example, the semiconductor process may include a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, etc. In some examples, the semiconductor process may be an evaporation process. However, the present disclosure is not limited to this. The concept of the carrier plate of the present disclosure in combination with elastic fasteners and wafer pads to carry and fix the wafer to be processed can be applied to any suitable semiconductor process that requires fixing the wafer on the carrier plate.
[0111] During the semiconductor process, the carrier plate 102, the wafer pad 200 and the wafer 300 to be processed may deform (e.g., expand / contract) due to temperature changes. Since the wafer pad 200 and the wafer 300 to be processed have similar or substantially the same thermal expansion coefficients, the wafer pad 200 and the wafer 300 to be processed have similar or substantially the same degree of deformation (e.g., expansion / contraction), that is, the relative positional relationship between the wafer pad 200 and the wafer 300 to be processed during the process may remain substantially unchanged. In this way, the relative positional relationship between the holding component 105b and the wafer pad 200 and the wafer 300 to be processed may also remain substantially unchanged or change slightly, thereby avoiding or greatly reducing the positional change of the holding component 105b at the side walls of the wafer pad 200 and the wafer 300 to be processed, thereby rubbing and damaging the side walls of the wafer pad and the wafer to be processed. Moreover, the wafer gasket is relatively thick and is not easily deformed or damaged when subjected to the clamping force from the clamping component. The wafer gasket bears most of the force of the clamping component, which can protect the wafer to be processed and reduce the risk of damage to the side wall of the wafer to be processed and wafer fragments.
[0112] Next, a semiconductor process is performed on the wafer to be processed. During the semiconductor process, the carrier plate, the wafer pad and the wafer to be processed can rotate along with the rotation of the planetary plate, so that each area of the wafer can be processed uniformly.
[0113] After the semiconductor process is completed, the holding component is removed from the card slot, and the processed wafer and the wafer gasket are removed from the carrier plate 102 in sequence. For example, the processed wafer and the wafer gasket can be removed in sequence by using tweezers, a suction pen, a fingertip, etc. The wafer gasket can be reused, for example, it can continue to be placed between the wafer and the carrier plate during the semiconductor process of other wafers to be processed to provide support for the wafer and protect the wafer from damage caused by the holding component, thereby reducing the risk of wafer fragments.
[0114] Fig.10 A schematic cross-sectional view of a processed wafer according to some embodiments of the present disclosure is shown.
[0115] refer to Fig.10 For example, in some embodiments, the semiconductor process includes a deposition process, such as an evaporation process, and the semiconductor process forms a material layer 303 on the surface of the wafer 300 to be processed. The wafer processed by the semiconductor process can subsequently continue to undergo other semiconductor processes to complete the manufacture of semiconductor devices.
[0116] In some embodiments, during a semiconductor process (e.g., a deposition process), a small amount of film may grow at the edge of the wafer pad, and no film will grow in other areas of the wafer pad because they are covered by the wafer to be processed. Therefore, the wafer pad can be reused continuously. In some embodiments, if the film thickness at the edge of the wafer pad reaches a certain level, the film can be removed for continued reuse. For example, the film at the edge of the wafer pad can be removed by an etching process (e.g., wet etching using a chemical solution).
[0117] In some examples, the cost of a single use of a wafer gasket is evaluated to be less than 1 / 100 of the value of the wafer to be processed, and the risk of wafer fragmentation (especially thinner wafers) can be greatly reduced. For example, the fragmentation rate of wafer slices with a thickness ranging from 50 microns to 200 microns can be controlled below 1% during processing, with stable mass production capabilities. The value of the wafer to be processed at this process step is much greater than the value of the wafer gasket material (wafer substrate material). For example, the wafer to be processed at this process step is usually close to the value of the finished product, for example, it can be several times or dozens of times the value of the wafer gasket material. Therefore, the wafer processing method of the disclosed embodiment can effectively reduce the risk of wafer slices being fragmented during processing at a relatively low cost.
[0118] The present disclosure provides a semiconductor structure, including a substrate and a material layer, wherein the material layer is formed on the substrate by any of the wafer processing methods described above. For example, the semiconductor structure may be Fig.10 The wafer structure shown may be Fig.10 The wafer structure shown is then subjected to subsequent semiconductor processes to form a semiconductor structure.
[0119] In the disclosed embodiment, the wafer is protected by the wafer processing method to prevent the wafer from being damaged during the processing, thereby improving the process yield and also improving the reliability and device performance of the formed semiconductor structure.
[0120] There are a few points to note:
[0121] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.
[0122] (2) Unless there is a conflict, the features of the same embodiment or different embodiments of the present disclosure may be combined with each other.
[0123] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A wafer processing method, characterized in that: include: A wafer to be processed and a process machine are provided, wherein the process machine comprises a carrier plate and an elastic fastener, the carrier plate has a clamping slot, the elastic fastener comprises an elastic component and a clamping component, the elastic component is located at a first side of the carrier plate in a first direction, the clamping component is connected to the elastic component and is located at a side of the carrier plate in a second direction, and the first direction and the second direction intersect; placing a wafer spacer on a second side of the carrier platter opposite the first side; Placing the wafer to be processed on a side of the wafer pad away from the carrier plate; The clamping component of the elastic fastener is placed in the clamping groove of the carrier plate, and the clamping component abuts against the side walls of the wafer pad and the wafer to be processed, so as to fix the wafer pad and the wafer to be processed on the carrier plate; as well as performing semiconductor processing on the wafer to be processed, The difference in thermal expansion coefficient between the wafer to be processed and the wafer gasket is smaller than the difference in thermal expansion coefficient between the wafer to be processed and the carrier plate.
2. The wafer processing method according to claim 1, characterized in that: The substrate material of the wafer to be processed and the material of the wafer pad have the same thermal expansion coefficient.
3. The wafer processing method according to claim 1, characterized in that: The substrate material of the wafer to be processed is the same as the material of the wafer pad.
4. The wafer processing method according to any one of claims 1 to 3, characterized in that: After the wafer gasket and the wafer to be processed are fixed on the carrier plate and during the semiconductor process, the orthographic projection of the wafer to be processed on a reference plane parallel to the carrier plate is located within the orthographic projection of the wafer gasket on the reference plane.
5. The wafer processing method according to any one of claims 1 to 3, characterized in that: In the first direction, the thickness of the wafer spacer is greater than the thickness of the wafer to be processed.
6. The wafer processing method according to any one of claims 1 to 3, characterized in that: The wafer pad has a groove and includes a central portion and an edge portion surrounding the central portion, the second thickness of the edge portion is greater than the first thickness of the central portion, and the groove is defined by an inner side wall of the edge portion and a surface of the central portion.
7. The wafer processing method according to claim 6, characterized in that: The first thickness of the central portion is greater than a thickness of the wafer to be processed.
8. The wafer processing method according to claim 6, characterized in that: The side of the wafer spacer having the groove faces the wafer to be processed, and the wafer to be processed is placed on the edge portion of the wafer spacer and is spaced apart from the central portion.
9. The wafer processing method according to claim 6, characterized in that: The first thickness is greater than or equal to 250 micrometers, the depth of the groove is greater than 100 micrometers, and the width of the orthographic projection of the edge portion on a reference plane parallel to the carrier plate is greater than or equal to 1 millimeter.
10. The wafer processing method according to claim 6, characterized in that: The method for forming the wafer spacer includes: providing an initial wafer spacer, the initial wafer spacer comprising an initial central portion and the edge portion surrounding the initial central portion; and A portion of the initial central portion is removed to reduce the thickness of the initial central portion and form the central portion.
11. The wafer processing method according to any one of claims 1 to 3, characterized in that: The card slot of the carrier plate includes a first card slot and a second card slot, and a first depth of the first card slot in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate is greater than a second depth of the second card slot in a direction parallel to the main surface of the carrier plate and perpendicular to the circumference of the carrier plate.
12. The wafer processing method according to claim 11, characterized in that: The carrier plate includes a carrier body and a plurality of protrusions, wherein the plurality of protrusions protrude from the carrier body in a direction parallel to a main surface of the carrier plate and perpendicular to a circumference of the carrier plate, and at least a portion of each slot is defined by a gap between two adjacent and spaced-apart protrusions among the plurality of protrusions.
13. The wafer processing method according to claim 12, characterized in that: The carrier body has a carrier edge, the multiple protrusions are located on a side of the carrier edge away from the carrier body, and the carrier body has a depression that is concave from the carrier edge toward the center of the carrier body, the depression is connected to the gap space between two adjacent protrusions among the multiple protrusions, and together define the first slot; the second slot is defined by the gap between two adjacent protrusions among the multiple protrusions and the carrier edge.
14. The wafer processing method according to claim 12, characterized in that: The bearing body comprises an arc-shaped edge, the bottom of the first clamping slot is located on the inner side of the arc-shaped edge close to the center of the bearing body, and the bottom of the second clamping slot is located at the arc-shaped edge.
15. The wafer processing method according to claim 12, characterized in that: The carrier plate includes at least two of the second slots.
16. The wafer processing method according to claim 12, characterized in that: The area of the carrier body in the direction parallel to the main surface of the carrier plate is smaller than the area of the wafer pad or the wafer to be processed in the direction parallel to the main surface of the carrier plate.
17. The wafer processing method according to claim 11, characterized in that: The clamping component of the elastic fastener includes a first clamping portion and a second clamping portion, the first clamping portion is configured to be used in conjunction with the first clamping slot, and the second clamping portion is configured to be used in conjunction with the second clamping slot; Before placing the wafer pad and the wafer to be processed on the carrier plate, placing the second clamping portion in the second clamping slot, and removing the first clamping portion from the first clamping slot; as well as After the wafer gasket and the wafer to be processed are placed on the carrier plate, the first clamping portion is placed in the first clamping groove to fix the wafer gasket and the wafer to be processed.
18. The wafer processing method according to any one of claims 1 to 3, characterized in that: The process machine also includes: a planetary disk located on the first side of the carrier disk; and A connecting shaft is located between the planetary disk and the carrier disk, and connects the planetary disk and the carrier disk, wherein the elastic component is connected to the connecting shaft. During the semiconductor process, the carrier plate, the wafer pad and the wafer to be processed are configured to rotate along with the rotation of the planetary plate.
19. The wafer processing method according to any one of claims 1 to 3, characterized in that: The semiconductor process includes a deposition process.
20. The wafer processing method according to any one of claims 1 to 3, characterized in that: The thickness of the wafer to be processed is less than 250 microns.
21. The wafer processing method according to any one of claims 1 to 3, characterized in that: The wafer to be processed includes a silicon-containing material, and the material of the wafer gasket includes a silicon-containing material or sapphire.
22. A semiconductor structure, characterized in that: include: substrate; as well as The material layer is formed on the substrate by the wafer processing method according to any one of claims 1 to 21.