Analog-to-digital converter, and method and circuit for detecting defects therein

Abstract

The application provides an analog-digital converter, and a method and circuit for detecting defects therein. The analog-digital converter has a built-in self-detection function, and comprises: a SAR ADC designed based on a redundant coding; an input unit configured to input a defect-sensitive input quantity into the SAR ADC; a conversion control unit configured to control the SAR ADC to convert the defect-sensitive input quantity, the control comprising: step a: setting the kth bit in a K-bit binary number output by the SAR ADC to a fixed value; step b: controlling the SAR ADC to convert the defect-sensitive input quantity to determine the values of the other bits in the K-bit binary number except the kth bit, thereby generating an output digital code D out (k); step c: changing the value of k in the range of 1 to K, and repeating steps a and b to generate K output digital codes D out (k); and a judgment unit configured to judge whether the SAR ADC has defects based on the K output digital codes D out (k).

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and more particularly, to an analog-to-digital converter with built-in self-test function, a method for detecting defects in an analog-to-digital conversion circuit, and a test circuit for detecting defects in an analog-to-digital conversion circuit. BACKGROUND

[0002] Analog-to-digital converters (ADCs) are devices for converting analog signals into digital signals. Successive-approximation register analog-to-digital converters (SAR ADCs) are a typical type of ADC, which, after sampling an analog input signal, compares the sampled analog input signal with a reference voltage generated under the control of a SAR logic circuit to generate a corresponding output digital signal. SAR ADCs are widely used in audio processing, video processing, and signal processing, etc.

[0003] SAR ADCs typically include capacitors, switches, comparators, and other devices. These devices can have manufacturing defects, such as inaccurate capacitor values, non-functional switches, and non-functional comparators, etc. These defects can cause incorrect outputs of the SAR ADC. To detect defects in the SAR ADC, different analog test voltages can be provided to the SAR ADC under test, and the output values are judged for accuracy; or a dedicated test circuit can be set up to test the SAR ADC. However, the existing methods and devices for testing SAR ADCs have the disadvantages of long testing time and large system overhead. SUMMARY

[0004] It is an object of the present application to provide a method or device for detecting defects in a successive-approximation analog-to-digital conversion circuit, which can quickly and cost-effectively detect defects in a successive-approximation analog-to-digital conversion circuit.

[0005] According to an aspect of the present application, there is provided an analog-to-digital converter with built-in self-test function. The analog-to-digital converter comprises: a successive approximation analog-to-digital conversion circuit (SAR ADC) based on a redundancy coding design; an input unit configured to input a defect-sensitive input quantity into the SAR ADC, wherein the defect-sensitive input quantity is an input voltage that can be represented by a plurality of K-bit binary numbers, K being a positive integer; a conversion control unit configured to control the SAR ADC to perform analog-to-digital conversion on the defect-sensitive input quantity, the control comprising: step a: setting a kth bit in a K-bit binary number output by the SAR ADC to a fixed value; step b: controlling the SAR ADC to perform successive approximation conversion on the defect-sensitive input quantity to determine values of bits other than the kth bit in the K-bit binary number, thereby generating an output digital code D out (k); and step c: changing the value of k in the range of 1 to K, and repeating the step a and the step b until K output digital codes D out (k) are generated; and a judgment unit configured to judge whether the SAR ADC has a defect based on the K output digital codes D out (k).

[0006] According to another aspect of the present application, there is provided a method for detecting a defect in an analog-to-digital conversion circuit. The method comprises: inputting a defect-sensitive input quantity into a successive approximation analog-to-digital conversion circuit (SAR ADC) based on a redundancy coding design, wherein the defect-sensitive input quantity is an input voltage that can be represented by a plurality of K-bit binary numbers, K being a positive integer; controlling the SAR ADC to perform analog-to-digital conversion on the defect-sensitive input quantity, the control comprising: step a: setting a kth bit in a K-bit binary number output by the SAR ADC to a fixed value; step b: controlling the SAR ADC to perform successive approximation conversion on the defect-sensitive input quantity to determine values of bits other than the kth bit in the K-bit binary number, thereby generating an output digital code D out (k); and step c: changing the value of k in the range of 1 to K, and repeating the step a and the step b until K output digital codes D out (k) are generated; and judging whether the SAR ADC has a defect based on the K output digital codes D out (k).

[0007] According to another aspect of the present application, a test circuit for detecting defects in an analog-to-digital conversion circuit is provided. The test circuit comprises: an input unit configured to input a defect-sensitive input quantity into a successive approximation register analog-to-digital conversion circuit (SAR ADC) designed based on a redundancy coding, wherein the defect-sensitive input quantity is an input voltage that can be represented by a plurality of K-bit binary numbers, K being a positive integer; a conversion control unit configured to control the SAR ADC to perform analog-to-digital conversion on the defect-sensitive input quantity, the control comprising: step a: setting a k-th bit in a K-bit binary number output by the SAR ADC to a fixed value; step b: controlling the SAR ADC to perform successive approximation conversion on the defect-sensitive input quantity to determine values of bits other than the k-th bit in the K-bit binary number, thereby generating an output digital code D out (k); and step c: changing the value of k in a range of 1 to K, and repeating the step a and the step b until K output digital codes D out (k) are generated; and a judgment unit configured to judge whether the SAR ADC has defects based on the K output digital codes D out (k).

[0008] The technical solution for detecting defects in the SAR ADC provided by the present application has a shorter test time compared with the prior art, and can be integrated with the SAR ADC to realize on-chip detection, thereby saving test resources.

[0009] The above is a summary of the present application, which may have simplified, generalized and omitted details, and therefore those skilled in the art should recognize that this section is only illustrative and is not intended to limit the scope of the present application in any way. This summary section is neither intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other features of the present application will become more fully understood from the following detailed description and the accompanying drawings, wherein: It is to be understood that these drawings depict only several embodiments of the present application and are therefore not to be considered limiting in scope of the application. The application will be described with additional specificity and detail through the use of the accompanying drawings.

[0011] Figure 1 A logic block diagram of an analog-to-digital converter with a built-in self-detection function according to an embodiment of the present application is shown;

[0012] Figure 2FIG2 shows a logic block diagram of a successive approximation analog-to-digital conversion circuit (SAR ADC) included in an analog-to-digital converter with a built-in self-detection function according to an embodiment of the present application;

[0013] Figure 3A and Figure 3B A schematic diagram showing a capacitor array and a switch array used in a SAR ADC according to an embodiment of the present application operating in a sampling phase and a conversion phase, respectively;

[0014] Figure 4A shows input and output curves of a non-defective SAR ADC under different conditions according to an embodiment of the present application;

[0015] Figure 4B Shown with Figure 4A The corresponding search path of the defect-free SAR ADC under different conditions;

[0016] Figure 5A The figure shows the working principle diagram of the SAR ADC circuit during the sampling phase when the capacitor in the SAR ADC is disconnected.

[0017] Figure 5B The figure shows the working principle of the SAR ADC circuit during the conversion phase when the capacitor in the SAR ADC is disconnected.

[0018] Figure 6A shows input and output curves of a SAR ADC with a capacitor disconnection under different conditions according to an embodiment of the present application;

[0019] Figure 6B Shown with Figure 6A The corresponding search path of the SAR ADC with capacitor disconnection under different conditions;

[0020] Figure 7A The figure shows the working principle diagram of the SAR ADC circuit during the sampling phase when the capacitor in the SAR ADC is short-circuited.

[0021] Figure 7B The figure shows the working principle of the SAR ADC circuit during the conversion phase when the capacitor in the SAR ADC is short-circuited.

[0022] Figure 8A shows input and output curves of a SAR ADC under different conditions with a capacitor short circuit according to an embodiment of the present application;

[0023] Figure 8B Shown with Figure 8A The corresponding search path of the SAR ADC with a shorted capacitor under different conditions;

[0024] Figure 9A Input and output graphs of the SAR ADC with inaccurate capacitance value of the existing capacitor under different conditions are shown according to the embodiments of the present application;

[0025] Figure 9B Input and output graphs of the SAR ADC with inaccurate capacitance value of the existing capacitor under different conditions are shown according to the embodiments of the present application; Figure 9A Search paths of the corresponding SAR ADC with inaccurate capacitance value of the existing capacitor under different conditions are shown;

[0026] Figure 10A Digital code graphs when each bit of the output digital code of the SAR ADC is set to 1 according to the embodiments of the present application are shown;

[0027] Figure 10B Digital code graphs when each bit of the output digital code of the SAR ADC is set to 0 according to the embodiments of the present application are shown;

[0028] Figure 11 A structure diagram of the setting circuit in the test circuit according to the embodiments of the present application is shown;

[0029] Figure 12 A flow chart of the method for detecting defects in the SAR ADC according to the embodiments of the present application is shown;

[0030] Figure 13 A structure diagram of the test circuit for detecting defects in the SAR ADC according to the embodiments of the present application is shown. DETAILED DESCRIPTION

[0031] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments can be utilized, and other changes can be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the Figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and form part of this disclosure.

[0032] The Successive-Approximation Register Analog-to-Digital Converter (SAR ADC) usually includes a sampling and holding circuit, a digital-to-analog converter (DAC), a comparator, and a Successive-Approximation Register (SAR) logic circuit. The sampling and holding circuit is used to measure the analog input voltage A. in Sampling to get the input voltage V in , and the input voltage V in Hold; DAC is used to output reference voltage V DAC ; The comparator is used to convert the input voltage V in The reference voltage V DAC The comparison is performed to generate a comparison result, and the comparison result is sent to the SAR logic circuit. The SAR logic circuit includes a control circuit (or control logic) and a register, wherein the control circuit is used to control the reference voltage V of the DAC output according to the comparison result. DAC The voltage value of the register can store the comparison result, and after completing the analog-to-digital conversion through multiple search steps, the comparison result in the register is used as the digital code D out Output.

[0033] SAR ADC coding designs can be categorized as either non-redundant or redundant. However, a problem with the successive approximation algorithm based on non-redundant coding is that the search intervals do not overlap. Once a search interval is eliminated, it will no longer be searched. This requires that every bit of the SAR ADC be accurately judged. If an error occurs (for example, a defective capacitor in the DAC), the correct digital code cannot be generated, resulting in errors in the ADC conversion result that may be significantly greater than the quantization error.

[0034] The successive approximation algorithm based on the redundancy coding design is to set multiple search intervals with overlapping ranges, so that the error caused by the wrong judgment of a bit in the overlapping search interval can be compensated in the subsequent conversion steps. The overlapping search interval can be referred to as a redundancy window, and the size of the redundancy window is determined by the specific circuit design. The SAR ADC based on the redundancy coding design can be implemented in various ways. For example, one is to reduce the weight factor (i.e., the sub_radix2 algorithm); another is to insert an additional judgment bit in the capacitor array with binary weight, which has the same weight as the adjacent bit, referred to as a redundancy bit; and another is to use a non-fixed weight factor, only to ensure that the average radix is less than 2.

[0035] Generally, for a SAR ADC with K-bit output digital code D out , the conversion result can be represented by the following formula (1):

[0036]

[0037] where D out represents the output digital code, SAR k represents the value of the kth bit of the output digital code D out (in the following, SAR k will also be represented by Bit k ), W k represents the weight value of the kth bit of the output digital code D out , and e q represents the conversion error. For the SAR ADC based on the redundancy coding design, the weight values of each bit of the output digital code D out satisfy the following formula (2), and the weight radix satisfies the following formula (3):

[0038]

[0039]

[0040] where K represents the total number of bits of the output digital code D out ; W k and W n represent the weight values of the kth bit and the nth bit of the output digital code D out , respectively; Et represents the error tolerance, i.e., the size of the redundancy window, and Et(n) represents the redundancy window of the nth bit of the output digital code D out ; a represents the weight radix; and 2 N represents the maximum value that can be represented by the output digital code D out .

[0041] One embodiment of the present application provides an analog-to-digital converter with built-in self test (BIST) function, which comprises the aforementioned SAR ADC designed based on redundancy coding and is capable of detecting defects in the SAR ADC.

[0042] Reference Figure 1 , which shows a logic block diagram of an analog-to-digital converter 10 with built-in self test function according to an embodiment of the present application. The analog-to-digital converter 10 comprises a SAR ADC 100 and a test circuit 200 coupled with the SAR ADC 100, wherein the test circuit 200 is configured to detect defects in the SAR ADC 100.

[0043] The SAR ADC 100 is a SAR ADC designed based on redundancy coding, for example, it can be implemented by using the aforementioned coding design with reduced weight factors or the coding design without fixed weight factors. The SAR ADC 100 is configured to convert an input voltage V in into an output digital code D out . The input voltage V in can be quantized into values ranging from 0 to (M-1). Each value from 0 to (M-1) represents a quantization interval, and the total number of quantization intervals is M. Each quantization interval is the smallest unit that the ADC can distinguish and represent, and the size of each quantization interval can be represented as LSB = V ref / M, where V ref is the reference voltage provided to the SAR ADC 100. The output digital code D out can be represented by a K-bit binary number, where M and K are both positive integers, and 2 K >M.

[0044] Reference Figure 2 , which shows a structure block diagram of the SAR ADC 100 according to an embodiment of the present application. Specifically, the SAR ADC 100 comprises a capacitor array 102, a switch array 104, a common-mode voltage (V cm ) generation circuit 106, a comparator 108, and a SAR logic circuit 110. In the SAR ADC 100, the sampling and holding of the voltage to be converted and the function of the DAC circuit can be realized by the capacitor array 102 and the switch array 104.

[0045] The SAR ADC 100 is capable of receiving a power signal (Power) and a clock signal (Clock). The clock signal includes a sampling clock signal and a conversion clock signal, which respectively control the SAR ADC 100 to work in a sampling phase or a conversion phase. In the sampling phase, the capacitor array 102 and the switch array 104 sample the input voltage to be converted under the control of the sampling clock signal. In the conversion phase, the capacitor array 102 and the switch array 104 generate the output digital code based on the sampled input voltage V in and the code word (e.g., a K-bit binary number) provided by the SAR logic circuit 110 to produce a comparison voltage V cmp ; the comparator 108 compares the comparison voltage V cmp with the common-mode voltage V cm and generates a comparison result D k , which is sent to the SAR logic circuit 110 for storage and as one bit of the output digital code D out . After the completion of the analog-to-digital conversion, the sequence of the comparison results D k stored in the SAR logic circuit 110 constitutes the output digital code D out .

[0046] Reference is made to Figure 3A and Figure 3B , which show the structure of the capacitor array 102 and the switch array 104 used in the SAR ADC 100 with a 5-bit output digital code D out in a specific example, in which Figure 3A shows the circuit connection diagram of the capacitor array 102 and the switch array 104 when the SAR ADC 100 works in the sampling phase; Figure 3B shows the circuit connection diagram of the capacitor array 102 and the switch array 104 when the SAR ADC 100 works in the holding or conversion phase.

[0047] As shown in Figure 3A and Figure 3B , the capacitor array 102 includes five capacitors C1 to C5 connected in parallel, and the switch array 104 includes five switches S1 to S5 connected in parallel. The first end of each of the capacitors C1 to C5 is coupled to the switch Sa and the inverting input terminal of the comparator 108, and the second end is coupled to the first end of a corresponding one of the switches S1 to S5. The second end of each of the switches S1 to S5 is switchable between the input voltage V in , the ground voltage V ss , and the reference voltage V ref .

[0048] In Figure 3A andFigure 3B In the example shown in FIG1 , the capacitance values ​​of the five parallel-connected capacitors C1 to C5 of the capacitor array 102 may be 1C, 2C, 3C, 4C, and 5C, respectively, where C is a common capacitance unit. In addition, the capacitor array 102 further includes a dummy capacitor Cd, and the capacitance value of the dummy capacitor Cd may be 1C. The sum of the capacitance values ​​of all capacitors in the capacitor array 102 corresponds to the total number of quantization intervals (i.e., M) of the SAR ADC 100, i.e., 5C+4C+3C+2C+1C+1C=16C. The digital code D output by the SAR ADC 100 is out The maximum capacitance that can be matched is: 5C+4C+3C+2C+1C=15C. In this example, switches S1 to S5 can be switched between V ref 、V in and V ss Similarly, the first terminal of the redundant capacitor Cd is coupled to the switch Sa and the inverting input terminal of the comparator 108, and the second terminal is coupled to the first terminal of the switch Sd, and the second terminal of the switch Sd can be switched between the input voltage V in and ground voltage V ss Switch between.

[0049] Before the SAR ADC 100 operates, the charge levels in all capacitors (Cd and C1 to C5) in the capacitor array 102 are zero. Figure 3A As shown, in the sampling phase, the switch Sa and the switch Sb are closed, and all switches (Sd and S1 to S5) in the switch array 104 are switched to the input voltage V in At this time, the first terminals of all capacitors (Cd and C1 to C5) are coupled to the common mode voltage V through the switch Sa. cm The second end is connected to the input voltage V through the switches Sd and S1 to S5 in the switch array 104. in Electrical connection, through the input voltage V in Charge each capacitor so that the voltage difference between the two ends of each capacitor reaches the voltage (V cm -V in ).

[0050] Then, if Figure 3B As shown, the switches Sa and Sb are disconnected, and the capacitors Cd and C1 to C5 are connected to the ground voltage V through the switches Sd and S1 to S5. ss Since the capacitors have no discharge path, the voltage difference between their two ends remains unchanged. At this time, the comparison voltage V cmp =V cm -V in .

[0051] Next, the switches S1 to S5 in the switch array 104 receive the codeword from the SAR logic circuit 110 and control the switches S1 to S5 to switch to the reference voltage V ref Or still with ground voltage V ss Connect to generate the voltage to be compared (the formula of the voltage to be compared can be found below), and input voltage V in The SAR logic circuit 110 outputs different code words and corresponding comparison results, and uses the successive approximation algorithm to search for the code words that match the input voltage V in the search interval. in The closest voltage to be compared, the code word corresponding to the closest voltage to be compared is the output digital code D out Specifically, in the jth (j is any positive integer between 1 and K) search step, the comparison voltage V cmp It can be expressed by the following formula (4):

[0052]

[0053] Among them, ∑ j C vref represents the number of all capacitors in the capacitor array 102 coupled to the reference voltage V in the jth search step. ref ΣC represents the sum of the capacitance values ​​of all capacitors in the capacitor array 102 .

[0054] The voltage difference V between the positive input terminal and the negative input terminal of the comparator 108 is diff It can be expressed by the following formula (5):

[0055]

[0056] It can be seen from formula (5) that the comparator 108 compares the common mode voltage V cm Compare with voltage V cmp When comparing, the input voltage V in The voltage to be compared If the common mode voltage V cm Greater than the comparison voltage V at the negative input cmp , refer to formula (5), that is The comparison result D output by the comparator 108 is k = logic 1, the SAR logic circuit 110 further compares the comparison result D output by the comparator 108 to the value of k =1, the voltage to be compared corresponding to the code word in this comparison is used as the lower limit of the next search interval; on the contrary, if the common mode voltage V cm Less than the comparison voltage V at the negative inputcmp , referring to equation (5), i.e. the comparison result D output by the comparator 108 k is logic 0, and the SAR logic circuit 110 further determines the upper limit of the search interval for the next step based on the comparison result D output by the comparator 108 k = 0. The comparison result D k will be sent to the SAR logic circuit 110 for storage and as one bit of the output digital code D out . It should be noted that in the first search step, the SAR logic circuit 110 outputs the most significant bit (MSB) of the code word as 1 and the remaining bits as 0. In a specific example, for example, with reference to Figure 3A , the SAR logic circuit 110 provides the code word “10000”, the least significant bit to the most significant bit of which controls the switches S1 to S5, respectively, so that the switch S5 is coupled to the reference voltage V ref , and the switches S1 to S4 are coupled to the ground voltage V ss , at this time ∑ j C vref = 5C, ∑C = 16C, the voltage to be compared is Therefore when the input voltage V in is greater than the voltage to be compared , the comparison result D output by the comparator 108 k is logic 1; when the input voltage V in is less than the voltage to be compared , the comparison result D output by the comparator 108 k is logic 0.

[0057] The analog-digital conversion process of the SAR ADC 100 shown in Figure 4A and Figure 4B is described below. Among them, Figure 4A is the input and output curve of the SAR ADC 100 under different conditions, Figure 4B shows the search path of the SAR ADC 100 corresponding to Figure 4A under different conditions.

[0058] Taking the value of the input voltage V in slightly greater than as an example, Figure 4A the curve 410 in Figure 4B shows that in the normal operation (Normal), the output digital code D is determined from the most significant bit (MSB) Bit5 to the least significant bit (LSB) Bit1 in turnout the process; Figure 4B The first row of the table in FIG. 1 1 shows the search path of the SAR ADC 100. Referring to FIGS. 1 1 and 10 simultaneously, Figure 4A and 4B In the first step, the SAR logic 1 10 provides the code word "10000", i.e. the control switch S5 is coupled to the reference voltage V ref while the switches S1 to S4 are coupled to the ground voltage V ss At this time After comparison by the comparator 108, V cmp is smaller than V cm , i.e. the voltage to be compared V is smaller than the input voltage V in , the output comparison result D5 is logic 1, so that it is determined that Bit5 of the output digital code D out is 1; in the second step, based on the value of Bit5, the SAR logic 1 10 sets the value of Bit4 to 1 and provides the code word "1 1000", i.e. the control switches S5, S4 are coupled to the reference voltage V ref while the switches S1 to S3 are coupled to the ground voltage V ss At this time After comparison by the comparator 108, V cmp is still smaller than V cm , i.e. the voltage to be compared V is smaller than the input voltage V in , the output comparison result D4 is logic 1, so that it is determined that Bit4 of the output digital code D out is 1; in the third step, based on the values of Bit5 and Bit4, the SAR logic 1 10 sets the value of Bit3 to 1 and provides the code word "1 1 100", i.e. the control switches S5, S4 and S3 are coupled to the reference voltage V ref while the switches S1 to S2 are coupled to the ground voltage V ss At this time After comparison by the comparator 108, V cmp is greater than V cm , i.e. the voltage to be compared V is greater than the input voltage V in , the output comparison result D3 is logic 0, so that it is determined that Bit3 of the output digital code D out is 0; in the fourth step, based on the values of Bit5 to Bit3, the SAR logic 1 10 provides the code word "1 1010", i.e. the control switches S5, S4 and S2 are coupled to the reference voltage V ref while the switches S1, S3 are coupled to the ground voltage V ss At this time After comparison by the comparator 108, V cmp is greater than V cmthe voltage to be compared greater than the input voltage V in , the comparison result D2 output is logic 0, thus determining that Bit2 of the output digital code D out is 0; in the fifth step, based on the values of Bit5 to Bit2, the SAR logic circuit 110 sets the value of Bit1 to 1 and provides the code word “11001”, i.e. the switches S5, S4 and S1 are coupled to the reference voltage V ref , while the switches S2, S3 are coupled to the ground voltage V ss , at this time After the judgment of the comparator 108, V cmp is still greater than V cm , i.e. the voltage to be compared is greater than the input voltage V in , the comparison result D1 output is logic 0, thus determining that Bit1 of the output digital code D out is 0. At this time, the values of each bit of the output digital code D out have been determined, the SAR ADC 100 outputs the conversion result “11000”, and after the weighted conversion, it is 5x1+4x1+3x0+2x0+1x0=9, which means that the input voltage

[0059] For the SAR ADC with redundant coding design, there are overlapping windows between some search intervals, and the error caused by the previous wrong code word can be compensated by the following code word. Returning to the SAR ADC 100 shown in Figure 2 and Figure 3A and 3B , the weight values W out of each bit of the output digital code D k correspond to the capacitance values of the five capacitors C1 to C5 in the capacitor array 102, i.e. W5=5, W4=4, W3=3, W2=2, and W1=1. It can be seen that the above weight values satisfy the aforementioned formula (2) and formula (3), that is, the SAR ADC 100 includes a redundant capacitor array and has a redundant window. Thus, the SAR ADC 100 can have multiple solutions for some specific input voltage V in . For different search paths or different coding sequences, these solutions can give the same conversion value.

[0060] Referring to the search path of the curve 420 in Figure 4A and the second row of the table in Figure 4B , it is shown that when the value of the input voltage V in is slightly greater than and the output digital code D outWhen Bit4 of is forced to be set to 0, the SAR ADC 100 searches the path "10000" → "10000" → "10100" → "10110" → "10101" and finally outputs the digital code "10101". Similarly, refer to Figure 4A Curve 430 and Figure 4B The third row of the table shows the search path, which shows the input voltage V in The value is slightly greater than And the digital code D will be output out When Bit5 of is forced to be set to 0, the SAR ADC 100 searches the path "00000" → "01000" → "01100" → "01110" → "01111" and finally outputs the digital code "01110". Figure 4A Curve 440 and Figure 4B The search path in the fourth row of the table shows the input voltage V in The value is slightly greater than And the digital code D will be output out When Bit3 of ADC100 is forced to be set to 1, SAR ADC100 searches the path "10100" → "11100" → "10100" → "10110" → "10101" and finally outputs the digital code "10101". Based on the above formula (1), it can be seen that the digital codes "11000", "10101" and "01110" can all represent the value 9, which is consistent with the input voltage V in The value corresponds to .

[0061] Based on the above discussion, it can be seen that when the SAR ADC 100 works normally, when Bit4 is forced to be 0, Bit5 is forced to be 0, or Bit3 is forced to be 1, the SAR ADC 100 can output the correct digital code D. out The following will be combined with Figure 5A and Figure 5B ,to Figure 9A and Figure 9B When the SAR ADC 100 has a defect, its output under different search paths is discussed to illustrate the principle of detecting the defect of the SAR ADC 100 in the present application.

[0062] refer to Figure 5A and Figure 5B , which shows a capacitor C in a capacitor array of a SAR ADC in an example k The two ends of the capacitor C j,j≠k Circuit diagram during normal operation. Figure 5AThe SAR ADC works in the sampling phase. k There is a short circuit at both ends, and the capacitor C cannot be used during the sampling phase. k Charge. Figure 5B The SAR ADC is shown in the conversion phase. k The two ends are broken, and the comparison voltage V cmp It is expressed by the following formula (6):

[0063]

[0064] Among them, ∑CC k Indicates the number of capacitors in the capacitor array except capacitor C k The sum of the capacitance values ​​of all capacitors except j≠k C vref Indicates the number of capacitors in the capacitor array except capacitor C k All other components are coupled to the reference voltage V ref The sum of the capacitance values ​​of the capacitors. Comparing formula (4) and formula (6), we can see that due to the capacitor C k A circuit breaker occurs at both ends, which will cause the comparison voltage V at the negative input of the comparator to drop during the SAR ADC conversion process. cmp This is inconsistent with the situation when there is no defect, resulting in inaccurate conversion results of the SAR ADC.

[0065] Figure 6A and Figure 6B by Figure 3A and Figure 3B The conversion process of the SAR ADC 100 is illustrated by taking the case where both ends of the capacitor C5 in the capacitor array 102 of the SAR ADC 100 are broken as an example. Figure 6A shows the input and output curves of the SAR ADC 100 under different conditions, Figure 6B Shown with Figure 6A The corresponding search path of the SAR ADC 100 under different conditions. in The value is slightly greater than For example, referring to curves 610 and 6A Figure 6B The search path of the first row of the table in FIG. 1 shows the output digital code D determined from MSB to LSB in normal operation (Normal). out In the process, the SAR ADC 100 searches the path “10000” → “11000” → “11100” → “11010” → “11011” and finally outputs the digital code “11010”. Figure 6A Curve 620 and Figure 6BThe search path in the second row of the table shows the output digital code D out In the case where Bit4 of is forcibly set to 0, the SAR ADC 100 searches the path "10000" → "10000" → "10100" → "10110" → "10111" and finally outputs the digital code "10111". Figure 6A Curve 630 and Figure 6B The search path in the third row of the table shows the output digital code D out In the case where Bit 5 of the ADC is forcibly set to 0, the SAR ADC 100 searches the path “00000” → “01000” → “01100” → “01010” → “01011” and finally outputs the digital code “01010”. Figure 6A Curve 640 and Figure 6B The search path in the fourth row of the table shows the output digital code D out In the case where Bit 3 of the ADC is forcibly set to 1, the SAR ADC 100 searches the path “10100” → “11000” → “10100” → “10110” → “10111” and finally outputs the digital code “10111”.

[0066] In the above example, although a defect occurs inside the SAR ADC 100 (ie, a capacitor is disconnected), the defect cannot be known from outside the circuit, and the D output by the SAR ADC 100 is still considered to be out The digital code value is credible, and the conversion result is calculated using formula (1). Based on the above formula (1), it can be seen that the digital codes "11010", "10111", "01010" and "10111" output under four different search paths represent the values ​​"11", "11", "6" and "11" respectively, and none of them can accurately represent the input voltage V in value.

[0067] refer to Figure 7A and Figure 7B , which shows a capacitor C in a capacitor array of an example SAR ADC k The two ends of the capacitor C j,j≠k The circuit schematic diagram during normal operation. Figure 7A The SAR ADC works in the sampling phase. k The two ends of the short circuit is equivalent to the input voltage V in Connect to the negative input of the comparator through an equivalent resistor. Figure 7B The SAR ADC is shown in the conversion phase. Similarly, due to the capacitor C kThe two ends of the comparator are short-circuited, and the comparison voltage V cmp It is expressed by the following formula (7):

[0068] V cmp =SAR k ×V ref (7)

[0069] Among them, SAR k Indicates the code word provided by the SAR logic circuit and the capacitor C k Comparing formula (7) with formula (4), it can be seen that due to the capacitor C k A short circuit at both ends will also cause the comparison voltage V at the negative input of the comparator to cmp This is inconsistent with the situation when there is no defect, resulting in inaccurate conversion results of the SAR ADC.

[0070] Figure 8A and Figure 8B by Figure 3A and Figure 3B The conversion process of the SAR ADC 100 is illustrated by taking the short circuit of both ends of the capacitor C3 in the capacitor array 102 of the SAR ADC 100 as an example. Figure 8A shows the input and output curves of the SAR ADC 100 under different conditions, Figure 8B Shown with Figure 8A The corresponding search path of the SAR ADC 100 under different conditions. in The value is slightly greater than For example, referring to curves 810 and 8A Figure 8B The search path of the first row of the table in FIG. 1 shows the output digital code D determined from MSB to LSB in normal operation (Normal). out In the process, SAR ADC100 searches the path “10000” → “11000” → “11000” → “11010” → “11011” and finally outputs the digital code “11011”. Figure 8A Curve 820 and Figure 8B The search path in the second row of the table shows the output digital code D out In the case where Bit4 of is forcibly set to 0, the SAR ADC 100 searches the path "10000" → "10000" → "10100" → "10010" → "10011" and finally outputs the digital code "10011". Figure 8A Curve 830 and Figure 8B The search path in the third row of the table shows the output digital code D outIn the case that Bit5 is forced to be 0, SAR ADC 100 goes through search paths “00000”→“01000”→“01100”→“01010”→“01011” and finally outputs digital code “01011”. Figure 8A In the case that Bit5 is forced to be 0, SAR ADC 100 goes through search paths “00000”→“01000”→“01100”→“01010”→“01011” and finally outputs digital code “01011”. Figure 8B The search paths of the fourth row of the table in out In the case that Bit3 is forced to be 1, SAR ADC 100 goes through search paths “10100”→“01100”→“00100”→“00110”→“00101” and finally outputs digital code “00100”.

[0071] Similarly, in the case that the internal defect (i.e., the short circuit) of SAR ADC 100 cannot be known from outside the circuit, the results of the conversion are still calculated using the above formula (1), it can be known that the digital codes “11011”, “10011”, “01011” and “00100” outputted under four different search paths represent values “12”, “8”, “7” and “3” respectively, which cannot accurately represent the value of input voltage V in .

[0072] In addition, in some circuit designs, a certain capacitor in the SAR ADC can be composed of multiple unit capacitors, when a defect (e.g., a short circuit or an open circuit) occurs, it can cause one or more unit capacitors that compose the capacitor to fail, thereby causing the capacitance value of the capacitor in the SAR ADC to be inaccurate, thereby affecting the accuracy of the conversion of the SAR ADC. For example, Figure 3A and Figure 3B The capacitance value of capacitor C3 in capacitor array 102 of SAR ADC 100 shown in

[0073] Figure 9A and Figure 9B The capacitance value of capacitor C4 in capacitor array 102 of SAR ADC 100 shown in Figure 3A and Figure 3B For example, the capacitance value of capacitor C4 in capacitor array 102 of SAR ADC 100 shown in Figure 9A shows the input and output curves of SAR ADC 100 under different conditions, Figure 9B shows the search paths of SAR ADC 100 under different conditions corresponding to Figure 9A For example, taking the value of input voltage V in to be slightly greater than , reference is made to curves 910 and Figure 9Bthe search path of the first row of the table shows that the output digital code D is determined sequentially from MSB to LSB in the normal operation (Normal) out After going through the search paths "10000"→"11000"→"11100"→"11010"→"11001", the SAR ADC 100 finally outputs the digital code "11000". Figure 9A the curve 920 in FIG. 9B and Figure 9B the search path of the second row of the table shows that the output digital code D out After going through the search paths "10000"→"10000"→"10100"→"10010"→"10011", the SAR ADC 100 finally outputs the digital code "10010". Figure 9A the curve 930 in FIG. 9C and Figure 9B the search path of the third row of the table shows that the output digital code D out After going through the search paths "00000"→"01000"→"01100"→"01110"→"01111", the SAR ADC 100 finally outputs the digital code "01110". Figure 9A the curve 940 in FIG. 9D and Figure 9B the search path of the fourth row of the table shows that the output digital code D out After going through the search paths "10100"→"01100"→"01100"→"01110"→"01111", the SAR ADC 100 finally outputs the digital code "01110".

[0074] Similarly, in the case where the internal defects (i.e., inaccurate capacitor values) of the SAR ADC 100 cannot be known from the outside of the circuit, the results of the conversion are calculated using the above formula (1), and it is found that the output digital codes "11000", "10010", "01110", and "01110" under four different search paths respectively represent the values "9", "7", "9", and "9", wherein some of the digital codes cannot accurately represent the value of the input voltage V in .

[0075] In summary, compared with the normal operation of the SAR ADC 100 shown in Figure 4A and Figure 4B , Figure 6A and Figure 6B the case where there is a broken capacitor in the SAR ADC 100 shown in Figure 8A and Figure 8B the case where there is a shorted capacitor in the SAR ADC 100 shown in Figure 9Aand Figure 9B In the case that the capacitance values of the capacitors in the SAR ADC 100 shown are inaccurate, all the outputs of the digital codes D out Based on the above discussion, for a certain input voltage V in If we change the search path strategically or intentionally based on the multiple digital codes, the output of the SAR ADC 100 should remain unchanged in the case of no defects, but the output may not accurately represent the input voltage V in This is the basic principle of the technical solution described in this application for defect detection of the SAR ADC 100.

[0076] Returning to Figure 1 The test circuit 200 of the present application includes an input unit 210, a conversion control unit 220 and a judgment unit 230 for detecting defects of the SAR ADC 100.

[0077] The input unit 210 is configured to input a defect-sensitive input quantity to the SAR ADC 100. Taking the output digital code D out of the SAR ADC 100 as an example, the defect-sensitive input quantity refers to an input voltage V in that can be represented by multiple K-bit binary numbers (also referred to as K-bit digital codes) after conversion by the SAR ADC 100.

[0078] Referring to Figure 10A and Figure 10B , which show the digital code diagram corresponding to the SAR ADC 100 in Figure 2 , the horizontal axis shows the input voltage V in corresponding to the quantization intervals 0 to 15, and the vertical axis shows the respective bits of the output digital code D out when K is 5, i.e. Bit1 to Bit5. For any input voltage V in corresponding to a quantization interval, before performing successive approximation conversion on the input voltage V in , the kth (any bit from 1st to Kth) bit in the K-bit digital code is set to 1 (or 0), and then the input voltage V in is converted to obtain the bits other than the kth bit in the K-bit digital code. If the final K-bit digital code can correctly represent the input voltage V in , it means that the kth bit is a sensitive bit, or the input voltage V in is sensitive to the kth bit, and such an input voltage belongs to the defect-sensitive input quantity.

[0079] Figure 10AThe white area in the figure indicates that after setting a certain bit in Bit1 to Bit5 to 1, there exists a K-bit digital code in the digital code domain that can represent the corresponding input voltage V in ; the black area indicates that after setting a certain bit in Bit1 to Bit5 to 1, there is no digital code in the digital code domain that can represent the corresponding input voltage V in . For example, for the input voltage corresponding to the quantization interval 0 to 1, setting any bit in Bit1 to Bit5 to 1 cannot obtain a K-bit digital code that can correctly represent the input voltage V in ; that is, the input voltage V in corresponding to the quantization interval 0 to 1 does not belong to the defect-sensitive input quantity; for the input voltage corresponding to the quantization interval 1 to 2, Bit1 is a sensitive bit, and when Bit1 is set to 1, a K-bit digital code that can correctly represent the input voltage V in can be obtained through successive approximation conversion, and when the other bits are set to 1, a K-bit digital code that can correctly represent the input voltage V in cannot be obtained; for the input voltage corresponding to the quantization interval 3 to 4, Bit1 to Bit3 are sensitive bits, and when Bit1 to Bit3 are respectively set to 1, three K-bit digital codes that can correctly represent the input voltage V in can be obtained; and for the input voltage corresponding to the quantization interval 8 to 9, any bit in Bit1 to Bit5 is a sensitive bit, and when Bit1 to Bit5 are respectively set to 1, five K-bit digital codes that can correctly represent the input voltage can be obtained. Taking the input voltage V in equal to 8.5 LSB (i.e., ) as an example, no matter which bit in Bit1 to Bit5 in the output digital code D out is set to 1, there exists a digital code in the digital code domain that can represent the input voltage V in equal to 8.5 LSB. That is, the input voltages V in corresponding to the quantization interval 1 to 2, the quantization interval 3 to 4, and the quantization interval 8 to 9 listed in the above example all belong to the defect-sensitive input quantity, however, for the input voltage corresponding to the quantization interval 1 to 2, only one K-bit digital code that can correctly compare the input voltage is obtained, and the defect in the circuit cannot be accurately judged according to the K-bit digital code. In order to improve the accuracy and efficiency of defect judgment, the embodiments of the present application prefer to select the input voltage that can be represented by multiple K-bit digital codes as the defect-sensitive input quantity input to the SAR ADC 100, for example, the input voltage corresponding to the quantization interval 3 to 4 and the quantization interval 8 to 9. In actual applications, in order to further improve the judgment efficiency, the input voltage corresponding to K sensitive bits can be further selected, for example, the input voltage corresponding to the quantization interval 8 to 9. Figure 10AIn the area below the horizontal axis, the white area shows the defect-sensitive input quantities corresponding to K sensitive bits, which are the input voltages corresponding to quantization intervals 5 to 7, 8 to 9, 10 to 11, 12 to 13, and 15 to 16.

[0080] Similarly, reference Figure 10B The white area indicates that after setting the value of a bit from Bit1 to Bit5 to 0, there is a digital code in the digital code domain that can represent the corresponding input voltage V in The black area indicates that after setting the value of a bit from Bit1 to Bit5 to 0, there is no digital code in the digital code domain that can represent the corresponding input voltage V in . Continue with input voltage V in For example, if the output digital code D is equal to 8.5LSB, out If any of Bits 1 to 5 in the digital code field is set to 0, there is a digital code that can represent an input voltage V equal to 8.5LSB. in .exist Figure 10B In the area below the horizontal axis, the white area shows the defect-sensitive input quantities corresponding to K sensitive bits, which are input voltages corresponding to quantization intervals 0 to 1, 3 to 6, and 8 to 10.

[0081] comprehensive Figure 10A and Figure 10B , Table 1 below shows the input voltage V in When the SAR ADC100 is not defective and equal to 8.5LSB, the output digital code D is out When any bit from Bit1 to Bit5 is set to 1 or 0, the output digital code D out The value of each bit and its corresponding numerical value.

[0082] Table 1V in Conversion result when the LSB is equal to 8.5LSB and the SAR ADC is not defective

[0083]

[0084]

[0085] The defect-sensitive input quantity can be determined during the circuit design phase. For example, in some embodiments, during the circuit design phase, after confirming the weight of each bit in the K-bit digital code, a behavioral model of the SAR ADC 100 can be established according to the formula (4) above. The default (i.e., no operation is performed on the digital code) and the k-th bit of the K-bit digital code corresponding to the input voltage is set to 1 (or 0) are respectively adopted. After the successive approximation conversion operation is completed, the output under the default condition is compared with the output when the k-th bit of the K-bit digital code is set to 1 (or 0). If the two are consistent, it means that the input voltage is sensitive to the k-th bit, that is, the input voltage is a defect-sensitive input quantity. By traversing the entire input range using the above method, all defect-sensitive input quantities can be obtained. In practical applications, all defect-sensitive input quantities can be determined manually or with computer assistance. For each specific design, a specific set of defect-sensitive input quantities can be obtained.

[0086] After the defect-sensitive input quantity is determined, the defect-sensitive input quantity can be input into the SAR ADC 100 through the input unit. The conversion control unit 220 is configured to control the SAR ADC 100 to perform analog-to-digital conversion on the defect-sensitive input quantity received from the input unit 210.

[0087] Specifically, the conversion control unit 220 controls the SAR ADC 100 including step a: setting the k-th bit of the K-bit binary number output by the SAR ADC 100 to a fixed value, where 1≤k≤K.

[0088] In some embodiments, the conversion control unit 220 may set the kth bit of the K-bit binary number output by the SAR ADC 100 to 1. In other embodiments, the conversion control unit 220 may set the kth bit of the K-bit binary number output by the SAR ADC 100 to 0.

[0089] In some embodiments, as Figure 1 As shown, the conversion control unit 220 includes a setting circuit 222. The setting circuit 222 is configured to set the trigger signal Set <k>, polarity signal Polarity <k>and an initial control value SAR <k>Generating a rewrite signal SAR_ow for setting the kth bit in a K-bit binary number to a fixed value <k>wherein a trigger signal Set is provided <k>indicates to reset the kth bit in a K-bit binary number, polarity signal Polarity <k>indicates setting the kth bit in a K-bit binary number to 0 or 1, initial control value SAR <k>The initial value of the kth bit of the code word provided by the SAR logic circuit 110 of the SAR ADC 100 is indicated.

[0090] With reference to Figure 11 which shows the specific structure of the setting circuit 222 in a specific example. The setting circuit 222 includes an OR gate 2221, an AND gate 2222, an NAND gate 2223, and an OR gate 2224. The first input end of the OR gate 2221 receives the inverted setting trigger signal Set <k>, the second input receives a polarity signal Polarity <k>, the output end is coupled to the first input end of the AND gate 2222. The first input end of the AND gate 2222 receives the output of the OR gate 2221, and the second input end receives the initial control value SAR <k>The output of the NOR gate 2224 is coupled to a first input of an AND gate 2225. The three inputs of the NAND gate 2225 receive the trigger signal Set <k>, polarity signal Polarity <k>and the initial control value SAR <k>, the output signal of the inverter is coupled to the second input of the OR gate 2224. The OR gate 2224 outputs a rewrite signal SAR_ow by performing OR operation on the output of the AND gate 2222 and the inverted signal of the output of the NAND gate 2223 <k>, and rewrite the signal SAR_ow <k>provided to the SAR ADC 100 for setting the kth bit of the K-bit binary number output by the SAR ADC 100 to 0. It can be appreciated that the specific implementation of the setting circuit 222 is not limited to Figure 11 the example shown in FIG. 2. In other embodiments, other structures can also be implemented to set the kth bit of the K-bit binary number output by the SAR ADC 100 to 1.

[0091] Continuing with the example of the SAR ADC 100 shown in Figure 2 , Figure 3A and Figure 3B , which is capable of converting a defect-sensitive input quantity (e.g., 8.5 LSB) into a digital code D out (5) represented by a 5-bit binary number, the conversion control unit 220, when performing step a, sets the 5th bit (i.e., Bit5) of the 5-bit binary number output by the SAR ADC 100 to 1.

[0092] The conversion control unit 220 controls the SAR ADC 100 to further include step b: controlling the SAR ADC 100 to perform successive approximation conversion on the defect-sensitive input quantity to determine the values of the other bits of the K-bit binary number except the kth bit, thereby generating an output digital code D out (k).

[0093] Continuing with the example of the SAR ADC 100 shown in Figure 2 , Figure 3A and Figure 3B , the conversion control unit 220, when performing step b, controls the SAR ADC 100 to perform successive approximation conversion on the defect-sensitive input quantity 8.5 LSB to determine the values of the other bits (i.e., Bit4, Bit3, Bit2, and Bit1) of the 5-bit binary number output except Bit5. According to Table 1 shown above, when the SAR ADC 100 is operating normally, it is capable of determining the values of Bit4 to Bit1 to be "0", "1", "0", and "0", respectively, after performing successive approximation conversion on the defect-sensitive input quantity 8.5 LSB. Thus, the digital code D out (5) output by the SAR ADC 100 is "10100".

[0094] Further, the conversion control unit 220 controls the SAR ADC 100 to further include step c: changing the value of k in the range of 1 to K, and repeating steps a and b until K output digital codes D out (k) are generated.

[0095] Continuing with the example of the SAR ADC 100 shown in Figure 2 , Figure 3A and Figure 3B The SAR ADC 100 shown is an example. The conversion control unit 220 changes the value of k in the range of 1 to 5, and repeatedly performs the aforementioned steps a and b until five corresponding output digital codes D out (k). Specifically, the conversion control unit 220 can change the value of k from 5 to 4, set the fourth bit (i.e., Bit4) of the five-bit binary number output by the SAR ADC 100 to 1, and control the SAR ADC 100 to perform successive approximation conversion on the defect-sensitive input quantity 8.5LSB to determine the values of the other bits (i.e., Bit5, Bit3, Bit2, and Bit1) of the five-bit binary number output except Bit4. Referring to Table 1, when the SAR ADC 100 is working normally, the digital code D out (4) is "01101". Similarly, the conversion control unit 220 can also control the value of k to be 3, 2, and 1 in turn, and repeatedly perform the aforementioned steps a and b to generate the digital codes D out (3) = "10100"; D out (2) = "10011"; D out (1) = "10011".

[0096] It should be noted that in the above example, the value of k is sequentially decreased from 5 to 1, i.e., the values of the bits of the output digital code D out are set in turn from MSB to LSB, but the present application is not limited thereto, and in other embodiments, the values of the bits of the output digital code D out may also be set in turn from LSB to MSB, or the values of the bits of the output digital code D out may be set in disorder. In addition, in the above example, the conversion control unit sets each bit of the K-bit binary number output by the SAR ADC 100 to 1, but the present application is not limited thereto, and in other embodiments, the conversion control unit sets each bit of the K-bit binary number output by the SAR ADC 100 to 0. As shown in Table 1 above, when the defect-sensitive input quantity is 8.5LSB, setting each bit of the five-bit binary number output by the SAR ADC 100 to 0 can also obtain five output digital codes D out (5) to D out (1).

[0097] The above is described in combination with Figure 1 , Figure 1 and Figure 10A The SAR ADC 100 shown in Figure 1 and Table 1 illustrate the conversion process and conversion results when the SAR ADC 100 is defect-free. However, as previously mentioned, the SAR ADC 100 may have defects such as open or shorted capacitors, or inaccurate capacitor values. For a defective SAR ADC 100, the test circuit controlling the SAR ADC 100 to perform analog-to-digital conversion on defect-sensitive input quantities will produce different results.

[0098] Refer to Table 2 below, which shows the output digital codes D when the defect sensitive input is equal to 8.5LSB and the capacitor C4 in the SAR ADC 100 is disconnected. out When any bit from Bit1 to Bit5 is set to 1 or 0, the output digital code D out As discussed above, when the capacitor in the SAR ADC 100 is disconnected, the comparison voltage V at the negative input of the comparator during the conversion process of the SAR ADC 100 will be cmp The inaccurate conversion results of the SARADC 100 are caused. Comparing Table 2 with Table 1, it can be seen that due to the open circuit of capacitor C4, multiple conversion results of the SARADC 100 are erroneous.

[0099] Table 2 V in Conversion result when the LSB is equal to 8.5LSB and C4 is disconnected in the SAR ADC

[0100]

[0101] Refer to Table 3 below, which shows the output digital codes D when the defect sensitive input is equal to 8.5LSB and the capacitor C4 in the SAR ADC 100 is short-circuited. out When any bit from Bit1 to Bit5 is set to 1 or 0, the output digital code D out Comparing Table 3 with Table 1, it can be seen that due to the short circuit of capacitor C4, multiple conversion results of SAR ADC 100 are erroneous.

[0102] Table 3V in Conversion result when equal to 8.5LSB and C4 is shorted in SAR ADC

[0103]

[0104] Referring to Table 4 below, which shows the conversion results of the SAR ADC 100 when the defect-sensitive input quantity equals to 8.5LSB and the capacitance value of the capacitor C5 in the SAR ADC 100 is inaccurate (e.g., reduced from 5C to 2C), respectively setting any one of Bit1 to Bit5 in the output digital code D out (k) to 1 or 0. out (k) to 1 or 0.

[0105] Table 4 V in Conversion results when the defect-sensitive input quantity equals to 8.5LSB and the C5 capacitance value in the SAR ADC is inaccurate

[0106]

[0107] Back to Figure 10B , the test circuit 200 of the present application further comprises a judging unit 230. The judging unit 230 is configured to judge whether the SAR ADC 100 has a defect based on the K output digital codes D out (k) generated by the SAR ADC 100.

[0108] In some embodiments, as shown in Figure 2 , the judging unit 230 further comprises a storage module 232 configured to store the K output digital codes D out (k) generated by the SAR ADC 100. For example, after each time the conversion control unit 220 controls the SAR ADC 100 to perform analog-digital conversion on the defect-sensitive input quantity to generate the digital code D out (k), the digital code D out (k) is transmitted to the storage module 232 for storage.

[0109] In some embodiments, the judging unit 230 judging whether the SAR ADC 100 has a defect comprises: comparing the difference between the maximum value max(D out (k)) and the minimum value min(D out (k)) in the K output digital codes D out (k) with a predefined threshold value ε; when the difference is less than the predefined threshold value ε, it is determined that the SAR ADC 100 does not have a defect; and when the difference is greater than or equal to the predefined threshold value ε, it is determined that the SAR ADC 100 has a defect. The predefined threshold value ε can be determined according to the deterministic error and the random error of the SAR ADC, and can vary with the specific design index of the SAR ADC.

[0110] Specifically, the conversion process of ADCs suffers from conversion errors due to various non-ideal factors, including deterministic errors and random errors. Among them, deterministic errors can be characterized by the non-linearities of ADCs, DNL (Differential Non-linearity) and INL (Integral Non-linearity). DNL, also known as differential non-linearity, refers to the difference between the distances of two adjacent scales of the ADC and the minimum resolution unit (LSB) of the ADC, reflecting the local microscopic non-linearity in the entire range. INL, on the other hand, refers to the accuracy of the ADC, which is the error value between the quantized value and the true value at each value point of the ADC, representing the absolute error of the measurement value. Due to various non-ideal factors, the DNL and INL of ADCs are usually not zero. The larger the DNL / INL, the more serious the non-linearity of the ADC itself, and the larger the error between the output digital result and the analog input quantity. For SAR ADCs, non-linearity comes from circuit mismatches, non-linearity of sampling circuits and comparator circuits, limited bandwidth of DACs, etc. For a SAR ADC with a given design specification, the degree of non-linearity (the maximum value of DNL / INL) can be determined according to the above sources. Therefore, for a certain analog input quantity, the error of the converted output result can also be determined. For a SAR ADC based on redundant coding design, the difference between the maximum value max(D out (k)) and the minimum value min(D out (k)) of the above-mentioned defects detection process due to the non-linearity of the SAR ADC itself can be further determined, denoted as the deterministic error deterministic .

[0111] Further, in addition to deterministic errors, there are also random errors in ADCs. Random errors mainly come from noise and aperture uncertainty. For a SAR ADC with a given design specification, the level of random error can be well estimated. Therefore, the difference between the maximum value max(D out (k)) and the minimum value min(D out (k)) of the above-mentioned defects detection process due to the random error of the SAR ADC can be further determined, denoted as the random error random .

[0112] In full consideration of the aforementioned deterministic error deterministic and random error random of the SAR ADC, the above-mentioned predefined threshold ε can be determined by the following formula (8):

[0113] ε ≥ deterministic + random (8)

[0114] It can be seen that the selection of the predefined threshold ε can be determined by the SAR ADC design indicators, where when the above formula (8) takes the equal sign, it means that the tolerance to SAR ADC defects is the minimum.

[0115] In one example, assuming that the predefined threshold ε is set to 2, the conversion results in Tables 1 to 4 are used as examples for judgment. It can be seen that max(D out (k))-min(D out (k))=0, which is less than the predefined threshold 2, then the SARADC can be judged to be non-defective; max(D out (k))-min(D out (k))=4, max(D out (k))-min(D out (k))=7, max(D out (k))-min(D out (k))=3, which are all greater than the predefined threshold 2, it can be determined that the SAR ADC has a defect.

[0116] In the above embodiment, the working process of the analog-to-digital converter 10 with built-in self-detection function of the present application is described with the defect sensitive input amount being 8.5LSB. In other embodiments, the number of defect sensitive input amounts can be multiple. For example, Figure 3A As shown, the digital code D will be output out When any of Bit 1 to Bit 5 in is set to 1, the defect sensitive input quantities include the input voltages 5 to 7, 8 to 9, 10 to 11, 12 to 13, and 15 to 16; or Figure 12 As shown, the digital code D will be output out When any of Bit 1 to Bit 5 is set to 0, the defect-sensitive input includes any input voltage from 0 to 1, 3 to 6, and 8 to 10. The input unit 210 is configured to sequentially input the above-mentioned multiple defect-sensitive inputs into the SAR ADC 100; the conversion control unit 220 performs the above-mentioned steps a to c on each defect-sensitive input and obtains the corresponding K output digital codes D. out (k); The judgment unit 230 outputs the K digital codes D corresponding to each defect sensitive input quantity. out (k) Determining whether there is a defect in the SAR ADC 100. Based on the conversion of multiple defect-sensitive input quantities, the accuracy and coverage of defect judgment can be increased.

[0117] In some embodiments, the judging unit 230 is capable of judging not only whether the SAR ADC 100 has a defect, but also the specific type of the defect of the SAR ADC 100. With reference to Tables 2-4 above, it can be seen that the K output digital codes D out (k) output by the SAR ADC 100 under different defect types are different, but have different characteristics. The judging unit 230 is capable of judging the type of the defect of the SAR ADC 100 and locating the defect position based on the different characteristics of the K output digital codes D out (k).

[0118] In some examples, the judging unit 230 can pre-store a defect lookup table in which the correspondence between different defect types and the characteristics of the K output digital codes D out (k) is pre-stored. Upon receiving the K output digital codes D out (k) output by the SAR ADC 100, the judging unit 230 can determine the corresponding defect type by consulting the defect lookup table.

[0119] It should be noted that in the above embodiments, the analog-to-digital converter with built-in self-detection function of the present application is described in combination with the specific structures of the SAR ADCs in Figure 1 , and Figure 12 and 3B . However, those skilled in the art can understand that the structures or configurations of the above SAR ADCs can be modified without departing from the scope of the present application. For example, the number of capacitors or switches included in the capacitors or switch array in the SAR ADC can be increased or decreased; for example, the specific implementation of the comparator or the SAR logic circuit can be changed; for example, the reference voltage V ref in the SAR ADC can be generated by the difference between the power supply voltage V dd and the ground voltage V ss , or by any two voltages V1 and V2 having a difference in the SAR ADC, etc. Further, in the above embodiments, the analog-to-digital converter with built-in self-detection function of the present application is described based on a SAR ADC based on a redundant-cap-array. However, the present application is not limited thereto, and the technical solution of the present application can also be used for defect detection of other types of SAR ADCs based on redundant coding design, such as a SAR ADC based on a redundant-mixed-C / R, etc.

[0120] According to another aspect of the present application, a method for detecting defects in a SAR ADC is provided.

[0121] Reference is made to Figure 12 , which shows a flowchart of a method 1200 for detecting defects in a SAR ADC according to an embodiment of the present application. The SAR ADC is designed based on a redundancy coding and is configured to convert an input voltage V in into an output digital code D out , where the input voltage V in can be quantized into a value in a range of 0 to M-1, and the output digital code D out can be represented by a K-bit binary number, M and K are both positive integers, and 2 K >M. For example, the method 1200 can be performed by a test circuit 200 as shown in Figure 1 to test the SAR ADC 100.

[0122] As shown in Figure 13 , in step S1210, a defect-sensitive input quantity is input into the SAR ADC, where the defect-sensitive input quantity can be represented by a plurality of K-bit binary numbers. Then, in step S1220, the SAR ADC is controlled to perform analog-digital conversion on the defect-sensitive input quantity. Referring to Figure 13 , step S1220 can include three sub-steps S1222, S1224 and S1226, where in sub-step S1222, the k-th bit of the K-bit binary number output by the SAR ADC is set to a fixed value, where 1≤k≤K; in sub-step S1224, the SAR ADC is controlled to perform successive approximation conversion on the defect-sensitive input quantity to determine the values of the bits of the K-bit binary number other than the k-th bit, thereby generating an output digital code D out (k); and in sub-step S1226, the value of k is changed in a range of 1 to K, for example, k is sequentially equal to K, K-1, …, 1, and steps a and b are repeatedly performed until K output digital codes D out (k) are generated. Thereafter, in step S1230, it is determined whether the SAR ADC has defects based on the K output digital codes D out (k).

[0123] In some embodiments, setting the k-th bit of the K-bit binary number output by the SAR ADC to a fixed value in sub-step S1222 includes setting the k-th bit of the K-bit binary number output by the SAR ADC to 0 or 1.

[0124] In some embodiments, setting the kth bit of the K-bit binary number output by the SAR ADC to 0 or 1 in sub-step 1222 includes: generating a rewrite signal for setting the kth bit of the K-bit binary number to a fixed value based on a set trigger signal, a polarity signal, and an initial control value, wherein the set trigger signal indicates that the kth bit of the K-bit binary number is to be reset, the polarity signal indicates that the fixed value is 0 or 1, and the initial control value indicates an initial value of the kth bit of the codeword provided by a successive approximation logic circuit of the SAR ADC; and setting the kth bit of the K-bit binary number output by the SAR ADC to 0 or 1 based on the rewrite signal.

[0125] In some embodiments, the most significant bit of the K-bit binary number corresponds to k=K, the least significant bit of the K-bit binary number corresponds to k=1, and changing the value of k within the range of 1 to K in sub-step 1225 includes: decreasing the value of k from K to 1 one by one.

[0126] In some embodiments, the method 1200 further includes: storing the K output digital codes D out (k).

[0127] In some embodiments, in step S1230, based on the K output digital codes D out (k) Determining whether the SAR ADC is defective includes: out The difference between the maximum and minimum values ​​in (k) is compared with a predefined threshold ε; when the difference is less than the predefined threshold ε, it is determined that the SAR ADC is not defective; and when the difference is greater than or equal to the predefined threshold ε, it is determined that the SAR ADC is defective.

[0128] In some embodiments, the number of defect-sensitive input quantities is multiple, and the method 1200 further includes: sequentially inputting the multiple defect-sensitive input quantities into the SAR ADC; performing the operations of steps a to c above on each defect-sensitive input quantity and obtaining corresponding K output digital codes D out (k); and K output digital codes D corresponding to each defect-sensitive input quantity out (k) Determine whether the SAR ADC is defective.

[0129] In some embodiments, the method 1200 further includes: determining the defect type of the SAR ADC based on the K output digital codes Dout(k).

[0130] The above detection method 1200 can be performed by, for example Figure 1 The test circuit 200 shown executes the method 1200 . Therefore, for more details about the method 1200 , reference can be made to the above description of the test circuit 200 , which will not be repeated here.

[0131] According to yet another aspect of the present application, a test circuit for detecting defects in a SAR ADC is provided.

[0132] refer to ​ , which shows a logic block diagram of a test circuit 1300 for detecting defects in a SAR ADC according to an embodiment of the present application. The SAR ADC is based on a redundant coding design and is configured to convert an input voltage V in Converted into output digital code D out , where the input voltage V in Can be quantized into a value in the range of 0 to M-1, and output digital code D out can be represented by a K-bit binary number, M and K are both positive integers, and 2 K >M.

[0133] like ​ As shown, the test circuit 1300 includes an input unit 1310, a conversion control unit 1320, and a judgment unit 1330. The input unit 1310 is configured to input a defect-sensitive input quantity into the SAR ADC, where the defect-sensitive input quantity can be represented by multiple K-bit binary numbers. The conversion control unit 1320 is configured to control the SAR ADC to perform analog-to-digital conversion on the defect-sensitive input quantity, wherein the control comprises: step a: setting the k-th bit of the K-bit binary number output by the SAR ADC to a fixed value, where 1≤k≤K; step b: controlling the SAR ADC to perform successive approximation conversion on the defect-sensitive input quantity to determine the values ​​of the other bits of the K-bit binary number except the k-th bit, thereby generating an output digital code D out (k); and step c: changing the value of k in the range of 1 to K, and repeating steps a and b until K corresponding output digital codes D are generated out (k). The judgment unit 1330 is configured to output the digital code D based on the K out (k) Determine whether the SAR ADC is defective.

[0134] The test circuit 1300 and ​ The test circuit 1300 is similar to the test circuit 200 shown in the figure, except that the test circuit 1300 is not integrated into the analog-to-digital converter but can be used independently, thereby being able to test different SAR ADCs. For more details about the test circuit 1300, please refer to the description of the test circuit 200 above and will not be repeated here.

[0135] It should be noted that the apparatus or circuit embodiments described above are merely illustrative, and that the division into units is merely a logical function division, and in actual implementation, another division manner can be adopted, for example, a plurality of units or components can be combined or integrated into another system, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be realized through a specific interface, and the indirect coupling or communication connection between the units can be electrical or other forms. The units described as separate components can be or can not be physically separated, and the components shown as units can be or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment. In addition, the steps of the method described above can be omitted or added according to needs, and in addition, a plurality of steps can be executed simultaneously or sequentially, and when a plurality of different steps are executed sequentially, the execution order can also be different in different embodiments.

[0136] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit. When the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions to make a computer device (which can be a personal computer, a mobile terminal, a server or a network device, etc.) execute all or part of the steps of the methods described in each embodiment of the present application.

[0137] Other changes to the disclosed embodiments can be understood and effected by a person of ordinary skill in the art in the technical field of the technology, upon studying the specification, the disclosure and the appended drawings and claims. In the claims, the word "comprising" does not exclude other elements and steps, and the words "a" or "an" do not exclude a plurality. In the practical application of the present application, one part can perform the functions of a plurality of technical features referred to in the claims. Any reference signs in the claims should not be understood as limiting the scope.< / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / k>

Claims

1. An analog-to-digital converter with a built-in self-detection function, characterized in that: The analog-to-digital converter comprises: Successive approximation analog-to-digital conversion circuit based on redundant coding design; an input unit configured to input a defect-sensitive input quantity into the successive approximation analog-to-digital conversion circuit, wherein the defect-sensitive input quantity is an input voltage that can be correctly represented by a plurality of K-bit binary numbers after conversion by the successive approximation analog-to-digital conversion circuit, where K is a positive integer; A conversion control unit is configured to control the successive approximation analog-to-digital conversion circuit to perform analog-to-digital conversion on the defect-sensitive input quantity, wherein the control includes: Step a: setting the kth bit of the K-bit binary number output by the successive approximation analog-to-digital conversion circuit to a fixed value; Step b: Control the successive approximation analog-to-digital conversion circuit to perform successive approximation conversion on the defect-sensitive input quantity to determine the values ​​of the other bits in the K-bit binary number except the k-th bit, thereby generating an output digital code D out (k); and Step c: Change the value of k in the range of 1 to K, and repeat steps a and b until K corresponding output digital codes D are generated. out (k); and A judgment unit configured to output digital codes D based on the K out (k) Determining whether the successive approximation analog-to-digital conversion circuit has a defect.

2. The analog-to-digital converter according to claim 1, wherein: The quantization interval of the input voltage converted by the successive approximation analog-to-digital conversion circuit is 0 to (M-1), where M is a positive integer greater than 1, and M<2 K .

3. The analog-to-digital converter according to claim 1, wherein: The fixed value is 0 or 1.

4. The analog-to-digital converter according to claim 3, wherein: The conversion control unit includes a setting circuit, which generates a rewrite signal for setting the kth bit of the K-bit binary number to a fixed value based on a setting trigger signal, a polarity signal and an initial control value, wherein the setting trigger signal indicates that the kth bit of the K-bit binary number is reset, the polarity signal indicates that the fixed value is 0 or 1, and the initial control value indicates the initial value of the kth bit of the codeword provided by the successive approximation logic circuit in the successive approximation analog-to-digital conversion circuit.

5. The analog-to-digital converter according to claim 1, wherein: The most significant bit of the K-bit binary number corresponds to k=K, the least significant bit of the K-bit binary number corresponds to k=1, and the conversion control unit is configured to decrease the value of k from K to 1 one by one.

6. The analog-to-digital converter according to claim 1, wherein: The judgment unit further includes a storage module, which is configured to store the K output digital codes D out (k).

7. The analog-to-digital converter according to claim 6, wherein: The determining unit is further configured to: The K output digital codes D out The difference between the maximum and minimum values ​​in (k) is compared with a predefined threshold ε; When the difference is less than the predefined threshold ε, it is determined that the successive approximation analog-to-digital conversion circuit has no defects; as well as When the difference is greater than or equal to the predefined threshold ε, it is determined that the successive approximation analog-to-digital conversion circuit has a defect.

8. The analog-to-digital converter according to claim 1, wherein: There are multiple defect-sensitive input quantities, and the input unit is configured to sequentially input the multiple defect-sensitive input quantities into the successive approximation analog-to-digital conversion circuit, and the conversion control unit is configured to perform the operations of steps a to c on each defect-sensitive input quantity and obtain corresponding K output digital codes D out (k), the judgment unit is configured to output K digital codes D corresponding to each defect sensitive input quantity out (k) Determining whether the successive approximation analog-to-digital conversion circuit has a defect.

9. The analog-to-digital converter according to claim 1, wherein: The judgment unit is further configured to output the K digital codes D based on the out (k) Determining the defect type of the successive approximation analog-to-digital conversion circuit.

10. The analog-to-digital converter according to claim 1, wherein: The successive approximation analog-to-digital conversion circuit includes a redundant capacitor array.

11. A method for detecting defects in an analog-to-digital conversion circuit, characterized in that: The method comprises: Inputting a defect-sensitive input quantity into a successive approximation analog-to-digital conversion circuit based on redundant coding design, wherein the defect-sensitive input quantity is an input voltage that can be correctly represented by a plurality of K-bit binary numbers after conversion by the successive approximation analog-to-digital conversion circuit; Controlling the successive approximation analog-to-digital conversion circuit to perform analog-to-digital conversion on the defect-sensitive input quantity, the controlling comprising: Step a: setting the kth bit of the K-bit binary number output by the successive approximation analog-to-digital conversion circuit to a fixed value; Step b: Control the successive approximation analog-to-digital conversion circuit to perform successive approximation conversion on the defect-sensitive input quantity to determine the values ​​of the other bits in the K-bit binary number except the k-th bit, thereby generating an output digital code D out (k); and Step c: Change the value of k in the range of 1 to K, and repeat steps a and b until K corresponding output digital codes D are generated. out (k); and Based on the K output digital codes D out (k) Determining whether the successive approximation analog-to-digital conversion circuit has a defect.

12. The method according to claim 11, characterized in that The quantization interval of the input voltage converted by the successive approximation analog-to-digital conversion circuit is 0 to (M-1), where M is a positive integer greater than 1, and M<2 K .

13. The method according to claim 11, characterized in that Setting the kth bit of the K-bit binary number output by the successive approximation analog-to-digital conversion circuit to a fixed value includes: setting the kth bit of the K-bit binary number output by the successive approximation analog-to-digital conversion circuit to 0 or 1.

14. The method according to claim 13, characterized in that Setting the kth bit of the K-bit binary number output by the successive approximation analog-to-digital conversion circuit to 0 or 1 comprises: generating a rewrite signal for setting the kth bit of the K-bit binary number to a fixed value based on a setting trigger signal, a polarity signal, and an initial control value, wherein the setting trigger signal indicates that the kth bit of the K-bit binary number is to be reset, the polarity signal indicates that the fixed value is 0 or 1, and the initial control value indicates an initial value of the kth bit of a codeword provided by a successive approximation logic circuit of the successive approximation analog-to-digital conversion circuit; and The k-th bit of the K-bit binary number output by the successive approximation analog-to-digital conversion circuit is set to 0 or 1 based on the rewrite signal.

15. The method according to claim 11, characterized in that The most significant bit of the K-bit binary number corresponds to k=K, the least significant bit of the K-bit binary number corresponds to k=1, and changing the value of k within the range of 1 to K includes: decreasing the value of k from K to 1 one by one.

16. The method according to claim 11, characterized in that The method further comprises: Store the K output digital codes D out (k).

17. The method according to claim 16, characterized in that Based on the K output digital codes D out (k) Determining whether the successive approximation analog-to-digital conversion circuit has a defect includes: The K output digital codes D out The difference between the maximum and minimum values ​​in (k) is compared with a predefined threshold ε; When the difference is less than the predefined threshold ε, it is determined that the successive approximation analog-to-digital conversion circuit has no defects; and When the difference is greater than or equal to the predefined threshold ε, it is determined that the successive approximation analog-to-digital conversion circuit has a defect.

18. The method according to claim 11, characterized in that There are multiple defect-sensitive input quantities, and the method further includes: inputting the plurality of defect-sensitive input quantities into the successive approximation analog-to-digital conversion circuit in sequence; Perform the operations from step a to step c for each defect-sensitive input and obtain the corresponding K output digital codes D out (k); and Based on the K output digital codes D corresponding to each defect sensitive input out (k) Determining whether the successive approximation analog-to-digital conversion circuit has a defect.

19. The method according to claim 11, wherein The method further comprises: Based on the K output digital codes D out (k) Determining the defect type of the successive approximation analog-to-digital conversion circuit.

20. A test circuit for detecting defects in an analog-to-digital conversion circuit, characterized in that: The test circuit comprises: an input unit configured to input a defect-sensitive input quantity into a successive approximation analog-to-digital conversion circuit based on a redundant coding design, wherein the defect-sensitive input quantity is an input voltage that can be correctly represented by a plurality of K-bit binary numbers after conversion by the successive approximation analog-to-digital conversion circuit, where K is a positive integer; A conversion control unit is configured to control the successive approximation analog-to-digital conversion circuit to perform analog-to-digital conversion on the defect-sensitive input quantity, wherein the control includes: Step a: setting the kth bit of the K-bit binary number output by the successive approximation analog-to-digital conversion circuit to a fixed value; Step b: Control the successive approximation analog-to-digital conversion circuit to perform successive approximation conversion on the defect-sensitive input quantity to determine the values ​​of the other bits in the K-bit binary number except the k-th bit, thereby generating an output digital code D out (k); and Step c: Change the value of k in the range of 1 to K, and repeat steps a and b until K corresponding output digital codes D are generated. out (k); and A judgment unit configured to output digital codes D based on the K out (k) Determining whether the successive approximation analog-to-digital conversion circuit has a defect.

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