Test structure and method for forming the same

Abstract

A test structure and a method for forming the same, wherein the test structure comprises: a substrate; a first device under test (DUT) located on the substrate, the first DUT having a first length dimension; a plurality of test keys located on the substrate, adjacent test keys having a first spacing dimension, the first length dimension being greater than the first spacing dimension; the first DUT being disposed between two test keys arranged at intervals; and the projections of the first DUT and the two test keys arranged at intervals onto the substrate having no overlapping area. Placing the larger first DUT between two test keys with a larger spacing dimension not only avoids intersection and short circuit between the first DUT and the electrically connected test keys, but also avoids placing the first DUT above or below the test keys, thereby increasing the overall longitudinal size of the test structure, and avoids placing the test structure inside a chip, thereby reducing the chip's integration level.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a test structure and a forming method thereof. Background Art

[0002] In the field of semiconductor manufacturing, with the development of technology, the size of semiconductor devices is getting smaller and smaller, while the complexity is getting higher and higher. In order to monitor the manufacturing process of semiconductor devices and ensure the reliability of semiconductor devices, it is common practice to form a test structure (test key) in the semiconductor device for testing and simulation of some key parameters of the semiconductor device to ensure the quality of the semiconductor device before leaving the factory.

[0003] The test structure is typically manufactured in the same semiconductor process as the semiconductor devices on the wafer, and the test structure and semiconductor devices have a mutual correspondence. Each layer of interconnect lines in the semiconductor device corresponds to a test line located on the same layer in the test structure, and each plug in the semiconductor device corresponds to a test plug located on the same layer in the test structure. Because the test structure and semiconductor devices are manufactured in the same process and have a mutual correspondence, the performance of the semiconductor devices on the wafer can be obtained by testing the performance of the test structure. Using the test structure to reflect the performance of the semiconductor devices on the wafer avoids damage to the semiconductor devices on the wafer.

[0004] However, the test structure in the prior art still has many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a test structure and a forming method thereof, so as to avoid forming the test structure inside a chip and thus reducing the integration of the chip.

[0006] To solve the above problems, the present invention provides a test structure, comprising: a substrate; a first device to be tested located on the substrate, the first device to be tested having a first length dimension along a first direction, the first direction being parallel to the top surface of the substrate; a plurality of test keys located on the substrate and arranged in sequence along the first direction, adjacent test keys having a first spacing dimension, the first length dimension being greater than the first spacing dimension; the first device to be tested is arranged between two test keys arranged at intervals, there is at least one test key between the two test keys arranged at intervals, the two test keys arranged at intervals have a second spacing dimension between them, and the second spacing dimension is greater than the first length dimension; the first device to be tested is electrically connected to the two test keys arranged at intervals, respectively; the first device to be tested and the two test keys arranged at intervals have no overlapping area in their projections toward the substrate.

[0007] Optionally, the test key includes: several first metal wiring layers arranged in sequence along the second direction, adjacent first metal wiring layers are electrically connected, and several layers of the first metal wiring layers have the same projection area toward the substrate, and the second direction is perpendicular to the top surface of the substrate.

[0008] Optionally, each of the first metal wiring layers has a plurality of anti-sag openings arranged in parallel.

[0009] Optionally, the anti-sag openings in adjacent first metal wiring layers are perpendicular to each other.

[0010] Optionally, the first device under test has a plurality of second metal wiring layers sequentially arranged along the second direction, and each second metal wiring layer is in the same layer as the corresponding first metal wiring layer in the test key.

[0011] Optionally, when the second metal wiring layer in the first device under test and the test key between the two test keys arranged at intervals have an overlapping area in the projection toward the substrate, the test key between the two test keys does not have the first metal wiring layer that is in the same layer as the second metal wiring layer.

[0012] Optionally, the first device under test does not have a second metal wiring layer in the same layer as the first metal wiring layer.

[0013] Optionally, there is a third spacing dimension between the first device under test and the electrically connected test key; the test structure also includes: a second device under test located on the substrate, the second device under test has a second length dimension along the first direction, and the second length dimension is smaller than the third spacing dimension; the second device under test can be arranged between any adjacent test keys; the second device under test is electrically connected to the adjacent test keys respectively; the second device under test and the adjacent test keys have no overlapping area in their projections toward the substrate.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a test structure, including: providing a substrate; forming a first device to be tested on the substrate, the first device to be tested having a first length dimension along a first direction, and the first direction is parallel to the top surface of the substrate; forming a plurality of test keys arranged in sequence along the first direction on the substrate, with a first spacing dimension between adjacent test keys, and the first length dimension being greater than the first spacing dimension; arranging the first device to be tested between two test keys arranged at intervals, with at least one test key between the two test keys arranged at intervals, and with a second spacing dimension between the two test keys arranged at intervals, and the second spacing dimension being greater than the first length dimension; electrically connecting the first device to be tested to the two test keys arranged at intervals, respectively; and arranging the first device to be tested so that it has no overlapping area with the two test keys arranged at intervals in projection toward the substrate.

[0015] Optionally, the test key includes: several first metal wiring layers arranged in sequence along the second direction, adjacent first metal wiring layers are electrically connected, and several layers of the first metal wiring layers have the same projection area toward the substrate, and the second direction is perpendicular to the top surface of the substrate.

[0016] Optionally, each of the first metal wiring layers has a plurality of anti-sag openings arranged in parallel.

[0017] Optionally, the anti-sag openings in adjacent first metal wiring layers are perpendicular to each other.

[0018] Optionally, the first device under test has a plurality of second metal wiring layers sequentially arranged along the second direction, and each second metal wiring layer is in the same layer as the corresponding first metal wiring layer in the test key.

[0019] Optionally, when the second metal wiring layer in the first device under test and the test key between the two test keys arranged at intervals have an overlapping area in the projection toward the substrate, the first metal wiring layer in the test key between the two test keys that is in the same layer as the second metal wiring layer is not formed.

[0020] Optionally, the first device under test does not have a second metal wiring layer in the same layer as the first metal wiring layer.

[0021] Optionally, a third spacing dimension is provided between the first device under test and the electrically connected test key; and the method further includes: forming a second device under test on the substrate, the second device under test having a second length dimension along the first direction, the second length dimension being smaller than the third spacing dimension; arranging the second device under test between any adjacent test keys; electrically connecting the second device under test to the adjacent test keys respectively; and arranging the second device under test so as to have no overlapping area with the adjacent test keys in their projections toward the substrate.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the test structure of the present invention, a large first DUT is positioned between two test keys with a larger spacing, and the projections of the first DUT and the two spaced test keys toward the substrate do not overlap. This not only prevents the first DUT from intersecting with the electrically connected test keys, thereby preventing a short circuit, but also prevents the first DUT from being positioned above or below the test keys, thereby increasing the overall longitudinal size of the test structure. This allows the test structure to be positioned between the scribe lines between chips, avoiding placement within the chip itself, which would reduce the chip's integration.

[0024] Furthermore, each first metal wiring layer has a plurality of parallel anti-sag openings. The anti-sag openings can prevent the problem of a middle region of the first metal wiring layer from being sagged during the planarization process, thereby improving the electrical contact of the first metal wiring layer.

[0025] Furthermore, the anti-sag openings in adjacent first metal wiring layers are perpendicular to each other. By arranging the anti-sag openings in adjacent layers vertically, the overall structure of the test key is more evenly distributed, thereby improving the conductive performance of the test key.

[0026] Furthermore, when the second metal wiring layer in the first device under test overlaps with the test key between the two test keys arranged at intervals as projected toward the substrate, the test key between the two test keys does not have a first metal wiring layer on the same layer as the second metal wiring layer. This prevents the test key between the two test keys from shorting the first device under test and thereby affecting test accuracy.

[0027] Furthermore, there is a third spacing dimension between the first device under test and the electrically connected test key; the test structure also includes: a second device under test located on the substrate, the second device under test having a second length dimension along the first direction, the second length dimension being smaller than the third spacing dimension; the second device under test can be arranged between any adjacent test keys; the second device under test is electrically connected to the adjacent test keys respectively; the second device under test and the adjacent test keys do not have an overlapping area when projected toward the substrate. Since the second length dimension is smaller than the third spacing dimension, there is sufficient space to place a small-sized second device under test so that it does not intersect with the first device under test and thereby affect the first device under test. Therefore, the small-sized second device under test can be arranged between any adjacent test keys, so that the test keys that have been used in testing the first device under test and the test keys located between two test keys arranged at intervals can still be used, thereby increasing the number of devices under test in the test structure and improving test efficiency.

[0028] In the method for forming a test structure according to the technical solution of the present invention, a large-sized first device under test is positioned between two test keys with a larger spacing, and the first device under test and the two spaced-apart test keys do not overlap when projected onto the substrate. This not only prevents the first device under test from intersecting with the electrically connected test keys and causing a short circuit, but also avoids placing the first device under test above or below the test keys, thereby increasing the overall longitudinal size of the test structure. This allows the test structure to be positioned between the scribe lines between chips, avoiding placing the test structure inside the chip, which would reduce the chip's integration density.

[0029] Furthermore, each first metal wiring layer has a plurality of parallel anti-sag openings. The anti-sag openings can prevent the problem of a middle region of the first metal wiring layer from being sagged during the planarization process, thereby improving the electrical contact of the first metal wiring layer.

[0030] Furthermore, the anti-sag openings in adjacent first metal wiring layers are perpendicular to each other. By arranging the anti-sag openings in adjacent layers vertically, the overall structure of the test key is more evenly distributed, thereby improving the conductive performance of the test key.

[0031] Furthermore, when the second metal wiring layer in the first device under test overlaps with the test key between the two test keys arranged at intervals when projected toward the substrate, the first metal wiring layer in the test key between the two test keys that is co-located with the second metal wiring layer is not formed. This prevents the test key between the two test keys from shorting the first device under test, thereby affecting test accuracy.

[0032] Furthermore, a third spacing dimension is provided between the first device under test and the electrically connected test key; the method further includes: forming a second device under test on the substrate, the second device under test having a second length dimension along the first direction, the second length dimension being smaller than the third spacing dimension; arranging the second device under test between any adjacent test keys; electrically connecting the second device under test to the adjacent test keys respectively; and arranging the second device under test so that its projections toward the substrate do not overlap with those of the adjacent test keys. Because the second length dimension is smaller than the third spacing dimension, there is sufficient space to place a small-sized second device under test so that it does not intersect with the first device under test and thereby affect the first device under test. Therefore, the small-sized second device under test can be placed between any adjacent test keys, allowing the test keys already used in testing the first device under test and the test keys located between two spaced test keys to still be used, thereby increasing the number of devices under test in the test structure and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of a structure in which the length dimension of the test structure exceeds the chip dimension;

[0034] Figure 2 It is a schematic diagram of the structure where the metal connection of the device under test intersects with the metal connection of the same layer in the test key;

[0035] Figure 3 It is a schematic diagram of the structure in which the device under test is placed on the upper side or lower side of the test key;

[0036] Figure 4 It is a structural schematic diagram in which the overall longitudinal dimension of the test structure exceeds the accommodation range of the scribe line;

[0037] Figure 5 is a schematic structural diagram of a test structure in an embodiment of the present invention;

[0038] Figure 6 is a schematic structural diagram of a test key in an embodiment of the present invention;

[0039] Figure 7 yes Figure 6 Schematic diagram of the cross section along line AA;

[0040] Figure 8 is a schematic structural diagram of adjacent first metal wiring layers in a test key in an embodiment of the present invention;

[0041] Figure 9 is a schematic structural diagram of a first device under test in an embodiment of the present invention;

[0042] Figure 10 yes Figure 9 Schematic diagram of the central structure. DETAILED DESCRIPTION

[0043] As mentioned in the background technology, there are still many problems with the test structure in the prior art. The following will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 It is a schematic diagram of a structure in which the length dimension of the test structure exceeds the chip dimension; Figure 2 It is a schematic diagram of the structure where the metal connection of the device under test intersects with the metal connection of the same layer in the test key; Figure 3 It is a schematic diagram of the structure in which the device under test is placed on the upper side or lower side of the test key; Figure 4 It is a structural schematic diagram showing that the overall longitudinal dimension of the test structure exceeds the accommodation range of the scribe groove.

[0045] There are two locations for test structures (Testkey TSK) to be placed on the wafer: one is inside the chip, and the other is in the scribe line between chips. If the length of a test structure 100 reaches 2500μm or more, it will far exceed the size of the chip 101 of some products. In this case, the test structure can only be placed in the scribe line 102 (such as Figure 1 shown).

[0046] As the wafer size increases, in order to obtain more effective chips 101, the size of the scribe groove 102 is gradually compressed. For some test structures 100, the device under test 1001 will exceed the spacing between two adjacent test keys 1002 (PAD) in the test structure due to the particularity of the critical size, and the cost of replacing the probe card is relatively high. The current practice is to place the device under test 1001 on the upper or lower side of the test key 1002. This is because some devices under test 1001 themselves require a large number of first metal connections 1001c. For example, if the device under test is used to test the capacitance of the overlapping portion between the gate 1001a and the source and drain 1001b, if such a device under test 1001 is forcibly placed between two test keys 1002, the very densely distributed first metal connections of the device under test 1001 will intersect with the second metal connections 1002a of the same layer in the test key 1002 (such as Figure 2 As shown), the source and drain electrodes 1001b and the gate electrode 1001a that were originally connected separately will be short-circuited, causing the test structure 100 to be scrapped. Therefore, the device under test 1001 needs to be placed on the upper side or lower side of the test key 1002 (as shown). Figure 3 shown).

[0047] However, placing the device under test 1001 on the upper side or the lower side of the test key 1002 makes the overall size of the test structure 100 in the longitudinal direction larger (e.g., Figure 4As shown in FIG, if the size exceeds the accommodation range of the scribe groove 102, it can only be considered to be placed inside the chip 101, which will reduce the integration of the chip.

[0048] On this basis, the present invention provides a test structure and a method for forming the same, in which a large-sized first device under test is placed between two test keys with a larger spacing, and the first device under test and the two spaced test keys do not overlap when projected toward the substrate. This not only avoids the first device under test from intersecting with the electrically connected test keys and causing a short circuit, but also avoids placing the first device under test above or below the test keys, thereby increasing the overall longitudinal size of the test structure. This allows the test structure to still be placed between the scribe grooves between chips, avoiding placing the test structure inside the chip, which would reduce the chip's integration.

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] Figure 5 is a schematic structural diagram of a test structure in an embodiment of the present invention; Figure 6 is a schematic structural diagram of a test key in an embodiment of the present invention; Figure 7 yes Figure 6 Schematic diagram of the cross section along line AA; Figure 8 is a schematic structural diagram of adjacent first metal wiring layers in a test key in an embodiment of the present invention; Figure 9 is a schematic structural diagram of a first device under test in an embodiment of the present invention; Figure 10 yes Figure 9 Schematic diagram of the central structure.

[0051] Please refer to Figure 5 A test structure includes: a substrate 200; a first device under test 201 located on the substrate 200, the first device under test 201 having a first length dimension L1 along a first direction X, the first direction X being parallel to the top surface of the substrate 200; a plurality of test keys 202 located on the substrate 200 and arranged in sequence along the first direction X, a first spacing dimension S1 being defined between adjacent test keys 202, and the first length dimension L1 being greater than the first spacing dimension S1; the first device under test 201 being disposed between two test keys 202 arranged at intervals, at least one test key 202 being located between the two test keys 202 arranged at intervals, a second spacing dimension S2 being defined between the two test keys 202 arranged at intervals, and the second spacing dimension S2 being greater than the first length dimension L1; the first device under test 201 being electrically connected to the two test keys 202 arranged at intervals, respectively; and the first device under test 201 and the two test keys 202 arranged at intervals having no overlapping area when projected toward the substrate 200.

[0052] A large first DUT 201 is placed between two test keys 202 with a larger spacing, and the projections of the first DUT 201 and the two spaced test keys 202 toward the substrate 200 do not overlap. This prevents the first DUT 201 from intersecting with the electrically connected test keys 202, which could cause a short circuit. It also prevents the first DUT 201 from being placed above or below the test keys 202, thereby increasing the overall longitudinal size of the test structure. This allows the test structure to be placed between the scribe lines between chips (not shown), avoiding placement inside the chip, which could reduce the chip's integration.

[0053] In this embodiment, the substrate 200 is made of silicon.

[0054] In other embodiments, the material of the substrate 200 may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0055] It should be noted that the number of the test keys 202 arranged in sequence along the first direction X is usually set to 22 or 24, which is mainly determined by the number of pin cards. The pin cards of different electrical test machine manufacturers are different.

[0056] Please continue to refer to Figure 5 In this embodiment, taking three test keys 202 as an example, namely, test keys 202 (A1, A2, and A3), the first length dimension L1 of the first device under test 201 is greater than the first spacing dimension S1 between test keys 202 (A1) and 202 (A2), but less than the second spacing dimension S2 between the test keys 202 (A1) and 202 (A3), which are arranged at intervals. Therefore, the first device under test 201 is positioned between test keys 202 (A1) and 202 (A3), and its projections onto the substrate 200 do not overlap with those of the test keys 202 (A1) and 202 (A3). However, the projections onto the substrate 200 of the first device under test 201 and the test key 202 (A2) do overlap.

[0057] Please refer to Figure 6 and Figure 7 In this embodiment, the test key 202 includes: a plurality of first metal wiring layers 2021 arranged in sequence along the second direction Y, adjacent first metal wiring layers 2021 are electrically connected, and the projection areas of the plurality of first metal wiring layers 2021 toward the substrate 200 are the same, and the second direction Y is perpendicular to the top surface of the substrate 200.

[0058] Please continue to refer to Figure 6In this embodiment, each first metal wiring layer 2021 has a plurality of parallel anti-sag openings 2022. The anti-sag openings 2022 prevent the occurrence of a sag in the middle region of the first metal wiring layer 2021 during the planarization process, thereby improving the electrical contact of the first metal wiring layer 2021.

[0059] Please refer to Figure 8 In this embodiment, the anti-sag openings 2022 in adjacent first metal wiring layers 2021 are perpendicular to each other. By arranging the anti-sag openings 2022 in adjacent layers vertically, the overall structure of the test key 202 is more evenly distributed, thereby improving the conductive performance of the test key 202.

[0060] Please refer to Figure 9 and Figure 10 In this embodiment, the first device under test 201 has a plurality of second metal wiring layers 2011 arranged in sequence along the second direction Y, and each second metal wiring layer 2011 is in the same layer as the corresponding first metal wiring layer 2021 in the test key 202.

[0061] Please continue to refer to Figure 9 and Figure 10 In one specific embodiment, the first device under test 201 is used to test the capacitance of the overlapping portion between the gate 2012 and the source / drain 2013. The second metal wiring layer 2011 is divided into two parts: one for individually electrically connecting all gates 2012, and the other for individually electrically connecting all source / drain 2013. The two parts must not short-circuit. In this embodiment, only one second metal wiring layer 2011 is required, and it is located on the same layer as the first metal wiring layer 2021, the bottommost layer of the test key 202.

[0062] In this embodiment, when the second metal wiring layer 2011 in the first device under test 201 overlaps with a test key 202 between two test keys 202 arranged at intervals when projected toward the substrate 200, the test key 202 between the two test keys 202 does not have a first metal wiring layer 2021 on the same layer as the second metal wiring layer 2011. This prevents the test key 202 between the two test keys 202 from short-circuiting the first device under test 201, thereby affecting test accuracy.

[0063] Continuing with the above-mentioned specific embodiment, the first device under test 201 and the test key 202 (A2) have an overlapping area in their projections toward the substrate 200, and the first device under test 201 also has a second metal wiring layer 2011. At this time, in order to avoid the test key 202 (A2) located in the bottom first metal wiring layer 2021 causing a short circuit to the first device under test 201, it is necessary to remove the test key 202 (A2) located in the bottom first metal wiring layer 2021, that is, the test key 202 (A2) located in the bottom first metal wiring layer 2021 is not formed during the manufacturing process.

[0064] In other embodiments, if the first device under test is electrically connected to the test keys (A1) and the test keys (A4) arranged at intervals, respectively, the first device under test and the test keys (A2) and the test keys (A3) have overlapping areas in their projections toward the substrate, and the corresponding test keys (A2) and the test keys (A3) need to omit the production of the first metal wiring layer located at the bottom layer.

[0065] In other embodiments, if the first device under test has three second metal wiring layers arranged along the second direction, the corresponding test key (A2) needs to omit the three first metal wiring layers located at the bottom layer.

[0066] In other embodiments, the first device under test may not have a second metal wiring layer in the same layer as the first metal wiring layer. In this case, the test key (A2) does not need to be fabricated in the first metal wiring layer at the bottom layer.

[0067] Please continue to refer to Figure 5 , there is a third spacing dimension S3 between the first device under test 201 and the electrically connected test key 202; the test structure also includes: a second device under test 203 located on the substrate 200, the second device under test 203 has a second length dimension L2 along the first direction X, and the second length dimension L2 is smaller than the third spacing dimension S3; the second device under test 203 can be arranged between any adjacent test keys 202; the second device under test 203 is electrically connected to the adjacent test keys 202 respectively; the second device under test 203 and the adjacent test keys 202 have no overlapping area when projected toward the substrate 200.

[0068] Because the second length dimension L2 is smaller than the third spacing dimension S3, there is sufficient space to accommodate a small-sized second DUT 203 without intersecting with the first DUT 201 (i.e., shorting the first DUT 201) and thereby affecting the first DUT 201. Therefore, the small-sized second DUT 203 can be placed between any adjacent test keys 202, allowing test keys 202 already used in testing the first DUT 201 and test keys 202 located between two spaced test keys 202 to remain usable. This increases the number of DUTs in the test structure and improves testing efficiency.

[0069] Please continue to refer to Figure 5 Continuing with the above specific embodiment, the second device under test 203 can be set between the test key 202 (A2) and the test key 202 (A3), and electrically connected to the test key 202 (A2) and the test key 202 (A3) respectively.

[0070] Accordingly, a method for forming a test structure is also provided in an embodiment of the present invention, please continue to refer to Figure 5 , including: providing a substrate 200; forming a first device under test 201 on the substrate 200, the first device under test 201 having a first length dimension L1 along a first direction X, and the first direction X being parallel to the top surface of the substrate 200; forming a plurality of test keys 202 arranged in sequence along the first direction X on the substrate 200, with a first spacing dimension S1 between adjacent test keys 202, and the first length dimension L1 being greater than the first spacing dimension S1; arranging the first device under test 201 between two test keys 202 arranged at intervals, with at least one test key 202 between the two test keys 202 arranged at intervals, and a second spacing dimension S2 between the two test keys 202 arranged at intervals, and the second spacing dimension S2 being greater than the first length dimension L1; electrically connecting the first device under test 201 to the two test keys 202 arranged at intervals respectively; arranging the first device under test 201 so that there is no overlapping area with the two test keys 202 arranged at intervals when projected toward the substrate 200.

[0071] A large first DUT 201 is placed between two test keys 202 with a larger spacing, and the projections of the first DUT 201 and the two spaced test keys 202 toward the substrate 200 do not overlap. This not only prevents the first DUT 201 from intersecting with the electrically connected test keys 202, which could cause a short circuit, but also prevents the first DUT 201 from being placed above or below the test keys 202, thereby increasing the overall longitudinal size of the test structure. This allows the test structure to be placed between the scribe lines between chips, avoiding placement inside the chip, which could reduce the chip's integration density.

[0072] Please continue to refer to Figure 6 and Figure 7 In this embodiment, the test key 202 includes: a plurality of first metal wiring layers 2021 arranged in sequence along the second direction Y, adjacent first metal wiring layers 2021 are electrically connected, and the projection areas of the plurality of first metal wiring layers 2021 toward the substrate 200 are the same, and the second direction Y is perpendicular to the top surface of the substrate 200.

[0073] Please continue to refer to Figure 6 In this embodiment, each first metal wiring layer 2021 has a plurality of parallel anti-sag openings 2022. The anti-sag openings 2022 prevent the occurrence of a sag in the middle region of the first metal wiring layer 2021 during the planarization process, thereby improving the electrical contact of the first metal wiring layer 2021.

[0074] Please continue to refer to Figure 8 In this embodiment, the anti-sag openings 2022 in adjacent first metal wiring layers 2021 are perpendicular to each other. By arranging the anti-sag openings 2022 in adjacent layers vertically, the overall structure of the test key 202 is more evenly distributed, thereby improving the conductive performance of the test key 202.

[0075] Please continue to refer to Figure 9 and Figure 10 In this embodiment, the first device under test 201 has a plurality of second metal wiring layers 2011 arranged in sequence along the second direction Y, and each second metal wiring layer 2011 is in the same layer as the corresponding first metal wiring layer 2021 in the test key 202.

[0076] In this embodiment, when the second metal wiring layer 2011 in the first device under test 201 overlaps with a test key 202 between two test keys 202 arranged at intervals when projected toward the substrate 200, a first metal wiring layer 2021 is not formed in the test key 202 between the two test keys 202, which is located on the same layer as the second metal wiring layer 2011. This prevents the test key 202 between the two test keys 202 from short-circuiting the first device under test 201, thereby affecting the accuracy of the test.

[0077] In other embodiments, the first device under test may not have the second metal wiring layer 2011 located in the same layer as the first metal wiring layer.

[0078] Please continue to refer to Figure 5In this embodiment, a third spacing dimension S3 is defined between the first DUT 201 and the electrically connected test key 202. The present invention further includes: forming a second DUT 203 on the substrate 200, wherein the second DUT 203 has a second length dimension L2 along the first direction X, and the second length dimension L2 is smaller than the third spacing dimension S3; placing the second DUT 203 between any adjacent test keys 202; electrically connecting the second DUT 203 to each adjacent test key 202; and arranging the second DUT 203 so that its projections toward the substrate 200 do not overlap with those of the adjacent test keys 202. Because the second length dimension L2 is smaller than the third spacing dimension S3, sufficient space is provided for the placement of the smaller second DUT 203 without intersecting with the first DUT 201 and thereby affecting the first DUT 201. Therefore, a small-sized second DUT 203 can be set between any adjacent test keys 202, so that the test key 202 used in testing the first DUT 201 and the test key 202 located between two test keys 202 set at intervals can still be used, thereby increasing the number of DUTs in the test structure and improving test efficiency.

[0079] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A test structure, characterized in that: include: substrate; a first device under test (DUT) located on the substrate, the first DUT having a first length dimension along a first direction parallel to a top surface of the substrate; a plurality of test keys on the substrate and arranged in sequence along the first direction, wherein a first spacing dimension exists between adjacent test keys, and the first length dimension is greater than the first spacing dimension; The first device under test is arranged between the two test keys arranged at intervals, there is at least one test key between the two test keys arranged at intervals, and there is a second spacing dimension between the two test keys arranged at intervals, and the second spacing dimension is greater than the first length dimension; The first device under test is electrically connected to the two test keys arranged at intervals; The first device under test and the two test keys arranged at intervals have no overlapping area when projected toward the substrate.

2. The test structure according to claim 1, wherein: The test key includes: several first metal wiring layers arranged in sequence along a second direction, adjacent first metal wiring layers are electrically connected, and several layers of the first metal wiring layers have the same projection area toward the substrate, and the second direction is perpendicular to the top surface of the substrate.

3. The test structure according to claim 2, wherein: Each of the first metal wiring layers has a plurality of anti-sag openings arranged in parallel.

4. The test structure according to claim 3, wherein: The anti-sag openings in adjacent first metal wiring layers are perpendicular to each other.

5. The test structure according to claim 2, wherein: The first device under test has a plurality of second metal wiring layers sequentially arranged along the second direction, and each of the second metal wiring layers is in the same layer as the corresponding first metal wiring layer in the test key.

6. The test structure according to claim 5, wherein: When the second metal wiring layer in the first device under test and the test key between the two test keys arranged at intervals have an overlapping area when projected toward the substrate, the test key between the two test keys does not have the first metal wiring layer in the same layer as the second metal wiring layer.

7. The test structure according to claim 2, wherein: The first device under test does not have a second metal wiring layer in the same layer as the first metal wiring layer.

8. The test structure according to claim 1, wherein: There is a third spacing dimension between the first device under test and the electrically connected test key; the test structure also includes: a second device under test located on the substrate, the second device under test has a second length dimension along the first direction, and the second length dimension is smaller than the third spacing dimension; the second device under test can be arranged between any adjacent test keys; the second device under test is electrically connected to the adjacent test keys respectively; the second device under test and the adjacent test keys have no overlapping area when projected toward the substrate.

9. A method for forming a test structure, characterized in that: include: providing a substrate; forming a first device under test on the substrate, wherein the first device under test has a first length dimension along a first direction, the first direction being parallel to the top surface of the substrate; forming a plurality of test keys sequentially arranged along the first direction on the substrate, with a first spacing dimension between adjacent test keys, and the first length dimension being greater than the first spacing dimension; The first device under test is arranged between two test keys arranged at intervals, wherein there is at least one test key between the two test keys arranged at intervals, and there is a second spacing dimension between the two test keys arranged at intervals, and the second spacing dimension is greater than the first length dimension; electrically connecting the first device under test to the two test keys arranged at intervals; The first device under test is arranged so as to have no overlapping area with the two test keys arranged at intervals when projected toward the substrate.

10. The method for forming a test structure according to claim 9, wherein: The test key includes: several first metal wiring layers arranged in sequence along a second direction, adjacent first metal wiring layers are electrically connected, and several layers of the first metal wiring layers have the same projection area toward the substrate, and the second direction is perpendicular to the top surface of the substrate.

11. The method for forming a test structure according to claim 10, wherein: Each of the first metal wiring layers has a plurality of anti-sag openings arranged in parallel.

12. The method for forming a test structure according to claim 11, wherein: The anti-sag openings in adjacent first metal wiring layers are perpendicular to each other.

13. The method for forming a test structure according to claim 10, wherein: The first device under test has a plurality of second metal wiring layers sequentially arranged along the second direction, and each of the second metal wiring layers is in the same layer as the corresponding first metal wiring layer in the test key.

14. The method for forming a test structure according to claim 13, wherein: When the second metal wiring layer in the first device under test and the test key between the two test keys arranged at intervals have an overlapping area when projected toward the substrate, the first metal wiring layer in the test key between the two test keys is not formed in the same layer as the second metal wiring layer.

15. The method for forming a test structure according to claim 10, wherein: The first device under test does not have a second metal wiring layer in the same layer as the first metal wiring layer.

16. The method for forming a test structure according to claim 9, wherein: There is a third spacing dimension between the first device under test and the electrically connected test key; the invention also includes: forming a second device under test on the substrate, the second device under test having a second length dimension along the first direction, and the second length dimension is smaller than the third spacing dimension; arranging the second device under test between any adjacent test keys; electrically connecting the second device under test to the adjacent test keys respectively; and arranging the second device under test to have no overlapping area with the adjacent test keys in their projections toward the substrate.

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