A double-sided microcrystalline heterojunction battery and its manufacturing method and photovoltaic module

Abstract

The present invention belongs to the technical field of silicon heterojunction cells, and specifically relates to a double-sided microcrystalline heterojunction cell and a manufacturing method thereof and a photovoltaic module, comprising a silicon wafer, a first intrinsic silicon layer arranged on the front side of the silicon wafer, and a second intrinsic amorphous silicon layer arranged on the back side of the silicon wafer, and further comprising: an N-type microcrystalline silicon oxygen doped layer and an N-type microcrystalline silicon doped layer arranged in sequence on the outer surface of the first intrinsic silicon layer, and a P-type microcrystalline silicon carbide doped layer and a P-type microcrystalline silicon doped layer arranged in sequence on the outer surface of the second intrinsic amorphous silicon layer, and controlling the ratio of the film thickness to the crystallization rate. The present invention can effectively improve the conductivity of the double-sided microcrystalline heterojunction cell, increase the light transmittance of the back side, and reduce the light loss of light entering the double-sided microcrystalline heterojunction cell from the back side, thereby improving the conversion efficiency of the double-sided microcrystalline heterojunction cell.

Description

Technical Field

[0001] The present invention belongs to the technical field of silicon heterojunction cells, and in particular relates to a double-sided microcrystalline heterojunction cell and a manufacturing method thereof and a photovoltaic module. Background Art

[0002] Hydrogenated amorphous silicon (a-Si:H), microcrystalline silicon thin film, and hydrogenated microcrystalline silicon thin film (μc-Si:H) have become commonly used window layer and emitter materials for double-sided crystalline silicon heterojunction solar cells due to their high stability, low cost, and easy preparation. Amorphous silicon has low conductivity and high activation energy, while microcrystalline silicon thin film has high conductivity, low activation energy, and light absorption. Therefore, heterojunction cells with microcrystalline structures on both sides have higher conversion efficiency.

[0003] However, the P-type hydrogenated microcrystalline silicon used on the back of the heterojunction battery has a narrow optical band gap and a structural mismatch with the intrinsic amorphous layer. The structural mismatch is reflected in the disordered atomic arrangement of the amorphous layer and the lack of clear lattice periodicity. Therefore, the inconsistency of the atomic spacing or relative position at different positions leads to structural inhomogeneity, which affects the electrical and optical properties.

[0004] In the existing technology, the commonly used technology for preparing P-type microcrystalline silicon carbide is tubular PECVD under high temperature conditions (800-1000°C) or PECVD under 150°C-200°C. It is usually necessary to prepare a seed layer to facilitate the nucleation growth of the film during the deposition process to form a microcrystalline structure.

[0005] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0006] The purpose of the present invention is to overcome the defect of low conversion efficiency of the existing double-sided microcrystalline heterojunction battery with amorphous silicon in the prior art, and to provide a double-sided microcrystalline heterojunction battery and its manufacturing method and photovoltaic module, which can effectively improve the conductivity of the double-sided microcrystalline heterojunction battery, increase the light transmittance of the back side, and reduce the light loss of the double-sided microcrystalline heterojunction battery entering the double-sided microcrystalline heterojunction battery from the back side, thereby improving the conversion efficiency of the double-sided microcrystalline heterojunction battery.

[0007] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a double-sided microcrystalline heterojunction battery, comprising a silicon wafer, a first intrinsic silicon layer arranged on the front side of the silicon wafer, and a second intrinsic amorphous silicon layer arranged on the back side of the silicon wafer, and also comprising: an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer arranged in sequence on the outer surface of the first intrinsic silicon layer, and a P-type microcrystalline silicon carbide-doped layer and a P-type microcrystalline silicon doped layer arranged in sequence on the outer surface of the second intrinsic amorphous silicon layer, the thickness ratio of the P-type microcrystalline silicon doped layer, the P-type microcrystalline silicon carbide-doped layer, the N-type microcrystalline silicon oxygen-doped layer, and the N-type microcrystalline silicon doped layer is 1:0.25-0.5:0.6-1:0.6-1, and the crystallization rate ratio of the P-type microcrystalline silicon doped layer, the P-type microcrystalline silicon carbide-doped layer, the N-type microcrystalline silicon oxygen-doped layer, and the N-type microcrystalline silicon doped layer is 1:0.5-0.9:0.5-1:0.5-1.

[0008] In some preferred embodiments of the present invention, the crystallization rate of the P-type microcrystalline silicon carbide doped layer is 30%-50%, and / or the crystallization rate of the P-type microcrystalline silicon carbide doped layer is 40%-70%.

[0009] In some preferred embodiments of the present invention, the thickness of the P-type microcrystalline silicon carbide doped layer is 2-8 nm, and the thickness of the P-type microcrystalline silicon doped layer is 10-30 nm.

[0010] In some preferred embodiments of the present invention, the thickness of the N-type microcrystalline silicon oxygen-doped layer is 10-20 nm, and the thickness of the N-type microcrystalline silicon doped layer is 2-8 nm.

[0011] In some preferred embodiments of the present invention, the ratio of the effective boron doping concentration of the P-type microcrystalline silicon doping layer, the effective boron doping concentration of the P-type microcrystalline silicon carbide doping layer and the effective phosphorus doping concentration of the N-type microcrystalline silicon oxygen doping layer, and the effective phosphorus doping concentration of the N-type microcrystalline silicon doping layer is 1:0.5-1.5:1-20:0.4-20.

[0012] In some preferred embodiments of the present invention, the ratio of the effective boron doping concentration to the effective carbon doping concentration of the P-type microcrystalline silicon carbide doping layer is 1:0.2-1.

[0013] In some preferred embodiments of the present invention, the effective boron doping concentration of the P-type microcrystalline silicon carbide doped layer is 5e18cm -3 -1.5e20 cm -3 .

[0014] In some preferred embodiments of the present invention, the effective boron doping concentration of the P-type microcrystalline silicon doping layer is 1e19 cm -3 -3e21 cm -3 The effective phosphorus doping concentration of the N-type microcrystalline silicon oxygen-doped layer is 1e18 cm -3 -5e20 cm -3The effective phosphorus doping concentration of the N-type microcrystalline silicon doping layer is 5e18 cm -3 -2e21 cm -3 .

[0015] In some preferred embodiments of the present invention, the thickness ratio of the P-type microcrystalline silicon doping layer, the P-type microcrystalline silicon carbide doping layer and the second intrinsic amorphous silicon layer is 1:0.25-0.5:0.3-0.5.

[0016] In some preferred embodiments of the present invention, the thickness of the second intrinsic amorphous silicon layer is 4-8 nm, and the thickness of the first intrinsic silicon layer is 3-6 nm.

[0017] In some preferred embodiments of the present invention, the double-sided microcrystalline heterojunction cell further includes a transparent conductive film and a metal silver gate electrode respectively disposed on the outer surface of the N-type microcrystalline silicon doped layer and the outer surface of the P-type microcrystalline silicon doped layer.

[0018] In a second aspect, the present invention provides a method for manufacturing a double-sided microcrystalline heterojunction battery, which is used to prepare the double-sided microcrystalline heterojunction battery described in the first aspect, and comprises the following steps:

[0019] S1, provide double-sided velvet silicon wafer;

[0020] S2, depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0021] S3, depositing a first intrinsic silicon layer on the front side of the silicon wafer;

[0022] S4, depositing an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer in sequence on the outer surface of the first intrinsic silicon layer;

[0023] S5. Directly deposit a P-type microcrystalline silicon carbide doped layer on the outer surface of the second intrinsic amorphous silicon layer. The corresponding deposition conditions include: temperature of 50-100°C, process gas of SiH 4 , CH 4 , B 2 H 6 , H 2 ;

[0024] S6. Depositing a P-type microcrystalline silicon doping layer on the outer surface of the P-type microcrystalline silicon carbide doping layer.

[0025] In a third aspect, the present invention provides a method for manufacturing a double-sided microcrystalline heterojunction battery, which is used to prepare the double-sided microcrystalline heterojunction battery described in the first aspect, and comprises the following steps:

[0026] S1, provide double-sided velvet silicon wafer;

[0027] S2, depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0028] S3, depositing a first intrinsic silicon layer on the front side of the silicon wafer;

[0029] S4, depositing an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer in sequence on the outer surface of the first intrinsic silicon layer;

[0030] S501, depositing a microcrystalline silicon carbide seed layer with a thickness of 1-2 nm on the outer surface of the second intrinsic amorphous silicon layer, wherein the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: a temperature of 50-150° C., a process gas of SiH 4 , H 2 Alternatively, the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: a temperature of 50-150°C, a process gas of SiH 4 , CH 4 , H 2 ;

[0031] S502, depositing a P-type microcrystalline silicon carbide doped layer on the outer surface of the microcrystalline silicon carbide seed layer, and the corresponding deposition conditions include: a temperature of 50-100° C., a process gas of SiH 4 , CH 4 , B 2 H 6 , H 2 ;

[0032] S6. Depositing a P-type microcrystalline silicon doping layer on the outer surface of the P-type microcrystalline silicon carbide doping layer.

[0033] In some preferred embodiments of the present invention, the method for manufacturing a bifacial microcrystalline heterojunction battery further includes at least one of the following features:

[0034] Feature 1: The deposition conditions of the P-type microcrystalline silicon carbide doped layer also include: gas pressure of 300-700 Pa, power density of 400-4000 mW / cm 2 , time is 15-40s;

[0035] Feature 2: The deposition conditions of the P-type microcrystalline silicon doped layer also include: the temperature is 100℃-150℃, the process gas is SiH 4 , H 2 , B 2 H 6 , air pressure is 300-700Pa, power density is 400-5000mW / cm 2 , deposition time is 180-240s;

[0036] Feature 3: The corresponding deposition conditions of the microcrystalline silicon carbide seed layer also include: gas pressure of 300-500Pa, power density of 400-1600mW / cm 2 , deposition time is 30-60s;

[0037] Feature 4: The deposition conditions of the N-type microcrystalline silicon oxygen-doped layer include: temperature of 100°C-150°C, process gas of SiH 4 , H 2 , CO 2 , PH 3 , air pressure is 300-700Pa, power density is 400-4000mW / cm 2 , deposition time is 160-200s;

[0038] Feature 5: The deposition conditions of the N-type microcrystalline silicon doped layer include: temperature of 100°C-150°C, process gas of SiH 4 , H 2 , PH 3 , air pressure is 300-700Pa, power density is 400-3000mW / cm 2 , deposition time is 20-60s;

[0039] Feature 6: The method for manufacturing the double-sided microcrystalline heterojunction battery further comprises:

[0040] S7, forming transparent conductive films on the outer surfaces of the N-type microcrystalline silicon doping layer and the P-type microcrystalline silicon doping layer respectively;

[0041] S8. Form metal silver gate electrodes on the outer surfaces of the transparent conductive film on the front and back sides respectively.

[0042] In a fourth aspect, the present invention provides a photovoltaic module, which includes the double-sided microcrystalline heterojunction battery described in the first aspect, or a double-sided microcrystalline heterojunction battery manufactured by the manufacturing method of the double-sided microcrystalline heterojunction battery described in the second aspect or the third aspect.

[0043] Beneficial effects:

[0044] The present invention can effectively improve the conductivity of the heterojunction battery, increase the light transmittance of the back side, and reduce the light loss of the light entering the heterojunction battery from the back side through the above technical scheme, especially by setting a specific double-sided microcrystalline passivation structure on the back side and the front side and matching the appropriate thickness ratio and crystallization ratio, thereby improving the conversion efficiency of the heterojunction battery. Among them, the microcrystalline stack of the P-type microcrystalline silicon carbide doped layer and the P-type microcrystalline silicon doped layer sequentially arranged on the back side has higher conductivity, higher optical transmittance and carrier mobility, and lower activation energy than the P-type amorphous silicon used in the traditional structure. The silicon carbide thickness ratio is relatively suitable and thin, which does not affect the conductive effect of the P-type microcrystalline silicon doped layer. At the same time, between the second intrinsic amorphous silicon layer and the P-type microcrystalline silicon doped layer, the wide band gap advantage of the P-type microcrystalline silicon carbide doped layer is utilized to adjust the band gap between the second intrinsic amorphous silicon layer and the P-type microcrystalline silicon doped layer to match.

[0045] The present invention also cooperates with an N-type microcrystalline silicon oxygen doping layer and an N-type microcrystalline silicon doping layer sequentially arranged on the outer surface of the first intrinsic silicon layer on the front side, which can improve the conductivity and light transmittance, and is beneficial to improving the Isc of the battery.

[0046] In the manufacturing method of the present invention, the deposition of the P-type microcrystalline silicon carbide doped layer utilizes a 50°C-100°C low-temperature deposition technology. On the one hand, it is beneficial to the growth of the microcrystalline structure of the P-type microcrystalline silicon carbide doped layer. On the other hand, during the low-temperature deposition process, it can ensure that other film layers of the heterojunction battery will not be damaged due to excessively high process temperatures, while maintaining a better passivation effect.

[0047] In a preferred manufacturing method of the present invention, the preparation of a P-type microcrystalline silicon carbide doped layer is a method that does not require a seed layer. It is a process for preparing a thickness-controlled thin film using PECVD technology at low temperature. Silicon carbide can be nucleated without forming a seed layer. The thickness of the P-type microcrystalline silicon carbide doped layer can be reduced by 0.5-2nm compared to the method of using a seed layer, which can shorten the coating time of the P-type microcrystalline silicon carbide doped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 It is a schematic structural diagram of a specific implementation mode of the double-sided microcrystalline heterojunction battery of the present invention.

[0050] Figure 2 The present invention is a process flow chart of the method for manufacturing a double-sided microcrystalline heterojunction battery.

[0051] Figure 3 Another process flow chart of the method for manufacturing a double-sided microcrystalline heterojunction battery of the present invention.

[0052] Description of Reference Numerals

[0053] 1. Front silver gate electrode, 2. Front transparent conductive film, 3. N-type microcrystalline stack, 4. First intrinsic amorphous silicon layer, 5. Silicon wafer, 6. Second intrinsic amorphous silicon layer, 7. P-type microcrystalline silicon carbide doped layer, 8. P-type microcrystalline silicon doped layer, 9. Back transparent conductive film, 10. Back silver gate electrode. DETAILED DESCRIPTION

[0054] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0056] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0057] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0058] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0059] In a first aspect, the present invention provides a double-sided microcrystalline heterojunction battery, comprising a silicon wafer, a first intrinsic silicon layer disposed on the front side of the silicon wafer, and a second intrinsic amorphous silicon layer disposed on the back side of the silicon wafer, and further comprising: an N-type microcrystalline silicon oxygen doped layer and an N-type microcrystalline silicon doped layer disposed in sequence on the outer surface of the first intrinsic silicon layer, a P-type microcrystalline silicon carbide doped layer and a P-type microcrystalline silicon doped layer disposed in sequence on the outer surface of the second intrinsic amorphous silicon layer, and the P-type microcrystalline silicon doped layer, the P-type microcrystalline silicon carbide doped layer and the N-type microcrystalline silicon oxygen doped layer. The thickness ratio of the doped layer and the N-type microcrystalline silicon doped layer is 1:0.25-0.5:0.6-1:0.6-1, preferably 1:0.25-0.35:0.6-1:0.6-1, and the crystallization rate ratio of the P-type microcrystalline silicon doped layer, the P-type microcrystalline silicon carbide doped layer and the N-type microcrystalline silicon oxygen doped layer and the N-type microcrystalline silicon doped layer is 1:0.5-0.9:0.5-1:0.5-1, preferably 1:0.5-0.8:0.5-0.87:0.5-1.

[0060] The present invention adopts a P-type microcrystalline silicon doping layer, a P-type microcrystalline silicon carbide doping layer and an N-type microcrystalline silicon oxygen doping layer and an N-type microcrystalline silicon doping layer with suitable thickness ratio and suitable crystallization rate ratio, which is beneficial to improving the Voc and FF of the battery.

[0061] In some preferred embodiments of the present invention, the crystallization rate of the P-type microcrystalline silicon carbide doped layer is 30%-50%, and / or the crystallization rate of the P-type microcrystalline silicon carbide doped layer is 40%-70%.

[0062] In some preferred embodiments of the present invention, the thickness of the P-type microcrystalline silicon carbide doped layer is 2-8 nm, and the thickness of the P-type microcrystalline silicon doped layer is 10-30 nm.

[0063] In some preferred embodiments of the present invention, the thickness of the N-type microcrystalline silicon oxygen-doped layer is 10-20 nm.

[0064] Preferably, the thickness of the N-type microcrystalline silicon doping layer is 2-8 nm.

[0065] In some preferred embodiments of the present invention, the ratio of the effective boron doping concentration of the P-type microcrystalline silicon doping layer, the effective boron doping concentration of the P-type microcrystalline silicon carbide doping layer, the effective phosphorus doping concentration of the N-type microcrystalline silicon oxygen doping layer, and the effective phosphorus doping concentration of the N-type microcrystalline silicon doping layer is 1:0.5-1.5:1-20:0.4-20, preferably 1:0.8-1.5:1-20:0.4-20, and further preferably 1:0.8-1.2:1-20:0.4-20. The use of the P-type microcrystalline silicon doping layer, the P-type microcrystalline silicon carbide doping layer, the N-type microcrystalline silicon oxygen doping layer, and the N-type microcrystalline silicon doping layer with a suitable effective doping concentration ratio is more conducive to increasing the light transmittance, improving the conductivity, and further improving the carrier mobility.

[0066] In some preferred embodiments of the present invention, the ratio of the effective boron doping concentration to the effective carbon doping concentration of the P-type microcrystalline silicon carbide doping layer is 1:0.2-1, preferably 1:0.2-0.5. The use of a P-type microcrystalline silicon carbide doping layer with a suitable ratio of the effective boron doping concentration to the effective carbon doping concentration is more conducive to improving the crystallization rate of the P-type microcrystalline silicon carbide doping layer.

[0067] In some preferred embodiments of the present invention, the effective boron doping concentration of the P-type microcrystalline silicon carbide doped layer is 5e18cm -3 -1.5e20 cm -3 , preferably 5e18 cm -3 -8e19 cm -3 .

[0068] In some preferred embodiments of the present invention, the effective boron doping concentration of the P-type microcrystalline silicon doping layer is 1e19 cm -3 -3e21 cm -3 .

[0069] Preferably, the effective phosphorus doping concentration of the N-type microcrystalline silicon oxygen-doped layer is 1e18 cm -3 -5e20 cm -3 The effective phosphorus doping concentration of the N-type microcrystalline silicon doping layer is 5e18 cm -3 -2e21 cm -3 .

[0070] In some preferred embodiments of the present invention, the thickness ratio of the P-type microcrystalline silicon doping layer, the P-type microcrystalline silicon carbide doping layer and the second intrinsic amorphous silicon layer is 1:0.25-0.5:0.3-0.5. The use of the P-type microcrystalline silicon doping layer, the P-type microcrystalline silicon carbide doping layer and the second intrinsic amorphous silicon layer with a suitable thickness ratio is more conducive to the structural matching between the microcrystalline and intrinsic amorphous silicon layers, thereby improving Voc.

[0071] In some preferred embodiments of the present invention, the thickness of the second intrinsic amorphous silicon layer is 4-8 nm.

[0072] Preferably, the thickness of the first intrinsic silicon layer is 3-6 nm.

[0073] In some preferred embodiments of the present invention, the double-sided microcrystalline heterojunction cell further includes a transparent conductive film and a metal silver gate electrode respectively disposed on the outer surface of the N-type microcrystalline silicon doped layer and the outer surface of the P-type microcrystalline silicon doped layer.

[0074] The sizes of the transparent conductive film and the metal silver gate electrode can refer to the prior art and can be used in the present invention. For example, the thickness of the transparent conductive film is preferably 70-120 nm.

[0075] Preferably, both the front and back sides of the silicon wafer are textured surfaces. The silicon wafer is, for example, preferably an N-type single crystal silicon wafer.

[0076] In a second aspect, the present invention provides a method for manufacturing a double-sided microcrystalline heterojunction battery, which is used to prepare the double-sided microcrystalline heterojunction battery described in the first aspect, and comprises the following steps:

[0077] S1, provide double-sided velvet silicon wafer;

[0078] S2, depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0079] S3, depositing a first intrinsic silicon layer on the front side of the silicon wafer;

[0080] S4, depositing an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer in sequence on the outer surface of the first intrinsic silicon layer;

[0081] S5. Directly deposit a P-type microcrystalline silicon carbide doped layer on the outer surface of the second intrinsic amorphous silicon layer. The corresponding deposition conditions include: temperature of 50-100°C, process gas of SiH 4 , CH 4 , B 2 H 6 , H 2 ;

[0082] S6. Depositing a P-type microcrystalline silicon doping layer on the outer surface of the P-type microcrystalline silicon carbide doping layer.

[0083] In the manufacturing method of the present invention, the seed layer may be deposited first, and then the P-type microcrystalline silicon carbide doped layer may be deposited. The seed layer may be deposited first by introducing a carbon source to form a silicon carbide nucleus seed or by not introducing a carbon source to form a silicon nucleus seed. Both methods may allow silicon carbide to grow on the seed to form a microcrystalline structure. The seed layer and the continuously growing silicon carbide microcrystalline structure together form a P-type microcrystalline silicon carbide doped layer.

[0084] In a third aspect, the present invention provides a method for manufacturing a double-sided microcrystalline heterojunction battery, which is used to prepare the double-sided microcrystalline heterojunction battery described in the first aspect, and comprises the following steps:

[0085] S1, provide double-sided velvet silicon wafer;

[0086] S2, depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer;

[0087] S3, depositing a first intrinsic silicon layer on the front side of the silicon wafer;

[0088] S4, depositing an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer in sequence on the outer surface of the first intrinsic silicon layer;

[0089] S501, depositing a microcrystalline silicon carbide seed layer with a thickness of 1-2 nm on the outer surface of the second intrinsic amorphous silicon layer, wherein the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: a temperature of 50-150° C., preferably 50-130° C., and a process gas of SiH 4 , H 2 Alternatively, the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: a temperature of 50-150°C, a process gas of SiH 4 , CH 4 , H 2 ;

[0090] S502, depositing a P-type microcrystalline silicon carbide doped layer on the outer surface of the microcrystalline silicon carbide seed layer, and the corresponding deposition conditions include: a temperature of 50-100° C., a process gas of SiH 4 , CH 4 , B 2 H 6 , H 2 ;

[0091] S6. Depositing a P-type microcrystalline silicon doping layer on the outer surface of the P-type microcrystalline silicon carbide doping layer.

[0092] In some preferred embodiments of the present invention, the deposition conditions of the P-type microcrystalline silicon carbide doped layer also include: a gas pressure of 300-700 Pa, a power density of 400-4000 mW / cm 2 The time is 15-40s. The P-type microcrystalline silicon carbide doping layer with suitable deposition conditions is more conducive to the crystallization of the P-type microcrystalline silicon carbide doping layer.

[0093] Further preferably, the deposition conditions of the P-type microcrystalline silicon carbide doped layer further include: SiH 4 The flow rate is 10-400sccm, preferably 20-400sccm, H 2 The flow rate is 10000-150000sccm, preferably 10000-50000sccm, CH 4 The flow rate is 1-20 sccm, preferably 1-20 sccm, B 2 H 6 The flow rate is 0.5-400 sccm, preferably 1-50 sccm (more preferably 1-30 sccm) or 30-400 sccm.

[0094] In the deposition of the P-type microcrystalline silicon carbide doped layer of the present invention, the B 2 H 6 The crystallization rate of the P-type microcrystalline silicon carbide doped layer can be regulated by increasing the flow gradient, as long as the P-type microcrystalline silicon carbide doped layer with the required crystallization rate can be obtained; for example, a small amount of B is added at the beginning of the preparation. 2 H 6It is conducive to the formation of crystal nuclei, and then the doping amount is increased on the basis of ensuring the formation of a microcrystalline structure to improve the conductivity of the film layer, so that the crystallization rate of the microcrystal is better. In some specific embodiments, B 2 H 6 The flow rate is gradually increased from 30 sccm to 400 sccm. The increment can be selected according to actual needs, preferably with a uniform increase.

[0095] In some preferred embodiments of the present invention, the deposition conditions of the P-type microcrystalline silicon doped layer also include: a temperature of 100° C. to 150° C., a process gas of SiH 4 , H 2 , B 2 H 6 , air pressure is 300-700Pa, power density is 400-5000mW / cm 2 , the deposition time is 180-240s. Using a P-type microcrystalline silicon doping layer under suitable deposition conditions is more conducive to improving the conductivity of the microcrystalline film layer.

[0096] Further preferably, the deposition conditions of the P-type microcrystalline silicon doping layer further include: SiH 4 The flow rate is 50-1000sccm, more preferably 100-400sccm, H 2 The flow rate is 10000-150000 sccm, more preferably 20000-50000 sccm, B 2 H 6 The flow rate is 10-400 sccm, more preferably 10-400 sccm.

[0097] In some preferred embodiments of the present invention, the corresponding deposition conditions of the microcrystalline silicon carbide seed layer also include: a gas pressure of 300-500 Pa, a power density of 400-1600 mW / cm 2 , more preferably 400-800mW / cm 2 , the deposition time is 30-60s.

[0098] Preferably, the corresponding deposition conditions of the microcrystalline silicon carbide seed layer also include: SiH 4 The flow rate is 60-100 sccm, H 2 The flow rate is 10000-150000 sccm. Furthermore, the process gas also contains CH 4 When 4 The flow rate is 1-20sccm.

[0099] In some preferred embodiments of the present invention, the deposition conditions of the N-type microcrystalline silicon oxygen-doped layer include: a temperature of 100° C. to 150° C., a process gas of SiH 4 , H 2 , CO2 , PH 3 , air pressure is 300-700Pa, power density is 400-2000mW / cm 2 The deposition time is 160-200s. The N-type microcrystalline silicon oxygen doped layer with suitable deposition conditions is more conducive to the growth of microcrystalline silicon oxygen window layer.

[0100] Further preferably, the deposition conditions of the N-type microcrystalline silicon oxygen-doped layer further include: SiH 4 The flow rate is 100-400sccm, H 2 The flow rate is 10000-150000sccm, more preferably 20000-40000sccm, CO 2 The flow rate is 10-400sccm, more preferably 30-400sccm, PH 3 The flow rate is 100-1000sccm, more preferably 300-1000sccm. In the present invention, CO 2 , PH 3 The crystallization rate of the N-type microcrystalline silicon oxygen-doped layer can be adjusted by increasing the flow gradient, as long as the N-type microcrystalline silicon oxygen-doped layer with the required crystallization rate can be obtained; for example, adding a small amount of CO at the beginning of the preparation 2 , PH 3 It is conducive to the formation of crystal nuclei, and then the doping amount is increased on the basis of ensuring the formation of a microcrystalline structure to improve the conductivity of the film layer, so that the crystallization rate of the microcrystal is better. In some specific embodiments, CO 2 The flow rate was increased from 30 sccm to 400 sccm, and the pH 3 The flow rate is gradually increased from 300 sccm to 1000 sccm. The increment can be selected according to actual needs, preferably a uniform increase.

[0101] Preferably, the deposition conditions of the N-type microcrystalline silicon doped layer include: a temperature of 100° C. to 150° C., a process gas of SiH 4 , H 2 , PH 3 , air pressure is 300-700Pa, power density is 400-3000mW / cm 2 , the deposition time is 20-60s. Further preferably, SiH 4 , H 2 , PH 3 The flow rate can refer to the range in the prior art, as long as the N-type microcrystalline silicon doping layer with the required target parameters can be obtained.

[0102] The N-type microcrystalline silicon oxygen doped layer, the N-type microcrystalline silicon doped layer, the P-type microcrystalline silicon carbide doped layer, and the P-type microcrystalline silicon doped layer described in the present invention are preferably deposited using PECVD technology.

[0103] The present invention preferably adopts the manufacturing method without a seed layer of the second aspect.

[0104] In some preferred embodiments of the present invention, the method for manufacturing the double-sided microcrystalline heterojunction battery further comprises:

[0105] S7, forming transparent conductive films on the outer surfaces of the N-type microcrystalline silicon doping layer and the P-type microcrystalline silicon doping layer respectively;

[0106] S8. Form metal silver gate electrodes on the outer surfaces of the transparent conductive film on the front and back sides respectively.

[0107] In the second and third aspects, S1 provides a method for providing a double-sided velvet-coated silicon wafer with reference to the prior art. For example, the process may include: using a texturing aqueous solution containing an alkali (such as KOH and / or NaOH) with a mass concentration of 3%-5% and a texturing additive with a mass concentration of 0.5%-5%, texturing and cleaning the silicon wafer at 50°C-90°C, preferably 60-85°C, to form a velvet surface with a pyramid structure on both sides of the silicon wafer.

[0108] The first intrinsic silicon layer and the second intrinsic amorphous silicon layer of the present invention may be deposited by PECVD technology. Preferably, the deposition conditions of the first intrinsic silicon layer and the second intrinsic amorphous silicon layer independently include: a process temperature of 150°C-200°C, a process gas of SiH 4 , H 2 , air pressure is 40-100Pa, power density is 40-400mW / cm 2 , the deposition time is 50-120s. Further preferably, SiH 4 The flow rate is 1000-10000sccm, H 2 The flow rate is 1000-50000sccm.

[0109] In a fourth aspect, the present invention provides a photovoltaic module, which includes the double-sided microcrystalline heterojunction battery described in the first aspect, or a double-sided microcrystalline heterojunction battery manufactured by the manufacturing method of the double-sided microcrystalline heterojunction battery described in the second aspect or the third aspect.

[0110] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0111] Example 1

[0112] refer to Figure 1 and Figure 2 , a high-efficiency double-sided microcrystalline heterojunction battery, which is manufactured by the following manufacturing method:

[0113] S1. Using a texturing aqueous solution containing 3% KOH and 0.5% texturing additive at 75° C., the N-type single crystal silicon wafer 5 is texturized and cleaned, and a velvet surface with a pyramid structure is formed on both sides of the silicon wafer 5 .

[0114] S2, using PECVD equipment to deposit a second intrinsic amorphous silicon layer 6 on the back of the silicon wafer 5, the conditions are: 180°C, the process gas is: SiH 4 , H 2 , SiH 4 The flow rate is 2400sccm, H 2 Flow rate: 8000sccm, gas pressure: 60Pa, power density: 100mW / cm 2 , deposition time 80s, thickness 6nm.

[0115] S3, using PECVD equipment to deposit the first intrinsic amorphous silicon layer 4 on the front side of the silicon wafer 5, the condition is 180°C, the process gas is: SiH 4 , H 2 , SiH 4 The flow rate is 2400sccm, H 2 Flow rate: 8000sccm, gas pressure: 60Pa, power density: 100mW / cm 2 , deposition time 70s, thickness 4nm.

[0116] S4, using PECVD equipment to sequentially deposit an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer on the front first intrinsic amorphous silicon layer 4 to form an N-type microcrystalline stack 3.

[0117] The conditions for the N-type microcrystalline silicon oxygen doping layer are: temperature 120°C, process gas: SiH 4 , H 2 , CO 2 , PH 3 , SiH 4 The flow rate is 220 sccm, H 2 The flow rate is 40000sccm, CO 2 The flow rate was increased from 30 sccm to 400 sccm by 10% and the pH 3 The flow rate was increased from 300 sccm to 1000 sccm by 17%, the gas pressure was 400 Pa, and the power density was 800 mW / cm 2 , deposition time 180s, thickness 15nm, crystallization rate 48%, effective phosphorus doping concentration 1e20 cm -3 .

[0118] The conditions for the N-type microcrystalline silicon doping layer are: temperature 120°C, process gas SiH 4 , H2 , PH 3 , SiH 4 The flow rate is 130sccm, H 2 Flow rate is 26000sccm, PH 3 The flow rate is 400sccm, the pressure is 300Pa, and the power density is 3000mW / cm 2 , deposition time is 30s; thickness is 4nm, crystallization rate is 40%, effective phosphorus doping concentration is 4e19 cm -3 .

[0119] S5, using PECVD equipment to deposit a P-type microcrystalline silicon carbide doped layer 7 on the second intrinsic amorphous silicon layer 6 on the back side, the condition is 60° C., process gas: SiH 4 , CH 4 , B 2 H 6 , H 2 , SiH 4 The flow rate is 100 sccm, H 2 The flow rate is 40000sccm, CH 4 The flow rate is 10sccm, B 2 H 6 The flow rate was increased from 8 sccm to 30 sccm by 25%; the pressure was 400 Pa and the power density was 4000 mW / cm 2 , duration 20s, the thickness of the P-type microcrystalline silicon carbide doped layer 7 is 4nm, and the crystallization rate is 40%. The effective boron doping concentration of the P-type microcrystalline silicon carbide doped layer 7 is 5e19 cm -3 , the effective carbon doping concentration is 2e19 cm -3 The ratio of the effective boron doping concentration to the effective carbon doping concentration of the P-type microcrystalline silicon carbide doping layer 7 is 1:0.4.

[0120] S6, using PECVD equipment to deposit a P-type microcrystalline silicon doping layer 8 on the P-type microcrystalline silicon carbide doping layer 7, the condition is 120° C., the process gas is: SiH 4 , B 2 H 6 , H 2 , SiH 4 The flow rate is 300sccm, H 2 The flow rate is 40000sccm, B 2 H 6 The flow rate was increased from 30 sccm to 400 sccm by 50%; the gas pressure was 500 Pa and the power density was 4000 mW / cm 2 , deposition time 200s, P-type microcrystalline silicon doping layer 8 thickness 15nm, crystallization rate 48%, effective boron doping concentration 1e20 cm-3 .

[0121] According to calculation, the thickness ratio of the P-type microcrystalline silicon doping layer 8, the P-type microcrystalline silicon carbide doping layer 7, the N-type microcrystalline silicon oxygen doping layer, and the N-type microcrystalline silicon doping layer is 1:0.27:1:0.27, and the crystallization ratio ratio of the P-type microcrystalline silicon doping layer 8, the P-type microcrystalline silicon carbide doping layer 7, the N-type microcrystalline silicon oxygen doping layer, and the N-type microcrystalline silicon doping layer is 1:0.83:1:0.83. The effective boron doping concentration ratio of the P-type microcrystalline silicon doping layer 8, the effective boron doping concentration of the P-type microcrystalline silicon carbide doping layer 7, the effective phosphorus doping concentration of the N-type microcrystalline silicon oxygen doping layer, and the effective phosphorus doping concentration of the N-type microcrystalline silicon doping layer is 1:0.5:1:0.4.

[0122] S7. Use PVD equipment to plate ITO films on the N-type microcrystalline stack 3 and the P-type microcrystalline silicon doped layer 8, respectively, to form a front transparent conductive film 2 and a back transparent conductive film 9, each with a thickness of 90 nm.

[0123] S8. Prepare a metal silver grid electrode on the ITO film using a screen printing device to form a front silver grid electrode 1 and a back silver grid electrode 10 respectively.

[0124] Example 2

[0125] Use Figure 3 The method shown in the embodiment 1 is different from that in the embodiment 1, a microcrystalline silicon carbide seed layer with a thickness of 1 nm is first deposited on the outer surface of the second intrinsic amorphous silicon layer in S5, and the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: a temperature of 80° C., a process gas of SiH 4 , H 2 , SiH 4 The flow rate is 60 sccm, H 2 The flow rate is 20000sccm, the pressure is 400Pa, and the power density is 500mW / cm 2 , for 30 seconds; then the step of depositing a P-type microcrystalline silicon carbide doped layer in S5 of Example 1 is performed (the deposition method of this part of the P-type microcrystalline silicon carbide doped layer is the same as that of Example 1), wherein the seed layer and the silicon carbide microcrystalline structure that continues to grow together form a P-type microcrystalline silicon carbide doped layer. The thickness of the obtained P-type microcrystalline silicon carbide doped layer is 5nm and the crystallization rate is 40%. The effective boron doping concentration of the P-type microcrystalline silicon carbide doped layer is 5e19cm -3 , the effective carbon doping concentration is 2e19 cm -3 .

[0126] Example 3

[0127] The method of Example 2 is followed, except that the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: temperature of 80° C., process gas of SiH 4, CH 4 , H 2 , SiH 4 The flow rate is 60 sccm, H 2 The flow rate is 20000sccm, CH 4 The flow rate is 10sccm, the pressure is 400Pa, and the power density is 500mW / cm 2 , for 40 seconds. The thickness of the obtained P-type microcrystalline silicon carbide doped layer is 5nm and the crystallization rate is 40%. The effective boron doping concentration of the P-type microcrystalline silicon carbide doped layer is 5e19 cm -3 , the effective carbon doping concentration is 2.1e19 cm -3 .

[0128] Example 4

[0129] The method of Example 1 is referred to, except that the thickness of the P-type microcrystalline silicon carbide doped layer is adjusted so that the ratio of the thickness of the P-type microcrystalline silicon doped layer to the thickness of the P-type microcrystalline silicon carbide doped layer is 1:0.4. The process parameters that need to be changed to meet the thickness adjustment of the P-type microcrystalline silicon carbide doped layer are: the duration is changed to 24s, and the thickness is 6nm.

[0130] Example 5

[0131] The method of Example 1 is referred to, except that the crystallization rate of the P-type microcrystalline silicon carbide doped layer is adjusted so that the ratio of the crystallization rate of the P-type microcrystalline silicon doped layer to the P-type microcrystalline silicon carbide doped layer is 1:0.9. The process parameters that need to be changed to meet this condition adjustment are: Change B 2 H 6 The flow rate is increased from 8 sccm to 50 sccm by 50%; the gas pressure is changed to 650 Pa; the power density is increased to 4200 mW / cm 2 .

[0132] Example 6

[0133] The method of Example 1 is referred to, except that the crystallization rate of the N-type microcrystalline silicon oxygen-doped layer is adjusted so that the ratio of the crystallization rate of the P-type microcrystalline silicon doped layer to the N-type microcrystalline silicon oxygen-doped layer is 1:0.9. The process parameters that need to be changed to meet this condition are: changing CO 2 The flow rate was increased from 10 sccm to 200 sccm by 50% gradient, PH 3 The flow rate was changed from 500 sccm to 1000 sccm in 20% increments.

[0134] Example 7

[0135] The method of Example 1 is referred to, except that the effective boron doping concentration of the P-type microcrystalline silicon carbide doping layer is adjusted so that the ratio of the effective boron doping concentration of the P-type microcrystalline silicon doping layer to the effective boron doping concentration of the P-type microcrystalline silicon carbide doping layer is 1:1.3. The ratio of the effective boron doping concentration to the effective carbon doping concentration of the P-type microcrystalline silicon carbide doping layer is calculated to be 1:1. The process parameters that need to be changed to meet this condition adjustment are: Change B 2 H 6 The flow rate was increased from 8 sccm to 30 sccm by 30% gradient, CH 4 The flow rate is 15 sccm.

[0136] Comparative Example 1

[0137] The method of Example 1 is referred to, except that the back structure is different. Specifically, a second intrinsic amorphous silicon layer and a P-type amorphous doped layer are deposited on the back of the silicon wafer, and a P-type microcrystalline silicon carbide doped layer is not contained. During the preparation, a P-type amorphous doped layer is deposited on the second intrinsic amorphous silicon layer on the back by PECVD equipment, with a thickness of 15 nm and an effective boron doping concentration being the same as the effective boron doping concentration of the P-type microcrystalline silicon doping layer in Example 1.

[0138] Comparative Example 2

[0139] The method of Example 1 is referred to, except that no N-type microcrystalline silicon doping layer is provided.

[0140] Comparative Example 3

[0141] The method of Example 1 is referred to, except that no P-type microcrystalline silicon carbide doping layer is provided.

[0142] Comparative Example 4

[0143] The method of Example 1 is referred to, except that the N-type microcrystalline silicon oxygen-doped layer on the front side is replaced by an N-type amorphous silicon doped layer, and the doping concentration remains unchanged.

[0144] Test Case

[0145] The batteries obtained in the above embodiments and comparative examples were subjected to performance tests of short-circuit current Isc, open-circuit voltage Voc, fill factor FF, and battery conversion efficiency Eta, and the results are shown in Table 1. The performance indicators of each embodiment and comparative examples 2-4 were converted using comparative example 1 as a reference benchmark. The data of comparative example 1 was normalized to 1.0000, and other examples were converted based on comparative example 1, such as the short-circuit current of embodiment 1 / the short-circuit current of comparative example 1 was 1.0030. When converted, the unit of short-circuit current Isc is A, the unit of open-circuit voltage Voc is V, the unit of fill factor FF is %, and the unit of battery conversion efficiency Eta is %.

[0146] Table 1

[0147]

[0148] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can effectively reduce the light loss entering the double-sided microcrystalline heterojunction battery from the back, and effectively improve the short-circuit current Isc, open-circuit voltage Voc, fill factor FF, and battery conversion efficiency Eta of the battery. In the present invention, the P-type microcrystalline silicon carbide doped layer is deposited by PECVD technology at a low temperature of 50°C-100°C. This scheme is conducive to the growth of the microcrystalline structure of the P-type microcrystalline silicon carbide doped layer, and there is no need to consider the damage of other film layers of the heterojunction battery due to excessive temperature during the deposition process.

[0149] Furthermore, according to Example 1 and Examples 2-7, it can be seen that the preferred battery structure of the present invention is more conducive to improving the short-circuit current Isc, open-circuit voltage Voc, fill factor FF, and battery conversion efficiency Eta of the battery.

[0150] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A double-sided microcrystalline heterojunction cell, comprising a silicon wafer, a first intrinsic silicon layer disposed on the front side of the silicon wafer, and a second intrinsic amorphous silicon layer disposed on the back side of the silicon wafer, characterized in that: Also includes: An N-type microcrystalline silicon oxygen doping layer and an N-type microcrystalline silicon doping layer are sequentially arranged on the outer surface of the first intrinsic silicon layer, and a P-type microcrystalline silicon carbide doping layer and a P-type microcrystalline silicon doping layer are sequentially arranged on the outer surface of the second intrinsic amorphous silicon layer, the thickness ratio of the P-type microcrystalline silicon doping layer, the P-type microcrystalline silicon carbide doping layer, the N-type microcrystalline silicon oxygen doping layer, and the N-type microcrystalline silicon doping layer is 1:0.25-0.5:0.6-1:0.6-1, and the P-type microcrystalline silicon doping layer, the P-type microcrystalline silicon carbide doping layer and the N-type microcrystalline silicon doping layer are 1:0.25-0.5:0.6-1:0.6-1. The ratio of the crystallization rate of the oxygen-doped layer and the N-type microcrystalline silicon doped layer is 1:0.5-0.9:0.5-1:0.5-1, the crystallization rate of the P-type microcrystalline silicon carbide doped layer is 30%-50%, the crystallization rate of the P-type microcrystalline silicon doped layer is 40%-70%, the thickness of the P-type microcrystalline silicon carbide doped layer is 2-8nm, the thickness of the P-type microcrystalline silicon doped layer is 10-30nm, the thickness of the N-type microcrystalline silicon oxygen-doped layer is 10-20nm, and the thickness of the N-type microcrystalline silicon doped layer is 2-8nm.

2. The double-sided microcrystalline heterojunction battery according to claim 1, characterized in that: The ratio of the effective boron doping concentration of the P-type microcrystalline silicon doping layer, the effective boron doping concentration of the P-type microcrystalline silicon carbide doping layer and the effective phosphorus doping concentration of the N-type microcrystalline silicon oxygen doping layer, the effective phosphorus doping concentration of the N-type microcrystalline silicon doping layer is 1:0.5-1.5:1-20:0.4-20.

3. The double-sided microcrystalline heterojunction battery according to claim 1, characterized in that: The ratio of the effective boron doping concentration to the effective carbon doping concentration of the P-type microcrystalline silicon carbide doping layer is 1:0.2-1.

4. The double-sided microcrystalline heterojunction battery according to any one of claims 1 to 3, characterized in that: The effective boron doping concentration of the P-type microcrystalline silicon carbide doped layer is 5e18 cm -3 -1.5e20 cm -3 .

5. The double-sided microcrystalline heterojunction battery according to any one of claims 1 to 3, characterized in that: The effective boron doping concentration of the P-type microcrystalline silicon doped layer is 1e19 cm -3 -3e21 cm -3 The effective phosphorus doping concentration of the N-type microcrystalline silicon oxygen-doped layer is 1e18 cm -3 -5e20 cm -3 The effective phosphorus doping concentration of the N-type microcrystalline silicon doping layer is 5e18 cm -3 -2e21 cm -3 .

6. The double-sided microcrystalline heterojunction battery according to claim 1, characterized in that: The thickness ratio of the P-type microcrystalline silicon doping layer, the P-type microcrystalline silicon carbide doping layer and the second intrinsic amorphous silicon layer is 1:0.25-0.5:0.3-0.5; And / or, the thickness of the second intrinsic amorphous silicon layer is 4-8 nm, and the thickness of the first intrinsic silicon layer is 3-6 nm.

7. The double-sided microcrystalline heterojunction battery according to claim 1, characterized in that: The double-sided microcrystalline heterojunction battery also includes a transparent conductive film and a metal silver gate electrode respectively arranged on the outer surface of the N-type microcrystalline silicon doping layer and the outer surface of the P-type microcrystalline silicon doping layer.

8. A method for manufacturing a double-sided microcrystalline heterojunction battery, characterized in that: It is used to prepare a double-sided microcrystalline heterojunction battery as described in any one of claims 1 to 7, and comprises the following steps: S1, provide double-sided velvet silicon wafer; S2, depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer; S3, depositing a first intrinsic silicon layer on the front side of the silicon wafer; S4, depositing an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer in sequence on the outer surface of the first intrinsic silicon layer; S5, directly depositing a P-type microcrystalline silicon carbide doped layer on the outer surface of the second intrinsic amorphous silicon layer, the corresponding deposition conditions include: temperature of 50-100° C., process gas of SiH4, CH4, B2H6, H2; S6. Depositing a P-type microcrystalline silicon doping layer on the outer surface of the P-type microcrystalline silicon carbide doping layer.

9. A method for manufacturing a double-sided microcrystalline heterojunction battery, characterized in that: It is used to prepare a double-sided microcrystalline heterojunction battery as described in any one of claims 1 to 7, and comprises the following steps: S1, provide double-sided velvet silicon wafer; S2, depositing a second intrinsic amorphous silicon layer on the back side of the silicon wafer; S3, depositing a first intrinsic silicon layer on the front side of the silicon wafer; S4, depositing an N-type microcrystalline silicon oxygen-doped layer and an N-type microcrystalline silicon doped layer in sequence on the outer surface of the first intrinsic silicon layer; S501, depositing a microcrystalline silicon carbide seed layer with a thickness of 1-2 nm on the outer surface of the second intrinsic amorphous silicon layer, wherein the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: a temperature of 50-150° C., and process gases of SiH4 and H2; or, the corresponding deposition conditions of the microcrystalline silicon carbide seed layer include: a temperature of 50-150° C., and process gases of SiH4, CH4, and H2; S502, depositing a P-type microcrystalline silicon carbide doped layer on the outer surface of the microcrystalline silicon carbide seed layer, wherein the corresponding deposition conditions include: a temperature of 50-100° C., and process gases of SiH4, CH4, B2H6, and H2; S6. Depositing a P-type microcrystalline silicon doping layer on the outer surface of the P-type microcrystalline silicon carbide doping layer.

10. The method for manufacturing a double-sided microcrystalline heterojunction battery according to claim 8 or 9, characterized in that: The method for manufacturing a double-sided microcrystalline heterojunction battery also includes at least one of the following features: Feature 1: The deposition conditions of the P-type microcrystalline silicon carbide doped layer also include: gas pressure of 300-700 Pa, power density of 400-4000 mW / cm 2 , time is 15-40s; Feature 2: The deposition conditions of the P-type microcrystalline silicon doped layer also include: temperature of 100°C-150°C, process gases of SiH4, H2, B2H6, gas pressure of 300-700Pa, power density of 400-5000mW / cm 2 , deposition time is 180-240s; Feature 3: The corresponding deposition conditions of the microcrystalline silicon carbide seed layer also include: gas pressure of 300-500Pa, power density of 400-1600mW / cm 2 , deposition time is 30-60s; Feature 4: Deposition conditions of N-type microcrystalline silicon oxygen-doped layer include: temperature of 100°C-150°C, process gas of SiH4, H2, CO2, PH3, gas pressure of 300-700Pa, power density of 400-4000mW / cm 2 , deposition time is 160-200s; Feature 5. The deposition conditions of the N-type microcrystalline silicon doped layer include: temperature of 100°C-150°C, process gases of SiH4, H2, PH3, gas pressure of 300-700Pa, power density of 400-3000mW / cm 2 , deposition time is 20-60s; Feature 6: The method for manufacturing the double-sided microcrystalline heterojunction battery further comprises: S7, forming transparent conductive films on the outer surfaces of the N-type microcrystalline silicon doping layer and the P-type microcrystalline silicon doping layer respectively; S8. Form metal silver gate electrodes on the outer surfaces of the transparent conductive film on the front and back sides respectively.

11. A photovoltaic module, characterized in that: It comprises a double-sided microcrystalline heterojunction battery as described in any one of claims 1 to 7, or a double-sided microcrystalline heterojunction battery manufactured by the manufacturing method of a double-sided microcrystalline heterojunction battery as described in any one of claims 8 to 10.

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