Light emitting chip and display panel

Abstract

The application relates to a light-emitting chip and a display panel. The light-emitting chip comprises a substrate, a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are stacked on the substrate, the light-emitting layer is located between the first and second semiconductor layers, and the first and second semiconductor layers respectively transmit electrons and holes towards the light-emitting layer to recombine and emit light after being excited; a first diffusion layer and a second diffusion layer are further arranged between the light-emitting layer and the second semiconductor layer, the first diffusion layer is located between the second semiconductor layer and the second diffusion layer, the band gap of the first diffusion layer is greater than the band gap of the second semiconductor layer and less than or equal to the band gap of the second diffusion layer, and the first and second diffusion layers are used for increasing the transmission angle of the holes so that the holes can more uniformly enter the light-emitting layer. The light-emitting chip of the application increases the transmission angle of the holes by setting the band gaps of the first and second diffusion layers, so that the holes can more uniformly enter the holes of the light-emitting layer, thereby improving the light-emitting efficiency of the light-emitting chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a light emitting chip and a display panel comprising the light emitting chip. BACKGROUND

[0002] In the technical field of display, a light emitting chip generally comprises a substrate, a first semiconductor layer, a light emitting layer and a second semiconductor layer which are stacked in sequence. The first semiconductor layer and the second semiconductor layer are excited by an external current to respectively transport electrons and holes towards the light emitting layer, and the electrons and the holes are allowed to recombine in the light emitting layer and emit light outward.

[0003] However, in the prior art, due to uneven distribution of current density, part of the electrons may pass through the light emitting layer into the second semiconductor layer to interact with the holes, thereby reducing the transmission angle of the holes in the second semiconductor layer, affecting the hole transmission from the second semiconductor layer to the light emitting layer, and reducing the recombination rate of the holes and the electrons in the light emitting layer, and further reducing the light emitting efficiency of the light emitting chip. SUMMARY

[0004] In view of the above deficiencies of the prior art, the present application aims to provide a light emitting chip with improved light emitting efficiency, and a display panel comprising the light emitting chip, which specifically comprises the following technical solutions.

[0005] In a first aspect, the present application provides a light emitting chip, comprising a substrate, and a first semiconductor layer, a light emitting layer and a second semiconductor layer which are stacked on the substrate. The light emitting layer is located between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are excited to respectively transport electrons and holes towards the light emitting layer for recombination and light emission.

[0006] A first diffusion layer and a second diffusion layer are further provided between the light emitting layer and the second semiconductor layer. The first diffusion layer is located between the second semiconductor layer and the second diffusion layer. The band gap of the first diffusion layer is greater than the band gap of the second semiconductor layer and less than or equal to the band gap of the second diffusion layer. The first diffusion layer and the second diffusion layer are used to increase the transmission angle of the holes to make the holes more uniformly enter the light emitting layer.

[0007] The light emitting chip of the present application stacks the first semiconductor layer, the light emitting layer and the second semiconductor layer on the surface of the substrate, so that the first semiconductor layer can be excited by the external current and transport electrons towards the light emitting layer, and the second semiconductor layer can be excited by the external current and transport holes towards the light emitting layer. The electrons of the first semiconductor layer and the holes of the second semiconductor layer can recombine in the light emitting layer and emit light outward, thereby realizing the display function of the light emitting chip of the present application.

[0008] The light emitting chip further sets the first diffusion layer and the second diffusion layer between the light emitting layer and the second semiconductor layer, so that the first diffusion layer and the second diffusion layer with the band gap width greater than that of the second semiconductor layer can cooperate with each other, increase the transmission angle of the holes transmitted from the second semiconductor layer to the light emitting layer, so that the holes can enter the light emitting layer more uniformly, improve the recombination rate of the holes and the electrons in the light emitting layer, and further improve the light emitting efficiency of the light emitting chip.

[0009] In an embodiment, the first diffusion layer is a P-type semiconductor, wherein the first diffusion layer contains one or more of aluminum element, gallium element and indium element; and / or the second diffusion layer is a P-type semiconductor, wherein the second diffusion layer contains one or more of aluminum element, gallium element and indium element.

[0010] In the embodiment, based on the content of the electrons being greater than that of the holes in the light emitting layer, the first diffusion layer and / or the second diffusion layer is set as a P-type semiconductor to cooperate with the second semiconductor layer, increase the content of the holes entering the light emitting layer, improve the recombination rate of the electrons and the holes in the light emitting layer, and further improve the light emitting efficiency of the light emitting chip.

[0011] In an embodiment, the light emitting chip further comprises a transition layer, the transition layer is arranged between the first diffusion layer and the second diffusion layer, and the band gap width of the transition layer is less than the band gap width of the first diffusion layer and the band gap width of the second diffusion layer.

[0012] In the embodiment, the transition layer with the band gap width less than that of the first diffusion layer and the second diffusion layer is arranged, so that the holes transmitted by the second semiconductor layer can be stored in the potential well structure formed by the cooperation of the first diffusion layer, the second diffusion layer and the transition layer, thereby improving the hole distribution between the second semiconductor layer and the light emitting layer, further increasing the transmission angle of the holes, and making the holes in the second semiconductor layer enter the light emitting layer more uniformly.

[0013] In an embodiment, the thickness of the first diffusion layer is between 5nm and 40nm; and / or, the thickness of the second diffusion layer is between 5nm and 40nm; and / or, the thickness of the transition layer is between 5nm and 40nm.

[0014] In an embodiment, the light emitting chip further comprises an intermediate layer, the intermediate layer is arranged between the first diffusion layer and the second diffusion layer, the doping source of the first diffusion layer and the doping source of the second diffusion layer both include magnesium element, and the intermediate layer is used to accept the magnesium element diffused from the first diffusion layer and the second diffusion layer to the intermediate layer, so as to reduce the growth crystal defects on the first diffusion layer and the second diffusion layer.

[0015] In the embodiment, the intermediate layer is arranged between the first diffusion layer and the second diffusion layer, so that the magnesium elements diffused from the first diffusion layer and the second diffusion layer can diffuse into the intermediate layer, and a doped extension region with a gradient change of the doping concentration of the magnesium elements can be formed between the intermediate layer and the first diffusion layer and between the intermediate layer and the second diffusion layer, thereby reducing the growth crystal defects on the first diffusion layer and the second diffusion layer.

[0016] In an embodiment, the intermediate layer is arranged between the first diffusion layer and the transition layer, and the intermediate layer is used to receive the magnesium elements diffused from the first diffusion layer and the transition layer to the intermediate layer, so as to reduce the growth crystal defects on the first diffusion layer and the transition layer; and / or the intermediate layer is arranged between the second diffusion layer and the transition layer, and the intermediate layer is used to receive the magnesium elements diffused from the second diffusion layer and the transition layer to the intermediate layer, so as to reduce the growth crystal defects on the second diffusion layer and the transition layer.

[0017] In the embodiment, the intermediate layer is arranged between the first diffusion layer and the transition layer, so that the magnesium elements diffused from the first diffusion layer and the transition layer can diffuse into the intermediate layer, and a doped extension region with a gradient change of the doping concentration of the magnesium elements can be formed between the intermediate layer and the first diffusion layer and between the intermediate layer and the transition layer, thereby reducing the growth crystal defects on the first diffusion layer and the transition layer.

[0018] and / or the intermediate layer is arranged between the second diffusion layer and the transition layer, so that the magnesium elements diffused from the second diffusion layer and the transition layer can diffuse into the intermediate layer, and a doped extension region with a gradient change of the doping concentration of the magnesium elements can be formed between the intermediate layer and the second diffusion layer and between the intermediate layer and the transition layer, thereby reducing the growth crystal defects on the second diffusion layer and the transition layer.

[0019] In an embodiment, the thickness of the intermediate layer is between 2 nm and 10 nm.

[0020] In the embodiment, the thickness of the intermediate layer is limited to between 2 nm and 10 nm, so as to avoid affecting the diffusion quality of the magnesium elements due to the too thin thickness of the intermediate layer, and to avoid affecting the transmission efficiency of the holes from the second semiconductor layer to the light-emitting layer due to the too thick thickness of the intermediate layer.

[0021] In an embodiment, the spacing between the second semiconductor layer and the light-emitting layer is between 12 nm and 300 nm.

[0022] In the embodiment, the spacing between the second semiconductor layer and the light-emitting layer is limited to between 12 nm and 300 nm, so as to avoid affecting the transmission efficiency of the holes in the second semiconductor layer to the light-emitting layer due to the too large spacing, and to avoid affecting the distribution of the holes due to the too small spacing, so that the electrons with a higher mobility can pass through the light-emitting layer into the second semiconductor layer.

[0023] In an embodiment, the first diffusion layer and the second diffusion layer each have a doping concentration greater than or equal to 1E18 atoms / cm 3 .

[0024] In the embodiment, the first diffusion layer and the second diffusion layer each have a doping concentration greater than or equal to 1E18 atoms / cm 3 , so that the hole content in the first diffusion layer and the second diffusion layer is relatively large, so as to increase the hole content entering the light-emitting layer.

[0025] In an embodiment, the light-emitting chip further comprises a buffer layer between the first semiconductor layer and the light-emitting layer, the buffer layer being used to release the stress between the first semiconductor layer and the light-emitting layer.

[0026] In the embodiment, the buffer layer is arranged between the first semiconductor layer and the light-emitting layer to release the stress between the first semiconductor layer and the light-emitting layer, so as to reduce the lattice mismatch on the first semiconductor layer and the light-emitting layer.

[0027] In a second aspect, the embodiments of the present application provide a display panel, comprising a driving backboard and a light-emitting chip, the light-emitting chip being carried on the driving backboard, and the driving backboard being used to control the light-emitting chip to emit light.

[0028] In the embodiment, the light-emitting chip is carried on the driving backboard, so that the driving backboard can control the electric signal to enter the light-emitting chip to drive the light-emitting chip to emit light, thereby realizing the display function of the display panel of the present application.

[0029] It can be understood that, since the display panel provided by the second aspect of the present application adopts the light-emitting chip provided by the first aspect of the present application, it also has the beneficial effect of improving the light-emitting efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 FIG. 1 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0031] Figure 2 FIG. 2 is a structural schematic diagram of a light-emitting chip provided in an embodiment of the present application;

[0032] Figure 3 FIG. 3 is another structural schematic diagram of a light-emitting chip provided in an embodiment of the present application;

[0033] Figure 4 FIG. 4 is another structural schematic diagram of a light-emitting chip provided in an embodiment of the present application;

[0034] Figure 5 FIG. 5 is another structural schematic diagram of a light-emitting chip provided in an embodiment of the present application;

[0035] Figure 6 Another structural schematic view of a light emitting chip provided in an embodiment of the present application;

[0036] Figure 7 Another structural schematic view of a light emitting chip provided in an embodiment of the present application;

[0037] Figure 8 Another structural schematic view of a light emitting chip provided in an embodiment of the present application;

[0038] Figure 9 Another structural schematic view of a light emitting chip provided in an embodiment of the present application;

[0039] Figure 10 A structural schematic view of a light emitting chip in the prior art.

[0040] The reference signs are: 200 - display panel; 201 - driving back plate; 100 - light emitting chip; 10 - substrate; 20 - first semiconductor layer; 30 - light emitting layer; 40 - second semiconductor layer; S - interval; 51 - first diffusion layer; D1 - first thickness; 52 - second diffusion layer; D2 - second thickness; 53 - transition layer; D3 - third thickness; 54 - intermediate layer; D4 - fourth thickness; 60 - buffer layer; 100' - light emitting chip; 10' - substrate; 20' - first semiconductor layer; 30' - light emitting layer; 40' - second semiconductor layer. DETAILED DESCRIPTION

[0041] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0042] The following description of the embodiments is provided with reference to the accompanying drawings, which illustrate specific embodiments in which the present application can be implemented. The serial numbers of the components in the text, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc., are only the direction of the accompanying drawings, therefore, the directional terms used are for better, clearer illustration and understanding of the present application, and are not indicative or implied that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0043] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or integrally connected; can be mechanically connected; can be directly connected, or indirectly connected through an intermediate medium; can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the drawings are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include", "may include", "contain" or "may contain" used in the present application represent the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit other one or more functions, operations, elements, etc. In addition, the terms "include" or "contain" represent the existence of the corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusion.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the specification of the present application is only for the purpose of describing specific embodiments and is not intended to limit the present application.

[0045] Please refer to Figure 1 The structural schematic diagram of the display panel 200 provided in an embodiment of the present application is shown.

[0046] As Figure 1 The display panel 200 provided by the present application includes a driving backboard 201 and a plurality of light emitting chips 100. Each light emitting chip 100 is mounted on the same surface of the driving backboard 201. The driving backboard 201 is further provided with a control chip (not shown in the figure) and a plurality of control circuits (not shown in the figure). The control chip is connected to each light emitting chip 100 through each control circuit, so that the control chip can provide control signals for each light emitting chip 100 through the control circuit. Each light emitting chip 100 emits light outward under the action of the control signal, thereby realizing the display function of the display panel 200 of the present application.

[0047] As Figure 1 The plurality of light emitting chips 100 are arrayed on the driving backboard 201. In other embodiments, the arrangement mode of the light emitting chips 100 can also be other modes, which are not particularly limited by the applicant.

[0048] On the other hand, in order to clearly show the structure in the display panel 200, Figure 1 Only the light emitting chip 100 and the driving back plate 201 are exemplarily introduced, and do not represent the actual structure and shape of the display panel 200. That is, in other embodiments of the display panel 200 of the present application, the shape and area of the driving back plate 201 can be adjusted according to the actual scene. At the same time, the shape, area and arrangement of each light emitting chip 100 can also be adjusted. In the actual display panel 200 product, the area of each light emitting chip 100 is usually small, and the arrangement density is usually large.

[0049] Please refer to Figure 2 The structure diagram of the light emitting chip 100 provided in an embodiment of the present application is shown.

[0050] As Figure 2 shown, the light emitting chip 100 provided by the present application includes a substrate 10, a first semiconductor layer 20, a light emitting layer 30 and a second semiconductor layer 40. Among them, the first semiconductor layer 20, the light emitting layer 30 and the second semiconductor layer 40 are sequentially stacked on the surface of the substrate 10. It can be understood that the first semiconductor layer 20 is an N-type semiconductor, which is used to provide electrons for the light emitting chip 100, and the second semiconductor layer 40 is a P-type semiconductor, which is used to provide holes for the light emitting chip 100. When the electric signal flows into the light emitting chip 100 and makes the light emitting chip 100 forward conducting, the current acting on the first semiconductor layer 20 will excite the electrons in the first semiconductor layer 20 to move to the second semiconductor layer 40. Correspondingly, the current acting on the second semiconductor layer 40 will excite the holes in the second semiconductor layer 40 to move to the first semiconductor layer 20. At the same time, when the above-mentioned holes and electrons meet and recombine, light will be emitted outward, thereby achieving the purpose of light emission.

[0051] At the same time, the light emitting layer 30 is located between the first semiconductor layer 20 and the second semiconductor layer 40, and the light emitting layer 30 is used to carry the electrons emitted from the first semiconductor layer 20 and the holes emitted from the second semiconductor layer 40. It can be understood that the light emitted by the light emitting chip 100 is emitted from the light emitting layer 30. On the other hand, the light emitting layer 30 will increase the recombination rate of electrons and holes, and improve the recombination light emitting efficiency of the light emitting chip 100.

[0052] The light emitting chip 100 provided by the present application further includes a first diffusion layer 51 and a second diffusion layer 52, both of which are arranged between the light emitting layer 30 and the second semiconductor layer 40, and the first diffusion layer 51 is located between the second semiconductor layer 40 and the second diffusion layer 52. Among them, the band gap of the first diffusion layer 51 is greater than the band gap of the second semiconductor layer 40, and less than or equal to the band gap of the second diffusion layer 52.

[0053] Based on the fact that the electron content in the first semiconductor layer 20 is relatively greater than the hole content in the second semiconductor layer 40, when the light emitting chip 100 is forwardly turned on, the electrons with high mobility in the first semiconductor layer 20 can pass through the light emitting layer 30 into the second semiconductor layer 40. It can be understood that the band gap of the first diffusion layer 51 is greater than the band gap of the second semiconductor layer 40, and the band gap of the second diffusion layer 52 is also greater than the band gap of the second semiconductor layer 40, so that the electrons with high mobility cannot pass through the second diffusion layer 52 and the first diffusion layer 51 into the second semiconductor layer 40, thereby avoiding the influence of the electrons with high mobility on the holes in the second semiconductor layer 40.

[0054] At the same time, based on the fact that the band gap of the second diffusion layer 52 is greater than the band gap of the second semiconductor layer 40, the holes in the second semiconductor layer 40 can be blocked from entering the light emitting layer 30. It can be understood that the first diffusion layer 51 can reduce the difference between the band gaps of the second diffusion layer 52 and the second semiconductor layer 40, so as to facilitate the holes in the second semiconductor layer 40 to enter the light emitting layer 30.

[0055] Therefore, the mutual matching of the first diffusion layer 51 and the second diffusion layer 52 can block the electrons in the first semiconductor layer 20 from entering the second semiconductor layer 40, thereby ensuring the hole content in the second semiconductor layer 40.

[0056] At the same time, the setting of the band gaps of the first diffusion layer 51 and the second diffusion layer 52 enables the holes in the second semiconductor layer 40 to pass through the first diffusion layer 51 and the second diffusion layer 52 into the light emitting layer 30. And increases the transmission angle of the holes in the second semiconductor layer 40, so that the holes in the second semiconductor layer 40 can more uniformly enter the light emitting layer 30, so as to increase the recombination rate of the electrons and holes in the light emitting layer 30. Further improve the light emitting efficiency of the light emitting chip 100 of the present application.

[0057] In an embodiment, the first diffusion layer 51 is a P-type semiconductor layer. Based on the fact that the majority carriers in the P-type semiconductor layer are holes. It can be understood that the first diffusion layer 51 is set to a P-type semiconductor layer, which is conducive to cooperating with the second semiconductor layer 40 to increase the hole content entering the light emitting layer 30, thereby increasing the recombination rate of the electrons and holes in the light emitting layer 30. Further improve the light emitting efficiency of the light emitting chip 100 of the present application.

[0058] The first diffusion layer 51 contains one or more of aluminum element, gallium element and indium element. For example, the first diffusion layer 51 can be Al x Ga (1-x-y) In x N. Wherein x is greater than or equal to 0 and less than or equal to 1; y is greater than or equal to 0 and less than or equal to 1.

[0059] The second diffusion layer 52 is a P-type semiconductor layer, which cooperates with the first diffusion layer 51 and the second semiconductor layer 40 to further increase the hole content in the light emitting chip 100 and improve the recombination rate of the electrons and holes in the light emitting layer 30.

[0060] The second diffusion layer 52 contains one or more of aluminum element, gallium element and indium element. For example, the second diffusion layer 52 can be Al x Ga (1-x-y) In x N, wherein x is greater than or equal to 0 and less than or equal to 1, and y is greater than or equal to 0 and less than or equal to 1.

[0061] In the embodiment, the materials of the first diffusion layer 51 and the second diffusion layer 52 can be different, so that the band gap of the first diffusion layer 51 is smaller than the band gap of the second diffusion layer 52.

[0062] It can be understood that the component sizes of the elements of the first diffusion layer 51 and the second diffusion layer 52 can be adjusted by the growth conditions. For example, one or more of the growth temperature, the growth rate, the growth pressure and the growth atmosphere in the growth conditions can be changed when the first diffusion layer 51 and the second diffusion layer 52 are generated. And the growth temperature is between 700-1100℃, the growth rate is between , the growth pressure is between 50-600mbar, and the ratio of nitrogen and hydrogen in the growth atmosphere is between 0%-100%.

[0063] In another embodiment, only the first diffusion layer 51 can be set as a P-type semiconductor layer. In another embodiment, only the second diffusion layer 52 can also be set as a P-type semiconductor layer.

[0064] Please refer to Figure 3 for another structural schematic diagram of the light emitting chip 100 provided in an embodiment of the present application.

[0065] As Figure 3 shown, the light emitting chip 100 further includes a transition layer 53, which is located between the first diffusion layer 51 and the second diffusion layer 52. The band gap of the transition layer 53 is smaller than the band gap of the first diffusion layer 51 and the band gap of the second diffusion layer 52.

[0066] The band gap of the transition layer 53 is set so that the transition layer 53 can cooperate with the first diffusion layer 51 and the second diffusion layer 52 to form a potential well structure. It can be understood that the holes in the second semiconductor layer 40 can be stored in the potential well structure when being transported to the light emitting layer 30. Thus, the holes can be stored in the potential well structure formed by the transition layer 53 when entering the light emitting layer 30, thereby increasing the hole distribution range between the second semiconductor layer 40 and the light emitting layer 30.

[0067] Meanwhile, when the light emitting chip 100 is forwardly conducted, the holes stored in the potential well structure can also be transported towards the light emitting layer 30, thereby increasing the transport angle of the holes and enabling the holes transported by the second semiconductor layer 40 to enter the light emitting layer 30 more uniformly.

[0068] In another embodiment, the transition layer 53 can also be arranged between the first diffusion layer 51 and the second semiconductor layer 40. In another embodiment, the transition layer 53 can also be arranged between the second diffusion layer 52 and the light emitting layer 30.

[0069] Please refer to Figure 4 for another structural schematic diagram of the light emitting chip 100 provided in an embodiment of the present application.

[0070] As Figure 4 shown, the light emitting chip 100 further comprises an intermediate layer 54 arranged between the first diffusion layer 51 and the second diffusion layer 52. The doping source of the first diffusion layer 51 and the doping source of the second diffusion layer 52 comprise magnesium elements, while the intermediate layer 54 does not contain magnesium elements. Due to the memory diffusion effect of the magnesium elements, it can be understood that the magnesium elements in the first diffusion layer 51 can diffuse to the intermediate layer 54 and enable a doping extension region with a gradient change in the doping concentration of the magnesium elements to be formed between the first diffusion layer 51 and the intermediate layer 54, thereby reducing the growth crystal defects on the first diffusion layer 51.

[0071] Meanwhile, the magnesium elements in the second diffusion layer 52 can also diffuse to the intermediate layer 54 and enable a doping extension region with a gradient change in the doping concentration of the magnesium elements to be formed between the second diffusion layer 52 and the intermediate layer 54, thereby reducing the growth crystal defects on the second diffusion layer 52.

[0072] It can be understood that the arrangement of the intermediate layer 54 can reduce the growth crystal defects on the first diffusion layer 51 and the second diffusion layer 52, and even possibly eliminate the growth crystal defects on the first diffusion layer 51 and the second diffusion layer 52, thereby improving the transport efficiency of the holes entering the light emitting layer 30 through the first diffusion layer 51, the second diffusion layer 52 and the intermediate layer 54 and improving the anti-static performance of the light emitting chip 100.

[0073] On the other hand, the magnesium element in the doping source of the first diffusion layer 51 and the doping source of the second diffusion layer 52 can also improve the electrical properties of the first diffusion layer 51 and the second diffusion layer 52.

[0074] In the embodiment, the material of the intermediate layer 54 can be GaN. In another embodiment, the material of the intermediate layer 54 can also be Al x Ga (1-x-y) In x N. Wherein, x is greater than or equal to 0 and less than or equal to 1; y is greater than or equal to 0 and less than or equal to 1. It can be understood that, in the growth process of the intermediate layer 54, the growth conditions of the intermediate layer 54 are between the growth conditions of the first diffusion layer 51 and the second diffusion layer 52, so that the composition of each element of the intermediate layer 54 is inconsistent with the composition of each element of the first diffusion layer 51 and the second diffusion layer 52.

[0075] Please refer to Figure 5 Another structural schematic diagram of the light emitting chip 100 provided in an embodiment of the present application is shown.

[0076] As Figure 5 shown, the intermediate layer 54 is arranged between the first diffusion layer 51 and the transition layer 53. The doping source of the first diffusion layer 51 and the doping source of the transition layer 53 include magnesium elements, and the intermediate layer 54 does not contain magnesium elements. Due to the memory diffusion effect of the magnesium element, it can be understood that the magnesium element in the first diffusion layer 51 can diffuse to the intermediate layer 54, and a doping extension region with a gradient change in the doping concentration of the magnesium element can be formed between the first diffusion layer 51 and the intermediate layer 54, thereby reducing the growth crystal defects on the first diffusion layer 51.

[0077] On the other hand, as Figure 5 shown, the intermediate layer 54 is also arranged between the second diffusion layer 52 and the transition layer 53. Based on the doping source of the second diffusion layer 52 and the doping source of the transition layer 53 include magnesium elements, and the intermediate layer 54 does not contain magnesium elements. It can be understood that the magnesium element in the second diffusion layer 52 can diffuse to the intermediate layer 54, and a doping extension region with a gradient change in the doping concentration of the magnesium element can be formed between the second diffusion layer 52 and the intermediate layer 54, thereby reducing the growth crystal defects on the second diffusion layer 52.

[0078] At the same time, the magnesium element in the transition layer 53 can also diffuse to the intermediate layer 54, and a doping extension region with a gradient change in the doping concentration of the magnesium element can be formed between the transition layer 53 and the intermediate layer 54, thereby reducing the growth crystal defects on the transition layer 53.

[0079] It can be understood that the setting of the intermediate layer 54 can reduce the growth crystal defects on the first diffusion layer 51, the second diffusion layer 52 and the transition layer 53, and even can eliminate the growth crystal defects on the first diffusion layer 51, the second diffusion layer 52 and the transition layer 53, thereby improving the transmission efficiency of the holes into the light-emitting layer 30 through the first diffusion layer 51, the second diffusion layer 52, the transition layer 53 and the intermediate layer 54, and improving the anti-static performance of the light-emitting chip 100.

[0080] On the other hand, the magnesium element in the doping source of the first diffusion layer 51, the doping source of the second diffusion layer 52 and the doping source of the transition layer 53 can be used to improve the electrical performance of the first diffusion layer 51, the second diffusion layer 52 and the transition layer 53.

[0081] In another embodiment, as shown in FIG. 4, the intermediate layer 54 can also be arranged between the first diffusion layer 51 and the second semiconductor layer 40 to reduce or eliminate the growth crystal defects on the first diffusion layer 51 and the second semiconductor layer 40. Figure 6 In another embodiment, as shown in FIG. 5, the intermediate layer 54 can also be arranged between the second diffusion layer 52 and the light-emitting layer 30 to reduce or eliminate the growth crystal defects between the second diffusion layer 52 and the light-emitting layer 30. Figure 7 In another embodiment, as shown in FIG. 6, the intermediate layer 54 can be arranged between the first diffusion layer 51 and the second semiconductor layer 40, and between the second diffusion layer 52 and the light-emitting layer 30, respectively. Figure 8

[0082] In an embodiment, referring back to FIG. 4, the fourth thickness D4 of the intermediate layer 54 is between 2nm-10nm. Figure 5 The doping concentration of the magnesium element in the first diffusion layer 51, the second diffusion layer 52 and the transition layer 53 is relatively high. It can be understood that when the fourth thickness D4 is less than 2nm, the quality of the magnesium element in the intermediate layer 54 forming a doped extension region with a doping concentration gradient is relatively poor, which can cause the difference between the magnesium doping concentration of the intermediate layer 54 and the magnesium doping concentration of the adjacent structure to be small. Thus, the diffusion quality of the magnesium element is relatively poor, and it is difficult to ensure the reduction of the growth crystal defects of the first diffusion layer 51, the second diffusion layer 52 and the transition layer 53.

[0083] The intermediate layer 54 can be arranged as undoped gallium nitride. It can be understood that when the fourth thickness D4 is greater than 10nm, the resistance of the intermediate layer 54 will be relatively large, thereby reducing the efficiency of the second semiconductor layer 40 transmitting holes to the light-emitting layer 30.

[0084]

[0085] ​​Therefore, the intermediate layer 54 with a thickness of 2nm-10nm can reduce the growth defects of the first diffusion layer 51, the second diffusion layer 52 and the transition layer 53, and can ensure the hole transport efficiency of the second semiconductor layer 40 to the light-emitting layer 30.

[0086] In an embodiment, referring back to Figure 5 , the interval S between the second semiconductor layer 40 and the light-emitting layer 30 is 12nm-300nm. It can be understood that when the interval S between the second semiconductor layer 40 and the light-emitting layer 30 is greater than 300nm, the holes in the second semiconductor layer 40 will be difficult to transport to the light-emitting layer 30 due to the too large interval S, thereby reducing the hole transport efficiency of the second semiconductor layer 40.

[0087] When the interval S between the second semiconductor layer 40 and the light-emitting layer 30 is less than 12nm, the first diffusion layer 51 and the second diffusion layer 52 between the second semiconductor layer 40 and the light-emitting layer 30 will reduce the blocking ability of the electrons, so that the electrons with high mobility in the first semiconductor layer 20 can enter the second semiconductor layer 40 to affect the distribution of holes.

[0088] Therefore, the interval S of 12nm-300nm can ensure the blocking effect of the first diffusion layer 51 and the second diffusion layer 52 to the electrons with high mobility, and also ensure the transport efficiency of the holes in the second semiconductor layer 40.

[0089] In an embodiment, as shown in Figure 5 , the first thickness D1 of the first diffusion layer 51 is 5nm-40nm.

[0090] In an embodiment, as shown in Figure 5 , the second thickness D2 of the second diffusion layer 52 is 5nm-40nm.

[0091] In an embodiment, as shown in Figure 5 , the third thickness D3 of the transition layer 53 is 5nm-40nm.

[0092] In an embodiment, the doping concentration of the first diffusion layer 51 and the doping concentration of the second diffusion layer 52 are both greater than or equal to 1E18atoms / cm 3 . The size of the doping concentration of the structure can affect the hole content in the structure. It can be understood that the doping concentration greater than or equal to 1E18atoms / cm 3 ensures the hole content in the first diffusion layer 51 and the second diffusion layer 52, and further ensures the hole content improvement effect of the first diffusion layer 51 and the second diffusion layer 52 to the light-emitting chip 100.

[0093] In one embodiment, the doping concentration of the transition layer 53 is also greater than or equal to 1E18 atoms / cm². 3 The doping concentration of a structure can affect the hole content within that structure. Understandably, a doping concentration greater than or equal to 1E¹⁸ atoms / cm² is desirable. 3 The doping concentration ensures the hole content in the transition layer 53. This further guarantees the effect of the transition layer 53 on improving the hole content of the light-emitting chip 100 of this application. Please refer to... Figure 9 The diagram shown is another structural schematic of the light-emitting chip 100 provided in one embodiment of this application.

[0094] like Figure 9 As shown, multiple transition layers 53 can be provided, and an intermediate layer 54 is provided between each pair of adjacent transition layers 53. The bandgap width of the intermediate layer 54 is smaller than the bandgap width of the two adjacent transition layers 53. It is understandable that the matching arrangement of multiple transition layers 53 and intermediate layers 54 allows alternating barriers and potential wells to be formed between the first diffusion layer 51 and the second diffusion layer 52, thereby expanding the hole storage range of the second semiconductor layer 40 and further increasing the hole propagation angle, thus enabling holes in the second semiconductor layer 40 to be more uniformly transported to the light-emitting layer 30.

[0095] In this embodiment, when preparing multiple transition layers 53, the growth conditions of any two adjacent transition layers 53 can be different, and the intermediate layer 54 can act as a transition between the growth conditions of the two adjacent transition layers 53. In another embodiment, the growth conditions of two adjacent transition layers 53 can also be the same, and the bandgap width of the intermediate layer 54 is smaller than the bandgap width of the two adjacent transition layers 53.

[0096] Please see Figure 10 The diagram shows a schematic of the structure of a light-emitting chip 100' in the prior art.

[0097] like Figure 10 As shown, in the prior art, the light-emitting chip 100' includes a substrate 10', a first semiconductor layer 20', a light-emitting layer 30', and a second semiconductor layer 40' stacked sequentially. The first semiconductor layer 20' is an N-type semiconductor, providing electrons to the light-emitting chip 100', and the second semiconductor layer 40' is a P-type semiconductor, providing holes to the light-emitting chip 100'. When an electrical signal flows into the light-emitting chip 100', causing it to forward conduct, electrons in the first semiconductor layer 20' and holes in the second semiconductor layer 40' are transported towards the light-emitting layer 30', and after recombination in the light-emitting layer 30', light is emitted outward, thereby realizing the display function of the light-emitting chip 100'.

[0098] In the prior art, there is a distribution unevenness based on the density of the current applied on the first semiconductor layer 20' and the second semiconductor layer 40'. It can be understood that part of the electrons in the first semiconductor layer 20' will have a higher mobility under the action of the current. Among them, the electrons with higher mobility can pass through the light-emitting layer 30' into the second semiconductor layer 40', and act with the holes in the second semiconductor layer 40'.

[0099] Since the content of electrons in the light-emitting chip 100' is greater than the content of holes, when the electrons with higher mobility act with the holes, the content of holes in the second semiconductor layer 40' is reduced, and the transmission angle of the second semiconductor layer 40' is reduced. Thus, the distribution of holes in the second semiconductor layer 40' in the light-emitting layer 30' is affected, the recombination rate of electrons and holes in the light-emitting layer 30' is reduced, and the light-emitting efficiency of the light-emitting chip 100' is relatively low.

[0100] Therefore, based on the larger band gap of the first diffusion layer 51 and the second diffusion layer 52. The light-emitting chip 100 of the present application increases the transmission angle of the holes transmitted from the second semiconductor layer 40 to the light-emitting layer 30 by setting the first diffusion layer 51 and the second diffusion layer 52, so that the holes of the second semiconductor layer 40 can more uniformly enter the light-emitting layer 30, thereby improving the light-emitting efficiency of the light-emitting chip 100 of the present application.

[0101] In an embodiment, referring back to Figure 9 The light-emitting chip 100 of the present application further comprises a buffer layer 60, which is arranged between the first semiconductor layer 20 and the light-emitting layer 30 to serve as a growth buffer between the first semiconductor layer 20 and the light-emitting layer 30. Thus, the stress between the first semiconductor layer 20 and the light-emitting layer 30 is released, and the lattice mismatch on the first semiconductor layer 20 and the light-emitting layer 30 is reduced.

[0102] It should be understood that the terms "first", "second" and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0103] In the description of the specification, the description using the terms "one embodiment", "some embodiments", "an exemplary embodiment", "an example", "a specific example" or "some examples" etc. means that the particular feature, structure, material or characteristic being described is included in at least one embodiment or example of the application. The illustrative appearances of the above-mentioned terms in various places in the specification are not necessarily intended to refer to the same embodiment or example. Moreover, the particular features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0104] It should be understood that the application is not limited to the examples described above, which can be modified or transformed by a person of ordinary skill in the art according to the above description, and all these modifications and transformations shall fall within the protection scope of the claims of the application. A person of ordinary skill in the art can understand that all or part of the processes of the above embodiments are implemented, and equivalent changes made according to the claims of the application still fall within the scope of the application.

Claims

1. A light emitting chip, characterized by The light emitting chip comprises a substrate, and a first semiconductor layer, a light emitting layer and a second semiconductor layer stacked on the substrate, the light emitting layer is located between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer respectively transport electrons and holes to the light emitting layer to recombine and emit light after being excited; A first diffusion layer and a second diffusion layer are further arranged between the light emitting layer and the second semiconductor layer, the first diffusion layer is located between the second semiconductor layer and the second diffusion layer, the band gap of the first diffusion layer is greater than the band gap of the second semiconductor layer and less than or equal to the band gap of the second diffusion layer, and the first diffusion layer and the second diffusion layer are used to increase the transmission angle of holes to make the holes more uniformly enter the light emitting layer; The light emitting chip further comprises a transition layer, the transition layer is arranged between the first diffusion layer and the second diffusion layer, and the band gap of the transition layer is less than the band gap of the first diffusion layer and the band gap of the second diffusion layer.

2. The light emitting die of claim 1, wherein, The first diffusion layer is a P-type semiconductor, wherein the first diffusion layer contains one or more of aluminum elements, gallium elements and indium elements; and / or The second diffusion layer is a P-type semiconductor, wherein the second diffusion layer contains one or more of aluminum elements, gallium elements and indium elements.

3. The light emitting die of claim 1, wherein, The thickness of the first diffusion layer is between 5nm and 40nm; and / or, the thickness of the second diffusion layer is between 5nm and 40nm; and / or, the thickness of the transition layer is between 5nm and 40nm.

4. The light emitting die of claim 1, wherein, The light emitting chip further comprises an intermediate layer, the intermediate layer is arranged between the first diffusion layer and the second diffusion layer, the doping source of the first diffusion layer and the doping source of the second diffusion layer both contain magnesium elements, and the intermediate layer is used to receive the magnesium elements diffused from the first diffusion layer and the second diffusion layer to the intermediate layer to reduce the growth crystal defects on the first diffusion layer and the second diffusion layer.

5. The light emitting die of claim 4, wherein, The intermediate layer is arranged between the first diffusion layer and the transition layer, and / or the intermediate layer is arranged between the second diffusion layer and the transition layer.

6. The light emitting chip according to claim 4 or 5, characterized in that The thickness of the intermediate layer is between 2nm and 10nm.

7. The light emitting die of any of claims 1-5, wherein, The distance between the second semiconductor layer and the light emitting layer is between 12nm and 300nm.

8. The light emitting die of any of claims 1-5, wherein, The doping concentration of the first diffusion layer and the doping concentration of the second diffusion layer are both greater than or equal to 1E18 atoms / cm3.

9. The light emitting die of any of claims 1-5, wherein, The light emitting chip further comprises a buffer layer, the buffer layer is located between the first semiconductor layer and the light emitting layer, and the buffer layer is used to release the stress between the first semiconductor layer and the light emitting layer.

10. A display panel, characterized by, The light emitting chip comprises a driving backboard and the light emitting chip as claimed in any one of claims 1-9, the light emitting chip is carried on the driving backboard, and the driving backboard is used to control the light emitting chip to emit light.

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