An effective value detection circuit and chip

Abstract

The present disclosure provides an effective value detection circuit and chip. In the effective value detection circuit, a frequency mixing circuit generates a frequency mixing signal according to an input signal and a preset signal; the input signal and the preset signal are both AC signals, and the frequency of the preset signal is lower than the frequency of the input signal; a square circuit generates a square signal according to the frequency mixing signal; a first filter circuit filters the square signal, retains the AC low-frequency component therein, and generates a first filter signal; a first logarithmic conversion circuit performs logarithmic conversion on the first filter signal, and generates an output signal representing the effective value of the input signal. A second filter circuit filters the square signal, retains the DC component and the AC low-frequency component in the square signal, and generates a second filter signal; a second logarithmic conversion circuit suppresses the DC component, performs logarithmic conversion on the AC low-frequency component in the second filter signal, and generates an output signal representing the effective value of the input signal. The present disclosure improves the sensitivity of detecting effective values.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to an effective value detection circuit and a chip. Background Art

[0002] The signal effective value detection circuit and chip are circuits and chips specifically used to measure the effective value of AC signals. Effective value, also known as root mean square value, is a physical quantity that describes the energy of AC signals. The signal effective value detection circuit and chip sample and process the input AC signal through a specific circuit design, and calculate the effective value of the signal.

[0003] Signal effective value detection circuits and chips are widely used in various scenarios in the field of communications to achieve real-time detection of signals and ensure communication quality. For example, in wireless communication base stations, they can be used to detect the effective value of base station transmitted and received signals to ensure signal coverage and quality; in wired communication systems, they can be used to detect the effective value of photoelectric signals to ensure transmission quality and stability.

[0004] The core technical indicator of signal effective value detection circuits and chips is sensitivity, which refers to the minimum signal amount that the chip can detect. For signal effective value detection chips, high sensitivity means the ability to accurately capture and measure the effective value of weak signals, which can enable signal effective value detection chips to better adapt to complex and changing communication environments, improve the signal quality of communication systems, and optimize the energy consumption management of communication systems, which is of great significance to improving the performance of communication systems. Summary of the invention

[0005] The embodiments of the present disclosure provide an effective value detection circuit and a chip with high sensitivity.

[0006] In a first aspect, an embodiment of the present disclosure provides an effective value detection circuit, comprising:

[0007] A mixing circuit, used for mixing an input signal and a preset signal to generate a mixed signal; the input signal and the preset signal are both AC signals, and the frequency of the preset signal is lower than the frequency of the input signal;

[0008] A squaring circuit, used for squaring the mixed signal to generate a square signal; the square signal includes an AC low-frequency component;

[0009] A first filtering circuit is used to filter the square signal, retain the AC low-frequency component in the square signal, and generate a first filtered signal;

[0010] The first logarithmic conversion circuit is used to perform logarithmic conversion on the first filtered signal to generate an output signal, where the output signal is used to represent the effective value of the input signal.

[0011] In a second aspect, an embodiment of the present disclosure provides another effective value detection circuit, comprising:

[0012] A mixing circuit, used for mixing an input signal and a preset signal to generate a mixed signal; the input signal and the preset signal are both AC signals, and the frequency of the preset signal is lower than the frequency of the input signal;

[0013] A squaring circuit, used for squaring the mixed signal to generate a square signal; the square signal includes an AC low-frequency component;

[0014] A second filtering circuit is used to filter the square signal, retain the DC component and AC low-frequency component in the square signal, and generate a second filtered signal;

[0015] The second logarithmic conversion circuit is used to suppress the DC component in the second filtered signal and perform logarithmic conversion on the AC low-frequency component in the second filtered signal to generate an output signal, wherein the output signal is used to represent the effective value of the input signal.

[0016] In a third aspect, an embodiment of the present disclosure provides an effective value detection chip, comprising an effective value detection circuit as in the first aspect or the second aspect.

[0017] The beneficial effects of the embodiments of the present disclosure are as follows: in the effective value detection circuit, a mixing circuit is used to mix a high-frequency input signal and a low-frequency preset signal to obtain a mixed signal; then a square circuit is used to square the mixed signal to obtain a square signal. Since the frequency of the preset signal is low, the square signal includes an AC low-frequency component; then, after filtering, the AC low-frequency component in the square signal is retained, and the signal amplitude of the AC low-frequency component can reflect the effective value square of the input signal; and then the output signal obtained after logarithmic conversion can represent the effective value of the input signal.

[0018] Here, there are two possible ways to perform filtering and logarithmic conversion. One is to use a first filtering circuit to filter the square signal, retain only the AC low-frequency component in the square signal to obtain a first filtered signal, and then use the first logarithmic conversion circuit to logarithmically convert the first filtered signal to obtain an output signal; the other is to use a second filtering circuit to filter the square signal, retain the AC low-frequency component and DC component in the square signal to obtain a second filtered signal, and then use a second logarithmic conversion circuit with a DC suppression effect to logarithmically convert the AC low-frequency component in the second filtered signal to obtain an output signal.

[0019] Thus, compared with the method of using a DC signal to reflect the effective value of the input signal, this solution avoids the influence of the DC offset voltage on the effective value caused by the mismatch of the square circuit itself, improves the detection sensitivity, and is conducive to achieving a larger detection dynamic range. At the same time, because the frequency of the preset signal is lower than the frequency of the input signal, the squared signal after the square processing includes an AC low-frequency component, and the AC low-frequency component is logarithmically converted. The output end of the square circuit only needs to completely retain the AC low-frequency component, and there is no need to completely retain the high-frequency signal. In other words, the output does not need to reflect the characteristics of the high-frequency signal, so the large bandwidth requirement of the square circuit can be reduced, and the difficulty of implementing the square circuit can be reduced; in addition, this solution can also avoid the logarithmic conversion circuit from detecting the high-frequency signal, reduce the difficulty of detection, and save power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of an effective value detection circuit provided by an embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of the frequency spectrum of an input signal and a preset signal provided in an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of a frequency spectrum of a mixing signal provided in an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of a frequency spectrum of a squared signal provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of a frequency spectrum of a first filtered signal provided in an embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of a spectrum of a second filtered signal provided in an embodiment of the present disclosure;

[0026] Figure 7 The structure diagram of the mixer circuit provided in the embodiment of the present disclosure is as follows Figure 1 ;

[0027] Figure 8 The structure diagram of the mixer circuit provided in the embodiment of the present disclosure is as follows Figure 2 ;

[0028] Fig. 9 The structure diagram of the mixer circuit provided in the embodiment of the present disclosure is as follows Figure 3 ;

[0029] Fig.10 The structure diagram of the mixer circuit provided in the embodiment of the present disclosure is as follows Figure 4 ;

[0030] Fig.11The structure diagram of the mixer circuit provided in the embodiment of the present disclosure is as follows Figure 5 ;

[0031] Fig.12 A schematic diagram of the composition structure of a square circuit provided in an embodiment of the present disclosure;

[0032] Fig.13 A schematic diagram of the composition structure of a first filter circuit provided in an embodiment of the present disclosure;

[0033] Fig.14 A schematic diagram of the composition structure of a first logarithmic conversion circuit provided in an embodiment of the present disclosure;

[0034] Fig.15 A schematic diagram of the structure of a second filter circuit provided in an embodiment of the present disclosure;

[0035] Fig.16 A schematic diagram of the structure of the second logarithmic conversion circuit provided in the embodiment of the present disclosure Figure 1 ;

[0036] Fig.17 A schematic diagram of the structure of the second logarithmic conversion circuit provided in the embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0039] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0041] In the effective value detection circuit, the square unit circuit (or square unit, square circuit, etc.) is generally used as the analog front-end circuit to square the AC signal and convert it into the square value of the signal. The square value is then filtered to extract the DC signal that reflects the square of the effective value of the signal. Usually, the DC square value is further logarithmically converted to reflect the size of the effective value of the signal.

[0042] Assume the input signal is ,in, A 1 is the amplitude of the input signal, is the angular frequency of the input signal, t is the time. Then theoretically the signal after square becomes:

[0043]

[0044] After filtering the signal, the DC value is extracted . Can be understood as effective value, DC value has a square relationship with the effective value, so the DC value It can reflect the square of the effective value of the signal. The value can be logarithmically converted to further directly reflect the size of the effective value. However, the square circuit itself often has an offset voltage caused by device mismatch, so the output after the square circuit often contains both the square of the effective value of the signal and the offset voltage of the square unit, which will lead to inaccurate measurement of the effective value of the signal, especially for weak signals. Therefore, the sensitivity of the effective value detection circuit is greatly impaired.

[0045] Based on this, an embodiment of the present disclosure provides an effective value detection circuit, including: a mixing circuit, used to mix an input signal and a preset signal to generate a mixed signal; the input signal and the preset signal are both AC signals, and the frequency of the preset signal is lower than the frequency of the input signal; a squaring circuit, used to square the mixed signal to generate a square signal; the square signal includes an AC low-frequency component; a filtering circuit, used to filter the square signal, at least retain the AC low-frequency component in the square signal, and generate a filtered signal (a first filtered signal or a second filtered signal); a logarithmic conversion circuit, used to logarithmically convert the AC low-frequency component in the filtered signal to generate an output signal, and the output signal is used to characterize the effective value of the input signal.

[0046] In this way, this scheme uses a mixing circuit to mix a high-frequency input signal and a low-frequency preset signal to obtain a mixed signal; then a square circuit is used to square the mixed signal to obtain a square signal. Since the frequency of the preset signal is low, the square signal includes an AC low-frequency component; then after filtering, the AC low-frequency component in the square signal is retained, and the signal amplitude in the AC low-frequency component can reflect the effective value square of the input signal; then the output signal obtained after logarithmic conversion can represent the effective value of the input signal. This scheme reflects the effective value of the input signal through the AC low-frequency component, which can avoid the influence of the DC offset voltage caused by the mismatch of the square circuit itself on the effective value, improve the detection sensitivity, and is conducive to achieving a larger detection dynamic range.

[0047] The implementation of “filter circuit + logarithmic conversion circuit” can be “first filter circuit + first logarithmic conversion circuit” or “second filter circuit + second logarithmic conversion circuit”. The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0048] In one embodiment of the present disclosure, Figure 1 As shown in (a), the effective value detection circuit 10 includes:

[0049] The mixer circuit 101 is used to mix the input signal and the preset signal to generate a mixed signal, wherein the frequency of the mixed signal includes the frequency information of the input signal and the preset signal, and the amplitude of the mixed signal is related to the amplitude of the input signal and the preset signal; the input signal and the preset signal are both AC signals, the frequency of the preset signal is lower than the frequency of the input signal, and the amplitude of the preset signal is a preset known value;

[0050] The square circuit 102 is used to square the mixed signal to generate a square signal. Because the square circuit 102 squares the signal after mixing the low-frequency preset signal, the square signal includes an AC low-frequency component, and the amplitude of the AC low-frequency component is related to the amplitude of the input signal and the preset signal.

[0051] The first filtering circuit 1031 is used to filter the square signal, retain the AC low-frequency component in the square signal, and generate a first filtered signal; the amplitude of the first filtered signal is related to the amplitudes of the input signal and the preset signal;

[0052] The first logarithmic conversion circuit 1041 is used to perform logarithmic conversion on the first filtered signal to generate an output signal; because the amplitude of the first filtered signal is related to the amplitude of the input signal and the preset signal, the size of the output signal is related to the amplitude of the input signal and the preset signal, and the amplitude of the preset signal is known, so the output signal can be used to reflect the effective value of the input signal, and the output signal can be used to characterize the effective value of the input signal. Because the first filtered signal retains the low-frequency AC signal, the logarithmic conversion of the low-frequency AC signal can characterize the effective value of the input signal, avoid the influence of the DC offset voltage of the square circuit on the effective value, and improve the sensitivity of the detection.

[0053] It should be noted that, in the embodiment of the present disclosure, the input signal can be recorded as V IN , which can be a differential AC signal. Figure 1 As shown, they are respectively recorded as positive phase input signal V IN+ and the inverting input signal V IN- The preset signal can be recorded as V P , or a differential AC signal, respectively recorded as the positive phase preset signal V P+ and the inverted preset signal V P- .

[0054] In some embodiments, the preset signal V P It can be the internal clock signal of the mixer circuit 101 (therefore, the preset signal can also be recorded as the clock signal CLK, and the differential preset signal can also be recorded as the positive phase preset signal CLK+ and the negative phase preset signal CLK-), so in Figure 1 The preset signal V is not shown. P In other embodiments, the preset signal V P It can also be a signal inputted externally to the mixer circuit 101, which is not specifically limited. Figure 1 Take this as an example to illustrate.

[0055] In the embodiment of the present disclosure, the input signal V IN For high frequency AC signal, the preset signal V P is a low-frequency AC signal. In short, the input signal V IN The frequency is higher than the preset signal V P The frequency of the input signal V IN The frequency can be high frequency, the preset signal V P The frequency can be low frequency. For example: the preset signal V P The frequency of the input signal V INThe frequency of the squared low-frequency AC signal and the high-frequency invalid signal can be effectively distinguished, so that in the subsequent filtering process, the high-frequency signal can be easily filtered out and the AC low-frequency component can be retained. For example, the input signal frequency is 1GHz and the preset signal frequency is 1MHz.

[0056] It should also be noted that in the embodiment of the present disclosure, the mixer circuit 101 is used to IN and preset signal V P The mixing process is performed to generate a mixed signal and send it to the square circuit 102. Here, the mixed signal can be recorded as V m , which can be specifically a differential AC signal, respectively recorded as a positive phase mixing signal V m+ and the inverted mixing signal V m- .

[0057] The square circuit 102 (or square unit, square unit circuit, etc.) receives the mixed signal V m After that, the mixing signal V m The square signal is processed to generate a square signal and sent to the first filter circuit 1031. Here, the square signal can be recorded as V s , which can be specifically a differential AC signal, respectively recorded as a positive phase square signal V s+ And the inverted square signal V s- Here, the squared signal V s It contains both DC components and AC components, and the AC components contain both high-frequency components and low-frequency components.

[0058] After receiving the square signal, the first filter circuit 1031 filters the square signal V s The DC component and AC high frequency component in the square signal V are retained. s The AC low-frequency component in the filter is used to generate a first filtered signal and send it to the first logarithmic conversion circuit 1041.

[0059] It can be seen that the first filtered signal only contains AC low-frequency components, and the first filtered signal is an AC low-frequency signal. Here, the first filtered signal can be recorded as V w1 , which can be specifically a differential AC signal, respectively recorded as the first positive phase filter signal V w1+ and the first inverted filtered signal V w1- .

[0060] The first logarithmic conversion circuit 1041 receives the first filtered signal V w1 After that, the first filtered signal V w1 Perform logarithmic conversion (or logarithmic envelope detection) to generate the output signal V out , since the first filtered signal V w1The input signal V contains only low-frequency AC components, so the low-frequency signal amplitude can reflect the effective value of the input signal. The first logarithmic conversion circuit 1041 can extract the amplitude of the low-frequency AC component and finally obtain the input signal V IN The effective value of the output signal V out (Also called output voltage V out ).

[0061] Next, we combine the spectrum Figure 1 The specific implementation principle of the effective value detection circuit 10 shown in (a) is described below. Figures 2 to 5 The input signal V IN , preset signal V P , Mixing signal V m , square signal V s and the first filtered signal V m1 In each spectrum diagram of the embodiments of the present disclosure, the horizontal axis is the frequency, the unit is Hertz (Hz), and the vertical axis is the amplitude, the unit is volt (V).

[0062] Assume that the input signal V IN for , the clock signal (ie, the preset signal) of the mixer circuit 101 is V P for :in, A 1 is the input signal V IN The amplitude of The input signal V IN The angular frequency, A 0 is the preset signal V P The amplitude of The preset signal V P The angular frequency, t For time, << .like Figure 2 As shown, for the original input signal V IN , which only contains A frequency component. The mixed signal V obtained after mixing m for:

[0063]

[0064] It can be seen from this that the mixing signal V m The frequency of the input signal and the frequency of the preset signal Related, the mixing signal V m The amplitude The amplitude of the input signal A 1 and the amplitude of the preset signal A 0 related. Figure 3 As shown, the mixing signal V m Contains two frequency components, namely: )and( ). In some embodiments, when 1GHz, When it is 1MHz, ( ) is 999MHz, ( ) is 1001MHz.

[0065] The mixed signal V m After being squared by the square circuit 102, it becomes a square signal Vs, and the derivation process is as follows:

[0066]

[0067] The square signal V s There is a DC component in the components of , its angular frequency is 0; there are AC high-frequency components, and the angular frequencies are ( )、( )and , the amplitudes of the three high-frequency AC components are , and because << , the frequencies of these three are very close; there is also an AC low-frequency component, the angular frequency is , the amplitude is That is to say, Figure 4 As shown, the square signal V s Contains five frequency components: 0, 2 、( )、 and In some embodiments, when 1GHz, When 1MHz, 2 2MHz, ( ) is 1998MHz, 2000MHz, is 2002MHz. (2MHz) is very different from the frequencies of 1998MHz, 2000MHz, and 2002MHz, so they can be easily distinguished by filtering.

[0068] Square signal V s The five components of the signal can be distinguished by frequency. After the distinction, the amplitude of the DC component and the AC low-frequency component can be written as and , both can reflect the input signal V INThe square of the effective value of size.

[0069] In this scheme, because the AC low-frequency component (frequency is 2 The output of the square circuit only needs to detect the low-frequency component of the AC (frequency is 2 The low-frequency signal of ( )、 and That is to say, the output does not need to reflect the characteristics of the high-frequency signal, so the large bandwidth requirement of the square circuit can be reduced, and the difficulty of implementing the square circuit can be reduced.

[0070] The first filter circuit 1031 is used to square the signal V s Filter the square signal V s The DC component and AC high-frequency component in the filter are filtered out. Figure 5 As shown, only the angular frequency is retained. The AC low-frequency component is obtained to obtain the first filtered signal V w1 .

[0071] For the first filtered signal V w1 For , its amplitude is: A= , this amplitude A can be detected by the logarithmic envelope detection circuit (ie, the first logarithmic conversion circuit 1041). Since A0 is known, the square of the effective value of the signal can be obtained based on A and A0. That is, the amplitude A= It can be used to reflect the size of the effective value.

[0072] Finally, the first logarithmic conversion circuit 1041 is used to convert the first filtered signal V containing only the AC low-frequency component w1 Logarithmic conversion is performed to obtain the output signal V out , extract the amplitude of the AC low-frequency component, and then the input signal V can be calculated IN The first logarithmic conversion circuit 1041 only needs to convert the frequency to 2 The low-frequency signal is logarithmically transformed without the need for high-frequency signals (frequency ( )、 and The logarithmic conversion of high-frequency signals can be performed to reduce the difficulty of implementing the logarithmic conversion circuit.

[0073] Thus, unlike the conventional structure which uses a DC signal to reflect the square of the effective value, since the offset voltage of the square circuit 102 itself is also in DC, the actual DC voltage is not , but +VOS. VOS represents the DC offset voltage of the square circuit 102. If a DC voltage is used, the accuracy of the output detection voltage is affected and the sensitivity of the signal effective value detection circuit is affected.

[0074] In order to improve accuracy and sensitivity, Figure 1 In the implementation shown in (a), the input stage first uses a mixer circuit 101 to mix the high frequency input signal V IN The mixed signal V is then squared using a square circuit 102. m The square is calculated, and then the low-frequency AC signal that can reflect the square of the effective value of the signal is extracted through the first filtering circuit 1031 (specifically, it can be a bandpass filter), and the offset voltage and invalid signal at DC and the invalid signal at high frequency are filtered out. Finally, the low-frequency AC signal is sent to the logarithmic envelope detection circuit (i.e., the first logarithmic conversion circuit 1041) to obtain the input signal V IN The effective value of the output signal V out This avoids the influence of the offset voltage caused by the mismatch of the components of the square circuit 102 itself on the detection result, improves the sensitivity of the overall detection circuit, and effectively expands the dynamic range of the detection circuit.

[0075] In some embodiments, the amplitude of the preset signal may be consistent with, or substantially equal to, the amplitude of the power supply voltage VDD of the effective value detection circuit 10, so that the first filtered signal V w1 The amplitude is larger. When the input signal is relatively small, the first logarithmic conversion circuit can also detect the first filtered signal V w1 The amplitude of the preset signal can be 3V~3.3V, thereby improving the sensitivity of the detection. For example, when the power supply voltage VDD is 3.3V, the amplitude of the preset signal can be 3V~3.3V.

[0076] The present disclosure also provides another effective value detection circuit 10, such as Figure 1 As shown in (b), the effective value detection circuit 10 includes:

[0077] The mixer circuit 101 is used to mix the input signal and the preset signal to generate a mixed signal; the input signal and the preset signal are both AC signals, and the frequency of the preset signal is lower than the frequency of the input signal;

[0078] The square circuit 102 is used to square the mixed signal to generate a square signal; the square signal includes an AC low-frequency component;

[0079] The second filtering circuit 1032 is used to filter the square signal, retain the DC component and AC low-frequency component in the square signal, and generate a second filtered signal;

[0080] The second logarithmic conversion circuit 1042 is used to suppress the DC component in the second filtered signal and perform logarithmic conversion on the AC low-frequency component in the second filtered signal to generate an output signal, and the output signal is used to represent the effective value of the input signal.

[0081] It should be noted that the working principle of the mixing circuit 101 and the square circuit 102 is the same as that of the above-mentioned Figure 1 Here, the square circuit 102 generates the square signal V s Sent to the second filtering circuit 1032.

[0082] The second filter circuit 1032 receives the square signal V s After filtering the square signal V s The AC high frequency components in the square signal V are retained. s The DC component and AC low-frequency component in the filter are combined to generate a second filtered signal and sent to the second logarithmic conversion circuit 1042. Here, the second filtered signal can be recorded as V w2 , which can be specifically a differential AC signal, respectively recorded as the second positive phase filter signal V w2+ and the second inverted filtered signal V w2- .

[0083] The second logarithmic conversion circuit 1042 receives the second filtered signal V w2 After that, the second filtered signal V w2 The DC component in the filter can be suppressed and eliminated, and the DC offset signal itself can also be suppressed and eliminated. w2 The AC low-frequency components in the signal are converted logarithmically (or logarithmic envelope detection) to generate the output signal V out Since all DC components are suppressed, only the AC low-frequency components are logarithmically converted, so the effective value of the input signal can be reflected by the low-frequency signal amplitude. The second logarithmic conversion circuit 1042 can extract the amplitude of the low-frequency AC signal and finally obtain an output signal reflecting the effective value of the input signal.

[0084] Next, we combine the spectrum Figure 1 The specific implementation principle of the effective value detection circuit 10 shown in (b) is described below. The input signal V IN , Mixing signal V m , square signal V s The spectrum diagram still refers to the above Figures 2 to 4 And related description, no further elaboration is given here, the second filtered signal V m2 Please refer to the spectrum diagram of Figure 6 .

[0085] like Figure 6As shown, the second filtering circuit 1032 is used to filter the AC high-frequency components in the square signal Vs, and the DC components and AC low-frequency components are retained to obtain the second filtered signal V w2 .like Figure 5 As shown, the second filtered signal V w2 Contains two frequency components: 0 (DC component), (AC low frequency component).

[0086] As before, the amplitude of the AC low-frequency component is: A= , this amplitude A can be detected by the logarithmic envelope detection circuit. A0 is known, and according to A and A0, the square of the effective value of the signal can be obtained .

[0087] Here, the second filtered signal V m2 The direct current (DC) component in the squaring circuit 102 contains the offset of the square circuit 102, which cannot accurately reflect the effective value of the signal. Therefore, in the embodiment of the present disclosure, the high-frequency input signal V is firstly mixed by the mixer circuit 101 at the input stage. IN The mixed signal V is then squared using a square circuit 102. m The square is calculated and then the mixed signal V is filtered through the second filter circuit 1032. m The low-frequency AC signal and DC signal that can reflect the square of the effective value of the signal are extracted. Finally, the low-frequency AC signal is sent to the logarithmic envelope detection circuit with DC offset suppression (i.e., the second logarithmic conversion circuit 1042) for processing. The DC invalid signal and offset are suppressed, that is, whether it is the offset of the square circuit 102 or the offset of the second logarithmic conversion circuit 1042 itself, as well as the DC component in the original signal, are suppressed. Only the low-frequency AC signal is detected by the logarithmic envelope to obtain the input signal V IN The effective value of the output signal V out .

[0088] In the embodiment of the present disclosure, the function of the mixer circuit 101 is to convert the high frequency input signal V IN With the preset signal V P Mixing is performed, wherein the preset signal V P The frequency is lower than the input signal V IN frequency; the square circuit 102 is used to square the mixed signal; the first filter circuit 1031 is used to filter out the AC high-frequency component and the DC component; the first logarithmic conversion circuit 1041 is used for logarithmic envelope detection; the second filter circuit 1032 is used to filter out the AC high-frequency component; the second logarithmic conversion circuit 1042 is used to suppress the DC component and logarithmic envelope detection.

[0089] The specific components of the mixing circuit 101 , the square circuit 102 , the first filtering circuit 1031 , the second filtering circuit 1032 , the first logarithmic conversion circuit 1041 and the second logarithmic conversion circuit 1042 are respectively described in detail below.

[0090] In some embodiments, the mixing circuit 101 is a mixer, see Figure 7 , which shows a schematic diagram of the composition structure of a mixing circuit (mixer) 101 provided in an embodiment of the present disclosure. Figure 7 As shown, the mixer may include a first switch circuit 111, a second switch circuit 112, a third switch circuit 113 and a fourth switch circuit 114;

[0091] The first end of the first switch circuit 111 and the first end of the second switch circuit 112 are connected as the first input end of the mixer circuit 101 for receiving the positive phase input signal V IN+ The first end of the third switch circuit 113 and the first end of the fourth switch circuit 114 are connected as the second input end of the mixer circuit 101 for receiving the inverted input signal V IN- The second end of the first switch circuit 111 and the second end of the third switch circuit 113 are connected as the first output end of the mixer circuit 101, for outputting the positive phase mixing signal V m+ The second end of the second switch circuit 112 and the second end of the fourth switch circuit 114 are connected as the second output end of the mixer circuit 101, for outputting the inverted mixing signal V m- ;

[0092] The first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 each include one or more control terminals, each control terminal receives a positive phase preset signal CLK+ or a negative phase preset signal CLK-, so as to control the conduction or disconnection of the corresponding first switch circuit 111 / second switch circuit 112 / third switch circuit 113 / fourth switch circuit 114.

[0093] It should be noted that the main function of the frequency mixer 101 is to convert the signal. During the operation of the frequency mixer 101, the control clock (i.e., the preset signal) can be used to control the first switch circuit 111, the second switch circuit 112, the third switch circuit 113, and the fourth switch circuit 114. Its working mechanism is to connect the positive input terminal and the negative input terminal to the positive output terminal and the negative output terminal respectively through four-way switches. By controlling the control clock of the four-way switch, the positive output terminal can be connected to the positive input terminal in a time period, and the negative output terminal can be connected to the negative input terminal at the same time. In another time period, the positive output terminal is connected to the negative input terminal, and the negative output terminal is connected to the positive input terminal, and finally the purpose of frequency mixing is achieved.

[0094] Here, each switch circuit can be specifically implemented by a combination of an N-type metal oxide semiconductor field effect transistor (NMOS) and a P-type metal oxide semiconductor field effect transistor (PMOS) or separately implements the four-way switch of the mixer, or can be implemented by an NPN or PNP transistor. Here, the positive phase preset signal CLK+ and the negative phase preset signal CLK- can be a pair of mutually inverted signals to achieve the control of turning on and off each switch circuit. In some embodiments, at least some of the switches in the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 can be different types of switches.

[0095] In the first implementation, see Figure 8 , which shows a detailed structural diagram of a mixing circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 8 As shown, if the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all transmission gates, the first control end of the first switch circuit 111, the second control end of the second switch circuit 112, the second control end of the third switch circuit 113 and the first control end of the fourth switch circuit 114 are all used to receive the positive phase preset signal CLK+; the second control end of the first switch circuit 111, the first control end of the second switch circuit 112, the first control end of the third switch circuit 113 and the second control end of the fourth switch circuit 114 are all used to receive the negative phase preset signal CLK-.

[0096] It should be noted that the transmission gate is composed of a PMOS tube and an NMOS tube, wherein the control end (gate) of the NMOS tube serves as the first control end of the transmission gate, and the control end (gate) of the PMOS tube serves as the second control end of the transmission gate. The first end of the PMOS tube and the first end of the NMOS tube are connected as the first end of the transmission gate, that is, the first end of the corresponding switch circuit; the second end of the PMOS tube and the second end of the NMOS tube are connected as the second end of the transmission gate, that is, the second end of the corresponding switch circuit. The two control ends of the transmission gate receive a pair of inverted positive-phase preset signals and inverted-phase preset signals, respectively, so as to realize the opening and closing of the four transmission gates as required.

[0097] In the second implementation, see Fig. 9 , which shows a detailed structural diagram of a mixing circuit provided by an embodiment of the present disclosure Figure 2 If the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all single-pole single-throw switches, the control end of the first switch circuit 111 and the control end of the fourth switch circuit 114 are both used to receive the positive phase preset signal CLK+, and the control end of the second switch circuit 112 and the control end of the third switch circuit 113 are both used to receive the negative phase preset signal CLK-.

[0098] In the third implementation, see Fig.10 , which shows a detailed structural diagram of a mixing circuit provided by an embodiment of the present disclosure Figure 3 If the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all NMOS transistors, the control end of the first switch circuit 111 and the control end of the fourth switch circuit 114 are used to receive the positive phase preset signal CLK+, and the control end of the second switch circuit 112 and the control end of the third switch circuit 113 are used to receive the negative phase preset signal CLK-.

[0099] In the fourth implementation, see Fig.11 , which shows a detailed structural diagram of a mixing circuit provided by an embodiment of the present disclosure Figure 4 If the first switch circuit 111, the second switch circuit 112, the third switch circuit 113 and the fourth switch circuit 114 are all PMOS tubes, the control end of the first switch circuit 111 and the control end of the fourth switch circuit 114 are used to receive the inverted preset signal CLK-, and the control end of the second switch circuit 112 and the control end of the third switch circuit 113 are used to receive the positive preset signal CLK+.

[0100] It should be noted that if the switching circuit is an NMOS tube or a PMOS tube, then the first end and the second end of the switching circuit can be the drain and source of the NMOS tube or the PMOS tube respectively, and the control end can be a gate. According to the signal received by the gate, the conduction and cutoff of the MOS tube are controlled to realize the conduction and cutoff of the switching circuit.

[0101] In some embodiments, see Fig.12 , which shows a schematic diagram of the composition structure of a square circuit 102 provided in an embodiment of the present disclosure. It is a square circuit based on a triode, such as Fig.12 As shown, the square circuit 102 includes: four transistors Q1, Q2, Q3 and Q4, and four resistors R connected to the four transistors respectively. E , capacitor C L , resistor R L1 and resistor R L2 , where: The base of transistors Q3 and Q4 receives bias voltage V CM, the bases of transistors Q1 and Q2 receive the bias voltage V CM (when the square circuit has no input) or an AC input signal (when the square circuit has input), where the AC input signal is the mixing signal V output by the mixing circuit 101 m , when the square circuit has input, the specific signals received by Q1 and Q2 are: and , capacitor C L One end of the resistor R L1 One end of the transistor Q1, the collector of the transistor Q2 are connected as the positive phase output end of the square circuit 102, and the positive phase square signal V is output. s+ (voltage signal); where I OUT is the positive phase output current, the resistor R L1 Convert it into a positive phase square signal V OUT+ . Resistance R L2 The collector of transistor Q3 and the collector of transistor Q4 are connected as the inverting output terminal of square circuit 102, and the inverted square signal V is output. s- (voltage signal); where I B is the reverse output current, the resistor R L2 Convert it into an inverted square signal V s- According to the three-pole tube formula, I OUT with I B Subtracting the input voltage signal (i.e. the mixing signal V m ) in a square relationship. The resulting square current is based on the two transistors being in a completely consistent state. In actual situations, it is difficult for the two transistors Q1 / Q2 and Q3 / Q4 to be completely consistent, and there is usually a certain mismatch, which will introduce an offset voltage into the circuit.

[0102] The first filter circuit 1031 may be a bandpass filter, see Fig.13 , which shows a specific structural schematic diagram of a first filtering circuit (bandpass filter) 1031 provided in an embodiment of the present disclosure. Fig.13 As shown, the first filtering circuit 1031 includes a first high-pass capacitor C HPF1 , the first high-pass resistor R HPF1 , the first low-pass capacitor C LPF1 , the first low-pass resistor R LPF1 , the second high-pass capacitor C HPF2 , the second high-pass resistor R HPF2 , the second low-pass capacitor C LPF2 , the second low-pass resistor R LPF2 ;

[0103] The first high-pass capacitor C HPF1The first end of the first filter circuit 1031 receives the positive phase square signal V s+ , the first high-pass capacitor C HPF1 The second end of the first high-pass resistor R HPF1 The first end of the first low-pass resistor R LPF1 The first end of the first high-pass resistor R HPF1 The second end of the first low-pass resistor R LPF1 The second end of the first low-pass capacitor C LPF1 The first end of the filter circuit 1031 is connected to the positive phase output end of the filter circuit 1031 to output the first positive phase filter signal V w1+ , the first low-pass capacitor C LPF1 The second end of is grounded;

[0104] The second high-pass capacitor C HPF2 The first end of the first filter circuit 1031 receives the inverted square signal V s- , the second high-pass capacitor C HPF2 The second end of the second high-pass resistor R HPF2 The first end of the second low-pass resistor R LPF2 The first end of the second high pass resistor R HPF2 The second end of the second low-pass resistor R LPF2 The second end of the second low-pass capacitor C LPF2 The first end of the filter circuit 1031 is connected to the inverting output end of the filter circuit 1031 to output the first inverted filtering signal V w1- , the second low-pass capacitor C LPF2 The second end is grounded.

[0105] It should be noted that a bandpass filter is a device that allows signals of a specific frequency band to pass through while shielding other frequency bands. In the embodiment of the present disclosure, the bandpass filter allows the AC low-frequency component to pass through while shielding the DC component and the AC high-frequency component.

[0106] like Fig.13 As shown, the bandpass filter can be considered to be composed of a high-pass filter and a low-pass filter. Among them, the first high-pass capacitor C HPF1 , the first high-pass resistor R HPF1 , the second high-pass capacitor C HPF2 , the second high-pass resistor R HPF2 A high-pass filter is formed, which squares the signal V s The DC components in the circuit are shielded, and the AC components (including AC low-frequency components and AC high-frequency components) are allowed to pass through.

[0107] The first low-pass capacitor C LPF1 , the first low-pass resistor R LPF1 , the second low-pass capacitor CLPF2 , the second low-pass resistor R LPF2 A low-pass filter is formed, which only allows low-frequency AC components to pass through and shields high-frequency AC components.

[0108] In the embodiment of the present disclosure, the frequency band allowed to pass by the first filter circuit 1031 can be combined with the actual preset signal V IN and input signal V P Specifically, the frequency band allowed to pass can be set by adjusting the sizes of each capacitor and resistor in the first filtering circuit 1031.

[0109] Fig.14 A schematic diagram of the composition structure of the first logarithmic conversion circuit 1041 provided in an embodiment of the present disclosure is shown in FIG. Fig.14 As shown, in some embodiments, the first logarithmic conversion circuit 1041 includes a plurality of cascaded limiting amplifiers 121 and a plurality of rectifier circuits 122; wherein:

[0110] The input end of the first stage limiting amplifier 121 is connected to the output end of the first filter circuit 1031 and receives the first filtered signal V w1 The output end of each limiting amplifier 121 is connected to the input end of a rectifier circuit 122, and the output ends of all rectifier circuits 122 are connected together to generate an output signal V out .

[0111] It should be noted that the logarithmic conversion circuit is also called the logarithmic envelope detection circuit. Fig.14 As shown, it is assumed that the first logarithmic conversion circuit 1041 includes N cascaded limiting amplifiers 121 (limiting amplifier 1, limiting amplifier 2...limiting amplifier N) and N+1 rectifier circuits (rectifier circuit 1, rectifier circuit 2...rectifier circuit N+1), where N is an integer greater than 0.

[0112] Here, the limiting amplifier 121 mainly amplifies the signal step by step, and when the signal reaches a certain level, the limiting amplifier will gradually reach the limiting value, so it is called a limiting amplifier. The main function of the rectifier circuit 122 (or rectifier) ​​is to convert the step-by-step output of the limiting amplifier 121 into a direct current, and the rectifier in the logarithmic conversion circuit has a logarithmic relationship between the output current and its own input voltage amplitude. Fig.14 As shown, the first logarithmic conversion circuit 1041 also includes a load resistor 123 connected to the output signal V out and the ground terminal to convert the current output by the multi-stage rectifier circuit 122 into a voltage signal.

[0113] exist Fig.14In the example shown, N+1 stages of rectifier circuits 122 are included, wherein: the input end of the first stage rectifier circuit 122 is connected to the output end of the first filter circuit 1031; the input end of the s-th stage rectifier circuit 122 is connected to the output end of the s-1th stage limiting amplifier 121, where s is an integer greater than 1 and less than or equal to N+1; the output ends of the N+1 rectifier circuits 122 are connected as the output end of the conversion circuit 12, for outputting the output signal V out .

[0114] In some other embodiments, N-stage rectifier circuits 122 may also be included. For example, the input end of each stage rectifier circuit 122 is connected to the output end of a limiting amplifier 121, and the output ends of all rectifier circuits 122 are connected to output the output signal V out Or, the input end of each stage of the rectifier circuit 122 is connected to the input end of a limiting amplifier 121, and the output ends of all rectifier circuits 122 are connected to output the output signal V out This is not specifically limited, but only Fig.14 Shown as an example.

[0115] like Fig.14 As shown, in the embodiment of the present disclosure, the limiting amplifier 121 and the rectifier circuit 122 can both be double-ended differential inputs. Each limiting amplifier 121 includes a positive input terminal (+), a negative input terminal (-), a positive output terminal (+) and a negative output terminal (-), and each rectifier circuit 122 includes a first input terminal, a second input terminal and an output terminal. Wherein:

[0116] The first input terminal of the first-stage rectifier circuit 122 and the positive-phase input terminal of the first-stage limiting amplifier 121 both receive the first positive-phase filter signal V w1+ The second input terminal of the first-stage rectifier circuit 122 and the inverting input terminal of the first-stage limiting amplifier 121 both receive the first inverted filtering signal V w1- ; The first input terminal of the s-th level rectifier circuit 122 and the positive phase input terminal of the s-th level limiting amplifier 121 are both connected to the positive phase output terminal of the s-1-th level limiting amplifier 121, and the second input terminal of the s-th level rectifier circuit 122 and the inverting input terminal of the s-th level limiting amplifier 121 are both connected to the inverting output terminal of the s-1-th level limiting amplifier 121.

[0117] In this way, logarithmic envelope detection can be implemented by using the cascaded limiting amplifier 121 and the rectifier circuit 122 to obtain a signal that can characterize the input signal V IN The effective value of the output signal V out .

[0118] In some embodiments, the second filter circuit 1032 may be a low pass filter. Fig.15, which shows a schematic diagram of the composition structure of a second filter circuit 1032 (low-pass filter) provided in an embodiment of the present disclosure. Fig.15 As shown, the second filter circuit 1032 includes a third low-pass resistor R LPF3 , the third low-pass capacitor C LPF3 , the fourth low-pass resistor R LPF4 , the fourth low-pass capacitor C LPF3 ;

[0119] The third low-pass resistor R LPF3 The first end of the third low-pass resistor R LPF3 The second end of the third low-pass capacitor C LPF3 The first end of the third low-pass capacitor C is connected to the positive phase output end of the second filter circuit 1032 to output the second positive phase filter signal Vw2+; LPF3 The second end of is grounded;

[0120] The fourth low-pass resistor R LPF4 The first end of the fourth low-pass resistor R LPF4 The second end of the fourth low-pass capacitor C LPF4 The first end of the fourth low-pass capacitor C is connected to the inverting output end of the second filter circuit 1032 to output the second inverted filter signal Vw2-; LPF4 The second end is grounded.

[0121] It should be noted that a low-pass filter is an electronic filter device that allows signals below the cut-off frequency to pass, but does not allow signals above the cut-off frequency to pass. In the embodiment of the present disclosure, the cut-off frequency can be combined with the actual preset signal V IN and input signal V P Specifically, the frequency band allowed to pass can be set by adjusting the sizes of each capacitor and resistor in the second filtering circuit 1032.

[0122] In the embodiment of the present disclosure, the second logarithmic conversion circuit 1042 is a logarithmic envelope detection circuit with a DC offset suppression loop. Fig.16 , which shows a schematic diagram of the composition structure of a second logarithmic conversion circuit 1042 provided in an embodiment of the present disclosure. Fig.16 As shown, the second logarithmic conversion circuit includes N cascaded limiting amplifiers 121, a plurality of rectifier circuits 122, and a feedback circuit 124; wherein:

[0123] The input end of the first stage limiting amplifier 121 is connected to the output end of the second filter circuit 1032 to receive the second filter signal V w2The output end of each limiting amplifier 121 is connected to the input end of a rectifier circuit 122, and the output ends of all rectifier circuits 122 are connected together to generate an output signal V out ;

[0124] The feedback circuit 124 is connected between the output end of the j-th level limiting amplifier 121 and the input end of the i-th level limiting amplifier 121, and is used to input a feedback signal F to the input end of the i-th level limiting amplifier 121, wherein the feedback signal F includes a DC portion of the output signal of the j-th level limiting amplifier 121, i and j are both integers greater than or equal to 1 and less than or equal to N, and j is greater than or equal to i.

[0125] It should be noted that Fig.16 The second logarithmic conversion circuit 1042 is shown in Fig.14 The first logarithmic conversion circuit 1041 is further provided with a feedback circuit 124. Fig.14 For the same parts, please refer to Fig.14 And the related description will not be repeated here.

[0126] The feedback circuit 124 (also called a DC offset suppression loop) is used to suppress the DC offset voltage in the input terminal and the amplification loop, so that the entire link works in a low offset state. Fig.16 In the example, the feedback circuit 124 is connected between the output end of the last stage (Nth stage) limiting amplifier 121 and the input end of the second stage limiting amplifier 121, i.e., i=2, j=N, so that the feedback circuit 124 receives the signal amplified by the Nth stage limiting amplifier 121. The feedback circuit 124 filters out the AC part of the signal output by the limiting amplifier N and only allows the DC part to pass, thereby obtaining a feedback signal F.

[0127] Here, the feedback signal F can be the DC part obtained directly after filtering out the AC part. An amplification factor can also be set in combination with actual conditions to amplify the DC part to obtain a feedback signal. The feedback signal then acts on the input end of the second-stage limiting amplifier 121 to suppress the DC signal. The DC signal includes the second filtered signal V w2 The DC part in the squaring circuit 102 (which includes the offset of the square circuit 102) and the offset voltage inside the second-stage limiting amplifier 121 to the N-stage limiting amplifier 121 (also a DC signal).

[0128] In other examples, the feedback circuit 124 may also be connected between the output end of any post-stage limiting amplifier 121 and the input end of any pre-stage limiting amplifier 121. When the loop gain formed by the i-th stage limiting amplifier 121 and the j-th stage limiting amplifier 121 and the feedback circuit 13 is larger, the offset voltage is suppressed more comprehensively.

[0129] For the feedback circuit 124, in some embodiments, as Fig.16 As shown, the feedback circuit 124 may include a feedback filter circuit 1241, and the feedback filter circuit 1241 is connected between the output end of the j-th stage limiting amplifier 121 and the input end of the i-th stage limiting amplifier 121;

[0130] The feedback filter circuit 1241 is used for receiving the output signal of the j-th limiting amplifier and filtering the output signal of the j-th limiting amplifier 121 to pass the DC part of the output signal of the j-th limiting amplifier 121 to generate a feedback signal.

[0131] It should be noted that the purpose of filtering by the feedback filter circuit 1241 is to distinguish the AC signal from the DC signal, and only allow the DC part to pass through, but not the AC part. Here, the feedback filter circuit 1241 can be a low-pass filter, which allows the DC part of the output signal of the j-th limiting amplifier to pass through, forming a feedback signal that is transmitted to the input end of the i-th limiting amplifier 121, and acts on the i-th limiting amplifier 121 to the j-th limiting amplifier 121 to suppress the DC signal.

[0132] The feedback signal formed by the feedback filter circuit 1241 includes only the DC part, and its feedback signal is in antiphase with the DC offset voltage of the cascaded limiting amplifier, and the feedback signal can cancel the DC offset voltage. Therefore, the feedback filter circuit 1241 and the forward path of the cascaded limiting amplifier itself form a negative feedback loop, which suppresses the DC offset voltage of the cascaded limiting amplifier to an extremely low value, and does not suppress the useful signal in AC.

[0133] For the feedback circuit 124, in some other embodiments, see Fig.17 , which shows a schematic diagram of the composition structure of a second logarithmic conversion circuit provided by an embodiment of the present disclosure Figure 2 .like Fig.17 As shown, the feedback circuit 124 may further include a feedback amplifier 1242, the input end of the feedback amplifier 1242 is connected to the output end of the feedback filter circuit 1241, and the output end of the feedback amplifier 1242 is connected to the input end of the i-th stage limiting amplifier 121; wherein: the feedback amplifier 1242 is used to amplify the feedback signal. The feedback amplifier 1242 may be a voltage amplifier, which is used to provide voltage gain.

[0134] It should be noted that in Fig.16 On the basis of Fig.17As shown, a feedback amplifier 1242 can also be set in the feedback circuit 124. The function of the feedback amplifier 1242 is to amplify the signal input therein. Since it is located in the feedback circuit 124 and plays a feedback role, it is called a feedback amplifier. The gain of the feedback amplifier 1242 can be greater than or equal to 1. The greater the gain, the stronger the suppression effect on the offset voltage. If the gain of the feedback amplifier 1242 is equal to 1, it means that the feedback amplifier 1242 does not work, which is equivalent to Fig.16 The feedback amplifier 1242 amplifies the feedback signal, and the amplified feedback signal has a stronger suppressive effect on the offset voltage in the limiting amplifier 121 .

[0135] It should be noted that, in the embodiments of the present disclosure, Fig.16 and Fig.17 As shown, for the differential signal, the feedback signal F output by the feedback filter circuit includes a positive phase feedback signal F+ and an inverted phase feedback signal F-, and the amplified feedback signal F' output by the feedback amplifier includes an amplified positive phase feedback signal F+' and an amplified inverted phase feedback signal F-'. The positive phase output terminal of the feedback amplifier 1242 is connected to the inverted phase input terminal of the i-th level limiting amplifier, and the inverted phase output terminal of the feedback amplifier 1242 is connected to the positive phase input terminal of the i-th level limiting amplifier. That is, the feedback circuit 124 feeds back the positive phase output terminal of the j-th level limiting amplifier 121 to the inverted phase input terminal of the i-th level limiting amplifier 121, and feeds back the inverted phase output terminal of the j-th level limiting amplifier 121 to the positive phase input terminal of the i-th level limiting amplifier 121, and undergoes filtering, amplification and other steps in between. Thereby, the DC signal is suppressed.

[0136] In other examples, the positive phase output terminal of the feedback amplifier 1242 may be inverted and connected to the positive phase input terminal of the i-th stage limiting amplifier 121, and the negative phase output terminal of the feedback amplifier 1242 may be inverted and connected to the negative phase input terminal of the i-th stage limiting amplifier 121.

[0137] If the feedback circuit 13 does not include the feedback amplifier 1242 (i.e. Fig.16 ), the positive-phase feedback signal F+ outputted from the first output terminal (positive-phase output terminal) of the feedback filter circuit 1241 is inverted and connected to the positive-phase input terminal of the i-th stage limiting amplifier 121; the negative-phase feedback signal F+ outputted from the second output terminal (inverting output terminal) of the feedback filter circuit 1241 is inverted and connected to the inverting input terminal of the i-th stage limiting amplifier 121.

[0138] The main function of the feedback circuit 124 is to suppress the DC signal by forming a negative feedback loop with the cascaded limiting amplifier, while not suppressing the AC signal. The working mechanism is to use the feedback filter circuit 1241 (low-pass filter), the DC signal will pass through the low-pass filter smoothly and be amplified by the feedback amplifier 1242 (if the feedback amplifier 1242 is included), forming a feedback coefficient greater than 1, and finally being suppressed by the negative feedback loop formed by the feedback circuit 124 and the cascaded limiting amplifier. However, for AC signals, due to the existence of the low-pass filter, the DC offset suppression feedback loop is equivalent to an open circuit, that is, the negative feedback loop does not work, so the AC signal will still be amplified step by step as if there is no feedback loop.

[0139] The feedback filter circuit 1241 in the feedback circuit 124 can be implemented by passive resistors and capacitors, or by passive resistors and capacitors combined with active amplifiers. As for the feedback amplifier 1242, it can be implemented by a single-stage amplifier structure, which can be a simple common-source amplifier or a more complex common-source common-gate amplifier structure. In addition, it can also be implemented by a multi-stage amplifier structure, such as a two-stage cascade amplifier, which will not be described in detail here.

[0140] In summary, the embodiments of the present disclosure provide an effective value detection circuit, which aims to characterize the effective value of a high-frequency input signal using a low-frequency AC signal, and provides two specific implementation methods. Figure 1 In the implementation shown in (a), the input stage first uses a mixing circuit to mix the high-frequency input signal, then uses a squaring circuit to square the mixed signal, and then uses a bandpass filter to extract a low-frequency AC signal that can reflect the square of the effective value of the signal. Finally, the low-frequency AC signal is logarithmically envelope detected to obtain an output signal corresponding to the effective value of the input high-frequency signal.

[0141] exist Figure 1 In the implementation shown in (b), the input stage first uses a mixing circuit to mix the high-frequency input signal, then uses a square circuit to square the mixed signal, and then uses a low-pass filter to extract the low-frequency AC signal and DC signal that can reflect the square of the effective value of the signal, and filter out the invalid signal at high frequency. Finally, the low-frequency AC signal is sent to the logarithmic envelope detection circuit with DC offset suppression, the DC invalid signal and offset voltage are suppressed, the low-frequency AC signal is detected by the logarithmic envelope, and the output signal corresponding to the effective value of the input high-frequency signal is obtained. The offset voltage caused by the mismatch of the square circuit's own devices is avoided, the sensitivity of the overall detection circuit is improved, and the dynamic range of the detection circuit is effectively expanded.

[0142] At the same time, because the frequency of the preset signal is lower than the frequency of the input signal, the squared signal after squaring includes an AC low-frequency component. The AC low-frequency component is logarithmically converted, and there is no need for a square circuit to retain a large-bandwidth high-frequency signal. Detection of the high-frequency signal can also be avoided, reducing the difficulty of square calculation and detection and saving power consumption.

[0143] In another embodiment of the present disclosure, an effective value detection chip is provided, comprising the effective value detection circuit 10 described in any one of the aforementioned embodiments.

[0144] It should be noted that in the disclosed embodiment, the new architecture of mixing, squaring, filtering and finally logarithmic envelope detection avoids the loss of sensitivity of the effective value detection circuit caused by the mismatch of the square unit itself, and achieves a larger detection dynamic range. The key point lies in the detection method and system architecture of mixing, squaring, filtering and finally logarithmic envelope detection.

[0145] In the disclosed embodiment, the amplitude of the signal at low frequency is used to reflect the effective value square of the input signal, and the DC signal and the high-frequency AC signal are further filtered out by bandpass filtering, leaving only the AC signal at low frequency. Then, the amplitude of the low-frequency AC signal is extracted by the low-frequency logarithmic envelope detection circuit (i.e., the first logarithmic conversion circuit 1041), and logarithmic conversion is performed to obtain an output signal reflecting the effective value of the input signal.

[0146] Alternatively, the amplitude of the signal at low frequency is used to reflect the effective value square of the input signal, and the high-frequency AC signal is further filtered out by low-pass filtering, leaving the AC signal and DC signal at low frequency. Then, the amplitude of the low-frequency AC signal is extracted through a low-frequency logarithmic envelope detection circuit with DC offset suppression (i.e., the second logarithmic conversion circuit 1042), and logarithmic conversion is performed to obtain an output signal reflecting the effective value of the input signal.

[0147] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0148] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0149] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0150] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0151] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0152] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0153] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. An effective value detection circuit, It is characterized in that include: A mixing circuit, used for mixing an input signal and a preset signal to generate a mixed signal; the input signal and the preset signal are both AC signals, and the frequency of the preset signal is lower than the frequency of the input signal; A squaring circuit, used for squaring the mixed signal to generate a square signal; the square signal includes an AC low-frequency component; A first filtering circuit is used to filter the square signal, retain the AC low-frequency component in the square signal, and generate a first filtered signal; The first logarithmic conversion circuit is used to perform logarithmic conversion on the first filtered signal to generate an output signal, where the output signal is used to represent the effective value of the input signal.

2. The circuit according to claim 1, It is characterized in that The first filtering circuit is used to filter the DC component and the AC high-frequency component in the square signal, and retain the AC low-frequency component in the square signal.

3. The circuit according to claim 2, It is characterized in that The first filtering circuit is a bandpass filter.

4. The circuit according to claim 1, It is characterized in that The first logarithmic conversion circuit includes a plurality of cascaded limiting amplifiers and a plurality of rectifier circuits; wherein: The input end of the first-stage limiting amplifier is connected to the output end of the first filtering circuit to receive the first filtered signal; the output end of each limiting amplifier is connected to the input end of one of the rectifier circuits, and the output ends of all the rectifier circuits are connected together to generate the output signal.

5. An effective value detection circuit, It is characterized in that include: A mixing circuit, used for mixing an input signal and a preset signal to generate a mixed signal; the input signal and the preset signal are both AC signals, and the frequency of the preset signal is lower than the frequency of the input signal; A squaring circuit, used for squaring the mixed signal to generate a square signal; the square signal includes an AC low-frequency component; A second filtering circuit is used to filter the square signal, retain the DC component and AC low-frequency component in the square signal, and generate a second filtered signal; The second logarithmic conversion circuit is used to suppress the DC component in the second filtered signal and perform logarithmic conversion on the AC low-frequency component in the second filtered signal to generate an output signal, wherein the output signal is used to represent the effective value of the input signal.

6. The circuit according to claim 5, It is characterized in that The second filtering circuit is used to filter the AC high-frequency components in the square signal and retain the DC components and AC low-frequency components in the square signal.

7. The circuit according to claim 6, It is characterized in that The second filtering circuit is a low-pass filter.

8. The circuit according to claim 5, It is characterized in that The second logarithmic conversion circuit includes N cascaded limiting amplifiers, multiple rectifier circuits, and a feedback circuit; wherein: The input end of the first-stage limiting amplifier is connected to the output end of the second filtering circuit to receive the second filtered signal; the output end of each of the limiting amplifiers is connected to the input end of one of the rectifier circuits, and the output ends of all the rectifier circuits are connected together to generate the output signal; The feedback circuit is connected between the output end of the j-th level limiting amplifier and the input end of the i-th level limiting amplifier, and is used to input a feedback signal to the input end of the i-th level limiting amplifier, wherein the feedback signal includes a DC portion of the output signal of the j-th level limiting amplifier, i and j are both integers greater than or equal to 1 and less than or equal to N, and j is greater than or equal to i.

9. The circuit according to claim 8, It is characterized in that The feedback circuit includes a feedback filter circuit for receiving the output signal of the j-th limiting amplifier and filtering the output signal of the j-th limiting amplifier to pass the DC part of the output signal of the j-th limiting amplifier to generate the feedback signal.

10. The circuit according to any one of claims 1 to 9, It is characterized in that The frequency of the preset signal is less than 1 / 20 of the frequency of the input signal; the amplitude of the preset signal is the same as the amplitude of the power supply voltage of the effective value detection circuit.

11. An effective value detection chip, It is characterized in that The invention comprises the effective value detection circuit as claimed in any one of claims 1 to 10.

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