Multi-channel SiPM data acquisition system, method, SiPM gamma ray detector and composite detector system

Abstract

This invention provides a multi-channel SiPM data acquisition system, method, SiPM-type gamma-ray detector, and composite detector system. In the data acquisition system, an ASIC chip compares the amplified SiPM signal with preset trigger selection conditions. If the amplified SiPM signal meets the trigger selection conditions, a first trigger signal is sent to the FPGA control board. The FPGA control board sends parameter configuration signals to the ASIC chip, controlling the configuration of the ASIC chip's parameters. Upon receiving the first trigger signal from the ASIC chip, it outputs a first control signal and a second control signal. This invention improves debugging efficiency, fully utilizes the positional sensitivity of the SiPM array, effectively reduces signal saturation problems caused by parallel readouts, and achieves a large signal dynamic range.

Description

Technical Field

[0001] This invention relates to the field of space astronomy technology, and in particular to a multi-channel SiPM data acquisition system, method, SiPM-type gamma-ray detector, and composite detector system. Background Technology

[0002] Silicon photomultiplier tubes (SiPMs) are increasingly being used in space astronomical exploration due to their advantages such as compact size and low operating voltage.

[0003] Currently, two-dimensional sensitive detectors composed of SiPM and scintillator strip arrays can be used for polarization measurement of medium and high energy gamma rays and imaging of encoding plates. The gamma ray SiPM array detectors carried by small satellites all use a data acquisition method of multiple signals connected in parallel and then read out by a single channel.

[0004] However, the above data acquisition method loses the position information of the SiPM array. The SiPM array detector lacks position sensitivity, and the amplifier gain in the SiPM data acquisition system is determined by a resistor with a fixed resistance value, which cannot be adjusted according to needs during satellite operation. Summary of the Invention

[0005] This invention provides a multi-channel SiPM data acquisition system, method, and composite detector system to address the shortcomings of existing SiPM data acquisition systems, which use a single-channel readout method after multiple signals are connected in parallel, resulting in a lack of position sensitivity and reduced system debugging efficiency due to the inability to adjust the amplifier gain in the SiPM data acquisition system according to requirements. The invention enables the readout of multi-channel signals from the SiPM array, fully utilizes the position sensitivity advantage of the SiPM array, and improves the debugging efficiency of the detector.

[0006] This invention provides a multi-channel SiPM data acquisition system for use in space astronomical detectors. The multi-channel SiPM data acquisition system includes a multi-channel SiPM signal input terminal, a SiPM signal output terminal, an ASIC chip, an FPGA control board, a back-end amplifier, an analog-to-digital converter, and a host computer.

[0007] The ASIC chip includes a first output terminal and a second output terminal. The first output terminal is connected to the FPGA control board, and the second output terminal is connected to the back-end amplifier. The ASIC chip is used to convert the multi-channel SiPM signal input from the multi-channel SiPM signal input terminal into a digital-to-analog converter, amplify and shape it, compare the amplified and shaped SiPM signal with a preset trigger selection condition, and send a first trigger signal to the FPGA control board if the amplified and shaped SiPM signal meets the trigger selection condition.

[0008] The FPGA control board includes a parameter configuration terminal, a third output terminal, and a fourth output terminal. The parameter configuration terminal and the third output terminal are respectively connected to the ASIC chip, and the fourth output terminal is connected to the analog-to-digital converter. The FPGA control board is used to send parameter configuration signals to the ASIC chip, and control the configuration of the parameters to be configured on the ASIC chip through the parameter configuration signals; and when receiving a first trigger signal sent by the ASIC chip, outputting a first control signal and a second control signal, using the first control signal to control the ASIC chip to serially output the amplified and shaped SiPM signal to the back-end amplifier; and using the second control signal to control the analog-to-digital converter to serially read the signal pulse amplitude of the SiPM signal output by the back-end amplifier.

[0009] The back-end amplifier is used to process the serially output multi-channel SiPM signal so that the signal pulse amplitude of the multi-channel SiPM signal is within the signal pulse amplitude range of the analog-to-digital converter.

[0010] The analog-to-digital converter is used to serially read the signal pulse amplitude of the SiPM signal under the control of the second control signal, and output the signal pulse amplitude of the multi-channel SiPM signal to the FPGA control board for buffering;

[0011] The host computer is connected to the FPGA control board, and the host computer is used to store the signal pulse amplitude of the multi-channel SiPM signal output by the FPGA control board.

[0012] According to the multi-channel SiPM data acquisition system provided by the present invention, the host computer is also connected to the ASIC chip, and the host computer is also used to send serial port commands to the ASIC chip. The serial port commands are used to control the ASIC chip to configure the parameters to be configured according to the parameter configuration signals. The parameters to be configured include the gain, molding time, signal triggering logic, threshold, and SiPM bias voltage of each channel SiPM signal.

[0013] According to the multi-channel SiPM data acquisition system provided by the present invention, the ASIC chip includes an 8-bit DAC, a front-end amplifier, a slow-forming amplifier, a fast-forming amplifier, a peak detection and hold module, and a signal discriminator;

[0014] The parameter configuration signal is a 20μs clock cycle signal, and the first control signal is a 20ns clock cycle signal;

[0015] The ASIC chip is used to convert the SiPM signal input from the SiPM signal input terminal into a digital-to-analog converter, amplify and shape it, compare the amplified and shaped SiPM signal with preset trigger selection conditions, and send a first trigger signal to the FPGA control board if the amplified and shaped SiPM signal meets the trigger selection conditions. Specifically, this includes: the ASIC chip receiving the SiPM signal, converting the SiPM signal into a digital-to-analog converter using the 8-bit DAC, and amplifying and shaping the converted SiPM signal using the front-end amplifier; the amplified and shaped SiPM signal is fanned out in two paths to the slow-shape amplifier and the fast-shape amplifier, respectively. The fast-forming amplifier is amplified twice and output, and its output is connected to the signal discriminator. The signal comparison threshold of the signal discriminator is provided by an instruction-adjustable DAC. After each SiPM signal is output through the signal discriminator, it is processed by "OR" logic inside the ASIC chip and then output as the first trigger signal. The output of the slow-forming amplifier is connected to the peak detection and hold module. When the FPGA receives the first trigger signal, it controls the peak detection and hold module to latch the multi-channel SiPM signals amplified twice by the slow-forming amplifier and outputs the latched multi-channel SiPM signals serially to the analog-to-digital converter under the control of the first control signal.

[0016] According to the multi-channel SiPM data acquisition system provided by the present invention, the ASIC chip further includes a register for storing the configuration results of the parameters to be configured.

[0017] In the multi-channel SiPM data acquisition system provided by the present invention, the first control signal is LVCMOS and LVDS level.

[0018] According to the multi-channel SiPM data acquisition system provided by the present invention, the FPGA control board outputs the signal pulse amplitude of the multi-channel SiPM signal to the host computer through serial communication.

[0019] According to the multi-channel SiPM data acquisition system provided by the present invention, the amplified and shaped SiPM signal satisfies the trigger selection condition, specifically including:

[0020] The amplified SiPM signal in any channel is greater than the set threshold.

[0021] According to the multi-channel SiPM data acquisition system provided by the present invention, the host computer is also used to display the signal pulse amplitude distribution diagram of the SiPM signal of the pre-selected channel in real time.

[0022] According to the multi-channel SiPM data acquisition system provided by the present invention, the FPGA control board further includes a fifth output terminal, which is connected to an external control slave device. The FPGA control board is also used to send a trigger selection signal to the external control slave device, and after receiving a second trigger signal from the external control slave device, to control the acquisition of the multi-channel SiPM signals input to the multi-channel SiPM signal input terminal. The external control slave device is used to judge the trigger selection signal, and after successful judgment, to distribute a second trigger signal to the FPGA control board. The second trigger signal is an I2C synchronous trigger signal.

[0023] According to the multi-channel SiPM data acquisition system provided by the present invention, the host computer is also connected to the external control slave device, and the host computer is also used to receive the TCP synchronization start / stop signal sent by the external control slave device, and to save the acquired multi-channel SiPM signals under the control of the TCP synchronization start / stop signal.

[0024] The present invention also provides a SiPM type gamma ray detector, comprising: the multi-channel SiPM data acquisition system as described above.

[0025] The present invention also provides a composite detector system, comprising: a control slave and at least two SiPM type gamma ray detectors as described above, each of the SiPM type gamma ray detectors being connected to the control slave.

[0026] The present invention also provides a multi-channel SiPM data acquisition method, which is implemented by a multi-channel SiPM data acquisition system as described in any of the preceding claims. The multi-channel SiPM data acquisition system includes a multi-channel SiPM signal input terminal, a SiPM signal output terminal, an ASIC chip, an FPGA control board, a back-end amplifier, an analog-to-digital converter, and a host computer.

[0027] The method includes:

[0028] The FPGA control board loads the first configuration parameters of the ASIC chip and sends a parameter configuration signal to the ASIC chip. Under the control of the parameter configuration signal, the first configuration parameters are written into the ASIC chip, wherein the first configuration parameters are the initial operating parameters of the ASIC chip.

[0029] The system determines whether the ASIC chip has received a serial port command from the host computer. If the serial port command is received, it is parsed to obtain the second configuration parameters of the ASIC chip, and the ASIC chip is updated to the second configuration parameters through the parameter configuration signal. If the serial port command is not received, it detects whether the ASIC chip has generated a first trigger signal. The serial port command includes the data acquisition mode of the ASIC chip, and the acquisition module includes a self-trigger working mode and an external trigger working mode.

[0030] When the ASIC chip generates a first trigger signal, it is determined whether the data acquisition mode of the ASIC chip is a self-triggered working mode or an externally triggered working mode.

[0031] The ASIC chip operates in a self-trigger mode for data acquisition. Under the action of the first trigger signal, the FPGA control board outputs a first control signal. Under the control of the first control signal, the ASIC chip performs peak hold on the amplified SiPM signal and serially outputs it to the back-end amplifier. The back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to the analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering. The FPGA control board uses serial communication to output the buffered signal pulse amplitude of each channel's SiPM signal to the host computer for storage.

[0032] The ASIC chip's data acquisition mode is an external trigger working mode. It determines whether the ASIC chip receives a second trigger signal from an external control slave within a preset time window, where the second trigger signal is an I2C trigger signal. Upon receiving the second trigger signal, the ASIC chip performs peak hold on the amplified and shaped SiPM signal and outputs it serially to a back-end amplifier. The back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to an analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering. The FPGA control board's serial communication mode outputs the buffered signal pulse amplitude of each channel's SiPM signal to a host computer for storage.

[0033] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the multi-channel SiPM data acquisition method as described above.

[0034] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the multi-channel SiPM data acquisition method as described above.

[0035] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the multi-channel SiPM data acquisition method as described above.

[0036] The multi-channel SiPM data acquisition system, method, SiPM gamma ray detector, and composite detector system provided by this invention compare the amplified SiPM signal with preset trigger selection conditions using an ASIC chip. If the amplified SiPM signal meets the trigger selection conditions, a first trigger signal is sent to the FPGA control board. The FPGA control board sends parameter configuration signals to the ASIC chip, controlling the configuration of the parameters to be configured on the ASIC chip. Upon receiving the first trigger signal from the ASIC chip, a first control signal and a second control signal are output. The first control signal controls the ASIC chip to serially output the amplified SiPM signal to a back-end amplifier. The back-end amplifier processes the serially output multi-channel SiPM signal to ensure that the signal pulse amplitude of the multi-channel SiPM signal is within the signal pulse amplitude range of the analog-to-digital converter (ADC). The second control signal controls the ADC to serially read the signal pulse amplitude of the SiPM signal output from the back-end amplifier and outputs the signal pulse amplitude of the multi-channel SiPM signal to the FPGA control board for buffering. The host computer stores the signal pulse amplitude of the multi-channel SiPM signal buffered and output by the FPGA control board. This invention uses ASIC technology to improve the SiPM array readout system used in space astronomy, transforming the single-channel signal readout data acquisition system into a multi-channel SiPM data acquisition system. This multi-channel SiPM data acquisition system is highly integrated and can adjust the operating parameters of the ASIC chip by sending commands, improving the debugging efficiency during the detector development process. It enables the SiPM array units to be read out separately, fully leveraging the positional sensitivity of the SiPM array, and effectively reducing the signal saturation problem caused by parallel readout, achieving a large signal dynamic range, thereby solving the space and power consumption problems of satellite payloads. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the structure of the multi-channel SiPM data acquisition system provided in an embodiment of the present invention.

[0039] Figure 2 This is a schematic block diagram of the internal configuration of the ASIC chip provided in the embodiment of the present invention.

[0040] Figure 3 This is a schematic diagram of 32-channel SiPM front-end signal coupling and ASIC configuration provided in an embodiment of the present invention.

[0041] Figure 4 This is a schematic diagram of the ASIC signal main amplifier and analog data signal conversion module provided in an embodiment of the present invention.

[0042] Figure 5 This is a schematic diagram of the FPGA control and serial communication module provided in an embodiment of the present invention.

[0043] Figure 6 This is one of the flowcharts of the multi-channel SiPM data acquisition method provided in the embodiments of the present invention.

[0044] Figure 7 This is the second flowchart of the multi-channel SiPM data acquisition method provided in this embodiment of the invention.

[0045] Figure 8 This is a schematic diagram of the single-channel input signal of SiPM and the single-channel amplified signal inside the ASIC provided in the embodiment of the present invention.

[0046] Figure 9 This is a schematic diagram of the analog signal serial readout waveform provided in an embodiment of the present invention.

[0047] Figure 10 This is a timing diagram of the slow control signal for the ASIC operating mode configuration provided in an embodiment of the present invention.

[0048] Figure 11 This is a timing diagram of the data acquisition fast control signal after the event is triggered, provided in an embodiment of the present invention.

[0049] Figure 12 This is a schematic diagram of the main interface of the host computer control software provided in an embodiment of the present invention.

[0050] Figure 13This is a schematic diagram of the single-spectrum interface of the host computer control software provided in an embodiment of the present invention.

[0051] Figure 14 This is obtained through offline data processing provided in the embodiments of the present invention. 241 Schematic diagram of Am pulse amplitude spectrum.

[0052] Figure 15 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0054] It should be noted that the serial numbers assigned to the components or objects described in this invention, such as "first" and "second", are only used to distinguish the components or objects described and do not have any sequential or technical meaning.

[0055] In practical applications, although the two-dimensional sensitive detector composed of SiPM and scintillator strip array can be used for polarization measurement of medium and high energy gamma rays, encoding plate imaging, etc., the SiPM arrays of gamma ray detectors currently carried by small satellites are all simplified schemes with multiple signals connected in parallel and read out by a single channel. The multi-channel data acquisition technology of SiPM array has not yet been realized in satellite orbit and lacks sufficient experimental verification.

[0056] Currently, the signal readout method of SiPM arrays in orbit all involves data acquisition by combining multiple signals and then amplifying a single signal, resulting in the loss of SiPM array position information. Multi-channel readout requires a highly integrated electronic system, necessitating the use of ASIC technology to address space and power consumption issues. Furthermore, the amplifier gain in current SiPM data acquisition systems is determined by a fixed-value resistor, which cannot be adjusted according to requirements during operation.

[0057] For example, Tsinghua University's GRID CubeSat project is used to detect the electromagnetic counterpart of gravitational waves. GRID's gamma-ray detection energy range is 10 keV to 2 MeV. GRID is carried on a 6U CubeSat (10cm × 20cm × 30cm). The GRID detector mainly consists of a novel scintillator GAGG and a SiPM array. The SiPM array uses a parallel single-channel readout method and does not have multi-channel signal readout capability.

[0058] In the "All-Sky Monitor for High-Energy Electromagnetic Counterparts of Gravitational Wave Bursts" project at the Institute of High Energy Physics, the gamma / X-ray detectors (GRDs) on satellites A, B, and C are used to measure and locate gamma-ray energy spectra. The GRDs employ high-output lanthanum bromide (LaBr3:Ce) crystals in conjunction with novel SiPM photomultiplier devices. The GRD's SiPM array consists of 64 cells, using a parallel readout method, with all 64 channels combined into a single readout. The SiPM cells are evenly arranged on the front of a three-inch diameter circuit board. To increase the collection efficiency of scintillation light, Tyvek diffuse reflective films are adhered to the gaps between the SiPM cells. The back of the SiPM circuit board houses the GRD's front-end amplifier, which amplifies and shapes the SiPM signals. The front-end amplifiers of the GRDs on satellites A, B, and C are divided into high and low gain amplifiers, but all only read out the signals from all SiPM channels in parallel, lacking multi-channel signal readout functionality. To address the aforementioned problems, this invention provides a multi-channel SiPM data acquisition system for space astronomical exploration. It solves the key issues of signal acquisition and trigger selection logic in multi-channel SiPM signal readout, and is of great significance to the technical applications of space astronomical exploration. This invention can modify the amplifier gain by sending commands. The purpose of this invention is to utilize advanced ASIC technology to process multi-channel signals from SiPM arrays, improving the traditional single-channel data acquisition method of SiPM arrays to multi-channel data acquisition, thereby increasing the detector's position sensitivity. The following describes... Figures 1-5 The present invention describes a multi-channel SiPM data acquisition system.

[0059] Figure 1 An exemplary schematic diagram of the multi-channel SiPM data acquisition system provided in an embodiment of the present invention is shown, with reference to... Figure 1 As shown, this multi-channel SiPM data acquisition system is applied to a space astronomical detector and includes: a multi-channel SiPM signal input terminal IN, a SiPM signal output terminal OUT, an ASIC chip 100, an FPGA control board 200, a back-end amplifier 300, an analog-to-digital converter 400, and a host computer 500.

[0060] The ASIC chip 100 includes a first output terminal A and a second output terminal B. The first output terminal A is connected to the FPGA control board 200, and the second output terminal B is connected to the back-end amplifier 300. The ASIC chip 100 is used to convert the multi-channel SiPM signal input from the multi-channel SiPM signal input terminal into a digital-to-analog converter, amplify and shape it, compare the amplified and shaped SiPM signal with a preset trigger selection condition, and send a first trigger signal to the FPGA control board 200 if the amplified and shaped SiPM signal meets the trigger selection condition.

[0061] The FPGA control board 200 includes a parameter configuration terminal C, a third output terminal D, and a fourth output terminal E. The parameter configuration terminal C and the third output terminal D are respectively connected to the ASIC chip 100, and the fourth output terminal E is connected to the analog-to-digital converter 400. The FPGA control board 200 is used to send parameter configuration signals to the ASIC chip 100, and to control the configuration of the parameters to be configured on the ASIC chip 100 through the parameter configuration signals; and, upon receiving a first trigger signal sent by the ASIC chip 100, to output a first control signal and a second control signal. The first control signal controls the ASIC chip 100 to serially output the amplified and shaped SiPM signal to the back-end amplifier 300; and the second control signal controls the analog-to-digital converter 400 to serially read the signal pulse amplitude of the SiPM signal output by the back-end amplifier 300.

[0062] Specifically, the configurable parameters of the ASIC chip are the operating parameters of the ASIC chip; the first control signal is used to control the ASIC chip 100 to serially output the amplified SiPM signal to the back-end amplifier, and the second control signal is used to control the analog-to-digital converter to serially read the signal pulse amplitude of the SiPM signal output by the back-end amplifier.

[0063] The back-end amplifier 300 is used to process the serially output multi-channel SiPM signal so that the signal pulse amplitude of the multi-channel SiPM signal is within the signal pulse amplitude range of the analog-to-digital converter 400.

[0064] The analog-to-digital converter 400 is used to serially read the signal pulse amplitude of the SiPM signal under the control of the second control signal, and output the signal pulse amplitude of the multi-channel SiPM signal to the FPGA control board 200 for buffering.

[0065] The host computer 500 is connected to the FPGA control board 200, and the host computer 500 is used to store the signal pulse amplitude of the multi-channel SiPM signal output by the FPGA control board 200.

[0066] In possible embodiments, the parameters to be configured include operating parameters such as the gain, molding time, signal triggering logic, threshold, and SiPM bias voltage of each channel's SiPM signal. Therefore, the multi-channel SiPM data acquisition system provided in this embodiment of the invention, based on a multi-channel signal readout application-specific integrated circuit (ASIC) chip, can configure the signal gain, molding time, signal triggering logic, threshold, and SiPM bias voltage of each channel using instructions.

[0067] In some possible implementations, the multi-channel SiPM data acquisition system provided by this solution includes 32 SiPM (Silicon Photomultiplier Tube) readout channels, enabling simultaneous reading of all 32 SiPM channels. In possible embodiments, the ASIC chip used for multi-channel SiPM signal processing is an application-specific integrated circuit, such as the Citiroc 1A ASIC chip. The host computer is a PC, and the software on the PC is used for parameter configuration, data storage, and real-time monitoring.

[0068] In a possible embodiment, the multi-channel signals of the SiPM array are connected to the ASIC chip via connectors. The ASIC has functions of signal amplification and shaping, trigger logic configuration, multi-channel signal hold, and gain correction. When the input SiPM signal meets the trigger selection condition inside the ASIC chip, the ASIC chip will input a signal to the FPGA control board to trigger. In this embodiment, the trigger selection condition can be set to any channel's amplified SiPM signal being greater than a set threshold. That is, the signal triggering condition is that if any one of the 32 SiPM signal input channels is greater than the set threshold, it is determined that the trigger selection condition is met, and at this time, the ASIC chip inputs a signal to the FPGA control board to trigger.

[0069] In a possible embodiment, the first control signal is LVCMOS and LVDS level, that is, the FPGA control board controls the ASIC chip through LVCMOS and LVDS level.

[0070] In some possible implementations, the host computer 500 is also connected to the ASIC chip 100, and the host computer 500 is also used to send serial port commands to the ASIC chip 100, wherein the serial port commands control the ASIC chip to configure the parameters to be configured according to the parameter configuration signal.

[0071] In a possible embodiment, the ASIC chip also includes a register for storing the configuration result of the parameter to be configured.

[0072] Specifically, after the multi-channel SiPM data acquisition system is powered on, the configuration parameters stored on the FPGA control board are loaded first. Then, the FPGA control board writes the configuration parameters into the ASIC configuration register. After the ASIC chip completes the default parameter configuration, it enters the standby state.

[0073] In a possible embodiment, the FPGA control board outputs the signal pulse amplitude of the multi-channel SiPM signal to the host computer via serial communication.

[0074] In a possible embodiment, the ASIC chip includes an 8-bit DAC, a front-end amplifier, a slow-forming amplifier, a fast-forming amplifier, a peak detection and hold module, and a signal discriminator; the parameter configuration signal is a 20μs clock cycle signal, and the first control signal is a 20ns clock cycle signal;

[0075] The ASIC chip is used to convert the SiPM signal input from the SiPM signal input terminal into a digital-to-analog converter, amplify and shape it, compare the amplified and shaped SiPM signal with preset trigger selection conditions, and send a first trigger signal to the FPGA control board if the amplified and shaped SiPM signal meets the trigger selection conditions. Specifically, this includes: the ASIC chip receiving the SiPM signal, converting the SiPM signal into a digital-to-analog converter using the 8-bit DAC, and amplifying and shaping the converted SiPM signal using the front-end amplifier; the amplified and shaped SiPM signal is fanned out into two paths, one to the slow shaping amplifier and the other to the fast shaping amplifier. The fast-forming amplifier output is connected to the signal discriminator. The signal comparison threshold of the signal discriminator is provided by an instruction-adjustable DAC. After each SiPM signal is output through the signal discriminator, it is processed by "OR" logic inside the ASIC chip to output the first trigger signal. The output of the slow-forming amplifier is connected to the peak detection and hold module. When the FPGA receives the first trigger signal, it controls the peak detection and hold module to latch the multi-channel SiPM signal output by the slow-forming amplifier and serially outputs the latched multi-channel SiPM signal to the analog-to-digital converter under the control of the first control signal.

[0076] Specifically, the multi-channel SiPM data acquisition system acquires multi-channel SiPM signals in two modes: self-triggered mode and external trigger mode. In self-triggered mode, the SiPM signal is compared with the trigger selection conditions internal to the ASIC chip, and a signal is output to trigger the acquisition when the conditions are met. Specifically, in self-triggered mode, the FPGA's slow signal (20μs clock cycle), i.e., the parameter configuration signal, is used to configure the ASIC's operating mode. For example... Figure 2 A schematic block diagram of the internal configuration of an ASIC chip provided in an embodiment of the present invention is shown, as follows: Figure 2As shown, for each channel, the SiPM signal is connected to the ASIC chip and then in parallel with the chip's internal 8-bit DAC (digital-to-analog converter) module. This module can be programmed to change its voltage value, thus fine-tuning the SiPM's operating voltage. The SiPM signal is AC-coupled and enters the front-end amplifier for first-stage amplification. The amplifier gain and molding time can be adjusted via external commands. The amplified signal is fanned out in two paths to the slow-forming and fast-forming amplifiers. The output of the slow-forming amplifier is connected to the peak detection and hold module. When it receives a control signal from the FPGA control board, it serially outputs the latched analog signal for processing by the back-end analog-to-digital converter. The output of the fast-forming amplifier is connected to the signal discriminator. The signal comparison threshold of the signal discriminator is provided by the command-adjustable DAC. The discriminator outputs the SiPM signal for all channels, which is then processed by an "OR" logic within the ASIC chip to trigger the output signal.

[0077] In self-triggered mode, the FPGA's fast signal (20ns clock cycle) is used to control the ASIC's acquisition of physical events. After the ASIC generates a trigger signal, the FPGA first controls the ASIC to latch the multi-channel signals, and then the ASIC serially outputs the multiple analog signals. The multiple analog signals are processed by a back-end amplifier to match the signal amplitude range of the analog-to-digital converter (ADC). The FPGA controls the ADC to serially read the signal amplitude, store it in the FPGA control board's internal buffer, and transmit the data to the PC via serial communication. The PC's host computer software saves the input SIPM data and can plot the signal pulse amplitude distribution of the selected channel in real time.

[0078] In external trigger mode, the external control slave receives the trigger selection logic output from the FPGA control board, makes a logical judgment, and then sends an I2C synchronous trigger signal to the FPGA control board. Upon triggering, the FPGA control board controls the ASIC chip to acquire the signal. The external control slave also sends a TCP synchronous start / stop signal to the data acquisition system, controlling the host computer to save the input SiPM data.

[0079] In some possible implementations, in the external trigger operating mode, the FPGA control board further includes a fifth output terminal connected to an external control slave device. The FPGA control board is also used to send a trigger selection signal to the external control slave device, and upon receiving a second trigger signal from the external control slave device, to control the ASIC chip to acquire the multi-channel SiPM signals input to the multi-channel SiPM signal input terminal. The second trigger signal is an I2C synchronization trigger signal, such as an I2C synchronization trigger data packet, distributed by the external control slave device to the FPGA control board after successful judgment of the trigger selection signal. Furthermore, a host computer is also connected to the external control slave device, and the host computer is also used to receive a TCP synchronization start / stop signal sent by the external control slave device, and to save the acquired multi-channel SiPM signals under the control of the TCP synchronization start / stop signal.

[0080] In possible embodiments, such as Figure 1 As shown, the FPGA control board of the multi-channel SiPM data acquisition system can be connected to an external control slave. The FPGA control board sends a trigger selection signal to the external control slave. After receiving the second trigger signal (synchronous trigger signal) from the external control slave, the FPGA control board achieves the external trigger working mode. In the external trigger working mode, the FPGA control board controls the ASIC chip to acquire the multi-channel SiPM signals input to the multi-channel SiPM signal input terminal. Here, the second trigger signal is an I2C synchronous trigger signal. The external control slave judges the trigger selection signal, and if the judgment is successful, it distributes the signal to the FPGA control board. Furthermore, the host computer of the multi-channel SiPM data acquisition system is also connected to the external control slave. The host computer receives the TCP synchronous start / stop signal sent by the external control slave. Under the control of the TCP synchronous start / stop signal, the host computer saves the acquired multi-channel SiPM signals, completing the SiPM signal data acquisition in the external trigger mode.

[0081] In possible implementations, Figure 3 The schematic diagram of the 32-channel SiPM front-end signal coupling and ASIC configuration provided in an embodiment of the present invention is shown, as follows: Figure 3 As shown, each SiPM signal is connected to the ASIC input pin in. <n>(N is the channel number) Simultaneously, a 50Ω filter resistor and a nF capacitor are connected in series to the power supply analog ground AVSS. The ASIC pin configuration is as follows: Figure 3 As shown, the pin configuration is mainly divided into the power configuration pin group (UAAC), the signal input group (UAAB), and the IO port group (UAAD). In the IO port group, pins whose names begin with 'v' are voltage configuration pins, and out_lg (low gain signal output) and out_hg (high gain signal output) are analog output signal pins. In this embodiment of the invention, only out_lg is used as an ASIC signal output and connected to the main amplifier at the back end; the remaining pins are digital control pins.

[0082] In possible implementations, Figure 4 The schematic diagram of the ASIC signal main amplifier and analog data signal conversion module provided in the embodiment of the present invention is shown, as follows: Figure 4 As shown, the ASIC output signal is amplified by a two-stage inverting amplifier (LM6172). The first-stage amplifier uses a reference voltage source, model LM385, which, together with a sliding rheostat, generates an adjustable reference voltage to adjust the signal baseline. The amplified signal is then converted from analog to digital by an AD9243 chip, and the data is buffered in the FPGA. Subsequently, it is transmitted to the PC host computer via serial communication.

[0083] It should be noted that although using existing discrete components to build a data acquisition system can partially realize the functions of an ASIC chip, each channel of the system requires a separate amplifier and digital-to-analog converter chip, resulting in a much larger size and higher power consumption than the solution in this embodiment of the invention.

[0084] In a possible embodiment, Figure 5 The schematic diagram of the FPGA control and serial communication module provided in the embodiment of the present invention is shown, as follows: Figure 5 As shown, the FPGA model is XC3S250E, and the rest are standard peripheral configuration chips for this FPGA chip. AMS1117 provides power to the FPGA, and XCF02V0SC is the program configuration memory. The serial communication module uses RS232 for data transmission and configuration command reception.

[0085] The multi-channel SiPM data acquisition system provided in this invention enables the readout of multi-channel signals from the SiPM array. It can send commands to adjust amplifier gain, threshold, trigger logic, and other operating parameters in real time, fully leveraging the positional sensitivity of the SiPM array. This multi-channel SiPM data acquisition system features high integration, addressing the space and power consumption issues of satellite payloads. Furthermore, the host computer control system designed in this invention enables real-time monitoring and command control of the SiPM data acquisition system, improving the debugging efficiency during the development of the detector in which the multi-channel SiPM data acquisition system is located.

[0086] In some possible implementations, a SiPM-type gamma ray detector is also provided, comprising: a multi-channel SiPM data acquisition system as described above.

[0087] The multi-channel SiPM data acquisition system provided in this invention enables SiPM-type gamma-ray detectors in space astronomy to possess position-sensitive characteristics, thereby facilitating gamma-ray burst polarization measurement and location. To meet the requirements for adjusting satellite operating parameters in orbit, the system can send commands to change the acquisition modes, gain, threshold, and SiPM operating voltage of each signal, allowing for flexible parameter configuration according to actual mission requirements, thus improving the versatility and flexibility of the data acquisition system.

[0088] The present invention also provides a composite detector system, comprising: a control slave and at least two SiPM type gamma ray detectors as described above, each of the SiPM type gamma ray detectors being connected to the control slave.

[0089] Based on the above embodiments, this invention also provides a composite detector system, including a control slave and at least two SiPM type gamma ray detectors as described above, each SiPM type gamma ray detector being connected to the control slave.

[0090] In a possible embodiment, the composite detector system connects multiple detectors to a control slave device. The control slave device sends synchronous trigger signals to each detector, controlling the multi-channel SiPM data acquisition system of each detector to acquire multi-channel SiPM signals. For example, the composite detector system provides a trigger selection signal and cooperates with other detector systems via I2C communication to achieve synchronous trigger signal acquisition. To monitor the status of the data acquisition system in real time, the host computer control software provided in this embodiment monitors the energy spectrum and count rate of the data in real time. The data obtained by the data acquisition system can be directly saved, or the host computer can listen to the TCP protocol and parse instructions to realize the synchronous start and stop of data acquisition and data file storage.

[0091] The multi-channel SiPM data acquisition system of this invention enables the readout of multi-channel signals from the SiPM array. It can send commands to adjust amplifier gain, threshold, trigger logic and other operating parameters in real time, giving full play to the position sensitivity advantage of the SiPM array. At the same time, the multi-channel SiPM data acquisition electronics system has high integration, which can solve the space and power consumption problems of satellite payloads.

[0092] In some possible implementations, a multi-channel SiPM data acquisition method is also provided, which is implemented by the above-mentioned multi-channel SiPM data acquisition system. The multi-channel SiPM data acquisition system includes a multi-channel SiPM signal input terminal, a SiPM signal output terminal, an ASIC chip, an FPGA control board, a back-end amplifier, an analog-to-digital converter, and a host computer.

[0093] Figure 6 This is one of the flowcharts illustrating the multi-channel SiPM data acquisition method provided in this embodiment of the invention, such as... Figure 6 As shown, the multi-channel SiPM data acquisition method includes:

[0094] Step 610: Load the first configuration parameters of the ASIC chip through the FPGA control board, and send a parameter configuration signal to the ASIC chip. Under the control of the parameter configuration signal, write the first configuration parameters into the ASIC chip, wherein the first configuration parameters are the initial operating parameters of the ASIC chip.

[0095] Step 620: Determine whether the ASIC chip has received a serial port command sent by the host computer. If the serial port command is received, parse the serial port command to obtain the second configuration parameters of the ASIC chip, and update the ASIC chip to the second configuration parameters through the parameter configuration signal. If the serial port command is not received, detect whether the ASIC chip has generated a first trigger signal. The serial port command includes the data acquisition mode of the ASIC chip, and the acquisition module includes a self-trigger working mode and an external trigger working mode.

[0096] Step 630: When the ASIC chip generates the first trigger signal, determine whether the data acquisition mode of the ASIC chip is a self-trigger working mode or an external trigger working mode.

[0097] Step 640: The data acquisition mode of the ASIC chip is a self-trigger working mode. Under the action of the first trigger signal, the FPGA control board outputs a first control signal. Under the control of the first control signal, the ASIC chip performs peak holding on the amplified and shaped SiPM signal and outputs it serially to the back-end amplifier. The back-end amplifier performs back-end processing on each channel SiPM signal and outputs it to the analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel SiPM signal and outputs the signal pulse amplitude of each channel SiPM signal to the FPGA control board for buffering. The FPGA control board outputs the buffered signal pulse amplitude of each channel SiPM signal to the host computer for storage through the serial communication mode of the FPGA control board.

[0098] Step 650: The data acquisition mode of the ASIC chip is an external trigger working mode. It is determined whether the ASIC chip receives a second trigger signal sent by an external control slave within a preset time window. The second trigger signal is an I2C trigger signal. Upon receiving the second trigger signal, the ASIC chip performs peak hold on the amplified and shaped SiPM signal and outputs it serially to the back-end amplifier. The back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to the analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering. The FPGA control board uses serial communication mode to output the buffered signal pulse amplitude of each channel's SiPM signal to the host computer for storage.

[0099] In a possible embodiment, Figure 7 This is a second schematic flowchart of the multi-channel SiPM data acquisition method provided in an embodiment of the present invention, as shown below. Figure 7 As shown, after the system powers on, it first loads the configuration parameters stored in the FPGA. Then, the FPGA writes the 1144-bit configuration parameters to the ASIC configuration register via a slow control signal. After the ASIC completes the default parameter configuration, it enters standby mode. After one FPGA clock cycle (20ns) in standby mode, it checks whether a serial port command sent by the host computer has been received. If a serial port command is received, the command data is parsed, and the parsing result includes the new configuration parameters of the ASIC chip. In other words, the serial port command includes the configuration requirements corresponding to the new task requirements. Then, the ASIC configuration register is refreshed via the slow control signal, and the system returns to standby mode. If no serial port command is received, it checks whether the ASIC has generated a signal trigger. The signal trigger condition is that any one of the 32 SiPM signal input channels is greater than a set threshold. If there is no trigger signal, the system returns to standby mode. After the ASIC generates a signal trigger, the multi-channel SiPM data acquisition system will determine the data acquisition mode, which is configured by the serial port command from the host computer. In self-triggered mode, once the ASIC is triggered, the multi-channel SiPM data acquisition system maintains the peak value of the slowly molded SiPM signal. The input SiPM signal and the amplified signal inside the ASIC are then compared. Figure 8 As shown. The FPGA controls the ASIC to serially output 32 channels of signals via a fast signal, with the peak amplitude as shown. Figure 9 As shown, the analog-to-digital converter is controlled to read the signal amplitude. After the amplitude of the 32-channel SiPM signal is read, the FPGA transmits the data via serial communication. If the multi-channel SiPM data acquisition system is not in self-trigger mode, it will determine whether an I2C trigger signal from an external control slave is received within a 400ns time window. If an I2C trigger signal is received, subsequent signal acquisition will proceed; otherwise, it will return to standby mode to wait for the next data acquisition.

[0100] In some possible implementations, this scheme specifically describes the FPGA control timing diagram. The FPGA in the multi-channel SiPM data acquisition system is used for module control, transmission, and command reception functions. Data transmission and command sending utilize standard RS232 and I2C serial bus timings. The ASIC operating state configuration and data acquisition timings designed in this embodiment are divided into slow control signal timings and fast control signal timings. The slow control signal timings for ASIC parameter configuration are as follows: Figure 10 As shown, the ASIC chip first performs internal configuration. The FPGA writes 1144-bit configuration parameters to the ASIC's internal registers using a slow signal (20μs clock cycle) timing. `gclk` is the FPGA global clock; configuration data can be written to the ASIC's internal registers when `select` and `rstb_sr` signals are high. `clk_sr` is the clock signal for data writing; `srin_sr` (data line) writes to the ASIC buffer on the rising edge of `clk_sr`. Configuration parameters are input serially via the `srin_sr` signal. When all data has been written, the `load_sr` signal generates a rising edge, writing the ASIC's configuration buffer data to the registers, completing the ASIC's operating mode control. The fast control signal timing for physical event acquisition is as follows... Figure 11 As shown, once the data acquisition system is triggered, the FPGA generates... Figure 11 The fast signal control timing enables the ASIC to complete the data acquisition of physical events. gclk is the FPGA global clock. In standby mode, the differential signals Val_Evt_p and Val_Evt_n are set high and low respectively, enabling the ASIC signal trigger. The differential signals Raz_chn_p and Raz_chan_n are set low and high respectively, canceling the ASIC trigger signal latch. trig is the data acquisition trigger signal, active low. After the trigger is generated, rstb_read first resets the ASIC's digital signal module. After the ASIC amplifies and shapes the input signal, the signal holding signals hold_hg and hold_lg are set high, latching the maximum signal amplitude of all channels. The read enable signal srin_read generates a rising edge, starting the serial signal readout process of each channel of the ASIC. Each time clk_read generates a rising edge, the ASIC outputs one signal amplitude in sequence from 0 to 31, generating a total of 32 rising edges. After the ASIC output signal stabilizes, the adc_clk_out signal generates a rising edge, controlling the ADC to perform analog-to-digital conversion. Because the ADC has an internal buffer, three additional rising edges are generated to push out all the conversion data inside the ADC.

[0101] In some possible implementations, to enable real-time control and monitoring of the multi-channel SiPM data acquisition system, this invention also designs a dedicated host computer control interface. This interface is developed based on Qt5 and uses an RS serial port to communicate with the data acquisition system. The host computer interface is as follows: Figure 12 and Figure 13 As shown, you can switch between the main interface and single spectrum by clicking the [Main Interface] and [Single Spectrum] buttons at the top of the window.

[0102] Specifically, Figure 12 This is a schematic diagram of the main interface of the host computer control software provided in an embodiment of the present invention. (See attached diagram.) Figure 12 In the host computer control software's main interface, the right side displays the operating parameter configuration. To start operation, first set the serial port number, baud rate, parity bit, and stop bits. Click the "Open Serial Port" button to begin communication with the data acquisition system hardware. The host computer's "charge shaping threshold" and "rapid shaping threshold" are used to set the signal trigger threshold of the ASIC in the data acquisition system, and "gain" is used to set the amplification factor of the ASIC front-end amplifier. The "Start Acquisition" button controls the data acquisition system to operate with default parameters, while "Baseline Acquisition" operates at a low threshold. The "End Acquisition" function sets the ASIC threshold to the highest level, disabling trigger signals. The "Outgoing Trigger Mode" button requires an external I2C trigger signal to trigger the data acquisition system before data acquisition. The "Self-Trigger Mode" button allows the system to operate independently of external triggers. The "Refresh Rate" setting sets the time interval for real-time energy spectrum refresh. If there are other types of custom serial port commands, they can be entered into the text input box in binary format (e.g., ...). Figure 12 If you select FF AA 00FF, click the "Send" button to activate the command.

[0103] Furthermore, clicking the "Remote Trigger" button enables the synchronous start / stop mode for data saving. The IP field displays the host computer's IP address and port. When the host computer detects a remote control command via TCP, it saves the binary data to the PC and uses the filename set by the remote control command. After setting the "Data Packet Size" input field, whenever the data size exceeds the set size, the system time is automatically used as the filename suffix for the saved data packet. If remote triggering is not enabled, clicking the "Start Saving" button will save the data. The left side of the control software's main interface displays real-time data plotting. The host computer parses the received data in real time; the horizontal axis of the pulse amplitude spectrum represents the ADC channel number, and the vertical axis represents the count. The host computer only displays the pulse amplitude spectrum of the first 25 channels simultaneously. If the remaining channels need to be displayed, they can be viewed in the "Single Spectrum" interface. The pulse amplitude spectrum of all channels can be switched between logarithmic and linear coordinate display on the y-axis using the "log" option. The display range of the y-axis is set using the "Count Upper Limit" and "Count Lower Limit," and the display range of the x-axis is set using the "ADC Upper Limit" and "ADC Lower Limit." The real-time plotting results can be saved as a JPG file using the "Save Image" button, and the processed pulse amplitude spectrum data can be saved as a CSV file. The "Clear Data" button is used to clear the plotting results. During data acquisition, the host computer will also display the "Receiver Count" and "Counting Frequency ( / s)" in real time.

[0104] In the host computer control software's "Single Spectrum" interface, such as Figure 13 As shown, the left side displays the pulse amplitude spectrum of a single channel. Entering 1-32 in the "Channel Selection" field allows you to switch between displaying data from all single channels. The display range of the horizontal axis is set via the input boxes for the upper and lower limits of the ADC. The displayed single-channel pulse amplitude spectrum and corresponding data are saved to the host computer software's runtime directory by clicking the "Save Image" button. The right side of the "Single Spectrum" interface displays a pseudo-color image of the first 25 channels. The color represents the average ADC amplitude of the channel, and the corresponding numerical value is displayed on the right. The pseudo-color image is used for real-time monitoring of the signal intensity distribution of the SiPM array.

[0105] In a possible embodiment, the binary data stored in the host computer control software can be analyzed using offline data. Figure 14 This is obtained through offline data processing provided in the embodiments of the present invention. 241 Schematic diagram of Am pulse amplitude spectrum Figure 14 This demonstrates the use of a multi-channel SiPM data acquisition system in conjunction with a SiPM array and a GAGG crystal array to test... 241 Offline data analysis results obtained from the Am radiation source. For clearer display, Figure 14 The offline data processing results selected single-channel data, and Gaussian fitting was performed on the full-energy peak of the 59.5 keV gamma rays.

[0106] The host computer control system designed in this invention can realize real-time monitoring and command control of the SiPM data acquisition system, thereby improving the debugging efficiency in the detector development process.

[0107] This invention provides a multi-channel SiPM data acquisition system, method, SiPM-type gamma-ray detector, and composite detector system. The system compares the amplified SiPM signal with preset trigger selection conditions using an ASIC chip. If the amplified SiPM signal meets the trigger selection conditions, a first trigger signal is sent to an FPGA control board. The FPGA control board then sends parameter configuration signals to the ASIC chip, controlling the configuration of the parameters to be configured on the ASIC chip. Upon receiving the first trigger signal from the ASIC chip, a first control signal and a second control signal are output. The first control signal controls the ASIC chip to serially output the amplified SiPM signal to a back-end amplifier. The second control signal controls an analog-to-digital converter to serially read the signal pulse amplitude of the SiPM signal output from the back-end amplifier. This invention uses ASIC technology to improve the SiPM array readout system for space astronomy, transforming a single-channel signal readout data acquisition system into a multi-channel data acquisition system. This multi-channel SiPM data acquisition system is highly integrated and can adjust amplifier gain, threshold, trigger logic, and other operating parameters via commands. This invention enables individual readout of SiPM array units, effectively reducing signal saturation issues caused by parallel readouts and achieving a large signal dynamic range. Therefore, this invention can be used in composite detector system layouts. For layout designs with multiple detectors, an interval grouping approach can be adopted. When acquiring large signals, the number of sampling paths can be reduced to avoid signal saturation within a channel. Furthermore, the host computer control software based on serial communication can configure the parameters of the multi-channel data acquisition system, allowing the host computer to analyze and plot data in real time, and supporting the storage of plots of raw and real-time data.

[0108] Figure 15 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 15 As shown, the electronic device may include: a processor 1510, a communications interface 1520, a memory 1530, and a communications bus 1540, wherein the processor 1510, the communications interface 1520, and the memory 1530 communicate with each other through the communications bus 1540.The processor 1510 can call logic instructions in the memory 1530 to execute a multi-channel SiPM data acquisition method. This method includes: loading first configuration parameters of the ASIC chip via the FPGA control board and sending a parameter configuration signal to the ASIC chip; writing the first configuration parameters into the ASIC chip under the control of the parameter configuration signal, wherein the first configuration parameters are the initial operating parameters of the ASIC chip; determining whether the ASIC chip has received a serial port instruction sent by a host computer; if the serial port instruction is received, parsing the serial port instruction to obtain second configuration parameters of the ASIC chip; updating the ASIC chip to the second configuration parameters via the parameter configuration signal; if the serial port instruction is not received, detecting whether the ASIC chip has generated a first trigger signal; wherein the serial port instruction includes the data acquisition mode of the ASIC chip, and the acquisition module includes a self-triggered operating mode and an external trigger operating mode; if the ASIC chip generates a first trigger signal, determining whether the data acquisition mode of the ASIC chip is a self-triggered operating mode or an external trigger operating mode; if the data acquisition mode of the ASIC chip is a self-triggered operating mode, the FPGA control board outputs a first control signal under the action of the first trigger signal; under the control of the first control signal, the ASIC chip is loaded with the first configuration parameters of the ASIC chip. The ASIC chip performs peak hold on the amplified and shaped SiPM signal and serially outputs it to a back-end amplifier. The back-end amplifier performs post-processing on each channel's SiPM signal and outputs it to an analog-to-digital converter (ADC). The ADC reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude to the FPGA control board for buffering. The FPGA control board uses serial communication to output the buffered signal pulse amplitudes of each channel's SiPM signal to a host computer for storage. The ASIC chip's data acquisition mode is an externally triggered operating mode, determining whether the ASIC chip receives external control within a preset time window. The second trigger signal sent by the machine, wherein the second trigger signal is an I2C trigger signal, upon receiving the second trigger signal, the ASIC chip performs peak hold on the amplified and shaped SiPM signal and serially outputs it to the back-end amplifier; the back-end amplifier performs back-end processing on each channel SiPM signal and outputs it to the analog-to-digital converter; the analog-to-digital converter reads the signal pulse amplitude of each channel SiPM signal and outputs the signal pulse amplitude of each channel SiPM signal to the FPGA control board for buffering; the buffered signal pulse amplitude of each channel SiPM signal is output to the host computer for storage through the serial communication mode of the FPGA control board.

[0109] Furthermore, the logical instructions in the aforementioned memory 1530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0110] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the multi-channel SiPM data acquisition method provided by the above methods. The method includes: loading first configuration parameters of the ASIC chip through the FPGA control board and sending a parameter configuration signal to the ASIC chip; writing the first configuration parameters into the ASIC chip under the control of the parameter configuration signal, wherein the first configuration parameters are the initial operating parameters of the ASIC chip; determining whether the ASIC chip receives a serial port instruction sent by a host computer; if the serial port instruction is received, parsing the serial port instruction to obtain second configuration parameters of the ASIC chip; updating the ASIC chip to the second configuration parameters through the parameter configuration signal; if the serial port instruction is not received, detecting whether the ASIC chip has generated a first trigger signal; wherein the serial port instruction includes the data acquisition mode of the ASIC chip, and the acquisition module includes a self-triggered working mode and an external trigger working mode; if the ASIC chip generates a first trigger signal, determining whether the data acquisition mode of the ASIC chip is a self-triggered working mode or an external trigger working mode; the data acquisition mode of the ASIC chip is... In the self-triggered operating mode, the FPGA control board outputs a first control signal under the action of the first trigger signal. Under the control of the first control signal, the ASIC chip performs peak hold on the amplified and shaped SiPM signal and outputs it serially to the back-end amplifier. The back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to the analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering. Through the serial communication mode of the FPGA control board, the buffered signal pulse amplitude of each channel's SiPM signal is output to the host computer for storage. The ASIC chip's data acquisition mode is an externally triggered working mode. It determines whether the ASIC chip receives a second trigger signal from an external control slave within a preset time window. The second trigger signal is an I2C trigger signal. Upon receiving the second trigger signal, the ASIC chip performs peak hold on the amplified and shaped SiPM signal and outputs it serially to a back-end amplifier. The back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to an analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering.The FPGA control board uses serial communication to output the signal pulse amplitudes of each buffered SiPM channel signal to the host computer for storage.

[0111] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the multi-channel SiPM data acquisition method provided by the methods described above. This method includes: loading first configuration parameters of the ASIC chip through the FPGA control board and sending a parameter configuration signal to the ASIC chip; writing the first configuration parameters into the ASIC chip under the control of the parameter configuration signal, wherein the first configuration parameters are the initial operating parameters of the ASIC chip; determining whether the ASIC chip has received a serial port command sent by a host computer; and, if the serial port command is received, parsing the serial port command to obtain... The second configuration parameters of the ASIC chip are updated to the second configuration parameters through the parameter configuration signal; in the absence of the serial port command, it is detected whether the ASIC chip has generated a first trigger signal; wherein, the serial port command includes the data acquisition mode of the ASIC chip, and the acquisition module includes a self-trigger working mode and an external trigger working mode; if the ASIC chip generates the first trigger signal, it is determined whether the data acquisition mode of the ASIC chip is a self-trigger working mode or an external trigger working mode; if the data acquisition mode of the ASIC chip is a self-trigger working mode, the FPGA control board outputs a first control signal under the action of the first trigger signal; Under the control of the first control signal, the ASIC chip performs peak holding on the amplified SiPM signal and serially outputs it to the back-end amplifier; the back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to the analog-to-digital converter; the analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering; the FPGA control board outputs the buffered signal pulse amplitude of each channel's SiPM signal to the host computer for storage via serial communication; the ASIC chip's data acquisition mode is an externally triggered working mode, determining whether the ASIC chip is within a preset time window. Whether a second trigger signal sent by an external control slave device is received, wherein the second trigger signal is an I2C trigger signal; if the second trigger signal is received, the ASIC chip performs peak hold on the amplified and shaped SiPM signal and serially outputs it to the back-end amplifier; the back-end amplifier performs back-end processing on each channel SiPM signal and outputs it to the analog-to-digital converter; the analog-to-digital converter reads the signal pulse amplitude of each channel SiPM signal and outputs the signal pulse amplitude of each channel SiPM signal to the FPGA control board for buffering; the FPGA control board outputs the buffered signal pulse amplitude of each channel SiPM signal to the host computer for storage through the serial communication mode of the FPGA control board.

[0112] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0113] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.< / n>

Claims

1. A multi-channel SiPM data acquisition system, applied to a space astronomical detector, characterized in that, The multi-channel SiPM data acquisition system includes a multi-channel SiPM signal input terminal, a SiPM signal output terminal, an ASIC chip, an FPGA control board, a back-end amplifier, an analog-to-digital converter, and a host computer. The ASIC chip includes a first output terminal and a second output terminal. The first output terminal is connected to the FPGA control board, and the second output terminal is connected to the back-end amplifier. The ASIC chip is used to convert the multi-channel SiPM signal input from the multi-channel SiPM signal input terminal into a digital-to-analog converter, amplify and shape it, compare the amplified and shaped SiPM signal with a preset trigger selection condition, and send a first trigger signal to the FPGA control board if the amplified and shaped SiPM signal meets the trigger selection condition. The FPGA control board includes a parameter configuration terminal, a third output terminal, and a fourth output terminal. The parameter configuration terminal and the third output terminal are respectively connected to the ASIC chip, and the fourth output terminal is connected to the analog-to-digital converter. The FPGA control board is used to send parameter configuration signals to the ASIC chip, and control the configuration of the parameters to be configured on the ASIC chip through the parameter configuration signals; and when receiving a first trigger signal sent by the ASIC chip, outputting a first control signal and a second control signal, using the first control signal to control the ASIC chip to serially output the amplified and shaped SiPM signal to the back-end amplifier; and using the second control signal to control the analog-to-digital converter to serially read the signal pulse amplitude of the SiPM signal output by the back-end amplifier. The back-end amplifier is used to process the serially output multi-channel SiPM signal so that the signal pulse amplitude of the multi-channel SiPM signal is within the signal pulse amplitude range of the analog-to-digital converter. The analog-to-digital converter is used to serially read the signal pulse amplitude of the SiPM signal under the control of the second control signal, and output the signal pulse amplitude of the multi-channel SiPM signal to the FPGA control board for buffering; The host computer is connected to the FPGA control board, and the host computer is used to store the signal pulse amplitude of the multi-channel SiPM signal output by the FPGA control board. The FPGA control board also includes a fifth output terminal, which is connected to an external control slave device. The FPGA control board is also used to send a trigger selection signal to the external control slave device, and after receiving a second trigger signal from the external control slave device, to control the acquisition of the multi-channel SiPM signal input to the multi-channel SiPM signal input terminal. The external control slave device is used to judge the trigger selection signal, and after successful judgment, to distribute a second trigger signal to the FPGA control board. The second trigger signal is an I2C synchronous trigger signal. The host computer is also connected to the external control slave device. The host computer is also used to receive TCP synchronization start / stop signals sent by the external control slave device and to save the acquired multi-channel SiPM signals under the control of the TCP synchronization start / stop signals.

2. The multi-channel SiPM data acquisition system according to claim 1, characterized in that, The host computer is also connected to the ASIC chip, and the host computer is also used to send serial port commands to the ASIC chip. The serial port commands are used to control the ASIC chip to configure the parameters to be configured according to the parameter configuration signals. The parameters to be configured include the gain, molding time, signal triggering logic, threshold, and SiPM bias voltage of each channel SiPM signal.

3. The multi-channel SiPM data acquisition system according to claim 2, characterized in that, The ASIC chip includes an 8-bit DAC, a front-end amplifier, a slow-forming amplifier, a fast-forming amplifier, a peak detection and hold module, and a signal discriminator. The parameter configuration signal is a 20 μs clock cycle signal, and the first control signal is a 20 ns clock cycle signal; The ASIC chip is used to convert the SiPM signal input from the SiPM signal input terminal into a digital-to-analog converter, amplify and shape it, compare the amplified and shaped SiPM signal with a preset trigger selection condition, and send a first trigger signal to the FPGA control board if the amplified and shaped SiPM signal meets the trigger selection condition. The specific steps include: The ASIC chip receives the SiPM signal, performs digital-to-analog conversion on the SiPM signal using the 8-bit DAC, and amplifies and shapes the converted SiPM signal using the front-end amplifier. The amplified SiPM signal is fanned out into two paths to the slow-forming amplifier and the fast-forming amplifier for secondary amplification and output. The output of the fast-forming amplifier is connected to the signal discriminator. The signal comparison threshold of the signal discriminator is provided by the instruction-adjustable DAC. After each SiPM signal is output by the signal discriminator, it is processed by "OR" logic within the ASIC chip to output the first trigger signal. The output of the slow-forming amplifier is connected to the peak detection and hold module. When the FPGA receives the first trigger signal, it controls the peak detection and hold module to latch the multi-channel SiPM signal output by the slow-forming amplifier and, under the control of the first control signal, serially outputs the latched multi-channel SiPM signal to the analog-to-digital converter.

4. The multi-channel SiPM data acquisition system according to claim 3, characterized in that, The ASIC chip also includes a register, which is used to store the configuration results of the parameters to be configured.

5. The multi-channel SiPM data acquisition system according to claim 1, characterized in that, The first control signal is at LVCMOS and LVDS levels.

6. The multi-channel SiPM data acquisition system according to claim 1, characterized in that, The FPGA control board outputs the signal pulse amplitude of the multi-channel SiPM signal to the host computer via serial communication.

7. The multi-channel SiPM data acquisition system according to claim 1, characterized in that, The amplified SiPM signal satisfies the trigger selection condition, specifically including: The amplified SiPM signal in any channel is greater than the set threshold.

8. The multi-channel SiPM data acquisition system according to claim 1, characterized in that, The host computer is also used to display the signal pulse amplitude distribution diagram of the SiPM signal of the pre-selected channel in real time.

9. A SiPM type gamma ray detector, characterized in that, include: The multi-channel SiPM data acquisition system as described in any one of claims 1-8.

10. A composite detector system, characterized in that, include: The system includes a control slave and at least two SiPM-type gamma ray detectors as described in claim 9, each of the SiPM-type gamma ray detectors being connected to the control slave.

11. A multi-channel SiPM data acquisition method, characterized in that, The method is implemented by the multi-channel SiPM data acquisition system according to any one of claims 1-8, wherein the multi-channel SiPM data acquisition system includes a multi-channel SiPM signal input terminal, a SiPM signal output terminal, an ASIC chip, an FPGA control board, a back-end amplifier, an analog-to-digital converter, and a host computer; The method includes: The FPGA control board loads the first configuration parameters of the ASIC chip and sends a parameter configuration signal to the ASIC chip. Under the control of the parameter configuration signal, the first configuration parameters are written into the ASIC chip, wherein the first configuration parameters are the initial operating parameters of the ASIC chip. The system determines whether the ASIC chip has received a serial port command from the host computer. If the serial port command is received, it parses the command to obtain the second configuration parameters of the ASIC chip, and updates the ASIC chip to the second configuration parameters using the parameter configuration signal. If the serial port command is not received, it detects whether the ASIC chip has generated a first trigger signal. The serial port command includes the data acquisition mode of the ASIC chip, which includes a self-trigger working mode and an external trigger working mode. When the ASIC chip generates a first trigger signal, it is determined whether the data acquisition mode of the ASIC chip is a self-triggered working mode or an externally triggered working mode. The ASIC chip operates in a self-trigger mode for data acquisition. Under the action of the first trigger signal, the FPGA control board outputs a first control signal. Under the control of the first control signal, the ASIC chip performs peak hold on the amplified SiPM signal and serially outputs it to the back-end amplifier. The back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to the analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering. The FPGA control board uses serial communication to output the buffered signal pulse amplitude of each channel's SiPM signal to the host computer for storage. The ASIC chip's data acquisition mode is an external trigger working mode. It determines whether the ASIC chip receives a second trigger signal from an external control slave within a preset time window, where the second trigger signal is an I2C trigger signal. Upon receiving the second trigger signal, the ASIC chip performs peak hold on the amplified and shaped SiPM signal and outputs it serially to a back-end amplifier. The back-end amplifier performs back-end processing on each channel's SiPM signal and outputs it to an analog-to-digital converter. The analog-to-digital converter reads the signal pulse amplitude of each channel's SiPM signal and outputs the signal pulse amplitude of each channel's SiPM signal to the FPGA control board for buffering. The FPGA control board's serial communication mode outputs the buffered signal pulse amplitude of each channel's SiPM signal to a host computer for storage.

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