Narrow pulse test method, narrow pulse test circuit and ATE test system
By down-frequency and conversion processing of the pulse signal in the narrow pulse test and measuring its frequency and voltage, the problem of difficulty in guaranteeing accuracy and stability in the narrow pulse test is solved, and more accurate test results are achieved.
Patent Information
- Application Number
- CN202411501031.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2044-10-25
AI Technical Summary
In narrow pulse test, due to the narrow pulse width of the test signal, it is susceptible to factors such as ringing, parasitic inductance and capacitance, which makes it difficult to guarantee the accuracy and stability of the test.
In narrow pulse test mode, the target pulse signal is down-frequency and conversion process to obtain an equivalent DC signal, and the frequency and voltage of the signal are measured to determine the pulse width and reduce the ringing phenomenon, parasitic inductance and capacitor to the test results. Influence.
Improve the accuracy and stability of narrow pulse tests, and reduce the interference impact and obtain more accurate test results by converting pulse width measurements into equivalent DC voltage and frequency measurements.
Smart Images
Figure CN119001411B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a narrow pulse test method, a narrow pulse test circuit, and an ATE test system. Background Art
[0002] The last process of integrated circuit manufacturing is the automatic test equipment (ATE) test, which is used to screen out chips that do not meet the design requirements and obtain chips that meet the design requirements. Among them, ATE testing includes testing various parameters of the chip, such as DC parameters, AC parameters, functional testing and logic testing. Narrow pulse testing is a common chip test, such as the minimum on-time and minimum off-time test in a direct current (DC)-DC converter, where a narrow pulse generally refers to a pulse with a pulse width of less than 100ns.
[0003] In narrow pulse testing, since the pulse width of the test signal is narrow and is affected by factors such as ringing, parasitic inductance and capacitance, the accuracy and stability of narrow pulse testing are difficult to guarantee. Summary of the invention
[0004] The present disclosure provides a narrow pulse test method, a narrow pulse test circuit and an ATE test system, which can improve the accuracy and stability of the narrow pulse test.
[0005] In a first aspect, the present disclosure provides a narrow pulse test method, which is applied to an automatic test equipment ATE test system. The narrow pulse test method includes:
[0006] In the narrow pulse test mode, the target pulse signal is frequency-reduced to obtain a first test signal, wherein the frequency of the first test signal is 1 / N of the frequency of the target pulse signal, where N is an integer greater than 1; the target pulse signal is converted to obtain a second test signal, which is an equivalent DC signal of the target pulse signal; the frequency of the first test signal and the voltage of the second test signal are measured; and the pulse width of the target pulse signal is determined based on the frequency of the first test signal and the voltage of the second test signal.
[0007] In some embodiments of the present disclosure, the step of down-converting the target pulse signal to obtain the first test signal includes:
[0008] The target pulse signal is subjected to N-frequency division processing to obtain the first test signal with a preset duty cycle.
[0009] In some embodiments of the present disclosure, converting the target pulse signal to obtain the second test signal includes:
[0010] Based on the first output resistor, the target pulse signal is converted into a first intermediate pulse signal to improve the driving capability of the target pulse signal; the high level of the first intermediate pulse signal is shifted to a preset voltage, and the low level of the first intermediate pulse signal is shifted to the ground potential to obtain a second intermediate pulse signal, and the frequency and pulse width of the second intermediate pulse signal are equal to those of the target pulse signal; the second intermediate pulse signal is converted into a DC signal to obtain an intermediate DC signal; based on the second output resistor, the intermediate DC signal is converted into the second test signal to improve the driving capability of the intermediate DC signal.
[0011] In some embodiments of the present disclosure, determining the pulse width of the target pulse signal according to the frequency of the first test signal and the voltage of the second test signal includes:
[0012] The pulse width of the target pulse signal is determined according to the high level of the second intermediate pulse signal, the frequency of the first test signal, and the voltage of the second test signal.
[0013] In some embodiments of the present disclosure, determining the pulse width of the target pulse signal according to the high level of the second intermediate pulse signal, the frequency of the first test signal, and the voltage of the second test signal includes:
[0014] The pulse width W of the target pulse signal is determined according to the following formula:
[0015] W=Vout / (Vin f N)
[0016] Wherein, Vout is the voltage of the second test signal, Vin is the high level of the second intermediate pulse signal, and f is the frequency of the first test signal.
[0017] In a second aspect, the present disclosure provides a narrow pulse test circuit, which is applied to a chip of an ATE test system. The narrow pulse test circuit includes a conversion module and a frequency reduction module.
[0018] The frequency reduction module is configured to, in a narrow pulse test mode, perform frequency reduction processing on a target pulse signal to obtain a first test signal, wherein the frequency of the first test signal is 1 / N of the frequency of the target pulse signal, where N is an integer greater than 1.
[0019] The conversion module is configured to, in the narrow pulse test mode, perform conversion processing on the target pulse signal to obtain a second test signal, where the second test signal is an equivalent DC signal of the target pulse signal.
[0020] The frequency of the first test signal and the voltage of the second test signal are used to determine the pulse width of the target pulse signal.
[0021] In some embodiments of the present disclosure, the frequency reduction module includes a frequency divider, an input end of the frequency divider is connected to an input end of the narrow pulse test circuit, and an output end of the frequency divider is connected to a first output end of the narrow pulse test circuit.
[0022] The frequency divider is configured to perform N-frequency division processing on the target pulse signal to obtain the first test signal with a preset duty cycle.
[0023] In some embodiments of the present disclosure, the conversion module includes a logic driving unit, an RC network unit and a voltage driving unit, the input end of the logic driving unit is connected to the input end of the narrow pulse test circuit, the output end of the logic driving unit is connected to the input end of the voltage driving unit through the RC network unit, and the output end of the voltage driving unit is connected to the second output end of the narrow pulse test circuit.
[0024] The logic driving unit is configured to, based on a first output resistor, convert the target pulse signal into a first intermediate pulse signal to improve the driving capability of the target pulse signal; shift the high level of the first intermediate pulse signal to a preset voltage, and shift the low level of the first intermediate pulse signal to a ground potential to obtain a second intermediate pulse signal, wherein the frequency and pulse width of the second intermediate pulse signal are equal to those of the target pulse signal.
[0025] The RC network unit is configured to convert the second intermediate pulse signal into a DC signal to obtain an intermediate DC signal. The voltage driving unit is configured to convert the second intermediate DC signal into the second test signal to improve the driving capability of the intermediate DC signal.
[0026] In some embodiments of the present disclosure, the RC network unit includes a plurality of stages of RC networks connected in series, and each stage of the RC network includes a resistor and a capacitor.
[0027] The first end of the resistor of the first-stage RC network is connected to the output end of the logic driving unit, and the second end of the resistor of the last-stage RC network is connected to the first plate of the capacitor of the last-stage RC network and the input end of the voltage driving unit. The second end of the resistor of the previous-stage RC network is connected to the first plate of the capacitor of the previous-stage RC network and the first end of the resistor of the next-stage RC network, and the second plates of the capacitors of each stage of the RC network are grounded.
[0028] In a third aspect, the present disclosure provides an ATE test system, including ATE and a chip connected to the ATE, wherein the chip includes any narrow pulse test circuit provided in the second aspect.
[0029] The ATE is configured to measure the frequency of the first test signal and the voltage of the second test signal, and determine the pulse width of the target pulse signal according to the frequency of the first test signal and the voltage of the second test signal.
[0030] The technical solution disclosed in the present invention provides a narrow pulse testing method, which includes: in a narrow pulse test mode, performing frequency reduction processing on a target pulse signal to obtain a first test signal, performing conversion processing on the target pulse signal to obtain a second test signal, measuring the frequency of the first test signal and the voltage of the second test signal, and determining the pulse width of the target pulse signal according to the frequency of the first test signal and the voltage of the second test signal. The pulse width measurement of the narrow pulse signal can be converted into the measurement of its equivalent DC voltage and frequency, while the ringing phenomenon, parasitic inductance and parasitic capacitance have little effect on the equivalent DC voltage and frequency of the narrow pulse signal, so that a relatively accurate pulse width of the narrow pulse signal can be obtained, thereby improving the accuracy and stability of the narrow pulse test. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:
[0032] Figure 1 A schematic diagram of a narrow pulse signal provided by the prior art;
[0033] Figure 2 A schematic diagram of a narrow pulse signal with ringing phenomenon is provided for the prior art;
[0034] Figure 3 A schematic diagram of the structure of an ATE test system provided in an embodiment of the present disclosure;
[0035] Figure 4 A schematic diagram of a narrow pulse testing method provided by an embodiment of the present disclosure;
[0036] Figure 5 A schematic flow chart of another narrow pulse testing method provided by an embodiment of the present disclosure;
[0037] Figure 6 A schematic diagram of various signals provided for embodiments of the present disclosure;
[0038] Figure 7A schematic diagram of the structure of a narrow pulse test circuit provided by an embodiment of the present disclosure;
[0039] Figure 8 A circuit diagram of a narrow pulse test circuit provided by an embodiment of the present disclosure;
[0040] Fig. 9 A circuit diagram of another narrow pulse test circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.
[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.
[0043] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.
[0044] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.
[0045] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0046] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two). Similarly, "plurality groups" and "at least two groups" mean more than two groups (including two).
[0047] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.
[0048] Figure 1 A schematic diagram of a narrow pulse signal provided by the prior art, such as Figure 1 As shown, the chip pin outputs the original narrow pulse signal, and the original narrow pulse signal is sampled to obtain a sampled pulse signal. Ideally, the sampled original narrow pulse signal is the same as the original narrow pulse signal. A voltage sampling point is set in the ATE test system. Timing starts when the voltage at the rising edge of the original narrow pulse signal is greater than the voltage sampling point, and ends when the voltage at the falling edge is lower than the voltage sampling point. The pulse width of the original narrow pulse signal is T1, and the ideal pulse width of the sampled narrow pulse signal is T1.
[0049] However, in the actual test of ATE, the ATE test system has certain parasitic inductance and capacitance due to factors such as long wiring, too many physical contact points and too many vias on the printed circuit board. The introduction of parasitic capacitance will slow down the rising and falling edges of the sampled narrow pulse waveform, resulting in the measured pulse width T2 of the sampled narrow pulse signal being smaller than the ideal pulse width T1. Parasitic capacitance and parasitic inductance are very small and have little effect on conventional test items and wide pulse tests, but have a more obvious effect on narrow pulse tests, making it difficult to accurately test narrow pulses.
[0050] Figure 2 A schematic diagram of a narrow pulse signal with ringing phenomenon is provided for the prior art, such as Figure 2 As shown in the figure, when the original narrow pulse signal output by the chip pin has a ringing phenomenon, the parasitic inductance and parasitic capacitance introduced by the ATE test system will aggravate the deterioration of the waveform, making the ringing phenomenon of the sampled narrow pulse signal more severe. The high level of the sampled narrow pulse signal appears lower than the voltage sampling point during the ringing process, and the actual pulse width of the sampled narrow pulse signal detected is T3, which affects the accuracy and stability of the narrow pulse test.
[0051] In view of this, the present disclosure provides a narrow pulse testing method, by down-converting a target pulse signal in a narrow pulse test mode to obtain a first test signal, converting the target pulse signal to obtain a second test signal, measuring the frequency of the first test signal and the voltage of the second test signal, and determining the pulse width of the target pulse signal according to the frequency of the first test signal and the voltage of the second test signal. The pulse width measurement of the narrow pulse signal can be converted into the measurement of its equivalent DC voltage and frequency, while the ringing phenomenon, parasitic inductance and parasitic capacitance have little effect on the equivalent DC voltage and frequency of the narrow pulse signal, so that a relatively accurate pulse width of the narrow pulse signal can be obtained, thereby improving the accuracy and stability of the narrow pulse test.
[0052] Figure 3 A schematic diagram of the structure of an ATE test system provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the ATE test system includes an ATE and a chip connected to the ATE. The chip includes any narrow pulse test circuit 100 provided in the embodiment of the present disclosure. In the narrow pulse test mode, the narrow pulse test circuit 100 can receive a narrow pulse signal with a pulse width less than 100ns, that is, a target pulse signal Snp, and obtain a first detection signal S1 and a second detection signal S2 according to the target pulse signal Snp.
[0053] The ATE may receive the first test signal S1 and the second test signal S2, measure the frequency of the first test signal S1 and the voltage of the second test signal S2, and determine the pulse width of the target pulse signal Snp according to the frequency of the first test signal S1 and the voltage of the second test signal S2.
[0054] The present disclosure also provides a narrow pulse testing method, which is applied to the ATE testing system provided in the above embodiment.
[0055] Figure 4 A schematic diagram of a narrow pulse test method provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, the specific steps of the narrow pulse test method include:
[0056] S101, in a narrow pulse test mode, a narrow pulse test circuit performs frequency reduction processing on a target pulse signal to obtain a first test signal.
[0057] The frequency of the first test signal is 1 / N of the frequency of the target pulse signal, where N is an integer greater than 1.
[0058] Exemplarily, in the narrow pulse test mode, the narrow pulse test circuit can receive the target pulse signal Snp, and perform N-division processing on the target pulse signal Snp based on the divider to obtain a first test signal S1 with a preset duty cycle, wherein the preset duty cycle can be any value between 10% and 90%, for example, the preset duty cycle is 50%.
[0059] In other embodiments, the narrow pulse test circuit can perform frequency reduction processing on the target pulse signal based on the frequency reduction circuit to obtain a first test signal S1, and the frequency of the first test signal S1 is 1 / N of the frequency of the target pulse signal Snp.
[0060] S102, the narrow pulse test circuit converts the target pulse signal to obtain a second test signal.
[0061] The second test signal is an equivalent DC signal of the target pulse signal.
[0062] Exemplarily, the narrow pulse test circuit can perform AC-to-DC conversion on the target pulse signal Snp based on the AC-to-DC conversion circuit to obtain an equivalent DC signal, namely, the second test signal S2.
[0063] In other embodiments, the narrow pulse test circuit can first isolate the target pulse signal Snp based on the isolation circuit to obtain a stable target pulse signal Snp, and then convert the isolated target pulse signal Snp into DC based on the AC / DC conversion circuit to obtain an accurate second test signal S2.
[0064] In some other embodiments, the narrow pulse test circuit can first shape the target pulse signal Snp based on the shaping circuit to obtain a high-quality target pulse signal Snp, and then based on the AC / DC conversion circuit, perform AC-to-DC conversion on the shaped target pulse signal Snp to obtain an accurate second test signal S2.
[0065] In some other embodiments, the narrow pulse test circuit can first isolate the target pulse signal Snp based on the isolation circuit, and then shape the isolated target pulse signal Snp based on the shaping circuit, or first shape the target pulse signal Snp based on the shaping circuit, and then isolate the shaped target pulse signal Snp based on the isolation circuit to obtain a high-quality and stable target pulse signal Snp, and finally perform AC-to-DC conversion on the shaped and isolated target pulse signal Snp to obtain an accurate second test signal S2.
[0066] S103 , the ATE measures the frequency of the first test signal and the voltage of the second test signal.
[0067] Exemplarily, ATE can receive a first test signal S1 and a second test signal S2 sent by a narrow pulse test circuit, and measure the frequency f of the first test signal S1 based on a measurement module. Since the frequency f of the first test signal S1 is 1 / N of the frequency f' of the target pulse signal Snp, the frequency f' of the target pulse signal Snp can be obtained based on the measured frequency f of the first test signal S1.
[0068] In addition, ATE can also measure the voltage Vout of the second test signal S2 based on the measurement module. Since the second test signal S2 is an equivalent DC signal of the target pulse signal Snp, the voltage Vout of the second test signal S2 can be considered as the equivalent DC voltage Vout' of the target pulse signal Snp.
[0069] S104, the ATE determines a pulse width of a target pulse signal according to a frequency of the first test signal and a voltage of the second test signal.
[0070] Exemplarily, the equivalent DC voltage Vout' of the target pulse signal Snp, the high level Vin' of the target pulse signal Snp, the frequency f' of the target pulse signal Snp and the pulse width W of the target pulse signal Snp satisfy the following formula:
[0071] Vout'=Vin' (f' W) (1)
[0072] On the basis of formula (1), according to the frequency f' of the target pulse signal Snp = N * the frequency f of the first test signal S1, the equivalent DC voltage Vout' of the target pulse signal Snp = the voltage Vout of the second test signal S2, the following formula can be obtained:
[0073] W=Vout / (Vin' f N) (2)
[0074] Thus, the ATE substitutes the frequency f of the first test signal S1, the voltage Vout of the second test signal S2 and the high level Vin' of the target pulse signal Snp into formula (2) based on the calculation module, and calculates the pulse width W of the target pulse signal Snp.
[0075] To summarize, by down-converting the target pulse signal in the narrow pulse test mode to obtain a first test signal, converting the target pulse signal to obtain a second test signal, measuring the frequency of the first test signal and the voltage of the second test signal, and determining the pulse width of the target pulse signal based on the frequency of the first test signal and the voltage of the second test signal, the pulse width measurement of the narrow pulse signal can be converted into the measurement of its equivalent DC voltage and frequency, while the ringing phenomenon, parasitic inductance and parasitic capacitance have little effect on the equivalent DC voltage and frequency of the narrow pulse signal, so that a relatively accurate pulse width of the narrow pulse signal can be obtained, thereby improving the accuracy and stability of the narrow pulse test.
[0076] In some embodiments, Figure 5 A schematic diagram of a flow chart of another narrow pulse testing method provided by an embodiment of the present disclosure, Figure 5 for Figure 4 Based on the illustrated embodiment, a possible implementation method for executing S102 is specifically described as follows:
[0077] S201, the narrow pulse test circuit converts the target pulse signal into a first intermediate pulse signal based on the first output resistor to improve the driving capability of the target pulse signal.
[0078] Exemplarily, the driving capability of the target pulse signal Snp may be weak, and the output resistance of the intermediate stage of the narrow pulse test circuit is the first output resistance. Based on the first output resistance, the narrow pulse test circuit can improve the driving capability of the target pulse signal Snp without changing the frequency and pulse width of the target pulse signal Snp, thereby obtaining a first intermediate pulse signal.
[0079] S202, the narrow pulse test circuit shifts the high level of the first intermediate pulse signal to a preset voltage, and shifts the low level of the first intermediate pulse signal to a ground potential, to obtain a second intermediate pulse signal.
[0080] The frequency and pulse width of the second intermediate pulse signal and the target pulse signal are equal.
[0081] For example, Figure 6 A schematic diagram of various signals provided in the embodiments of the present disclosure, such as Figure 6 The high and low levels of the target pulse signal Snp shown may be unstable and / or not recognized by ATE, and the first intermediate pulse signal Smp1 differs from the target pulse signal Snp only in driving capability. Therefore, the high and low levels of the first intermediate pulse signal Smp1 may be unstable and / or not recognized by ATE.
[0082] The narrow pulse test circuit can shift the high level of the first intermediate pulse signal Smp1 to a preset voltage Vcc recognizable by ATE based on the level shift circuit, and shift the low level of the first intermediate pulse signal Smp1 to a ground potential GND recognizable by ATE. Without changing the frequency and pulse width of the first intermediate pulse signal Smp1, the first intermediate pulse signal Smp1 can be converted into a stable second intermediate pulse signal Smp2 recognizable by ATE.
[0083] In this way, the driving capability of the target pulse signal Snp can be improved through the narrow pulse test circuit, and the high level of the target pulse signal Snp can be shifted to the preset voltage Vcc, and the low level of the target pulse signal Snp can be shifted to the ground potential GND. Without changing the frequency and pulse width of the target pulse signal Snp, the target pulse signal Snp can be converted into a stable pulse signal with stronger driving capability that can be recognized by ATE.
[0084] S203, the narrow pulse test circuit converts the second intermediate pulse signal into a DC signal to obtain an intermediate DC signal.
[0085] Exemplarily, the narrow pulse test circuit can convert the second intermediate pulse signal Smp2 into a corresponding DC signal based on a low-pass filter circuit, thereby obtaining an intermediate DC signal Sdc or an intermediate DC signal Sdc', such as Figure 6 For example, the low-pass filter circuit is a single-stage RC network or a multi-stage RC network, and the intermediate DC signal Sdc obtained based on the multi-stage RC network has a higher smoothness than the intermediate DC signal Sdc' obtained based on the single-stage RC network.
[0086] S204, the narrow pulse test circuit converts the intermediate DC signal into a second test signal based on the second output resistor to improve the driving capability of the intermediate DC signal.
[0087] Exemplarily, the process of converting the second intermediate pulse signal Smp2 into the intermediate DC signal Sdc weakens the driving capability of the signal, so that the driving capability of the intermediate DC signal Sdc is relatively weak.
[0088] An output resistor of the narrow pulse test circuit is the second output resistor. Based on the second output resistor, the narrow pulse test circuit can only improve the driving capability of the intermediate DC signal Sdc without changing other parameters of the intermediate DC signal Sdc, thereby obtaining the second test signal S2.
[0089] In this way, the target pulse signal is converted into a first intermediate pulse signal based on the first output resistor through the narrow pulse test circuit to improve the driving capability of the target pulse signal, the high level of the first intermediate pulse signal is shifted to a preset voltage, and the low level of the first intermediate pulse signal is shifted to the ground potential to obtain a second intermediate pulse signal, and the second intermediate pulse signal is converted into a DC signal to obtain an intermediate DC signal, and based on the second output resistor, the intermediate DC signal is converted into a second test signal to improve the driving capability of the intermediate DC signal, so that a stable narrow pulse signal with strong driving capability that can be recognized by ATE can be obtained, and it is converted into an equivalent DC signal with strong driving capability, which can improve the accuracy of the equivalent DC voltage of the narrow pulse signal, thereby improving the accuracy of the narrow pulse test.
[0090] In other embodiments, the narrow pulse test circuit first shifts the high level of the target pulse signal to a preset voltage, and shifts the low level of the target pulse signal to the ground potential to obtain a third intermediate pulse signal, and then converts the third intermediate pulse signal into a second intermediate pulse signal based on the first output resistor to improve the driving capability of the third intermediate pulse signal.
[0091] Exemplarily, the narrow pulse test circuit can shift the high level of the target pulse signal Snp to a preset voltage and the low level of the target pulse signal to the ground potential based on the level shift circuit, and can convert the target pulse signal Snp into a stable third intermediate pulse signal Smp3 recognizable by ATE without changing the frequency and pulse width of the target pulse signal Snp.
[0092] The output resistance of the intermediate stage of the narrow pulse test circuit is the first output resistance. Based on the first output resistance, the narrow pulse test circuit improves the driving capability of the third intermediate pulse signal Smp3 without changing the frequency and pulse width of the third intermediate pulse signal Smp3, thereby obtaining the second intermediate pulse signal. That is, the driving capability of the target pulse signal Snp is improved without changing the frequency and pulse width of the target pulse signal Snp, so that a stable narrow pulse signal with strong driving capability that can be recognized by ATE can be obtained.
[0093] Based on the above embodiment, a specific description of a possible implementation method when executing S104 is as follows:
[0094] The ATE determines the pulse width of the target pulse signal according to the high level of the second intermediate pulse signal, the frequency of the first test signal, and the voltage of the second test signal.
[0095] Exemplarily, the pulse width of the second intermediate pulse signal Smp2 can be expressed as Vout'' / (Vin f''), wherein Vout'' is the equivalent DC voltage of the second intermediate pulse signal Smp2, Vin is the high level of the second intermediate pulse signal Smp2, and f'' is the frequency of the second intermediate pulse signal Smp2.
[0096] Based on the above embodiment, the pulse width of the second intermediate pulse signal Smp2 = the pulse width W of the target pulse signal Snp, the equivalent DC voltage Vout'' of the second intermediate pulse signal Smp2 = the voltage Vout of the second test signal S2, and the frequency f'' of the second intermediate pulse signal Smp2 = the frequency f' of the target pulse signal Snp = N The frequency f of the first test signal S1, and therefore the pulse width W of the target pulse signal Snp, can be expressed as:
[0097] W=Vout / (Vin f N) (3)
[0098] In this way, the ATE substitutes the frequency f of the first test signal S1, the voltage Vout of the second test signal S2 and the high level Vin of the second intermediate pulse signal Smp2 into formula (3) based on the calculation module, and calculates the pulse width W of the target pulse signal Snp.
[0099] The embodiment of the present disclosure further provides a narrow pulse test circuit. In the chip of the ATE test system provided in the above embodiment, the narrow pulse test circuit can execute S101 and S102 in the embodiment of the method of the present disclosure and the steps corresponding to S101 and S102.
[0100] Figure 7 A schematic diagram of a narrow pulse test circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the narrow pulse test circuit 100 includes a conversion module 110 and a frequency reduction module 120, wherein the input end of the conversion module 110 and the input end of the frequency reduction module 120 are connected to the input end of the narrow pulse test circuit 100, the output end of the frequency reduction module 120 is connected to the first output end of the narrow pulse test circuit 100, and the output end of the conversion module 110 is connected to the second output end of the narrow pulse test circuit 100.
[0101] The frequency reduction module 120 is configured to, in the narrow pulse test mode, perform frequency reduction processing on the target pulse signal Snp to obtain a first test signal S1, wherein the frequency of the first test signal S1 is 1 / N of the frequency of the target pulse signal Snp, where N is an integer greater than 1. The conversion module 110 is configured to, in the narrow pulse test mode, perform conversion processing on the target pulse signal Snp to obtain a second test signal S2, wherein the second test signal S2 is an equivalent DC signal of the target pulse signal Snp.
[0102] The frequency of the first test signal S1 and the voltage of the second test signal S2 are used to determine the pulse width of the target pulse signal Snp.
[0103] For example, Figure 7 As shown, the frequency reduction module 120 includes a frequency divider 121 , an input end of the frequency divider 121 is connected to an input end of the narrow pulse test circuit 100 , and an output end of the frequency divider 121 is connected to a first output end of the narrow pulse test circuit 100 .
[0104] When the ATE test system is in the narrow pulse test mode, the divider 121 can receive the target pulse signal Snp and perform N-division processing on the target pulse signal Snp to obtain a first test signal S1 with a preset duty cycle, wherein the preset duty cycle can be any value between 10% and 90%, for example, the preset duty cycle is 50%.
[0105] In other embodiments, the frequency reduction module 120 includes a frequency reduction circuit. When the ATE test system is in a narrow pulse test mode, the frequency reduction circuit can receive a target pulse signal Snp and perform frequency reduction processing on the target pulse signal Snp to obtain a first test signal S1, and the frequency of the first test signal S1 is 1 / N of the frequency of the target pulse signal Snp.
[0106] Exemplarily, the conversion module 110 includes an AC-DC conversion circuit. When the ATE test system is in a narrow pulse test mode, the AC-DC conversion circuit can receive a target pulse signal Snp and perform AC-to-DC conversion on the target pulse signal Snp to obtain an equivalent DC signal, i.e., a second test signal S2.
[0107] In other embodiments, the conversion module 110 includes an isolation circuit and an AC / DC conversion circuit. When the ATE test system is in a narrow pulse test mode, the isolation circuit can receive a target pulse signal Snp and isolate the target pulse signal Snp to obtain a stable target pulse signal Snp. The AC / DC conversion circuit performs AC-to-DC conversion on the isolated target pulse signal Snp to obtain an accurate second test signal S2.
[0108] In some other embodiments, the conversion module 110 includes a shaping circuit and an AC / DC conversion circuit. When the ATE test system is in a narrow pulse test mode, the shaping circuit can receive a target pulse signal Snp and shape the target pulse signal Snp to obtain a high-quality target pulse signal Snp. The AC / DC conversion circuit converts the shaped target pulse signal Snp from AC to DC to obtain an accurate second test signal S2.
[0109] In some other embodiments, the conversion module 110 includes a shaping circuit, an isolation circuit and an AC / DC conversion circuit. When the ATE test system is in a narrow pulse test mode, the isolation circuit receives the target pulse signal Snp and isolates the target pulse signal Snp, and the shaping circuit shapes the isolated target pulse signal Snp. Alternatively, the shaping circuit receives the target pulse signal Snp and shapes the target pulse signal Snp, and the isolation circuit isolates the shaped target pulse signal Snp to obtain a high-quality and stable target pulse signal Snp, and the AC / DC conversion circuit converts the shaped and isolated target pulse signal Snp from AC to DC to obtain an accurate second test signal S2.
[0110] The ATE substitutes the frequency f of the first test signal S1, the voltage Vout of the second test signal S2 and the high level Vin' of the target pulse signal Snp into formula (2) to calculate the pulse width W of the target pulse signal Snp.
[0111] In the disclosed embodiment, the narrow pulse test circuit includes a conversion module and a frequency reduction module. In the narrow pulse test mode, the frequency reduction module performs frequency reduction processing on the target pulse signal to obtain a first test signal, and the conversion module performs conversion processing on the target pulse signal to obtain a second test signal. The frequency of the first test signal and the voltage of the second test signal are used to determine the pulse width of the target pulse signal. The pulse width measurement of the narrow pulse signal can be converted into the measurement of its equivalent DC voltage and frequency. The ringing phenomenon, parasitic inductance and parasitic capacitance have little effect on the equivalent DC voltage and frequency of the narrow pulse signal. Therefore, a relatively accurate pulse width of the narrow pulse signal can be obtained, thereby improving the accuracy and stability of the narrow pulse test.
[0112] In some embodiments, Figure 8 A circuit diagram of a narrow pulse test circuit provided by an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the conversion module 110 includes a logic driving unit 111 , an RC network unit 112 and a voltage driving unit 113 .
[0113] Among them, the input end of the logic driving unit 111 is connected to the input end of the narrow pulse test circuit 100, the output end of the logic driving unit 111 is connected to the input end of the voltage driving unit 113 through the RC network unit 112, and the output end of the voltage driving unit 113 is connected to the second output end of the narrow pulse test circuit 100.
[0114] The logic driving unit 111 is configured to, based on the first output resistor, convert the target pulse signal Snp into a first intermediate pulse signal Smp1 to improve the driving capability of the target pulse signal Snp, shift the high level of the first intermediate pulse signal Smp1 to a preset voltage Vcc, and shift the low level of the first intermediate pulse signal Smp1 to the ground potential GND to obtain a second intermediate pulse signal Smp2, and the frequency and pulse width of the second intermediate pulse signal Smp2 are equal to those of the target pulse signal Snp.
[0115] The RC network unit 112 is configured to convert the second intermediate pulse signal Smp2 into a DC signal to obtain an intermediate DC signal Sdc. The voltage driving unit 113 is configured to convert the intermediate DC signal Sdc into a second test signal S2 based on the second output resistor to improve the driving capability of the intermediate DC signal Sdc.
[0116] Exemplarily, the driving capability of the target pulse signal Snp is weak, and the output resistance of the intermediate stage of the logic driving unit 111 is the first output resistance. The logic driving unit 111 can isolate the target pulse signal Snp and, based on the first output resistance, improve the driving capability of the target pulse signal Snp without changing the frequency and pulse width of the target pulse signal Snp, thereby obtaining the first intermediate pulse signal Smp1.
[0117] In addition, the high level and low level of the target pulse signal Snp may generally be unstable and / or not recognized by ATE, and the first intermediate pulse signal Smp1 differs from the target pulse signal Snp only in driving capability, so the high level and low level of the first intermediate pulse signal Smp1 may be unstable and / or not recognized by ATE.
[0118] The logic driving unit 111 can shift the high level of the first intermediate pulse signal Smp1 to a preset voltage Vcc recognizable by ATE, and shift the low level of the first intermediate pulse signal Smp1 to a ground potential GND recognizable by ATE, and can convert the first intermediate pulse signal Smp1 into a stable second intermediate pulse signal Smp2 recognizable by ATE without changing the frequency and pulse width of the first intermediate pulse signal Smp1.
[0119] In this way, the logic driving unit 111 can improve the driving capability of the target pulse signal Snp, and can also shift the high level of the target pulse signal Snp to the preset voltage Vcc, and shift the low level of the target pulse signal Snp to the ground potential GND. Without changing the frequency and pulse width of the target pulse signal Snp, the target pulse signal Snp can be converted into a stable pulse signal with stronger driving capability that can be recognized by ATE.
[0120] For example, Figure 8As shown, the RC network unit 112 includes a multi-stage RC network connected in series, and each stage of the RC network includes a resistor R and a capacitor C, wherein the first end of the resistor R of the first stage RC network is connected to the output end of the logic driving unit 111, the second end of the resistor R of the last stage RC network is connected to the first plate of the capacitor C of the last stage RC network and the input end of the voltage driving unit 113, the second end of the resistor R of the previous stage RC network is connected to the first plate of the capacitor C of the previous stage RC network and the first end of the resistor R of the next stage RC network, and the second plate of the capacitor C of each stage of the RC network is grounded.
[0121] For example, Figure 8 As shown, the RC network unit 112 includes two stages of RC networks connected in series, namely a first stage RC network and a second stage RC network.
[0122] Among them, the first end of the resistor R of the first-level RC network is connected to the output end of the logic driving unit 111, the second end of the resistor R of the first-level RC network is connected to the first plate of the capacitor C of the first-level RC network and the first end of the resistor R of the second-level RC network, the second end of the resistor R of the second-level RC network is connected to the first plate of the capacitor C of the second-level RC network and the input end of the voltage driving unit 113, and the second plate of the capacitor C of the first-level RC network and the second plate of the capacitor C of the second-level RC network are grounded.
[0123] For another example, Fig. 9 A circuit diagram of another narrow pulse test circuit provided by an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the RC network unit 112 includes three stages of RC networks connected in series, namely a first stage RC network, a second stage RC network and a third stage RC network.
[0124] Among them, the first end of the resistor R of the first-level RC network is connected to the output end of the logic driving unit 111, the second end of the resistor R of the first-level RC network is connected to the first plate of the capacitor C of the first-level RC network and the first end of the resistor R of the second-level RC network, and the second end of the resistor R of the second-level RC network is connected to the first plate of the capacitor C of the second-level RC network and the first end of the resistor R of the third-level RC network.
[0125] The second end of the resistor R of the third-level RC network is connected to the first plate of the capacitor C of the third-level RC network and the input end of the voltage driving unit 113, and the second plate of the capacitor C of the first-level RC network, the second plate of the capacitor C of the second-level RC network and the second plate of the capacitor C of the third-level RC network are grounded.
[0126] It should be noted that Figure 8 and Fig. 9The RC network unit 112 is exemplified by taking a two-level RC network and a three-level RC network as examples. In practical applications, the RC network unit 112 may also be a three-level or higher RC network.
[0127] In the positive cycle of the second intermediate pulse signal Smp2, the RC network unit 112 is in a charging state, and in the negative cycle of the second intermediate pulse signal Smp2, the RC network unit 112 is in a discharging state, and the capacitor C in the RC network unit 112 is charged and discharged with the change of the second intermediate pulse signal Smp2, so the voltage of the capacitor C fluctuates around the DC signal equivalent to the second intermediate pulse signal Smp2. Since the capacitor C needs to be charged and the charging time constant is R'C', where R' is the resistance value of the resistor R and C' is the capacitance value of the capacitor C, the existence of the resistor R makes the capacitor C unable to change with the change of the high-frequency signal, so the RC network unit 112 can filter out the high-frequency part.
[0128] Since the narrow pulse test circuit 100 is arranged inside the chip, considering the chip area, the capacitor C is generally set to be smaller and the resistor R is set to be larger, which can reduce the voltage loss of the second test signal S2. However, the voltage ripple of the second test signal S2 is larger, so a multi-stage RC network can be used to improve the smoothness of the second test signal S2.
[0129] However, the driving capability of the multi-stage RC network output signal is relatively weak, that is, the driving capability of the intermediate DC signal Sdc is relatively weak. The output resistance of the voltage driving unit 113 is the second output resistance. Based on the second output resistance, the voltage driving unit 113 can only improve the driving capability of the intermediate DC signal Sdc without changing other parameters of the intermediate DC signal Sdc, thereby obtaining the second test signal S2.
[0130] In other implementations, the RC network unit 112 may also be a single-stage RC network.
[0131] In the disclosed embodiment, the conversion module includes a logic driving unit, an RC network unit and a voltage driving unit. The logic driving unit converts the target pulse signal into a first intermediate pulse signal based on a first output resistor to improve the driving capability of the target pulse signal, shifts the high level of the first intermediate pulse signal to a preset voltage, and shifts the low level of the first intermediate pulse signal to the ground potential to obtain a second intermediate pulse signal. The RC network unit converts the second intermediate pulse signal into a DC signal to obtain an intermediate DC signal. The voltage driving unit converts the intermediate DC signal into a second test signal based on the second output resistor, so as to obtain a stable narrow pulse signal with strong driving capability that can be recognized by ATE, and converts it into an equivalent DC signal with strong driving capability, which can improve the accuracy of the equivalent DC voltage of the narrow pulse signal, thereby improving the accuracy of the narrow pulse test.
[0132] In other embodiments, the logic driving unit 111 is configured to shift the high level of the target pulse signal Snp to a preset voltage Vcc, and shift the low level of the target pulse signal Snp to a ground potential GND, to obtain a third intermediate pulse signal Smp3, and based on the first output resistor, convert the third intermediate pulse signal Smp3 into a second intermediate pulse signal Smp2 to improve the driving capability of the third intermediate pulse signal Smp3.
[0133] Exemplarily, the logic driving unit 111 can isolate the target pulse signal Snp, shift the high level of the target pulse signal Snp to a preset voltage, and shift the low level of the target pulse signal to the ground potential, and can convert the target pulse signal Snp into a stable third intermediate pulse signal Smp3 recognizable by ATE without changing the frequency and pulse width of the target pulse signal Snp.
[0134] The output resistance of the logic driving unit 111 is the first output resistance. Based on the first output resistance, the logic driving unit 111 improves the driving capability of the third intermediate pulse signal Smp3 without changing the frequency and pulse width of the third intermediate pulse signal Smp3, thereby obtaining the second intermediate pulse signal Smp2. That is, the driving capability of the target pulse signal Snp is improved without changing the frequency and pulse width of the target pulse signal Snp, so that a stable narrow pulse signal with strong driving capability that can be recognized by ATE can be obtained.
[0135] The embodiment of the present disclosure further provides a chip, comprising the narrow pulse test circuit 100 provided in any of the above embodiments.
[0136] Exemplarily, the chip may be a switching power supply chip or a power management chip, etc.
[0137] The chip provided by the implementation of the present disclosure includes the narrow pulse test circuit 100 provided in any embodiment, and has the functional modules and beneficial effects of the narrow pulse test circuit 100, which will not be repeated here.
[0138] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.
[0139] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.
Claims
1. A narrow pulse testing method, characterized in that: Applied in an automatic test equipment ATE test system, the method comprises: In the narrow pulse test mode, the target pulse signal is frequency-reduced to obtain a first test signal, wherein the frequency of the first test signal is 1 / N of the frequency of the target pulse signal, where N is an integer greater than 1; Converting the target pulse signal to obtain a second test signal, where the second test signal is an equivalent DC signal of the target pulse signal; measuring a frequency of the first test signal and a voltage of the second test signal; determining a pulse width of the target pulse signal according to the frequency of the first test signal and the voltage of the second test signal; The converting and processing the target pulse signal to obtain a second test signal comprises: Based on the first output resistor, converting the target pulse signal into a first intermediate pulse signal to improve the driving capability of the target pulse signal; Shifting the high level of the first intermediate pulse signal to a preset voltage and the low level of the first intermediate pulse signal to a ground potential to obtain a second intermediate pulse signal, wherein the frequency and pulse width of the second intermediate pulse signal are equal to those of the target pulse signal; Converting the second intermediate pulse signal into a DC signal to obtain an intermediate DC signal; Based on the second output resistor, converting the intermediate DC signal into the second test signal to improve the driving capability of the intermediate DC signal; Determining the pulse width of the target pulse signal according to the frequency of the first test signal and the voltage of the second test signal includes: determining a pulse width of the target pulse signal according to a high level of the second intermediate pulse signal, a frequency of the first test signal, and a voltage of the second test signal; The step of determining the pulse width of the target pulse signal according to the high level of the second intermediate pulse signal, the frequency of the first test signal and the voltage of the second test signal further comprises: The pulse width W of the target pulse signal is determined according to the following formula: W=Vout / (Vin f N) Wherein, Vout is the voltage of the second test signal, Vin is the high level of the second intermediate pulse signal, and f is the frequency of the first test signal.
2. The method according to claim 1, characterized in that The step of performing frequency reduction processing on the target pulse signal to obtain the first test signal comprises: The target pulse signal is subjected to N-frequency division processing to obtain the first test signal with a preset duty cycle.
3. A narrow pulse test circuit, characterized in that: Applied in an ATE test system, the narrow pulse test circuit comprises: a conversion module and a frequency reduction module; The narrow pulse test circuit is used to execute the method according to claim 1 or 2.
4. The narrow pulse test circuit according to claim 3, characterized in that: The frequency reduction module includes a frequency divider; The input end of the frequency divider is connected to the input end of the narrow pulse test circuit, and the output end of the frequency divider is connected to the first output end of the narrow pulse test circuit; The frequency divider is configured to perform N-frequency division processing on the target pulse signal to obtain the first test signal with a preset duty cycle.
5. The narrow pulse test circuit according to claim 3, characterized in that: The conversion module includes a logic driving unit, an RC network unit and a voltage driving unit; The input end of the logic driving unit is connected to the input end of the narrow pulse test circuit, the output end of the logic driving unit is connected to the input end of the voltage driving unit through the RC network unit, and the output end of the voltage driving unit is connected to the second output end of the narrow pulse test circuit; The logic driving unit is configured to, based on the first output resistor, convert the target pulse signal into the first intermediate pulse signal to improve the driving capability of the target pulse signal; shift the high level of the first intermediate pulse signal to the preset voltage, and shift the low level of the first intermediate pulse signal to the ground potential to obtain the second intermediate pulse signal; The RC network unit is configured to convert the second intermediate pulse signal into a DC signal to obtain the intermediate DC signal; The voltage driving unit is configured to convert the intermediate DC signal into the second test signal based on the second output resistance to improve the driving capability of the intermediate DC signal.
6. The narrow pulse test circuit according to claim 5, characterized in that: The RC network unit includes a plurality of RC networks connected in series, each RC network including a resistor and a capacitor; A first end of the resistor of the first-stage RC network is connected to the output end of the logic driving unit, and a second end of the resistor of the last-stage RC network is connected to the first plate of the capacitor of the last-stage RC network and the input end of the voltage driving unit; The second end of the resistor of the previous RC network is connected to the first plate of the capacitor of the previous RC network and the first end of the resistor of the next RC network, and the second plates of the capacitors of each stage of the RC network are grounded.
7. An ATE test system, characterized in that: comprising ATE and a chip connected to the ATE; The ATE test system is used to execute the method according to claim 1 or 2.