Overlay mark, semiconductor structure, and method of measuring overlay error

Abstract

The disclosure provides an overlay mark, a semiconductor structure and a method for measuring overlay error, the overlay mark is used for the semiconductor structure, the semiconductor structure comprises a substrate, the overlay mark is located on the substrate, and the overlay mark comprises: a first pattern layer and a second pattern layer, the first pattern layer and the second pattern layer are formed in different patterning processes, and the orthographic projections of the first pattern layer and the second pattern layer on the substrate do not overlap; the first pattern layer and the second pattern layer both comprise a plurality of marks arranged at intervals, and the extension directions of at least part of the marks and the interval arrangement directions intersect with each other; each mark comprises a plurality of sub-marks, and in the same mark, the two ends of the extension directions of the plurality of sub-marks are located at the two ends of the extension direction of the mark. Therefore, the overlay mark, the semiconductor structure and the method for measuring overlay error provided by the disclosure can ensure the measurement accuracy of the overlay error, thereby improving the yield and the yield of the product.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for measuring overlay marks, semiconductor structures, and overlay errors. Background Technology

[0002] In semiconductor manufacturing, photolithography is a crucial process for transferring circuit patterns. Photolithography involves transferring patterns from a photomask onto a wafer through exposure and development. A fundamental metric for photolithography is overlay (OVL) error, which reflects the alignment between lines in different layers. When the alignment between a layer and the preceding layer exceeds the tolerance limit, open or short circuits may occur in the interlayer circuitry, affecting the yield of the semiconductor structure.

[0003] In related technologies, a wafer may include multiple semiconductor chips and dicing zones that separate the multiple semiconductor chips. Overlay marks may be formed within the dicing zones.

[0004] However, existing overlay markings can affect the accuracy of overlay error measurement. Summary of the Invention

[0005] This disclosure provides a method for measuring overlay marks, semiconductor structures, and overlay errors, which can ensure the accuracy of overlay error measurement, thereby improving product yield and productivity.

[0006] The embodiments disclosed herein provide the following technical solutions:

[0007] A first aspect of this disclosure provides an overlay mark for a semiconductor structure. The semiconductor structure includes a substrate, and the overlay mark is located on the substrate. The overlay mark includes a first pattern layer and a second pattern layer, which are formed in different patterning processes. The orthographic projections of the first and second pattern layers on the substrate do not overlap. Both the first and second pattern layers include a plurality of marks spaced apart, and the extension directions of at least a portion of the marks intersect the spacing direction. Each mark includes a plurality of sub-marks, and in the same mark, the ends of the extension directions of the multiple sub-marks are located at the ends of the extension direction of the mark.

[0008] The overlay markings provided in this disclosure can be used in semiconductor structures, which may include a substrate, on which the overlay markings are located. The overlay markings may include a first patterning layer and a second patterning layer, which are formed in different patterning processes, and their orthogonal projections onto the substrate do not overlap. Both the first and second patterning layers include a plurality of markings spaced apart, with at least a portion of the markings having extension directions that intersect the spacing direction. Each marking may include a plurality of sub-markers, where the ends of the extension directions of the sub-markers are located at the ends of the marking's extension direction. This avoids interference from the ends of the sub-markers' extension directions with the image accuracy of the marking's edges perpendicular to the marking's extension direction, resulting in higher accuracy of the acquired edge signals perpendicular to the marking's extension direction. This ensures the accuracy of overlay error measurement and improves product yield and productivity.

[0009] In one possible implementation, the plurality of marks includes a plurality of first marks, which are all spaced apart along a first direction, and the extension direction of the plurality of first marks intersects the first direction at an angle.

[0010] The semiconductor structure includes multiple first dicing regions and multiple second dicing regions. The multiple first dicing regions extend along a first direction and are spaced apart along a second direction. The multiple second dicing regions extend along a second direction and are spaced apart along a first direction. The multiple first dicing regions and multiple second dicing regions intersect each other and define multiple chip regions.

[0011] The semiconductor structure includes a third patterning layer and a fourth patterning layer. The third patterning layer and the first patterning layer are formed in the same patterning process, and the fourth patterning layer and the second patterning layer are formed in the same patterning process. Both the third and fourth patterning layers are located on the substrate of the chip region, and the overlay marks are located on the substrate of the first dicing region and / or the second dicing region.

[0012] The overprinting error of the third and fourth pattern layers can be obtained by measuring the overprinting error between the first and second pattern layers.

[0013] In one possible implementation, a third or fourth patterning layer forms multiple active regions in each chip region, and the extension direction of the first marker is the same as the extension direction of the active regions.

[0014] This can improve the consistency between the fabrication effect of the first marker and the active region, thereby better reflecting the etching effect of the active region in the chip area.

[0015] Within the same tag, multiple sub-tags extend in the same direction as the tag, and these sub-tags are spaced apart.

[0016] This allows the overlay markings to better reflect the etching effect of the circuit components in the chip area.

[0017] In one possible implementation, the plurality of marks includes a plurality of second marks, which are all spaced apart along a second direction, and the extension direction of the plurality of second marks is different from the second direction.

[0018] The second overlay error of the first pattern layer and the second pattern layer along the extension direction perpendicular to the second mark can be obtained through the second mark.

[0019] In one possible implementation, the extension directions of the plurality of second marks intersect perpendicularly with the extension direction of the first mark.

[0020] It can be used to obtain the overprinting error of the first pattern layer and the second pattern layer in any direction on the plane of the substrate, so as to fully reflect the actual overprinting error of the first pattern layer and the second pattern layer.

[0021] In one possible implementation, along the extension direction of the second mark, there is an overprinting error a between the first marks of the first pattern layer and the second pattern layer; along the extension direction of the first mark, there is an overprinting error b between the second marks of the first pattern layer and the second pattern layer.

[0022] Along the first direction, there is an overlay error x between the first pattern layer and the second pattern layer; along the second direction, there is an overlay error y between the first pattern layer and the second pattern layer; the extension direction of the first mark has an angle θ with the first direction; the first direction and the second direction are perpendicular to each other;

[0023] x, a, b, and θ satisfy the formula: x = b * cosθ + a * sinθ;

[0024] y, a, b, and θ satisfy the formula: y = b*sinθ - a*cosθ.

[0025] In one possible implementation, the extension direction of the plurality of second marks is the same as the extension direction of the first mark.

[0026] This can improve the accuracy of measuring the overlay error of the first pattern layer and the second pattern layer along the extension direction perpendicular to the first mark.

[0027] In one possible implementation, along the extension direction perpendicular to the first mark, there is an overlay error 'a' between the first marks of the first pattern layer and the second pattern layer, and between the second marks of the first pattern layer and the second pattern layer.

[0028] Along the first direction, there is an overlay error x between the first pattern layer and the second pattern layer; along the second direction, there is an overlay error y between the first pattern layer and the second pattern layer; the extension direction of the first mark has an angle θ with the first direction; the first direction and the second direction are perpendicular to each other;

[0029] x, a, and θ satisfy the formula: x = a * sinθ;

[0030] y, a, and θ satisfy the formula: y = -a*cosθ.

[0031] A second aspect of this disclosure provides a semiconductor structure including a substrate and the overlay marks described in the first aspect above, the overlay marks being located on the substrate.

[0032] The semiconductor structure provided in this disclosure includes overlay marks, which can be used on the semiconductor structure. The semiconductor structure includes a substrate, and the overlay marks are located on the substrate. The overlay marks may include a first pattern layer and a second pattern layer, which are formed in different patterning processes. The orthographic projections of the first and second pattern layers on the substrate do not overlap. Both the first and second pattern layers include a plurality of marks spaced apart, and at least a portion of the marks have extension directions that intersect with the spacing direction. Each mark may include a plurality of sub-marks. In the same mark, the ends of the extension directions of the multiple sub-marks are located at the ends of the extension direction of the mark, thereby avoiding interference from the ends of the extension directions of the sub-marks with the image accuracy of the marks along the edges perpendicular to the extension direction of the marks. This results in higher accuracy of the edge signals of the marks perpendicular to the extension direction of the marks, thereby ensuring the measurement accuracy of overlay errors and improving product yield and productivity.

[0033] A third aspect of this disclosure provides a method for measuring overlay error, providing an overlay mark for a semiconductor structure. The semiconductor structure includes a substrate, and the overlay mark is located on the substrate. The overlay mark includes a first pattern layer and a second pattern layer, which are formed in different patterning processes. The orthographic projections of the first and second pattern layers on the substrate do not overlap. Both the first and second pattern layers include a plurality of marks spaced apart, and the extension directions of at least a portion of the marks intersect the spacing direction. Each mark includes a plurality of sub-marks, and in the same mark, the ends of the extension directions of the multiple sub-marks are located at the ends of the extension direction of the mark.

[0034] Obtain images of the first pattern layer and the second pattern layer;

[0035] Extract the grayscale signals of the images of the first pattern layer and the second pattern layer;

[0036] The overlay error of the first pattern layer and the second pattern layer is obtained based on the grayscale signal.

[0037] The overlay error measurement method provided in this disclosure can be used to measure the overlay error of overlay marks. The overlay marks can be used in a semiconductor structure, which may include a substrate, and the overlay marks are located on the substrate. The overlay marks may include a first pattern layer and a second pattern layer, which are formed in different patterning processes, and their orthogonal projections onto the substrate do not overlap. Both the first and second pattern layers include a plurality of marks spaced apart, with at least a portion of the marks having extension directions that intersect the spacing direction. Each mark may include a plurality of sub-marks. In the same mark, the ends of the extension directions of the multiple sub-marks are located at the ends of the mark's extension direction, thereby avoiding interference from the ends of the sub-marks' extension directions with the image accuracy of the mark's edges perpendicular to the mark's extension direction. This results in higher accuracy of the edge signals acquired perpendicular to the mark's extension direction, ensuring the accuracy of the overlay error measurement and improving product yield and productivity.

[0038] The structure of this disclosure, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1a This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0041] Figure 1b A top view of the active region, bit line, and gate in a chip region provided for an embodiment of this disclosure;

[0042] Figure 2 This is a schematic diagram of the structure of the overlay mark provided in an embodiment of the present disclosure;

[0043] Figure 3 Another schematic diagram of the overlay mark provided in this embodiment of the disclosure;

[0044] Figure 4 This is a schematic diagram of the structure of the first pattern layer provided in an embodiment of the present disclosure;

[0045] Figure 5This is a schematic diagram of the structure of the second patterned layer provided in an embodiment of the present disclosure;

[0046] Figure 6 This is a schematic diagram of the structure of the first marker group provided in an embodiment of the present disclosure;

[0047] Figure 7 This is a schematic diagram of the structure of the second marker group provided in an embodiment of this disclosure;

[0048] Figure 8 This is another structural schematic diagram of the second marker group provided in an embodiment of the present disclosure;

[0049] Figure 9 A schematic diagram illustrating the conversion of overlay error a into overlay error x and overlay error y according to embodiments of this disclosure;

[0050] Figure 10 A schematic diagram illustrating the conversion of overlay errors a and b into overlay errors x and y, as provided in the embodiments of this disclosure;

[0051] Figure 11 A flowchart illustrating the method for measuring overlay error provided in this embodiment of the disclosure;

[0052] Figure 12 This is a schematic diagram of the structure of the first mark for overlay marking provided in an embodiment of the present disclosure;

[0053] Figure 13 A scanning electron microscope image of a marker in a related technology that includes multiple sub-markers;

[0054] Figure 14 A schematic diagram of the overlay error of N overlay marks in a semiconductor structure in a related measurement technique;

[0055] Figure 15 A scanning electron microscope image of a marker comprising multiple sub-markers provided in an embodiment of this disclosure;

[0056] Figure 16 This is a schematic diagram for measuring the overlay error of N overlay marks in a semiconductor structure according to an embodiment of this disclosure.

[0057] Explanation of reference numerals in the attached figures:

[0058] 200 / 100: Semiconductor structure; 100a: First dicing zone;

[0059] 100b: Second cutting track area; 100c: Chip area;

[0060] 101: Overprint mark; 110: First pattern layer;

[0061] 120: Second pattern layer; 230 / 130: Markings;

[0062] 131a: First marker group; 131: First marker;

[0063] 132a: Second marker group; 132: Second marker;

[0064] 233 / 133: Sub-marker; 141: Gate;

[0065] 142: Bit line; 143: Active region. Detailed Implementation

[0066] In the manufacturing process of integrated circuits (ICs), a complete chip typically undergoes 10 to 20 photolithography processes. Besides the resolution of the photolithography machine, alignment accuracy is another parameter affecting the error in the photolithography process. Overlay marks can be formed within the dicing area of ​​the wafer, and the overlay error of these marks can then be measured to reflect the overlay quality within the chip.

[0067] The overlay marks can be located on a substrate and can include a first pattern layer and a second pattern layer. The first pattern layer can be formed on the substrate before the second pattern layer, and the orthographic projections of the first and second pattern layers on the substrate do not overlap. Both the first and second pattern layers include multiple marks extending along a first direction, with the multiple marks arranged parallel and equidistantly, and also spaced apart along a second direction, wherein the first and second directions are perpendicular to each other. By acquiring images of the first and second pattern layers and extracting the edge information of the multiple marks on both sides of the first pattern layer in the second direction, the first center line of the multiple marks in the first pattern layer can be determined. Similarly, the second center line of the multiple marks in the second pattern layer can be determined. By measuring the positional offset of the first and second center lines in the second direction, the overlay error of the preceding layer containing the first pattern layer and the current layer containing the second pattern layer in the second direction can be obtained. Each mark includes multiple sub-marks, and within the same mark, the two ends of the extension directions of the multiple sub-marks are respectively located on both sides of the mark's second direction.

[0068] However, within the same marker, the two ends of the extension directions of multiple sub-markers are located on both sides of the marker's second direction. This means that the two ends of the extension directions of the multiple sub-markers form the edges of the marker along the second direction. During the exposure process for preparing the sub-markers, diffraction occurs in the mask, causing the ends of the extended directions of the formed sub-markers to become smaller. This results in uneven edges of the marker along the second direction, leading to poor accuracy in the acquired images of the marker's edges along the second direction. Consequently, the accuracy of the acquired edge information along the second direction is reduced, decreasing the accuracy of overlay error measurement and affecting overlay control, ultimately impacting product yield and productivity.

[0069] This disclosure provides an overlay mark, a semiconductor structure, and a method for measuring overlay error. The overlay mark can be used in the semiconductor structure, which may include a substrate, and the overlay mark is located on the substrate. The overlay mark may include a first pattern layer and a second pattern layer, which are formed in different patterning processes, and their orthogonal projections onto the substrate do not overlap. Both the first and second pattern layers include a plurality of marks spaced apart, with at least a portion of the marks having extension directions that intersect the spacing direction. Each mark may include a plurality of sub-marks, where the ends of the extension directions of the sub-marks are located at the ends of the mark's extension direction, thereby avoiding interference from the ends of the sub-marks' extension directions with the image accuracy of the mark's edges perpendicular to the mark's extension direction. This results in higher accuracy of the edge signals acquired perpendicular to the mark's extension direction, ensuring the accuracy of the overlay error measurement and improving product yield and productivity.

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0071] The following will combine Figures 1a-16 The semiconductor structure 100 provided in the embodiments of this disclosure will be described.

[0072] In some embodiments, semiconductor structure 100 may include a wafer. A wafer can refer to a silicon wafer used in the fabrication of silicon semiconductor integrated circuits; it is called a wafer because its shape is typically circular.

[0073] In some embodiments, see Figure 1a and Figure 1bThe semiconductor structure 100 may include a plurality of first dicing regions 100a and a plurality of second dicing regions 100b. The plurality of first dicing regions 100a may extend along a first direction X and be spaced apart along a second direction Y. The plurality of second dicing regions 100b may extend along the second direction Y and be spaced apart along the first direction X. The plurality of first dicing regions 100a and the plurality of second dicing regions 100b are interleaved and define a plurality of chip regions 100c. For example, the plurality of chip regions 100c may be arranged in an array.

[0074] It is understood that the first direction X and the second direction Y can intersect at an angle or be perpendicular to each other. This embodiment of the disclosure uses the example of the first direction X and the second direction Y being perpendicular to each other for illustration.

[0075] For example, various circuit elements, such as diodes, transistors, field-effect transistors, low-power resistors, inductors, and capacitors, can be formed in the chip region 100c. After the circuit elements in the chip region 100c are processed, they are cut along the cutting channels (first cutting channel 100a and second cutting channel 100b) to obtain multiple independent chips.

[0076] Understandably, this is done to simplify the illustration. Figure 1a The linear structure in the image shows the dicing channel area located between chip regions 100c. In reality, the dicing channel area can be a structure with a certain width and depth so that after cutting along the dicing channel area, a chip with a regular and uniform shape can be formed.

[0077] The chip can be a logic chip, a memory chip, or a power chip. Memory chips can include, but are not limited to, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash Memory, Resistive Random Access Memory, Phase-Change Random Access Memory, or Magnetoresistive Non-Volatile Random Access Memory.

[0078] This disclosure uses a memory chip as an example for illustration.

[0079] In some embodiments, see Figure 2 and Figure 3The semiconductor structure 100 may include overlay marks 101, which may be located on the substrate of the first dicing region 100a and / or the second dicing region 100b, and can prevent the pattern of the overlay marks 101 from interfering with the pattern of the circuit elements in the chip region 100c. The overlay marks 101 may include a first pattern layer 110 and a second pattern layer 120, which are formed in different patterning processes. One of the first pattern layer 110 and the second pattern layer 120 may be the current layer and the other may be the previous layer.

[0080] For example, the first pattern layer 110 and the second pattern layer 120 can be protrusions, grooves, or ion implantation regions disposed within the dicing zone. The orthographic projections of the first pattern layer 110 and the second pattern layer 120 onto the substrate do not overlap, thereby facilitating the measurement of overlay errors.

[0081] In some embodiments, the semiconductor structure 100 may include a third patterning layer and a fourth patterning layer, both of which may be located on the substrate of the chip region 100c. The third patterning layer may be formed in the same patterning process as the first patterning layer 110, and the first patterning layer 110 may be used to reflect the position and fabrication status of the third patterning layer. The fourth patterning layer may be formed in the same patterning process as the second patterning layer 120, and the second patterning layer 120 may be used to reflect the position and fabrication status of the fourth patterning layer. Therefore, the overlay error between the third and fourth patterning layers can be obtained by measuring the overlay error between the first patterning layer 110 and the second patterning layer 120.

[0082] For example, see Figure 1b Each chip region 100c can have multiple active regions 143, and each active region 143 can extend in the same direction. At least some of the markings 130 can extend in a direction parallel to the extension direction of the active regions 143, thereby improving the consistency of the fabrication effect of these markings 130 and the active regions 143. This allows these markings 130 to better reflect the fabrication effect of the active regions 143 in the chip region 100c, and thus better reflect the overlay error of each layer in the chip region 100c. For example, the extension direction of the first marking 131 can be parallel to the extension direction of the active regions 143.

[0083] It is understood that the third and fourth pattern layers can be patterns of circuit elements in chip region 100c. For example, they can be active region layers, gate dielectric layers, gate layers, source layers, drain layers, bit line layers, etc., of transistors. All active regions 143 on the semiconductor structure 100 collectively form the active region layer; similarly, all gates 141 collectively form the gate layer, and all bit lines 142 collectively form the bit line layer. Taking the third or fourth pattern layer as an active region layer as an example, the third or fourth pattern layer can form multiple active regions 143 in each chip region 100c.

[0084] In some embodiments, the semiconductor structure 100 of the chip region 100c may include multiple transistors. The angle between the extension direction of the active region 143 of the transistor and the second direction Y can be in the range of 20°-30°, thereby increasing the arrangement density of the active region 143 and improving the storage performance of the fabricated memory chip. Additionally, the extension direction of at least one of the other structural layers located on the active region 143 of the transistor, such as a bit line layer or a gate layer, may have a certain angle with the extension direction of the active region 143.

[0085] In some embodiments, the semiconductor structure 100 may include a substrate. The substrate material may be any one or more of single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compounds, gallium-arsenic compounds, gallium-phosphorus compounds, gallium-sulfur compounds, etc., or other materials known to those skilled in the art. The substrate may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate may provide a supporting foundation for other structural layers on the substrate.

[0086] The overlay mark 101 provided in the embodiments of this disclosure will be described below.

[0087] In some embodiments, the overlay mark 101 may be located on the substrate of the first cutting channel region 100a and / or the second cutting channel region 100b. Exemplarily, other structural layers may also be provided between the substrate and the first pattern layer 110 and the second pattern layer 120. The first pattern layer 110 and the second pattern layer 120 may be located on different other structural layers on the substrate, or the first pattern layer 110 and the second pattern layer 120 may be located on the same other structural layer on the substrate, or at least one of the first pattern layer 110 and the second pattern layer 120 may be in direct contact with the substrate.

[0088] See Figure 4 and Figure 5 Both the first pattern layer 110 and the second pattern layer 120 may include a plurality of marks 130 spaced apart, and the extension direction of at least a portion of the marks 130 intersects the spacing direction.

[0089] In related technologies, by setting the two ends of the extension direction of multiple sub-markers at the edges perpendicular to the extension direction of the mark (taking the extension direction of the mark as the length direction of the mark and the perpendicularity to the extension direction of the mark as the width direction as an example), the edges on both sides of the width direction of the mark become uneven, resulting in poor accuracy of the acquired images of the edges on both sides of the width direction of the mark. This leads to poor accuracy of the acquired edge information on both sides of the width direction of the mark, thereby reducing the measurement accuracy of overlay error, which in turn affects the control of overlay and the yield and productivity of the product.

[0090] For example, see Figures 6-8 Each mark 130 may include multiple sub-markers 133. Within the same mark 130, the ends of the extension directions of the multiple sub-markers 133 can be located at the ends of the extension direction of the mark 130. In this embodiment, by setting the ends of the extension directions of the multiple sub-markers 133 at the ends of the extension direction of the mark 130, uneven edges are located at the ends of the extension direction of the mark 130 rather than on both sides of the width direction of the mark 130. This makes the edges on both sides of the width direction of the mark 130 more uniform, improving the accuracy of the acquired images of the edges on both sides of the width direction of the mark 130, thereby improving the accuracy of the acquired edge information on both sides of the width direction of the mark 130. In other words, the ends of the extension directions of the sub-markers 133 can be prevented from interfering with the image accuracy of the edges of the mark 130 along the edges perpendicular to the extension direction of the mark 130. When acquiring signals from the edges of the mark 130 perpendicular to the extension direction of the mark 130, the signal accuracy is higher, thus ensuring the measurement accuracy of overlay errors and improving product yield and productivity.

[0091] For example, within the same mark 130, the extension directions of multiple sub-marks 133 can all be the same as the extension direction of mark 130, and the multiple sub-marks 133 are spaced apart. This configuration allows the same mark 130 to be formed using multiple finer sub-marks 133, making the linewidth of the sub-marks 133 closer to the linewidth of the circuit element pattern within the chip region 100c. This improves the consistency of the fabrication effect between the overlay mark 101 and the circuit element pattern of the chip region 100c; for example, it results in better etching consistency, allowing the overlay mark 101 to better reflect the etching effect of the circuit elements in the chip region 100c. Furthermore, the multiple sub-marks 133 can be evenly distributed within the same mark 130, thereby avoiding measurement signal loss.

[0092] It is understandable that within the same marker 130, the extension lengths of any two sub-markers 133 can be the same or different. There is a spacing between any two adjacent sub-markers 133, and any two spacings can be the same or different.

[0093] In some embodiments, see Figure 2 and Figure 3 The multiple marks 130 of the first pattern layer 110 may include multiple first marks 131 and multiple second marks 132. The multiple first marks 131 are spaced apart along a first direction X and extend along direction A. The multiple second marks 132 are spaced apart along a second direction Y and extend along either direction B or direction A. Similarly, the multiple marks 130 of the second pattern layer 120 may include multiple first marks 131 and multiple second marks 132. The multiple first marks 131 are spaced apart along a first direction X and extend along direction A. The multiple second marks 132 are spaced apart along a second direction Y and extend along either direction B or direction A.

[0094] In some embodiments, see Figure 4 and Figure 5 The plurality of marks 130 in the first pattern layer 110 and the plurality of marks 130 in the second pattern layer 120 can each include a plurality of first marks 131. The plurality of first marks 131 can be spaced apart along the first direction X, and can collectively form a first mark group 131a. The number of first mark groups 131a can be at least two. When the number of first mark groups 131a is at least two, the at least two first mark groups 131a are arranged at intervals and are centrally symmetrical. The first mark groups 131a of the first pattern layer 110 and the first mark groups 131a of the second pattern layer 120 can be arranged in a one-to-one correspondence. For example, the extension direction A of the plurality of first marks 131 can intersect the first direction X at an angle.

[0095] Specifically, the first overlay error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the first mark 131 can be obtained by acquiring the center lines of all the first marks 131 of the first pattern layer 110 along the extension direction perpendicular to the first mark 131, and the center lines of all the first marks 131 of the second pattern layer 120 along the extension direction perpendicular to the first mark 131, and calculating the position offset of the two center lines.

[0096] In some embodiments, see Figure 4 and Figure 5Both the plurality of marks 130 in the first pattern layer 110 and the plurality of marks 130 in the second pattern layer 120 may include a plurality of second marks 132. The plurality of second marks 132 may be spaced apart along the second direction Y, and may collectively form a second mark group 132a. The number of second mark groups 132a may be at least two. When the number of second mark groups 132a is at least two, the at least two second mark groups 132a are arranged at intervals and are centrally symmetrical. The second mark groups 132a of the first pattern layer 110 and the second mark groups 132a of the second pattern layer 120 may be arranged in a one-to-one correspondence. For example, the extension direction of the plurality of second marks 132 may be different from the second direction Y. For example, the extension direction of the plurality of second marks 132 may be direction B or direction A.

[0097] Specifically, the second overlay error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the second mark 132 can be obtained by acquiring the center lines of all the second marks 132 of the first pattern layer 110 along the extension direction perpendicular to the second mark 132, and calculating the positional offset of the two center lines.

[0098] In some embodiments, the plurality of marks 130 of the first pattern layer 110 and the plurality of marks 130 of the second pattern layer 120 may each include a plurality of first marks 131, and the plurality of marks 130 of the first pattern layer 110 and the plurality of marks 130 of the second pattern layer 120 may each include a plurality of second marks 132, thereby enabling the acquisition of a first overprinting error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the first mark 131, and a second overprinting error along the extension direction perpendicular to the second mark 132.

[0099] For example, see Figure 4 and Figure 5 In the first pattern layer 110 or the second pattern layer 120, a plurality of first marks 131 arranged at intervals along the first direction X form a first mark group 131a, and the number of first mark groups 131a is at least one. A plurality of second marks 132 arranged at intervals along the second direction Y form a second mark group 132a, and the number of second mark groups 132a is at least one. In embodiments where there are at least two first mark groups 131a and two mark groups 132a, the first mark groups 131a and the second mark groups 132a are arranged alternately along a circular trajectory and are centrally symmetrical.

[0100] For example, the first mark group 131a and the second mark group 132a are arranged alternately along a circular trajectory or a regular polygonal trajectory. The two first mark groups 131a located on the diagonal of the circular trajectory are rotationally symmetrical with respect to the center of the circular trajectory. In the two first mark groups 131a on a diagonal, one first mark group 131a rotates 180° around the center of the circular trajectory and then coincides with the other first mark group 131a. The two second mark groups 132a located on the diagonal of the circular trajectory are rotationally symmetrical with respect to the center of the circular trajectory, and the principle is similar to that of the first mark group 131a, so it will not be described again.

[0101] In some embodiments, the extension direction of the first mark 131 may be the same as the extension direction of at least a portion of the pattern of the third pattern layer, thereby improving the consistency of the fabrication effect of the first mark 131 and the pattern of the third pattern layer. For example, the etching effect consistency is better, so that the first mark 131 can better reflect the etching effect of the pattern of the third pattern layer, and thus reflect the overlay error of each film layer in the chip region 100c. Alternatively, the extension direction of the first mark 131 may be the same as the extension direction of at least a portion of the pattern of the fourth pattern layer, thereby improving the consistency of the fabrication effect of the first mark 131 and the pattern of the fourth pattern layer. The principle of this has been explained and will not be repeated here. The extension directions of the patterns of the third pattern layer and the fourth pattern layer may be the same or different. In embodiments where the extension directions of at least a portion of the patterns of the third pattern layer and the fourth pattern layer are the same, the extension direction of the first mark 131 may be the same as the extension directions of at least a portion of the patterns of both the third and fourth pattern layers, thereby improving the consistency of the fabrication effect of the first mark 131 and the patterns of both the third and fourth pattern layers. The principle of this has been explained and will not be repeated here.

[0102] Understandably, the higher the similarity of the parameters between two patterns, the higher the consistency of their fabrication results; for example, the etching effects will be similar. The parameters of the patterns can include the direction of extension, linewidth, etc.

[0103] For example, when at least one of the third pattern layer and / or the fourth pattern layer is the active region 143 of a transistor in the chip region 100c or other structural layers that extend in the same direction as the active region, the angle between the active region, the other structural layers extending in the same direction as the active region and the second direction Y is in the range of 20°-30°, the angle between the first mark 131 and the second direction Y can also be in the range of 20°-30°. This ensures a high density of the active region 143 while maintaining good consistency in the etching of the first mark 131 with the third pattern layer and / or the fourth pattern layer, allowing the first mark 131 to better reflect the etching effect of the third pattern layer and / or the fourth pattern layer, thereby reflecting the overlay error of each film layer in the chip region 100c. For example, the angle between the first mark 131 and the second direction Y can be 20°, 23°, 25°, 28°, 30°, or any value between 20° and 30°.

[0104] It is understood that the extension direction of the second mark 132 may be the same as the extension direction of at least part of the pattern of the third pattern layer and / or the fourth pattern layer, thereby improving the consistency of the preparation effect of the second mark 132 with the pattern of the third pattern layer and / or the fourth pattern layer. The principle is similar to that of the first mark 131, and will not be repeated here.

[0105] The overprinted mark 101 may have only one of the first mark 131 and the second mark 132, or the overprinted mark 101 may have both the first mark 131 and the second mark 132. This embodiment of the disclosure is illustrated by taking the overprinted mark 101 having both the first mark 131 and the second mark 132 as an example.

[0106] The following description uses the example of the second mark 132 having the same extension direction as the first mark 131 provided in the embodiments of this disclosure as an example.

[0107] See Figure 3 The extension direction of the second mark 132 can be the same as the extension direction of the first mark 131 (both are direction A). With this setting, the first and second overlay errors are both overlay errors along the extension direction perpendicular to the first mark 131. For example, the average overlay error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the first mark 131 can be obtained by averaging the first and second overlay errors. This can improve the accuracy of measuring the overlay error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the first mark 131.

[0108] The overprinting error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the first mark 131 can be converted into the overprinting error of the first pattern layer 110 and the second pattern layer 120 along the first direction X and the second direction Y, so as to facilitate the calculation of overprinting error and the unification of direction.

[0109] See Figure 3 and Figure 9 The extension direction of the first mark 131 is A. Along the extension direction perpendicular to the first mark 131, there is an overlay error 'a' between the first mark 131 of the first pattern layer 110 and the second pattern layer 120, and between the second mark 132 of the first pattern layer 110 and the second pattern layer 120. For example, the overlay error 'a' is obtained by averaging the first overlay error and the second overlay error. The extension direction A of the first mark 131 forms an angle θ with the first direction X, and the first direction X and the second direction Y are perpendicular to each other. The overlay error component of 'a' in the first direction X is a*sinθ, and the overlay error component of 'a' in the second direction Y is -a*cosθ.

[0110] Along the first direction X, there is an overprinting error x between the first pattern layer 110 and the second pattern layer 120; along the second direction Y, there is an overprinting error y between the first pattern layer 110 and the second pattern layer 120. The component of the overprinting error a in the first direction X is the overprinting error x, and the component of the overprinting error a in the second direction Y is the overprinting error y.

[0111] x, a, and θ satisfy Formula 1: x = a * sinθ;

[0112] y, a, and θ satisfy Formula 2: y = -a*cosθ.

[0113] In some embodiments, the extension direction of the second mark 132 may intersect with the extension direction of the first mark 131, thereby obtaining the overprinting error of the first pattern layer 110 and the second pattern layer 120 along two different directions, which increases the number of directions of the obtained overprinting error of the first pattern layer 110 and the second pattern layer 120, and better reflects the actual overprinting error of the first pattern layer 110 and the second pattern layer 120.

[0114] The following description uses the example of the extension direction of the second mark 132 being perpendicular to the extension direction of the first mark 131 provided in the embodiments of this disclosure.

[0115] See Figure 2The extension directions of multiple second marks 132 can intersect perpendicularly with the extension direction of the first mark 131, thereby obtaining the overlay error in the two perpendicularly intersecting directions of the first pattern layer 110 and the second pattern layer 120. This can be used to obtain the overlay error of the first pattern layer 110 and the second pattern layer 120 in any direction on the plane of the substrate, so as to fully reflect the actual overlay error of the first pattern layer 110 and the second pattern layer 120.

[0116] The overprinting errors of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the first mark 131 and along the extension direction perpendicular to the second mark 132 can be converted into overprinting errors of the first pattern layer 110 and the second pattern layer 120 along the first direction X and the second direction Y, so as to facilitate the calculation of overprinting errors and the unification of directions.

[0117] See Figure 2 and Figure 10 Along the extension direction B of the second mark 132 (i.e., perpendicular to the extension direction A of the first mark 131), there is an overprinting error 'a' between the first mark 131 of the first pattern layer 110 and the second pattern layer 120; along the extension direction A of the first mark 131 (i.e., perpendicular to the extension direction B of the second mark 132), there is an overprinting error 'b' between the second mark 132 of the first pattern layer 110 and the second pattern layer 120. In other words, the first overprinting error is overprinting error 'a', and the second overprinting error is overprinting error 'b'. The extension direction A of the first mark 131 forms an angle θ with the first direction X, and the first direction X and the second direction Y are perpendicular to each other.

[0118] The overprinting error 'a' has an overprinting error component of a*sinθ in the first direction X, and an overprinting error component of -a*cosθ in the second direction Y. The overprinting error 'b' has an overprinting error component of b*cosθ in the first direction X, and an overprinting error component of b*sinθ in the second direction Y.

[0119] Along the first direction X, there is an overlay error x between the first pattern layer 110 and the second pattern layer 120; along the second direction Y, there is an overlay error y between the first pattern layer 110 and the second pattern layer 120. The overlay error x is obtained by adding the components of the overlay error a and the overlay error b in the first direction X, and the overlay error y is obtained by adding the components of the overlay error a and the overlay error b in the second direction Y.

[0120] x, a, b, and θ satisfy Formula 3: x = b * cosθ + a * sinθ;

[0121] y, a, b, and θ satisfy Formula 4: y = b*sinθ - a*cosθ.

[0122] The following describes the method for measuring overlay error provided in the embodiments of this disclosure.

[0123] The method for measuring overprinting error can be used to measure the overprinting error of the overprinting mark 101 in the above embodiment.

[0124] See Figure 11 The measurement method may include:

[0125] S100: Provide an overlay mark for a semiconductor structure, the semiconductor structure including a substrate, the overlay mark being located on the substrate, the overlay mark including a first pattern layer and a second pattern layer, the first pattern layer and the second pattern layer being formed in different patterning processes, the orthographic projections of the first pattern layer and the second pattern layer on the substrate not overlapping; both the first pattern layer and the second pattern layer include a plurality of marks spaced apart, at least a portion of the marks having extension directions that intersect with the spacing direction; each mark includes a plurality of sub-marks, in the same mark, the ends of the extension directions of the plurality of sub-marks are located at the ends of the extension direction of the mark.

[0126] First, an overlay mark 101 is provided in the above embodiments. The overlay mark 101 can be used in a semiconductor structure 100, which may include a substrate. The overlay mark 101 may be located on the substrate. The overlay mark 101 may include a first patterning layer 110 and a second patterning layer 120, which are formed in different patterning processes. The first patterning layer 110 and the second patterning layer 120 may be protrusions, trenches, or ion implantation regions disposed in the dicing area. The orthographic projections of the first patterning layer 110 and the second patterning layer 120 on the substrate do not overlap, thereby facilitating the measurement of overlay errors.

[0127] See Figure 2 and Figure 3 Both the first pattern layer 110 and the second pattern layer 120 may include a plurality of spaced-apart marks 130, with at least a portion of the marks 130 having extension directions and spacing directions that intersect each other. See also Figures 6-8 Each mark 130 may include multiple sub-marks 133. In the same mark 130, the two ends of the extension direction of the multiple sub-marks 133 can be located at the two ends of the extension direction of the mark 130. This can avoid the ends of the extension direction of the sub-marks 133 interfering with the image accuracy of the mark 130 along the two sides perpendicular to the extension direction of the mark 130. This makes the accuracy of the acquired signal of the two sides perpendicular to the extension direction of the mark 130 higher, thereby ensuring the measurement accuracy of the overlay error and improving the product yield and productivity.

[0128] S200: Obtain images of the first pattern layer and the second pattern layer.

[0129] Images of the first pattern layer 110 and the second pattern layer 120 can be acquired using an overlay measurement device. Exemplary overlay measurement devices may include, but are not limited to, scanning electron microscopes (SEM), atomic force microscopes (AFM), scanning transmission electron microscopes (STM), or optical microscopes.

[0130] S300: Extract the grayscale signals of the images of the first pattern layer and the second pattern layer.

[0131] After acquiring images of the first pattern layer 110 and the second pattern layer 120 using the overlay measurement device, the grayscale analysis of the images of the first pattern layer 110 and the second pattern layer 120 may be performed using the overlay measurement device, for example, see Figure 6 and Figure 7 This allows for the extraction of grayscale signals from a portion of the image (i.e., the analysis region D), thereby improving the efficiency of grayscale analysis. Furthermore, based on the grayscale analysis, the image pixels of the first pattern layer 110 and the second pattern layer 120 are converted into waveforms S.

[0132] S400: Obtain the overlay error of the first pattern layer and the second pattern layer based on the grayscale signal.

[0133] After acquiring waveform S, the process may include acquiring the positions of the peaks and troughs in waveform S, obtaining the center line of the image from the positions of the peaks and troughs, and confirming the overlay error of the first pattern layer and the second pattern layer based on the position offset of the center line.

[0134] The following explanation uses the example of obtaining the first set of etching errors by dividing the first mark group 131a into two within the same pattern layer. (See also...) Figure 12In the first pattern layer 110, analysis regions D1 and D2 can be selected on the patterns of the two first mark groups 131a. Along the extension direction perpendicular to the first mark 131, grayscale signals of multiple first marks 131 in analysis region D1 are extracted and converted into waveform S1. Similarly, along the extension direction perpendicular to the first mark 131, grayscale signals of multiple first marks 131 in analysis region D2 are extracted and converted into waveform S2. Then, the center line O1 of the two first mark groups 131a is obtained based on waveforms S1 and S2. Likewise, in the second pattern layer 120, analysis regions D3 and D4 can be selected on the patterns of the two first mark groups 131a. Along the extension direction perpendicular to the first mark 131, grayscale signals of multiple first marks 131 in analysis region D3 are extracted and converted into waveform S3. Along the extension direction perpendicular to the first mark 131, grayscale signals of multiple first marks 131 in the analysis area D4 are extracted and converted into waveform S4. Then, the center line O2 of the two first mark groups 131a is obtained according to waveform S3 and waveform S4. Then, the relative displacement between the center line O1 and the center line O2 is obtained, which is the first overlay error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the first mark 131.

[0135] The center lines O1 and O2 may have a preset difference, which can be the difference between the first pattern layer 110 and the second pattern layer 120 when the first alignment error is 0 (i.e., there is no first alignment error and they are perfectly aligned). The measured difference between the center lines O1 and O2 along the extension direction perpendicular to the first mark 131 minus the preset difference equals the relative displacement between the center lines O1 and O2.

[0136] Similarly, when obtaining the second overlay error by using two second mark groups 132a within the same pattern layer, the relative displacement between the center lines of the two second mark groups 132a in the first pattern layer 110 and the center lines of the two second mark groups 132a in the second pattern layer 120 can be obtained to determine the second overlay error of the first pattern layer 110 and the second pattern layer 120 along the extension direction perpendicular to the second mark 132a. The principle is the same as that for obtaining the first overlay error and will not be elaborated further. The overlay error of the first pattern layer 110 and the second pattern layer 120 can be used to reflect the alignment accuracy of the third and fourth pattern layers.

[0137] Figure 13 In the related art, in the same mark 230, the two ends of the extension direction of a plurality of sub-marks 233 are located on both sides perpendicular to the extension direction of mark 230. Figure 14A schematic diagram of the overlay error of N overlay marks on a semiconductor structure 200, which is related to the measurement technique, is shown. Figure 15 As shown in this embodiment of the present disclosure, in the same mark 130, the two ends of the extension direction of a plurality of sub-marks 133 are all located at the two ends of the extension direction of mark 130. Figure 16 A schematic diagram showing the overlay error of N overlay marks 101 on a semiconductor structure 100 of an embodiment of the present disclosure is illustrated. Figure 14 and Figure 16 In the diagram, Mean represents the average overlay error of N overlay marks, and Sigma represents the average standard deviation. Each point in the diagram represents an overlay mark, and the length and direction of the line connecting the points (i.e., overlay marks) represent the magnitude and direction of the overlay error of that mark. M3S represents the Mean value + 3 * Sigma value, and the alignment accuracy of the overlay marks can be determined by the M3S value. N is a positive integer greater than or equal to 1.

[0138] contrast Figure 14 and Figure 16 In related technologies, the M3S values ​​for the first and second directions obtained are 6.2368 and 7.0727, respectively, and the residual values ​​after model correction are relatively large. In the embodiments of this disclosure, the M3S values ​​for the first and second directions obtained are 2.7749 and 1.8408, respectively, and the residual values ​​after model correction are relatively small. Therefore, the alignment accuracy of the overlay marks provided in the embodiments of this disclosure is high, which is beneficial to the product yield and production rate.

[0139] It should be noted that the numerical values ​​and ranges involved in the embodiments of this disclosure are approximate values. Due to the influence of the manufacturing process, there may be a certain range of errors, which can be considered negligible by those skilled in the art.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An overlay mark for a semiconductor structure, the semiconductor structure including a substrate, the overlay mark being located on the substrate, characterized in that, The overlay mark includes: a first pattern layer and a second pattern layer, the first pattern layer and the second pattern layer are formed in different patterning processes, and the orthographic projections of the first pattern layer and the second pattern layer on the substrate do not overlap; Both the first pattern layer and the second pattern layer include a plurality of marks spaced apart, and at least a portion of the marks extend in directions that intersect with the spacing direction; Each of the aforementioned marks includes multiple sub-markers, and in the same mark, the two ends of the extension direction of the multiple sub-markers are located at the two ends of the extension direction of the mark; The semiconductor structure includes a third patterning layer and a fourth patterning layer. The third patterning layer and the first patterning layer are formed in the same patterning process, and the fourth patterning layer and the second patterning layer are formed in the same patterning process. Both the third patterning layer and the fourth patterning layer are located on the substrate of the chip region, and the overlay mark is located on the substrate of the first dicing region and / or the second dicing region. The third pattern layer or the fourth pattern layer forms multiple active regions in each of the chip regions, and the extension direction of the first mark is the same as the extension direction of the active region; And / or, in the same mark, the extension direction of a plurality of sub-marks is the same as the extension direction of the mark, and the plurality of sub-marks are spaced apart; The plurality of marks include a plurality of second marks, all of which are spaced apart along a second direction, and the extension direction of the plurality of second marks is different from the second direction; The extension directions of the plurality of second marks intersect perpendicularly with the extension direction of the first mark; Along the extension direction of the second mark, there is an overprinting error a between the first mark of the first pattern layer and the first mark of the second pattern layer; along the extension direction of the first mark, there is an overprinting error b between the second mark of the first pattern layer and the second mark of the second pattern layer. Along the first direction, there is an overlay error x between the first pattern layer and the second pattern layer; along the second direction, there is an overlay error y between the first pattern layer and the second pattern layer; the extension direction of the first mark has an angle θ with the first direction; the first direction and the second direction are perpendicular to each other; The x, a, b, and θ satisfy the formula: x = b * cosθ + a * sinθ; The y, a, b, and θ satisfy the formula: y = b*sinθ - a*cosθ.

2. The overprinting mark according to claim 1, characterized in that, The plurality of marks include a plurality of first marks, the plurality of first marks being spaced apart along a first direction, and the extension direction of the plurality of first marks intersecting the first direction at an angle; The semiconductor structure includes a plurality of first dicing regions and a plurality of second dicing regions. The plurality of first dicing regions extend along a first direction and are spaced apart along a second direction. The plurality of second dicing regions extend along the second direction and are spaced apart along the first direction. The plurality of first dicing regions and the plurality of second dicing regions intersect each other and define a plurality of chip regions.

3. A semiconductor structure, characterized in that, It includes a substrate and an overlay mark as described in any one of claims 1-2, wherein the overlay mark is located on the substrate.

4. A method for measuring the overprinting error of the overprinting mark according to any one of claims 1-2, characterized in that, An overlay mark is provided for a semiconductor structure, the semiconductor structure including a substrate, the overlay mark being located on the substrate, the overlay mark including a first patterning layer and a second patterning layer, the first patterning layer and the second patterning layer being formed in different patterning processes, the orthographic projections of the first patterning layer and the second patterning layer on the substrate not overlapping; both the first patterning layer and the second patterning layer include a plurality of marks spaced apart, at least a portion of the marks having extension directions intersecting the spacing directions; each mark includes a plurality of sub-marks, in the same mark, the ends of the extension directions of the plurality of sub-marks being located at the ends of the extension direction of the mark; Obtain images of the first pattern layer and the second pattern layer; Extract the grayscale signals of the images of the first pattern layer and the second pattern layer; The overlay error between the first pattern layer and the second pattern layer is obtained based on the grayscale signal.

Images