A method of overlay error measurement, a semiconductor process method and a semiconductor structure

Abstract

The application provides an overlay error measurement method, a semiconductor process method and a semiconductor structure. The measurement method comprises: providing a structure to be measured, which comprises a lower structure layer, an intermediate structure layer and an upper structure layer; the lower structure layer comprises a first hole filled with a first material; the upper structure layer comprises a groove filled with a photoetching layer, and the photoetching layer comprises a second hole formed by exposure and development; the three structure layers are respectively provided with corresponding overlay marks; and the overlay error between adjacent structure layers is obtained by simultaneously exposing and imaging the positions of corresponding overlay coordinates of the three structure layers according to the overlay marks. The overlay pattern is obtained by simultaneously imaging the same overlay coordinates of the three structure layers, the delay time of transferring and positioning required for measuring adjacent overlay patterns twice is saved, the process efficiency is improved, the interference of variables introduced by measuring the overlay patterns of different overlay coordinates twice on the overlay error is reduced, and the product yield is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a method for measuring overlay error, a semiconductor process method and a semiconductor structure. BACKGROUND

[0002] Damascene is a process for forming a metal interconnection pattern, which forms a hole in a medium first, then deposits copper in the hole, and finally performs chemical mechanical planarization to obtain the desired metal interconnection pattern, so that copper can replace aluminum as the interconnection material to reduce resistivity, improve reliability, and increase the rate of forming copper interconnection pattern. Dual Damascene is a process that uses Damascene to form a via for connecting metal patterns and a trench above the via for placing metal patterns. It is divided into three methods: Trench First, Via First, and Self Aligned. The Trench First method first forms a trench in the medium layer on the lower metal, then sets a photoresist in the trench, exposes and develops the photoresist, and etches the medium layer downward to form a hole that exposes the lower metal, and then fills the hole and the trench with upper metal.

[0003] However, in order to ensure that the position of the formed hole is aligned with the lower metal and the upper metal, and to ensure the effectiveness of the electrical connection of the metal interconnection, the overlay pattern of the photoresist formed after exposure and development of the photoresist needs to be measured with the lower metal and the upper trench to obtain the overlay error between the photoresist pattern and the lower metal and the upper trench.

[0004] In the prior art, it is customary to first measure the overlay pattern of the lower metal and the photoresist, and then measure the overlay pattern of the photoresist and the upper trench. In this process, two imaging is needed at two coordinate positions to obtain two overlay patterns, so the structure layer confusion during imaging increases the possibility of obtaining incorrect overlay patterns. At the same time, the transfer and repositioning process between the two coordinate positions also takes more time, and introduces variables in the obtained overlay error due to different exposure positions of the photoresist after exposure and development.

[0005] Therefore, there is an urgent need for a method for measuring the overlay error of the photoresist pattern formed by via in the Trench First process, which can improve the measurement efficiency and reduce the influence of irrelevant variables in the measurement.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of those skilled in the art, and the above technical scheme cannot be considered as known to those skilled in the art only because it is described in the part of the background of the present application. SUMMARY

[0007] In view of the above disadvantages of the prior art, the purpose of the present application is to provide a method for measuring overlay error, a semiconductor process method and a semiconductor structure, which are used to solve the problems of low efficiency and low accuracy of measuring overlay error in the prior art.

[0008] To achieve the above purpose, the present application provides a method for measuring overlay error, which comprises the following steps:

[0009] providing a structure to be measured, which comprises, from bottom to top, a lower structure layer, an intermediate structure layer and an upper structure layer, wherein the lower structure layer contains a first hole filled with a first material, the upper structure layer comprises a groove filled with a photoetching layer, and the photoetching layer comprises a second hole formed by exposure and development, which is located at a position corresponding to the first hole and exposes part of the intermediate structure layer through the photoetching layer;

[0010] The structure to be measured has a preset overlay coordinate, which is arranged in correspondence with a preset position of the second hole to be measured, and the lower structure layer has a first overlay mark arranged at a position corresponding to the overlay coordinate, the photoetching layer has a second overlay mark arranged at a position corresponding to the overlay coordinate, and the upper structure layer has a third overlay mark arranged at a position corresponding to the overlay coordinate.

[0011] The position of the overlay coordinate is determined according to any one of the first overlay mark, the second overlay mark or the third overlay mark, the lower structure layer, the photoetching layer and the upper structure layer are confirmed according to the first overlay mark, the second overlay mark and the third overlay mark, and the lower structure layer, the photoetching layer and the upper structure layer at the position corresponding to the overlay coordinate are simultaneously exposed and imaged to obtain a common overlay pattern; in the common overlay pattern, the distance between the pattern profile of the first hole of the lower structure layer and the second hole to be measured of the photoetching layer is a first overlay error, and the distance between the pattern profile of the second hole to be measured of the photoetching layer and the groove of the upper structure layer is a second overlay error; the imaging information in the common overlay pattern obtained by exposure and imaging is processed to obtain the first overlay error and the second overlay error.

[0012] Optionally, the lower structure layer comprises a first dielectric layer, the first hole is located in the first dielectric layer, the first material is a first metal, and the first metal fills the first hole; the middle structure layer comprises a second dielectric layer; and the upper structure layer comprises a third dielectric layer, and the groove is located in the third dielectric layer.

[0013] Optionally, the first dielectric layer, the second dielectric layer and the third dielectric layer are made of the same material.

[0014] Optionally, the to-be-measured structure has two or more preset overlay coordinates, different overlay coordinates correspond to different preset positions of the second hole to be measured, and exposure imaging is performed on each overlay coordinate to obtain a common overlay pattern, and each common overlay pattern is processed to obtain a first overlay error and a second overlay error.

[0015] Optionally, each overlay coordinate is uniformly distributed around the center axis of the second hole to be measured.

[0016] Optionally, the to-be-measured structure is manufactured by a process with a size of 28 nm or less.

[0017] The application further provides a semiconductor process method, which comprises:

[0018] A1: measuring the first overlay error and the second overlay error of the to-be-measured structure by using any one of the overlay error measurement methods described above;

[0019] A2: determining whether the first overlay error and the second overlay error are within a preset error range; when the first overlay error and the second overlay error are both within the preset error range, etching the middle structure layer through the second hole to be measured of the photoetching layer to form a through hole in the middle structure layer, and the through hole exposes the first material in the first hole; when the first overlay error or the second overlay error is outside the preset error range, removing the original photoetching layer, re-forming a photoetching layer, calculating an overlay error compensation value through the first overlay error and the second overlay error, adjusting the exposure position and range of the photoetching layer through the overlay error compensation value to adjust the position and critical dimension of the second hole to be measured obtained by exposure and development of the re-formed photoetching layer, obtaining a new to-be-measured structure, and returning to step A1.

[0020] Optionally, after forming the via in step A2, a second material is filled into the via, the second material filling the via of the intermediate structure layer and the trench of the upper structure layer, so that the first material in the first hole and the second material in the via and the trench form effective electrical connection.

[0021] The present application also provides a semiconductor structure prepared by any one of the semiconductor process methods described above, the semiconductor structure comprising a lower structure layer, an intermediate structure layer and an upper structure layer; the lower structure layer comprising a first hole, the first hole being filled with a first material; the intermediate structure layer being provided with a via, the via exposing the first material in the first hole; the upper structure layer being provided with a trench, the bottom of the trench exposing the via.

[0022] Optionally, the lower structure layer comprises a first dielectric layer, the first hole being located in the first dielectric layer, the first material being a first metal, the first metal being filled in the first hole; the intermediate structure layer comprising a second dielectric layer, the second dielectric layer being provided with the via, the via exposing the first metal in the first hole; the upper structure layer comprising a third dielectric layer, the third dielectric layer being provided with the trench; the trench and the via being provided with a second material, the second material being a second metal, the second metal in the trench and the via and the first metal in the first hole forming effective electrical connection.

[0023] As described above, the overlay error measurement method, the semiconductor process method and the semiconductor structure of the present application have the following beneficial effects:

[0024] The present application simultaneously images the overlay patterns of the three-layer structure by the same overlay coordinates, thus saving the delay time of transferring and positioning required for measuring adjacent overlay patterns twice, improving the process efficiency; at the same time, reducing the interference of variables introduced by measuring the overlay patterns of different overlay coordinates twice on the overlay error, which is conducive to improving the product yield. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A structural schematic diagram showing the structure to be measured in step 1 of the overlay error measurement method of the embodiment 1 of the present application.

[0026] Figure 2 A structural schematic diagram showing the overlay pattern obtained in the prior art.

[0027] Figure 3 A structural schematic diagram showing the overlay pattern of the second hole in the prior art.

[0028] Figure 4A structure diagram showing the difference of the pattern after exposure and development of the photoetching layer in the prior art.

[0029] Figure 5 A structure diagram showing the common overlay pattern obtained in the overlay error measurement method of the embodiment 1 of the present application.

[0030] Figure 6 A structure diagram showing the common overlay pattern obtained in an example of the overlay error measurement method of the embodiment 1 of the present application.

[0031] Figure 7 A structure diagram showing the structure of the structure to be measured in an example of the overlay error measurement method of the embodiment 1 of the present application.

[0032] Element number explanation

[0033] 11, lower structure layer; 111, first hole; 112, first material; 12, intermediate structure layer; 13, upper structure layer; 131, trench; 132, photoetching layer; 133, second hole; 14, first overlay pattern; 15, second overlay pattern; 16, common overlay pattern;

[0034] 21, first dielectric layer; 211, first metal; 22, second dielectric layer; 23, third dielectric layer. DETAILED DESCRIPTION

[0035] The above description is only used to explain the present application and not intended to limit the present application. The present application can be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.

[0036] In the detailed description of the embodiments of the present application, the schematic diagrams showing the structures of the devices are partially enlarged without the general scale for the convenience of description, and the schematic diagrams are only examples which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions including length, width and depth should be included in the actual manufacture.

[0037] For the convenience of description, the spatial relationship words such as "under", "below", "lower than", "under", "above", "upper" and the like can be used to describe the relationship of one element or feature with other elements or features shown in the drawings. It should be understood that these spatial relationship words are intended to include the other directions of the device in use or operation in addition to the directions depicted in the drawings.

[0038] In the context of the present application, a structure described as being "on" a second feature "over" a first feature can include embodiments in which the first and second features form direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features can not be in direct contact.

[0039] It should be noted that the diagrams provided in the embodiments are only schematic and that for purposes of explanation of the basic idea of the application, only the components relevant to the application are shown in the diagrams, not the number, shape and size of the components as they are in actual implementation. The shapes, number and proportions of the components in actual implementation can be changed arbitrarily, and the layout pattern of the components can be more complex.

[0040] Embodiment 1:

[0041] The application provides a method for measuring overlay error, which comprises the following steps:

[0042] Step 1: providing a structure to be measured, which comprises, from bottom to top, a lower structure layer, an intermediate structure layer and an upper structure layer, wherein the lower structure layer contains a first hole filled with a first material, and the upper structure layer comprises a groove filled with a photoetching layer, and the photoetching layer comprises a second hole formed by exposure and development, the second hole is located at a position corresponding to the first hole, and the second hole penetrates through the photoetching layer to expose part of the intermediate structure layer;

[0043] Step 2: the structure to be measured has a preset overlay coordinate; the overlay coordinate is arranged in correspondence with a preset position of the second hole to be measured; a first overlay mark is arranged on the lower structure layer at a position corresponding to the overlay coordinate; a second overlay mark is arranged on the photoetching layer at a position corresponding to the overlay coordinate; and a third overlay mark is arranged on the upper structure layer at a position corresponding to the overlay coordinate.

[0044] Step 3: Determine the position of the overlay coordinates based on any one of the first overlay mark, the second overlay mark, or the third overlay mark; confirm the lower structural layer, the photolithography layer, and the upper structural layer based on the first overlay mark, the second overlay mark, and the third overlay mark; simultaneously expose and image the lower structural layer, the photolithography layer, and the upper structural layer at the position corresponding to the overlay coordinates to obtain a common overlay pattern; in the common overlay pattern, the pattern contour distance between the first hole in the lower structural layer and the second hole to be measured in the photolithography layer is the first overlay error, and the pattern contour distance between the second hole to be measured in the photolithography layer and the groove in the upper structural layer is the second overlay error; process the imaging information in the common overlay pattern obtained by exposure imaging to obtain the first overlay error and the second overlay error.

[0045] The overlay error measurement method of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of the overlay error measurement method protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0046] First, proceed to step 1, as follows: Figure 1 As shown, a structure to be measured is provided. The structure to be measured includes, from bottom to top, a lower structural layer 11, an intermediate structural layer 12, and an upper structural layer 13. The lower structural layer 11 includes a first hole 111, which is filled with a first material 112. The upper structural layer 13 includes a trench 131, which is filled with a photolithography layer 132. The photolithography layer 132 includes a second hole 133 formed by exposure and development. The second hole 133 is located at a position corresponding to the first hole 111 and penetrates the photolithography layer 132 to expose a portion of the intermediate structural layer 12.

[0047] In one embodiment, the structure to be measured is fabricated using a process of less than or equal to 28 nanometers.

[0048] When used in process technologies of 28 nanometers or less, this invention provides a higher accuracy in measuring overlay errors than existing technologies, thus meeting the accuracy requirements for overlay error measurement at even smaller linewidths and spacings. Specifically, this invention can also be used to measure the overlay errors of structures under test in other process technologies.

[0049] Then, step 2 is performed, the structure to be measured has preset overlay coordinates; the overlay coordinates are arranged in correspondence with the preset positions of the second holes 133 to be measured; the first overlay mark is arranged on the position of the lower structure layer 11 corresponding to the overlay coordinates, the second overlay mark is arranged on the position of the photoetching layer 132 corresponding to the overlay coordinates, and the third overlay mark is arranged on the position of the upper structure layer 13 corresponding to the overlay coordinates.

[0050] Finally, step 3 is performed, the position of the overlay coordinates is determined according to any one of the first overlay mark, the second overlay mark or the third overlay mark, the lower structure layer 11, the photoetching layer 132 and the upper structure layer 13 are confirmed according to the first overlay mark, the second overlay mark and the third overlay mark, and the lower structure layer 11, the photoetching layer 132 and the upper structure layer 13 corresponding to the overlay coordinates are simultaneously exposed and imaged to obtain a common overlay pattern 16; in the common overlay pattern 16, the distance between the first hole 111 of the lower structure layer 11 and the second hole 133 to be measured of the photoetching layer 132 is the first overlay error, and the distance between the second hole 133 to be measured of the photoetching layer 132 and the groove 131 of the upper structure layer 13 is the second overlay error; the imaging information in the common overlay pattern 16 obtained by exposure and imaging is processed to obtain the first overlay error and the second overlay error.

[0051] In the prior art, when the overlay error of the upper structure layer 13 and the lower structure layer 11 of the intermediate structure layer 12 needs to be measured, the first overlay pattern 14 shown in FIG. 1A and the second overlay pattern 15 shown in FIG. 1B are generally obtained by two times of imaging respectively, which include the second hole 133 to be measured of the photoetching layer 132 and the first hole 111 of the lower structure layer 11, and the second hole 133 to be measured of the photoetching layer 132 and the groove 131 of the upper structure layer 13. Figure 2 However, in the measurement process, the corresponding structure layer is positioned by searching for the overlay mark of the corresponding structure layer, and when the overlay marks on different structure layers are close, overlapping and confusion may occur, resulting in the problem of finding wrong overlay marks and measuring wrong structure layers during imaging. When two times of imaging are performed respectively, the risk of measurement error is further increased, and the accuracy of overlay error measurement is further reduced. Meanwhile, as shown in FIG. 1A and FIG. 1B, Figure 3As shown, the 8 overlay coordinates of the second hole 133 of the photoetching layer 132 are imaged to form overlay patterns, each group of overlay patterns includes the first overlay pattern 14 of the photoetching layer 132 and the lower structure layer 11 and the second overlay pattern 15 of the photoetching layer 132 and the upper structure layer 13, and the structure layer of different layers needs to be transferred and positioned to form the overlay pattern during the imaging between the two times, and the process of repositioning and the step of re-imaging also need to take more time, resulting in low measurement efficiency; in addition, the corresponding structures on the upper structure layer 13 and the lower structure layer 11 need to be imaged during the two times of imaging, so that the coordinate positions exposed during the two times of imaging are difficult to ensure completely the same, and the exposure light source directions of different positions of the photoetching layer 132 are different during the exposure and development of the photoetching layer 132, for example Figure 4 As shown, the photoetching layer 132 is placed on the middle structure layer 12, and the size of the pattern obtained after the exposure and development of the photoetching layer 132 will have an uncertain size region ΔL according to the different exposure directions, causing the patterns of the photoetching layer 132 at different positions after the exposure and development to have differences, and when imaging at different coordinate positions, the imaging positions of the second hole 133 of the photoetching layer 132 located on the upper structure layer 13 will have differences, resulting in differences in the patterns of the second hole 133 of the imaging, so that the overlay error OL obtained by the final measurement introduces irrelevant variables caused by the different patterns of different positions of the photoetching layer 132, reduces the reliability of the overlay error, and it is difficult to obtain a yield-stable product.

[0052] The present application simultaneously images three structure layers at the same overlay coordinate to obtain a common overlay pattern 16, as shown in the figure Figure 5 As shown, the common overlay pattern 16 includes the trench 131 of the upper structure layer 13, the second hole 133 to be measured of the photoetching layer 132, and the first hole 111 of the lower structure layer 11, so that the overlay errors of the adjacent two layers of the three structure layers can be measured in one overlay pattern, without the need to image twice to measure the overlay errors of the two groups of adjacent two layers of structure layers, thereby saving the time of transferring and positioning for imaging the two overlay coordinates during the two times of imaging and the time of re-imaging, greatly improving the measurement efficiency; at the same time, since only one imaging is needed, the risk of measuring the wrong structure layer caused by the confusion of the marks is reduced; in addition, since the common overlay pattern 16 is the overlay error of the three structure layers imaged at one overlay coordinate, the difference variable of the patterns of different positions of the photoetching layer 132 will not be introduced, so that the reliability of the overlay error can be improved, and the stability of the product yield can be improved.

[0053] Specifically, the first overlay mark, the second overlay mark and the third overlay mark are used to distinguish the lower structure layer 11, the photoetching layer 132 and the upper structure layer 13, so as to determine the structure layer for exposure imaging; meanwhile, the position of the overlay coordinate can be determined by searching any one of the first overlay mark, the second overlay mark or the third overlay mark, so as to determine the accurate position for exposure imaging.

[0054] In one embodiment, one initial mark is arranged at each of the four top corners of the structure to be measured, and the initial mark can be used to determine the rough position of the second hole 133 to be measured; before the position of the overlay coordinate is determined by any one of the first overlay mark, the second overlay mark or the third overlay mark, the rough position of the second hole 133 to be measured is first positioned by the initial mark, and then the overlay coordinate is accurately positioned by any one of the first overlay mark, the second overlay mark or the third overlay mark at the position of the second hole 133 to be measured.

[0055] In one embodiment, the structure to be measured has two or more preset overlay coordinates, and different overlay coordinates correspond to different preset positions of the second hole 133 to be measured, and exposure imaging is performed on each overlay coordinate to obtain a common overlay pattern 16, and each common overlay pattern 16 is processed to obtain a first overlay error and a second overlay error.

[0056] According to the present application, the overlay errors at different positions can be measured, so that more accurate overlay error compensation values can be calculated subsequently, and the position and size accuracy of the subsequent through holes can be improved.

[0057] In one embodiment, the structure to be measured has 4-12 preset overlay coordinates.

[0058] According to the present application, at least four overlay coordinates are arranged to be arranged on four sides of the through hole, and at most 12 overlay coordinates are arranged, so that the overlay error measurement at multiple positions is ensured while the measurement workload is avoided, and the balance between work efficiency and measurement reliability is achieved. Specifically, other numbers of overlay coordinates can also be arranged according to requirements.

[0059] In one embodiment, the structure to be measured has eight preset overlay coordinates, as shown in FIG. 8, and exposure imaging is performed on each overlay coordinate to obtain a common overlay pattern 16. Figure 6

[0060] ​In one embodiment, each of the overlay coordinates is uniformly distributed around the center axis of the second hole 133 to be measured, as shown in Figure 6 The imaging of each of the overlay coordinates obtains a common overlay pattern 16.

[0061] The present application reduces the random error value of overlay error measurement by uniformly distributing a plurality of overlay coordinates.

[0062] In one embodiment, as shown in Figure 7 In the structure to be measured, the lower structure layer 11 includes a first dielectric layer 21, the first hole 111 is located in the first dielectric layer 21, the first material 112 is a first metal 211, and the first metal 211 fills the first hole 111; the intermediate structure layer 12 includes a second dielectric layer 22; and the upper structure layer 13 includes a third dielectric layer 23, and the trench 131 is located in the third dielectric layer 23.

[0063] In the prior art, when the Trench First process is used in the double damascene process, overlay error measurement needs to be performed on the photoresist pattern (second hole 133) forming the via and the trench 131 of the upper structure layer 13 and the first hole 111 of the lower structure layer 11. When the overlay error is within the error range, the correct hole position and size can be obtained through the photoresist. If the overlay error is outside the error range, the overlay compensation value needs to be calculated based on the obtained overlay error, the exposure position or range of the photoresist needs to be adjusted, the original photoresist needs to be removed, and new photoresist needs to be formed for new exposure and development to obtain a via with correct position and size to meet the pattern requirements of metal interconnection. However, when the overlay error is measured by imaging twice, the aforementioned problems of long measurement time and many factors affecting the measurement result also occur, which leads to the final failure to obtain a via with correct position.

[0064] The present application applies the foregoing scheme to the overlay error between the second hole 133 of the photoresist layer 132 to be measured and the trench 131 of the upper metal pattern and the first hole 111 of the lower metal pattern when the via is formed in the Trench First process in the double damascene process. This structure is the most common application scenario in semiconductor processes that require overlay error measurement of the photoresist layer 132 and the upper structure layer 13 and the lower structure layer 11, and is also the application scenario of the technical problem discovered by the present application. Specifically, the scheme of the present application can also be applied to non-Trench First processes that require overlay error measurement of three adjacent structure layers, which are within the protection scope of the present application.

[0065] In one embodiment, the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23 are made of the same material.

[0066] The present application makes the materials of the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23 the same, so that the adhesion between the structures is better, the structural reliability is stronger, the resolution obtained by simultaneous imaging when measuring overlay error is higher, and the overlay error measurement result is more accurate.

[0067] In one embodiment, the first dielectric layer 21, the second dielectric layer 22, and the third dielectric layer 23 are made of SiCOH or SiCN and other suitable dielectric materials or a combination thereof.

[0068] Embodiment 2:

[0069] The present embodiment provides a semiconductor process method, which comprises:

[0070] A1: using any one of the overlay error measurement methods in embodiment 1 to measure the first overlay error and the second overlay error of the to-be-measured structure;

[0071] A2: determining whether the first overlay error and the second overlay error are within a preset error range; when the first overlay error and the second overlay error are both within the preset error range, etching the intermediate structure layer through the second hole of the photoresist layer to be measured to form a via in the intermediate structure layer, the via exposing the first material in the first hole; when the first overlay error or the second overlay error is outside the preset error range, removing the original photoresist layer, re-forming a photoresist layer, calculating an overlay error compensation value from the first overlay error and the second overlay error, adjusting the exposure position and range of the photoresist layer through the overlay error compensation value to adjust the position and critical dimension of the second hole to be measured obtained by exposure and development of the re-formed photoresist layer, obtaining a new to-be-measured structure, and returning to step A1.

[0072] The present application improves the overall efficiency of the semiconductor process method and the yield of the products obtained by the process by using the measurement result obtained by the overlay error measurement method in embodiment 1 to inspect or adjust the position of the second hole to be measured of the photoresist layer.

[0073] In one embodiment, after forming the via in step A2, a second material is filled in the via, the second material filling the via of the intermediate structure layer and the trench of the upper structure layer, so that the first material in the first hole and the second material in the via and the trench form an effective electrical connection.

[0074] The application measures the overlay error of the second hole to be measured in the photoetching layer for preparing the through hole and the first hole and the trench of the upper and lower structure layers by the foregoing scheme, ensures the alignment between the through hole and the trench and the first hole, and thus ensures the conductive connection between the first material and the second material.

[0075] Embodiment 3

[0076] The semiconductor structure is prepared by any one of the semiconductor process methods in Embodiment 2, and comprises a lower structure layer, an intermediate structure layer and an upper structure layer; the lower structure layer comprises a first hole, and the first hole is filled with a first material; the intermediate structure layer is provided with a through hole, and the through hole exposes the first material in the first hole; and the upper structure layer is provided with a trench, and the bottom of the trench exposes the through hole.

[0077] The semiconductor process method in Embodiment 2 greatly improves the alignment degree of the prepared through hole, the trench and the first hole.

[0078] In one embodiment, the lower structure layer comprises a first dielectric layer, and the first hole is located in the first dielectric layer; the first material is a first metal, and the first metal is filled in the first hole; the intermediate structure layer comprises a second dielectric layer, and the second dielectric layer is provided with the through hole, and the through hole exposes the first metal in the first hole; the upper structure layer comprises a third dielectric layer, and the third dielectric layer is provided with the trench; the trench and the through hole are provided with a second material, the second material is a second metal, and the second metal in the trench and the through hole forms an effective electrical connection with the first metal in the first hole.

[0079] The foregoing scheme improves the alignment degree of the through hole, the trench and the first hole, thereby ensuring the conductive connection between the first metal and the second metal, and is beneficial to improving the yield reliability of the semiconductor structure.

[0080] In summary, the overlay error measurement method, the semiconductor process method and the semiconductor structure can simultaneously image the overlay pattern by imaging the same overlay coordinates of the three-layer structure, save the delay time of transferring and positioning required for measuring adjacent overlay patterns twice, improve the process efficiency, reduce the interference of variables introduced by measuring the overlay patterns of different overlay coordinates twice on the overlay error, and are beneficial to improving the product yield.

[0081] Therefore, the application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0082] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A method of overlay error measurement, the method comprising: The overlay error measurement method comprises: The structure to be measured comprises, from bottom to top, a lower structure layer, an intermediate structure layer and an upper structure layer, the lower structure layer contains a first hole filled with a first material, the upper structure layer comprises a trench filled with a photoetching layer, the photoetching layer comprises a second hole formed by exposure and development, the second hole is located at a position corresponding to the first hole, and the second hole exposes part of the intermediate structure layer. The structure to be measured has preset overlay coordinates corresponding to the preset positions of the second holes to be measured, the lower structure layer has a first overlay mark at a position corresponding to the overlay coordinates, the photoetching layer has a second overlay mark at a position corresponding to the overlay coordinates, and the upper structure layer has a third overlay mark at a position corresponding to the overlay coordinates. The positions of the overlay coordinates are determined according to any one of the first overlay mark, the second overlay mark or the third overlay mark, the lower structure layer, the photoetching layer and the upper structure layer are confirmed according to the first overlay mark, the second overlay mark and the third overlay mark, and the lower structure layer, the photoetching layer and the upper structure layer at positions corresponding to the overlay coordinates are simultaneously exposed and imaged to obtain a common overlay pattern; in the common overlay pattern, the distance between the first hole of the lower structure layer and the pattern profile of the second hole to be measured of the photoetching layer corresponding to the first hole is a first overlay error, and the distance between the second hole to be measured of the photoetching layer and the trench of the upper structure layer corresponding to the second hole is a second overlay error; and imaging information in the common overlay pattern obtained by exposure and imaging is processed to obtain the first overlay error and the second overlay error.

2. The method of pitch and roll error measurement according to claim 1, wherein, The lower structure layer comprises a first dielectric layer, the first hole is located in the first dielectric layer, the first material is a first metal, and the first metal is filled in the first hole; and the intermediate structure layer comprises a second dielectric layer. The upper structure layer comprises a third dielectric layer, and the trench is located in the third dielectric layer.

3. The method of pitch and roll estimation according to claim 1 or 2, wherein, The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are the same.

4. The method of pitch and roll estimation according to claim 1, wherein, The structure to be measured has two or more preset overlay coordinates, different overlay coordinates correspond to different preset positions of the second holes to be measured, each overlay coordinate is exposed and imaged to obtain a common overlay pattern, and each common overlay pattern is processed to obtain a first overlay error and a second overlay error.

5. The method of pitch and roll estimation according to claim 4, wherein, Each overlay coordinate is uniformly distributed around the center axis of the second hole to be measured.

6. The method of pitch and roll estimation according to claim 1, wherein, The structure to be measured is manufactured by a process with a size of 28 nm or less.

7. A semiconductor process method, comprising: A1: measuring the first overlay error and the second overlay error of the structure to be measured by using the overlay error measurement method according to any one of claims 1-6. A2: judging whether the first overlay error and the second overlay error are within a preset error range; when the first overlay error and the second overlay error are both within the preset error range, etching the intermediate structure layer through the second hole of the photolithography layer to be measured to form a via in the intermediate structure layer, the via exposing the first material in the first hole; when the first overlay error or the second overlay error is outside the preset error range, removing the original photolithography layer, re-forming a photolithography layer, calculating an overlay error compensation value through the first overlay error and the second overlay error, adjusting the exposure position and range of the photolithography layer through the overlay error compensation value to adjust the position and critical dimension of the second hole to be measured obtained by exposing and developing the re-formed photolithography layer, obtaining a new structure to be measured, and returning to step A1.

8. The semiconductor process method of claim 7, wherein, After the via is formed in step A2, a second material is filled in the via, the second material filling the via of the intermediate structure layer and the trench of the upper structure layer, so that the first material in the first hole and the second material in the via and the trench form an effective electrical connection.

9. A semiconductor structure, characterized by The semiconductor structure is prepared by the semiconductor process method of any one of claims 7-8, the semiconductor structure comprising a lower structure layer, an intermediate structure layer and an upper structure layer; the lower structure layer comprising a first hole, the first hole being filled with a first material; the intermediate structure layer being provided with a via, the via exposing the first material in the first hole; the upper structure layer being provided with a trench, the bottom of the trench exposing the via.

10. The semiconductor structure of claim 9, wherein, The lower structure layer comprises a first dielectric layer, the first hole is located in the first dielectric layer, the first material is a first metal, and the first metal is filled in the first hole; the intermediate structure layer comprises a second dielectric layer, the via is provided in the second dielectric layer, and the via exposes the first metal in the first hole; the upper structure layer comprises a third dielectric layer, and the trench is provided in the third dielectric layer; the second material is provided in the trench and the via, the second material is a second metal, and the second metal in the trench and the via forms an effective electrical connection with the first metal in the first hole. The lower structure layer comprises a first dielectric layer, the first hole is located in the first dielectric layer, the first material is a first metal, and the first metal is filled in the first hole; the intermediate structure layer comprises a second dielectric layer, the via is provided in the second dielectric layer, and the via exposes the first metal in the first hole; the upper structure layer comprises a third dielectric layer, and the trench is provided in the third dielectric layer; the second material is provided in the trench and the via, the second material is a second metal, and the second metal in the trench and the via forms an effective electrical connection with the first metal in the first hole.

Images