An image generation system for multi-electron beam lithography equipment and its manufacturing method

Abstract

This invention discloses an image generation system for multi-electron beam lithography equipment and its manufacturing method. The image generation system is the core component, capable of deflecting the electron beam incident through an aperture, redirecting the focused electron beam to different positions to achieve exposure at different points within a write field. Through a control chip and transmission lines, different voltages are applied to the top metal electrode of the image generation system. The top electrode is connected to the sidewall electrodes; by adjusting the voltage applied to the top electrode, the voltage of the sidewall electrodes is adjusted to control the electric field strength, thereby achieving functions such as deflection and projection of the incident electron beam, ultimately projecting the beam spot to any position within the write field.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano manufacturing technology, specifically relating to an image generation system for multi-electron beam lithography equipment and its manufacturing method. Background Technology

[0002] The development of advanced node integrated circuit manufacturing technologies at 3nm and below remains the primary solution for addressing the urgent need for high-performance, low-power high-end chips in applications such as AI transformation and digital transformation. Among these technologies, multi-electron-beam parallel lithography, with its advantages of high resolution, high throughput, and low manufacturing cost, is currently the only solution for the mask manufacturing of mass-produced chips at process nodes of 3nm and below, and holds an irreplaceable strategic position.

[0003] In traditional Gaussian beam lithography (GB) equipment, and even deformable beam lithography (combining apertures of different shapes to form a specific beam pattern), the electron optical system is mainly assembled from discrete modules such as electron guns, beam gates, apertures, electron lenses, and deflectors. These discrete and bulky components make it difficult to expand the number of electron beam columns. Therefore, efficiency is insufficient when manufacturing complex mask patterns at 3nm and below. In contrast, multi-electron beam lithography equipment uses MEMS manufacturing technology to integrate beam splitting, focusing, and deflection modules on-chip. Utilizing dedicated MEMS micro-aperture arrays, the number of electron beam columns can be expanded to hundreds, thousands, or even hundreds of thousands of areas, thereby achieving parallel multi-electron beam lithography and significantly improving mask manufacturing efficiency. As one of the core components of multi-electron beam lithography equipment, the image generation system plays a crucial role in deflecting the electron beam within a writing field. It is key to achieving large-scale parallel electron beam lithography and ensuring a beam spot size ≤12nm, necessitating the development of new low-cost, miniaturized, and high-performance device architectures and manufacturing solutions. Summary of the Invention

[0004] The purpose of this invention is to provide an image generation system for multi-electron beam lithography equipment and its manufacturing method. The image generation system includes a substrate (5), a sidewall insulating layer (6), a sidewall electrode diffusion barrier layer (7), a sidewall metal electrode (8), and an electrode (9). The electrode connects to the metal lines via a wiring layer, thereby controlling the sidewall voltage of different vias.

[0005] This invention employs a multi-electron beam lithography image generation system and its manufacturing method. Specifically, it operates by controlling a chip to distribute signals, applying different voltages to different electrodes in different vias, and applying opposite voltages to opposing electrodes to create a potential difference, thereby generating an electric field to deflect the electron beam within the via. The fabrication steps include: patterning the sidewalls of the vias on the front side of the wafer, filling them with metal electrodes, and etching the wafer from the back side. By adjusting the voltage difference, the incident electron beam is deflected, ultimately projecting the beam spot to any position in the write field. The write field size can be flexibly adjusted by controlling the exposure distance, which is beneficial for the miniaturization of the electron optical system.

[0006] An image generation system for multi-electron beam lithography includes an electron gun and collimation system 1, a beam shutter 2, an electron optical system 3, and a multi-electron beam image generation system. The multi-electron beam image generation system is assembled with the electron gun and collimation system 1, beam shutter 2, and electron optical system 3 via a central aperture axis. A high-energy electron beam is emitted from the electron gun, collimated by the collimation system 1, and then focused by the electron optical system 3. A potential difference is created by applying different voltages to the sidewalls of the multi-electron beam image generation system. The electric field generated by this potential difference deflects the focused electron beam, thereby achieving the same electron beam in the same field. The purpose of exposure at different positions; the switching between different writing fields is achieved by moving the workpiece stage; the beam gate 2 is used to control the electron beam exposure switch, which is turned on only when exposure is required; the multi-electron beam image generation system consists of a substrate 5, a substrate front dielectric layer 4, a sidewall insulating layer 6, a sidewall electrode diffusion barrier layer 7, a sidewall metal electrode 8, and a top metal electrode 9; the substrate front dielectric layer 4 is disposed on the substrate 5, the top metal electrode 9 is disposed on the substrate front dielectric layer 4, the side of the substrate 5 is the sidewall metal electrode 8, and the sidewall metal electrode 8 is connected to the substrate 5 through the sidewall electrode diffusion barrier layer 7 and the sidewall insulating layer 6.

[0007] Furthermore, the electron gun collimation system 1, beam gate 2, and electron optical system 3 are matched with the multi-electron beam image generation system, and have the same array combination and the same aperture axis.

[0008] Furthermore, the top metal electrode 9 is connected to an external signal transmission line via a redistribution layer RDL.

[0009] Furthermore, the substrate 5 is a highly doped double-sided polished silicon substrate with a crystal orientation of... <110> Doping concentration > 1e19 / cm 3 Resistivity less than 10 -2 Ω·cm.

[0010] Furthermore, the aperture shaft is divided into square aperture and round aperture according to the shape of the writing field. The voltage applied to the opposite electrode of each electrode is the opposite voltage, and the electron beam is deflected by the electric field generated by the potential difference with the opposite electrode.

[0011] Furthermore, the aperture array is >100×100.

[0012] Furthermore, the hole depth and diameter of the hole shaft are customized according to the deflection voltage requirements; a lower deflection voltage corresponds to a larger hole diameter and a larger hole depth.

[0013] Furthermore, the sidewall metal electrodes 8 and 9 are made of molybdenum, tungsten, aluminum, ruthenium, nickel, or copper.

[0014] The substrate front dielectric layer 4 is made of silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide dielectric insulating layer.

[0015] The sidewall insulating layer material of the image generation system is a polymer, silicon oxide, or silicon nitride;

[0016] The sidewall blocking / adhesive layer material in the image generation system is Ti, Ta, and their compounds.

[0017] A method for manufacturing an image generation system for multi-electron beam lithography equipment includes the following steps:

[0018] S1, Prepare substrate 5, and deposit a dielectric layer on the front side of the substrate using chemical vapor deposition (CVD) or thermal oxidation.

[0019] S2, after depositing the dielectric layer, spin-coating photoresist and patterning it; then using the photoresist as a mask, etching the front dielectric layer 4 of the substrate downwards;

[0020] S3, using the front dielectric layer 4 of the substrate as a mask, the substrate 5 is etched downwards using dry plasma etching;

[0021] S4, using thermal oxidation or chemical vapor deposition (CVD) to deposit a sidewall insulating layer 6 on the sidewall of the etched structure;

[0022] S5, using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to deposit an adhesion layer / barrier layer on the sidewall of the etched sidewall insulating layer 6, wherein the adhesion layer / barrier layer is a sidewall electrode diffusion barrier layer 7.

[0023] S6, use PVD or chemical vapor deposition (CVD) to deposit the seed layer required for electroplating;

[0024] S7, Electrochemically deposited ECD fills the sidewall metal electrode 8, wherein the sidewall metal electrode 8 is a Cu or W metal material;

[0025] S8, chemical mechanical polishing (CMP) removes excess metal and seed / blocking layers until the substrate front dielectric layer 4 is exposed;

[0026] S9, deposit metal onto the top of the wafer to complete the layout and wiring of the metal lines corresponding to different holes and top metal electrodes 9;

[0027] S10, the wafer is flipped over and a substrate front dielectric layer 4 is deposited on its back side as a hard mask;

[0028] S11, using photoresist, align and pattern the front dielectric layer of the substrate from the back side, then use the front dielectric layer of the substrate as a mask to etch silicon holes and etch through the holes to complete the electron beam lithography image generation structure.

[0029] Furthermore, in S1, the substrate used is a silicon substrate with a crystal orientation of <100> or <110> The doping concentration is 1e15~1e21 / cm 3 ;

[0030] In S2, the method of depositing an oxide layer can satisfy the function of a hard mask, and a certain thickness is still required after CMP.

[0031] In S3, the dry plasma etching method used is the BOSCH process, and the ratio of SF6:C4F8 gas and time during etching is 10:7 to 8:7.

[0032] In S4, the formula for calculating the thickness of the sidewall insulation layer is as follows:

[0033]

[0034] Where E is the electric field strength, ε is the dielectric constant of the material, U is the working voltage, σ is the safety factor, and T is the operating voltage. c P is the temperature correction factor. c This is the pressure correction factor;

[0035] In S5, the thickness of the adhesion layer / barrier layer is 2-10 nm, and the materials include TiW, Ti, Ta, TaN, Ti and Mn4N; the deposition methods include PVD, CVD and ALD; ALD is used to achieve continuous and conformal deposition;

[0036] In S6, the seed layer thickness is 10–40 nm;

[0037] In S7, the copper electroplating voltage is 0.55–0.7V, and the solution is CuSO4 / H2SO4 / NaCl / polymer with concentrations of 1 mol / L, 0.5 mol / L, and 0.001 mol / L, respectively.

[0038] In S11, the etching method is a combination of plasma dry etching and wet etching. The dry etching uses the BOSCH process; after etching the silicon vias, the sidewalls are post-processed using either dry or wet etching to make them smoother. The dry etching gas used is SF6, and the wet etching solution is a combination of TMAH and IPA or a combination of KOH and IPA. The TMAH and IPA combination solution is 25% TMAH + 10% IPA at 50°C; the IPA combination solution is 30% KOH + 10% IPA at 50°C.

[0039] The method for preparing a micro-hole array in the image generation system proposed in this invention comprises the following steps:

[0040] S1, Prepare a silicon substrate (5) and deposit a dielectric layer on the front side of the substrate using chemical vapor deposition (CVD) or thermal oxidation.

[0041] S2, after depositing the dielectric layer, spin-coating photoresist and patterning it; then etching the dielectric layer downwards using the photoresist as a mask;

[0042] S3, using the dielectric layer as a mask, dry plasma etching is used to etch the silicon substrate downwards;

[0043] S4. An insulating layer is deposited on the sidewall of the etched structure using thermal oxidation or CVD.

[0044] S5, deposit an adhesion layer / barrier layer on the sidewall of the etched structure using physical vapor deposition (CVD) or chemical vapor deposition (CVD);

[0045] S6, use PVD or CVD to deposit the seed layer required for electroplating;

[0046] S7, Electrochemical deposition (ECD) fills the sidewall metal electrode (metal material such as Cu or W);

[0047] S8, Chemical Mechanical Polishing (CMP) removes excess metal and seed / barrier layers until the dielectric layer is exposed;

[0048] S9, deposit metal onto the top of the wafer to complete the layout and wiring of metal lines corresponding to different holes and metal electrodes;

[0049] S10, flip the wafer and deposit a dielectric layer (e.g., silicon oxide, silicon nitride) on its back as a hard mask;

[0050] In step S11, photoresist is used to align and pattern the dielectric layer from the back side. Then, silicon vias are etched using the dielectric layer as a mask, and the vias are etched through. The electrode sidewalls are then polished using dry or wet post-processing methods. This completes the electron beam lithography pattern generation structure.

[0051] The image generation system structure of this invention is characterized in that: the micro-aperture array unit, electron gun collimation system, beam gate, and electron optical system can be fabricated in a single MPW fabrication, or they can be fabricated separately and then integrated and packaged together using leads or optical fibers to complete functions such as beam convergence, scaling, and focusing.

[0052] The image generation system structure of this invention is characterized in that: the micro-aperture array unit can deflect multiple electron beams by optimizing the potential of the sidewall electrodes;

[0053] The image generation system structure of this invention is characterized by the following: the purpose of etching holes of varying diameters at the bottom of the micro-aperture array unit is to prevent the electron beam from bombarding the substrate and causing exposure failure. The purpose of the redistribution layer is to connect each electrode of each hole to a wire and a control chip, enabling individual and flexible control of each electron beam.

[0054] As described above, the multi-electron beam lithography equipment image generation system and its manufacturing method of the present invention have the following beneficial effects:

[0055] 1. The micro-hole array and control chip can be manufactured separately, reducing process complexity and cost;

[0056] 2. Electron beams can be more efficiently focused, scaled, and concentrated through electrodes on the front side and through-hole sidewalls of the silicon wafer; the two-part beam-concentrating structure on the front and back sides can greatly ensure the achievement of sub-10nm beam spot.

[0057] 3. The fabrication process of the micro-hole array for the image generation system is fully compatible with CMOS technology, resulting in low cost and easy integration;

[0058] 4. This image generation system has advantages such as simple process, high reliability, miniaturization and easy integration, and can be applied to multi-electron beam parallel lithography manufacturing equipment for 3nm and below node chips. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the application of the present invention to a multi-electron beam image generation structure;

[0060] Figure 2-13 Here is a flowchart illustrating the fabrication process of the micropore array unit in the image generation system of this invention:

[0061] Figure 2 A schematic diagram of the double-polished silicon substrate prepared in step S1 of the method for fabricating a micro-pore array for an image generation system.

[0062] Figure 3 This is a schematic diagram of the structure after depositing a dielectric layer on the front side of a silicon wafer in step S1 of the fabrication method of a micro-hole array for an image generation system.

[0063] Figure 4 This is a schematic diagram of the structure after patterning the dielectric layer in step S2, which is a specific step in the fabrication method of the micro-pore array for the image generation system.

[0064] Figure 5 This is a schematic diagram of the structure after patterning the dielectric layer and etching the substrate using the dielectric layer as a mask in step S3 of the method for fabricating a micro-hole array for an image generation system.

[0065] Figure 6 This is a schematic diagram of the structure with insulating layer / barrier layer / seed layer obtained after specific steps S4, S5, and S6 in the fabrication method of micro-pore array for image generation system.

[0066] Figure 7 This is a schematic diagram of the structure after electroplating and depositing copper electrodes in step S7 of the method for fabricating a micro-pore array for an image generation system.

[0067] Figure 8 This is a schematic diagram of the structure after CMP removal of excess copper and deposition of the top metal electrode in step S8, which is a specific step in the fabrication method of the micro-pore array of the image generation system.

[0068] Figure 9 , 10 This is a schematic diagram of the structure after patterning the top metal electrode in step S9 of the method for fabricating a micro-pore array for an image generation system.

[0069] Figure 11 This is a schematic diagram of the structure after flipping the wafer, depositing a dielectric layer, and patterning it in step S10, which is a method for fabricating a micro-pore array for an image generation system.

[0070] Figure 12 This is a method for fabricating a micro-aperture array for an image generation system. Specifically, in step S11, a schematic diagram of the structure after preliminary etching of the substrate using a dielectric layer as a mask is shown.

[0071] Figure 13 The method for fabricating a micro-hole array for an image generation system includes a specific step S11 in which the structure is again homogenized, exposed, and etched to penetrate the substrate, resulting in a schematic diagram of the final single-hole structure of the image generator.

[0072] The following explanation is provided in conjunction with the accompanying drawings:

[0073] 1—Electron gun collimation system; 2—Beam brake; 3—Electron optics system; 4—Substrate front dielectric layer; 5—Image generator substrate; 6—Sidewall electrode insulating layer; 7—Sidewall electrode blocking layer; 8—Sidewall electrode; 9—Top metal electrode. Detailed Implementation

[0074] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] Please see Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show some of the relevant process flows in the present invention, and not all the detailed process steps when implemented according to the actual process flow. The process flows and related experimental parameters in actual implementation can be changed according to actual needs.

[0076] This embodiment provides an image generation system for multi-electron beam lithography and its manufacturing method. It is constructed by connecting and encapsulating a control chip unit, an electron optical system, and an electron gun collimation system via transmission lines and redistribution layers. The image generation micro-aperture array unit serves as the core component, including a silicon substrate, a top electrode, and sidewall electrodes.

[0077] An image generation system for multi-electron beam lithography includes an electron gun and collimation system 1, a beam shutter 2, an electron optical system 3, and a multi-electron beam image generation system. The multi-electron beam image generation system is assembled with the electron gun and collimation system 1, beam shutter 2, and electron optical system 3 via a central aperture axis. A high-energy electron beam is emitted from the electron gun, collimated by the collimation system 1, and then focused by the electron optical system 3. A potential difference is created by applying different voltages to the sidewalls of the multi-electron beam image generation system. The electric field generated by this potential difference deflects the focused electron beam, thereby achieving the same electron beam in the same field. The purpose of exposure at different positions; the switching between different writing fields is achieved by moving the workpiece stage; the beam gate 2 is used to control the electron beam exposure switch, which is turned on only when exposure is required; the multi-electron beam image generation system consists of a substrate 5, a substrate front dielectric layer 4, a sidewall insulating layer 6, a sidewall electrode diffusion barrier layer 7, a sidewall metal electrode 8, and a top metal electrode 9; the substrate front dielectric layer 4 is disposed on the substrate 5, the top metal electrode 9 is disposed on the substrate front dielectric layer 4, the side of the substrate 5 is the sidewall metal electrode 8, and the sidewall metal electrode 8 is connected to the substrate 5 through the sidewall electrode diffusion barrier layer 7 and the sidewall insulating layer 6.

[0078] Furthermore, the electron gun collimation system 1, beam gate 2, and electron optical system 3 are matched with the multi-electron beam image generation system, and have the same array combination and the same aperture axis.

[0079] Furthermore, the top metal electrode 9 is connected to an external signal transmission line via a redistribution layer RDL.

[0080] Furthermore, the substrate 5 is a highly doped double-sided polished silicon substrate with a crystal orientation of... <110> Doping concentration > 1e19 / cm 3 Resistivity less than 10 -2 Ω·cm.

[0081] Furthermore, the aperture shaft is divided into square aperture and round aperture according to the shape of the writing field. The voltage applied to the opposite electrode of each electrode is the opposite voltage, and the electron beam is deflected by the electric field generated by the potential difference with the opposite electrode.

[0082] Furthermore, the aperture array is >100×100.

[0083] Furthermore, the hole depth and diameter of the hole shaft are customized according to the deflection voltage requirements; a lower deflection voltage corresponds to a larger hole diameter and a larger hole depth.

[0084] Furthermore, the sidewall metal electrodes 8 and 9 are made of molybdenum, tungsten, aluminum, ruthenium, nickel, or copper.

[0085] The substrate front dielectric layer 4 is made of silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide dielectric insulating layer.

[0086] The sidewall insulating layer material of the image generation system is a polymer, silicon oxide, or silicon nitride;

[0087] The sidewall blocking / adhesive layer material in the image generation system is Ti, Ta, and their compounds.

[0088] A method for manufacturing an image generation system for multi-electron beam lithography equipment includes the following steps:

[0089] S1, Prepare substrate 5, and deposit a dielectric layer on the front side of the substrate using chemical vapor deposition (CVD) or thermal oxidation.

[0090] S2, after depositing the dielectric layer, spin-coating photoresist and patterning it; then using the photoresist as a mask, etching the front dielectric layer 4 of the substrate downwards;

[0091] S3, using the front dielectric layer 4 of the substrate as a mask, the substrate 5 is etched downwards using dry plasma etching;

[0092] S4, using thermal oxidation or chemical vapor deposition (CVD) to deposit a sidewall insulating layer 6 on the sidewall of the etched structure;

[0093] S5, using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to deposit an adhesion layer / barrier layer on the sidewall of the etched sidewall insulating layer 6, wherein the adhesion layer / barrier layer is a sidewall electrode diffusion barrier layer 7.

[0094] S6, use PVD or chemical vapor deposition (CVD) to deposit the seed layer required for electroplating;

[0095] S7, Electrochemically deposited ECD fills the sidewall metal electrode 8, wherein the sidewall metal electrode 8 is a Cu or W metal material;

[0096] S8, chemical mechanical polishing (CMP) removes excess metal and seed / blocking layers until the substrate front dielectric layer 4 is exposed;

[0097] S9, deposit metal onto the top of the wafer to complete the layout and wiring of the metal lines corresponding to different holes and top metal electrodes 9;

[0098] S10, the wafer is flipped over and a substrate front dielectric layer 4 is deposited on its back side as a hard mask;

[0099] S11, using photoresist, align and pattern the front dielectric layer of the substrate from the back side, then use the front dielectric layer of the substrate as a mask to etch silicon holes and etch through the holes to complete the electron beam lithography image generation structure.

[0100] Example

[0101] A method for fabricating the above-mentioned image generation unit micropore array includes the following specific steps:

[0102] S1, Prepare a double-sided polished silicon substrate, crystal orientation <110> The doping concentration is N1e19 / cm. 3 ;

[0103] S2, 4µm thick oxide layer is deposited simultaneously on both sides of the silicon substrate using PECVD;

[0104] S3, apply photoresist to any side, expose, and use low-temperature (-20℃) etching method, CHF3 plasma etching, with a gas flow rate of 50-100 sccm, a power of 150-200 W, a bias power of 30-60 W, and an etching chamber pressure of 5-10 mTorr; then, remove the photoresist.

[0105] S4, using the oxide layer as a mask, the silicon substrate is etched using the BOSCH process, with a gas flow rate and an etching-passivation time ratio of 9:7.

[0106] S5 uses atomic layer deposition (ALD) to deposit a 30nm oxide layer on the trench sidewalls and bottom;

[0107] S6, using ALD, deposits a 10nm barrier layer TaN;

[0108] S7, using ion beam sputtering, deposits 10nm Ti;

[0109] S8, copper is filled into the through hole by electroplating. The electroplating voltage is 0.55-0.7V, and the solution is CuSO4 / H2SO4 / NaCl / polymer with concentrations of 1mol / L, 0.5mol / L, and 0.001mol / L, respectively.

[0110] S9, The aforementioned wafer is polished using CMP to remove excess copper and film layers;

[0111] S10, using ion beam sputtering to deposit a 50nm Mo thin film;

[0112] S11 uses photoresist as a mask to pattern a Mo metal thin film;

[0113] S12, flip the wafer and pattern the oxide layer using the same method as the front-side process;

[0114] S13 uses an oxide layer as a mask and employs dry etching. The BOSCH process etches nested holes of varying sizes into the silicon from the back side.

[0115] S14, continue using the BOSCH process to etch through the substrate;

[0116] S15, the sidewalls are polished and excess silicon is removed using a wet polishing method. The wet solution is a combination of TMAH and IPA (25% TMAH + 10% IPA, 50°C) to finally complete the image generation system structure.

[0117] The difference between this invention and traditional single-electron-beam lithography lies in the fact that the multi-electron-beam lithography image generation system can control multiple incident electron beams. The electron beams are focused and concentrated using an electric field in the electron optics system, and then deflected by the image generation system before reaching the workpiece stage surface, thus achieving simultaneous multi-beam exposure. The number of beams that can be controlled during multi-electron-beam exposure depends on the number of vias in the image generation system.

[0118] The specific embodiments, working principles, and preparation methods described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is not intended to limit the present invention, and any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An image generation system for multi-electron beam lithography equipment, characterized in that, It includes an electron gun collimation system (1), a beam gate (2), an electron optical system (3), and a multi-electron beam image generation system; the multi-electron beam image generation system is assembled with the electron gun collimation system (1), the beam gate (2), and the electron optical system (3) through the center of the aperture axis; after the high-energy electron beam is emitted by the electron gun, it is collimated by the electron gun collimation system (1), and then focused by the electron optical system (3). By applying different voltages to the sidewalls of the multi-electron beam image generation system, a potential difference is formed. The electric field formed by the potential difference deflects the electron beam that has completed the beam focusing, thereby achieving the purpose of exposing the electron beam at different positions in the same writing field; between different writing fields The switching is achieved by moving the workpiece stage; the beam gate (2) is used to control the electron beam exposure switch, and is only turned on when exposure is required; the multi-electron beam image generation system consists of a substrate (5), a substrate front dielectric layer (4), a sidewall insulating layer (6), a sidewall electrode diffusion barrier layer (7), a sidewall metal electrode (8), and a top metal electrode (9); the substrate front dielectric layer (4) is disposed on the substrate (5), the top metal electrode (9) is disposed on the substrate front dielectric layer (4), the side of the substrate (5) is the sidewall metal electrode (8), and the sidewall metal electrode (8) is connected to the substrate (5) through the sidewall electrode diffusion barrier layer (7) and the sidewall insulating layer (6); The electron gun collimation system (1), beam gate (2), and electron optical system (3) are matched with the multi-electron beam image generation system and have the same array combination and the same aperture axis.

2. The image generation system for multi-electron beam lithography equipment according to claim 1, characterized in that: The top metal electrode (9) is connected to an external signal transmission line via a redistribution layer (RDL).

3. The image generation system for multi-electron beam lithography equipment according to claim 1, characterized in that: The substrate (5) is a highly doped double-sided polished silicon substrate with crystal orientation... <110> Doping concentration > 1e19 / cm 3 Resistivity less than 10 -2 Ω·cm.

4. The image generation system for multi-electron beam lithography equipment according to claim 2, characterized in that: The array is >100×100.

5. The image generation system for multi-electron beam lithography equipment according to claim 1, characterized in that, The sidewall metal electrodes (8) and electrodes (9) are made of molybdenum, tungsten, aluminum, ruthenium, nickel, or copper. The substrate front dielectric layer (4) is made of silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide dielectric insulating layer. The sidewall insulating layer material of the image generation system is a polymer, silicon oxide, or silicon nitride; The sidewall blocking / adhesive layer material in the image generation system is Ti, Ta, and their compounds.

6. A method for manufacturing an image generation system for a multi-electron beam lithography apparatus as described in any one of claims 1 to 5, characterized in that, Includes the following steps: S1, Prepare a substrate (5) and deposit a dielectric layer on the front side of the substrate using chemical vapor deposition (CVD) or thermal oxidation. S2, after depositing the dielectric layer, spin-coating photoresist and patterning; then using the photoresist as a mask, etching the front dielectric layer of the substrate downwards (4); S3, using the front dielectric layer (4) of the substrate as a mask, the substrate (5) is etched downwards using dry plasma etching; S4, using thermal oxidation or chemical vapor deposition (CVD) to deposit a sidewall insulating layer on the sidewall of the etched structure (6); S5, using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to deposit an adhesion layer / barrier layer on the sidewall of the etched sidewall insulating layer (6), wherein the adhesion layer / barrier layer is a sidewall electrode diffusion barrier layer (7); S6, use PVD or chemical vapor deposition (CVD) to deposit the seed layer required for electroplating; S7, Electrochemically deposited ECD filling sidewall metal electrode (8), wherein the sidewall metal electrode (8) is Cu or W metal material; S8, chemical mechanical polishing (CMP) removes excess metal and seed / barrier layer until the substrate front dielectric layer is exposed (4); S9, deposit metal onto the top of the wafer to complete the layout and wiring of the metal lines corresponding to different holes and top metal electrodes (9); S10, the wafer is flipped over and a substrate front dielectric layer (4) is deposited on its back side as a hard mask; S11, using photoresist, align and pattern the front dielectric layer of the substrate from the back side, then use the front dielectric layer of the substrate as a mask to etch silicon holes and etch through the holes to complete the electron beam lithography image generation structure.

7. The manufacturing method of the multi-electron beam lithography equipment image generation system according to claim 6, characterized in that: In S1, the substrate used is a silicon substrate with a crystal orientation of <100> or <110> The doping concentration is 1e15~1e21 / cm 3 ; In S2, the method of depositing an oxide layer can satisfy the function of a hard mask, and a certain thickness is still required after CMP. In S3, the dry plasma etching method used is the BOSCH process, and the ratio of SF6:C4F8 gas and time during etching is 10:7 to 8:

7. In S4, the formula for calculating the thickness of the sidewall insulation layer is as follows: t ox =(E×3500×ε -0.64 ) / U×σ×(1+T c )×(1+P c ) Where E is the electric field strength, ε is the dielectric constant of the material, U is the working voltage, σ is the safety factor, and T is the operating voltage. c P is the temperature correction factor. c This is the pressure correction factor; In S5, the thickness of the adhesion layer / barrier layer is 2-10 nm, and the materials include TiW, Ti, Ta, TaN and Mn4N; the deposition methods include PVD and CVD. In S6, the seed layer thickness is 10–40 nm; In S7, the copper electroplating voltage is 0.55–0.7V, and the solution is a polymer of CuSO4, H2SO4, and NaCl with concentrations of 1 mol / L, 0.5 mol / L, and 0.001 mol / L, respectively. In S11, the etching method is a combination of plasma dry etching and wet etching. The dry etching uses the BOSCH process; after etching the silicon vias, the sidewalls are post-processed using either dry or wet etching to make them smoother. The dry etching gas used is SF6, and the wet etching solution is a combination of TMAH and IPA or a combination of KOH and IPA. The TMAH and IPA combination solution is 25% TMAH + 10% IPA at 50°C; the IPA combination solution is 30% KOH + 10% IPA at 50°C.

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