Dynamic voltage frequency adjustment circuit, method, chip and electronic device

Abstract

This application provides a dynamic voltage frequency regulation circuit, method, chip, and electronic device. In this application, during voltage frequency regulation, a clock module is controlled based on a working clock signal to adjust the clock frequency of the working clock signal to the voltage regulation frequency, wherein the voltage regulation frequency matches the duration of one voltage regulation operation performed by the voltage module. After adjustment to the voltage regulation frequency, the voltage module is controlled based on the working clock signal to adjust the voltage of the working voltage signal to the target voltage. After adjustment to the target voltage, the clock module is controlled based on the working clock signal to adjust the clock frequency of the working clock signal to the target frequency. Using this application, timing violations and voltage overshoot during voltage regulation can be at least partially avoided.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a dynamic voltage and frequency regulation circuit, method, chip, and electronic device. Background Technology

[0002] Dynamic Voltage and Frequency Scaling (DVFS) is a technique that balances performance and power consumption by dynamically adjusting the operating voltage and clock frequency. For example, it reduces power consumption by adjusting the operating voltage and clock frequency while meeting performance requirements. DVFS can be applied to chips as a system-level low-power design technique.

[0003] In related technologies, the following adjustment sequence is typically used: when it is necessary to increase voltage and frequency, the voltage should be increased to the target voltage first, and then the frequency should be increased to the target frequency; when it is necessary to decrease voltage and frequency, the frequency should be decreased to the target frequency first, and then the voltage should be decreased to the target voltage. However, the inventors discovered during the research and development process that, in some cases, timing violations and other problems may occur during the adjustment process. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a dynamic voltage frequency adjustment circuit, method, chip, and electronic device to solve the above technical problems.

[0005] In a first aspect, embodiments of this application provide a dynamic voltage frequency adjustment circuit, comprising: a voltage module for outputting a working voltage signal of a target module; a clock module for outputting a working clock signal of the target module; and a control module for: during voltage frequency adjustment, controlling the clock module to adjust the clock frequency of the working clock signal to the voltage adjustment frequency based on the working clock signal, wherein the voltage adjustment frequency matches the duration of one voltage adjustment performed by the voltage module; after adjustment to the voltage adjustment frequency, controlling the voltage module to adjust the voltage of the working voltage signal to the target voltage based on the working clock signal; and after adjustment to the target voltage, controlling the clock module to adjust the clock frequency of the working clock signal to the target frequency based on the working clock signal. The voltage adjustment is performed at the voltage adjustment frequency, and the voltage adjustment frequency matches the duration of one voltage adjustment. The voltage adjustment process can avoid the rising edge of the clock, thus at least partially avoiding timing violations and voltage overshoot during voltage adjustment.

[0006] Optionally, the half-clock cycle corresponding to the voltage regulation frequency is matched with the duration of one voltage regulation operation performed by the voltage module.

[0007] Optionally, the target frequency is selected from multiple preset operating frequencies, the voltage regulation frequency is different from the multiple preset operating frequencies, and the voltage regulation frequency is less than any of the preset operating frequencies.

[0008] Optionally, the control module is configured to, after adjusting to the voltage regulation frequency, determine a voltage sequence based on the voltage change amplitude between the current voltage and the target voltage; and control the voltage module to perform voltage regulation according to the voltage sequence to adjust the working voltage signal to the target voltage; wherein the voltage sequence includes the target voltage; or the voltage sequence includes the target voltage and one or more intermediate voltages with amplitudes between the current voltage and the target voltage.

[0009] Optionally, the target voltage is selected from a plurality of preset operating voltages, and the intermediate voltage is selected from the plurality of preset operating voltages.

[0010] Optionally, the control module includes: a first register; a second register; a voltage regulation unit for writing voltage data to the first register and writing first control data to the second register; wherein the first register and the second register are read and written based on a working clock signal; the second register outputs a voltage regulation enable signal based on the first control data; and a voltage module for adjusting the voltage of the working voltage signal to the voltage corresponding to the voltage data based on the voltage regulation enable signal.

[0011] Optionally, the control module further includes: a first delay unit for delaying the voltage regulation enable signal for a first duration; and a voltage module for adjusting the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the delayed voltage regulation enable signal.

[0012] Optionally, the voltage regulation unit is configured to: write voltage data corresponding to the current voltage regulation to a first register and write first control data to a second register when performing at least two voltage adjustments to progressively adjust the operating voltage signal to a target voltage; and after detecting the voltage corresponding to the voltage data output by the voltage module, or after a delay of at least one clock cycle corresponding to the operating clock signal, write voltage data corresponding to the next voltage adjustment to the first register and write first control data to the second register.

[0013] Optionally, the control module includes: a third register; a fourth register; a frequency modulation unit for writing frequency data to the third register and writing second control data to the fourth register; wherein the third register and the fourth register are read and written based on the working clock signal; the fourth register outputs a frequency modulation enable signal based on the second control data; and a clock module for adjusting the clock frequency of the working clock signal to the frequency corresponding to the frequency data based on the frequency modulation enable signal.

[0014] Optionally, the control module further includes: a second delay unit for delaying the frequency modulation enable signal for a second duration; wherein the clock module is used to adjust the clock frequency of the working clock signal to the frequency corresponding to the frequency data based on the frequency modulation enable signal.

[0015] Secondly, embodiments of this application provide a dynamic voltage frequency adjustment method, comprising: during voltage frequency adjustment, controlling a clock module to adjust the clock frequency of a working clock signal to a voltage adjustment frequency, wherein the voltage adjustment frequency matches the duration of one voltage adjustment performed by the voltage module; after adjustment to the voltage adjustment frequency, controlling the voltage module to adjust the voltage of the working voltage signal to a target voltage based on the working clock signal; and after adjustment to the target voltage, controlling the clock module to adjust the clock frequency of the working clock signal to the target frequency based on the working clock signal. The voltage adjustment is performed at the voltage adjustment frequency, and the voltage adjustment frequency matches the duration of one voltage adjustment. The voltage adjustment process can avoid the rising edge of the clock, thus at least partially avoiding timing violations and voltage overshoot during voltage adjustment.

[0016] Optionally, after adjusting to the voltage regulation frequency, controlling the voltage module to regulate the voltage of the working voltage signal to the target voltage based on the working clock signal includes: after adjusting to the voltage regulation frequency, determining a voltage sequence for voltage regulation based on the voltage change amplitude between the current voltage and the target voltage; controlling the voltage module to perform voltage regulation according to the voltage sequence to regulate the working voltage signal to the target voltage; wherein the voltage sequence includes the target voltage; or the voltage sequence includes the target voltage and one or more intermediate voltages with amplitudes between the current voltage and the target voltage.

[0017] Optionally, the voltage module is controlled to perform a voltage adjustment based on the working clock signal, including: writing the voltage data corresponding to this voltage adjustment to the first register, and writing the first control data to the second register; wherein the first register and the second register are read and written based on the working clock signal; the second register outputs a voltage regulation enable signal based on the first control data; the voltage module is used to adjust the voltage of the working voltage signal to the voltage corresponding to the voltage data based on the voltage regulation enable signal.

[0018] Optionally, after writing the voltage data corresponding to the current voltage adjustment to the first register and writing the first control data to the second register when performing at least two voltage adjustments, the method further includes: after detecting the voltage corresponding to the voltage data output by the voltage module, or after delaying at least one clock cycle corresponding to the working clock signal, writing the voltage data corresponding to the next voltage adjustment to the first register and writing the first control data to the second register.

[0019] Thirdly, embodiments of this application also provide a chip including the aforementioned dynamic voltage frequency adjustment circuit.

[0020] Fourthly, embodiments of this application also provide an electronic device, including a device body and a chip as described above disposed on the device body.

[0021] Fifthly, according to an embodiment of this application, a non-transient computer-readable storage medium stores computer instructions, wherein the computer instructions are used to cause the computer to execute the above-described dynamic voltage frequency adjustment method.

[0022] The dynamic voltage frequency regulation circuit, method, chip, and electronic device provided in this application consider that adjusting the voltage from high to low to a stable state is a process with a certain switching time. A voltage regulation frequency is set that matches the duration of one voltage regulation operation. Before voltage regulation, the clock frequency of the operating clock signal is adjusted to the voltage regulation frequency. At the voltage regulation frequency, the voltage of the operating voltage signal is adjusted to the target voltage. After voltage regulation is completed, the clock frequency of the operating clock signal is adjusted to the target frequency. Since the voltage regulation is performed at the voltage regulation frequency, and the voltage regulation frequency matches the duration of one voltage regulation operation, the voltage regulation process can avoid the rising edge of the clock, thus at least partially avoiding timing violations and voltage overshoot during voltage regulation.

[0023] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A structural block diagram of an exemplary electronic system provided in an embodiment of this application is shown.

[0026] Figure 2 An exemplary signal timing diagram is shown where the voltage regulation process is mismatched with the clock frequency.

[0027] Figure 3 A block diagram of the dynamic voltage and frequency regulation circuit provided in an embodiment of this application is shown.

[0028] Figure 4 A structural block diagram of an exemplary dynamic voltage and frequency regulation circuit provided in an embodiment of this application is shown.

[0029] Figure 5 A structural block diagram of an electronic system provided in an embodiment of this application is shown.

[0030] Figure 6A An exemplary signal timing diagram is shown for adjusting the clock frequency from F0 to the voltage regulation frequency.

[0031] Figure 6BAn exemplary signal timing diagram is shown for adjusting the voltage from V0 to V1.

[0032] Figure 6C An exemplary signal timing diagram is shown for adjusting the voltage from V1 to V2.

[0033] Figure 6D An exemplary signal timing diagram is shown for adjusting the clock frequency from the voltage regulation frequency to F2.

[0034] Figure 7 A flowchart of the dynamic voltage frequency adjustment method provided in an embodiment of this application is shown.

[0035] Figure 8 A flowchart of an exemplary dynamic voltage frequency regulation method provided in an embodiment of this application is shown. Detailed Implementation

[0036] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0037] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0039] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0040] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0041] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0042] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0043] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0044] DVFS is a technology that balances performance and power consumption by dynamically adjusting the operating voltage and clock frequency. Firstly, it combines... Figure 1 Exemplary application scenarios of the embodiments of this application are described below.

[0045] like Figure 1 As shown, Figure 1 An electronic system 10 provided in an embodiment of this application is illustrated schematically. This electronic system 10 may be a system-on-a-chip (SOC) or the like, capable of dynamic voltage and frequency regulation. Figure 1 As shown, the electronic system 10 may include: a load calculation unit 11, a target voltage calculation unit 12, a target frequency calculation unit 13, and an adjustment unit 14. It should be understood that... Figure 1 Only an exemplary block diagram for implementing dynamic voltage frequency regulation is shown. This application embodiment does not limit the electronic system 10.

[0046] The load calculation unit 11 is used to collect signals related to system load and calculate the system load. The load calculation unit 11 can be implemented in software or hardware. For example, a software implementation can place hooks in the kernel calls of the operating system, particularly the scheduler, to determine the system load based on the frequency of its calls. For example, a hardware implementation can calculate the current system load by collecting information on kernel signal interrupt lines, cache, memory bus usage, etc. It should be understood that the implementation method of the load calculation unit 11 is not limited in this application embodiment.

[0047] The target voltage calculation unit 12 is used to determine the target voltage based on the system load. The target frequency calculation unit 13 is used to determine the target frequency based on the system load. In some possible embodiments, for the same system, the higher the frequency, the higher the required voltage. As one implementation, the target frequency calculation unit 13 is used to determine the target frequency based on the system load, and the target voltage calculation unit 12 is used to determine the target voltage based on the target frequency.

[0048] As one possible implementation, the target frequency calculation unit 13 predicts the performance required by the system in the next time period based on the current load of the system. Various prediction algorithms can be selected; this prediction can be implemented in software or hardware. The target frequency calculation unit 13 converts the predicted performance into the required frequency (i.e., the target frequency), and the target voltage calculation unit 12 determines the target voltage based on the target frequency. It should be understood that the implementation methods of the target voltage calculation unit 12 and the target frequency calculation unit 13 are not limited in this application embodiment.

[0049] The adjustment unit 14 is used to adjust the operating voltage to the target voltage and the operating clock frequency to the target frequency. In related technologies, the following adjustment sequence is usually adopted: when it is necessary to increase the voltage and frequency, the voltage should be increased to the target voltage first, and then the frequency should be increased to the target frequency; when it is necessary to decrease the voltage and frequency, the frequency should be decreased to the target frequency first, and then the voltage should be decreased to the target voltage.

[0050] Voltage regulation is a process, and the output voltage usually reaches a stable state after a certain period of time. In some cases, the rising edge of the clock may occur outside the allowable range of the operating voltage before the output voltage stabilizes, resulting in a clock violation. Additionally, if the rising edge of the clock occurs near the lowest voltage point during the voltage regulation process, the circuit module may experience excessive load, potentially causing an overshoot in the output voltage, exceeding the allowable range of the operating voltage and rendering the circuit module malfunction.

[0051] For example, Figure 2 Several scenarios are illustrated where the operating clock frequency is inappropriate during output voltage regulation. For example... Figure 2As shown, the voltage regulation process is to step down from V1 to V2. In this example, the voltage is allowed to fluctuate within a certain range. The floating threshold voltage corresponding to V1 is V1th (for example, V1th is V1*(1-10%)). That is, the output voltage is between V1 and V1th, which is the allowable range of the operating voltage. The floating threshold voltage corresponding to V2 is V2th (for example, V2th is V2*(1-10%)). That is, the output voltage is between V2 and V2th, which is the allowable range of the operating voltage.

[0052] One situation is as follows Figure 2 As shown in the operating clock signal CLK0, the output voltage corresponding to the rising edge P0 of CLK0 is VP0, which is less than V1th and outside the allowable range of the operating voltage. Another scenario is as follows... Figure 2 As shown in the operating clock signal CLK1, the output voltage corresponding to the rising edge P1 of CLK1 is VP1, which is less than V2th, outside the allowable range of the operating voltage. The situation corresponding to CLK0 and CLK1 may cause timing violations. Another scenario is as follows... Figure 2 As shown in the working clock signal CLK2, the output voltage corresponding to the rising edge P2 of CLK2 is VP2. VP2 is near the minimum voltage V3 during the voltage drop from V1 to V2. In the case corresponding to CLK2, the circuit module's operation may cause excessive load, potentially leading to an overshoot in the output voltage, exceeding the allowable range of the working voltage, and causing the circuit module to malfunction.

[0053] This application relates to improvements to the adjustment unit 14 to solve at least some of the aforementioned technical problems. The embodiments of this application are described below with reference to the accompanying drawings.

[0054] This application provides a dynamic voltage frequency regulation circuit. The circuit sets a voltage regulation frequency that matches the duration of a single voltage regulation operation. Before voltage regulation, the clock frequency of the operating clock signal is adjusted to the voltage regulation frequency. At the voltage regulation frequency, the voltage of the operating voltage signal is regulated to the target voltage. After voltage regulation is completed, the clock frequency of the operating clock signal is adjusted back to the target frequency. Since the voltage regulation is performed at the voltage regulation frequency, and the voltage regulation frequency matches the duration of a single voltage regulation operation, the voltage regulation process can avoid the rising edge of the clock, thus at least partially preventing timing violations and voltage overshoot during voltage regulation.

[0055] Figure 3 The dynamic voltage frequency adjustment circuit 300 provided in an embodiment of this application is shown, such as... Figure 3As shown, the dynamic voltage and frequency adjustment circuit 300 includes a voltage module 310, a clock module 320, and a control module 330. The voltage module 310 outputs the operating voltage signal of the target module; the clock module 320 outputs the operating clock signal of the target module; and the control module 330, during voltage and frequency adjustment, controls the clock module 310 to adjust the clock frequency of the operating clock signal to the voltage adjustment frequency based on the operating clock signal, wherein the voltage adjustment frequency matches the duration of one voltage adjustment performed by the voltage module 320; after adjustment to the voltage adjustment frequency, the control module 330 adjusts the voltage of the operating voltage signal to the target voltage based on the operating clock signal; and after adjustment to the target voltage, the control module 310 adjusts the clock frequency of the operating clock signal to the target frequency based on the operating clock signal.

[0056] In this embodiment, a single voltage regulation by the voltage module 310 refers to the process by which the voltage module 310 adjusts the operating voltage signal from one voltage to another, for example, adjusting the operating voltage from 5V to 3V. Matching the voltage regulation frequency with the duration of a single voltage regulation by the voltage module 310 means that the duration of the clock cycle corresponding to the voltage regulation frequency is greater than or equal to the duration required for the voltage module 310 to perform a single voltage regulation, so that a single voltage regulation is completed within one clock cycle corresponding to the voltage regulation frequency. That is, voltage regulation begins after the rising edge of the clock cycle and reaches the allowable range of the operating voltage before the rising edge of the next clock cycle. Furthermore, voltage regulation can begin after the rising edge of the clock cycle and reach the target voltage before the rising edge of the next clock cycle.

[0057] For example, when adjusting the operating voltage from 5V to 3V, the target voltage of the operating voltage signal is 3V. After the operating voltage signal reaches 3*(1-10%)V (i.e., 2.7V), the system can work normally. The allowable range of the operating voltage is that the voltage is greater than 2.7V, that is, the voltage adjustment starts after the rising edge of the clock cycle and reaches 2.7V before the rising edge of the next clock cycle.

[0058] For example, when adjusting the operating voltage from 5V to 3V, voltage adjustment can begin after the rising edge of the clock cycle and reach the target voltage, i.e., 3V, before the rising edge of the next clock cycle.

[0059] In this embodiment, voltage regulation is performed at the voltage regulation frequency and can be completed within one clock cycle corresponding to the voltage regulation frequency. Therefore, the voltage regulation process can avoid the rising edge of the clock, avoiding timing violations and voltage overshoot during the voltage regulation process, and improving the reliability of the voltage regulation and frequency regulation process.

[0060] The clock tree may flip if the voltage is outside the allowable range at the falling edge of the clock. In some implementations, to avoid a falling edge during voltage regulation, half a clock cycle corresponding to the voltage regulation frequency is matched with the duration of one voltage adjustment by the voltage module. That is, a voltage regulation process is completed within half a clock cycle corresponding to the voltage regulation frequency, i.e., voltage regulation begins after the rising edge of the clock cycle and reaches the allowable operating voltage range before the falling edge of the same clock cycle. With this implementation, the voltage output can stabilize before the falling edge of the clock arrives, meaning the voltage at the falling edge is outside the allowable operating voltage range.

[0061] The larger the voltage change amplitude, the longer the voltage regulation time. In this embodiment, the voltage regulation frequency can be set according to the voltage change amplitude of the possible voltage regulation process. The voltage regulation frequency can be preset according to the voltage change amplitude of the possible voltage regulation process. For example, the voltage regulation time required for the possible voltage change amplitude of the voltage regulation process can be tested, and the voltage regulation frequency can be determined based on the test time.

[0062] In some implementations, the target frequency is selected from a plurality of preset operating frequencies. The voltage regulation frequency is different from these plurality of preset operating frequencies, and the voltage regulation frequency is less than any of the preset operating frequencies.

[0063] As one implementation method, the maximum voltage change amplitude involved in a single voltage regulation can be determined, and the duration of one clock cycle corresponding to the voltage regulation frequency can be determined based on the duration required for the maximum voltage change amplitude. With this implementation method, any voltage regulation process can use the same voltage regulation frequency, at which most of the voltage regulation process can be completed within one or half a clock cycle. For example, if the duration corresponding to the maximum voltage change amplitude of the voltage regulation process is t1, and one clock cycle corresponding to the voltage regulation frequency is T1, then T1 can be set to be greater than or equal to t1. As another example, if the duration corresponding to the maximum voltage change amplitude of the voltage regulation process is t2, and one clock cycle corresponding to the voltage regulation frequency is T2, then T2 / 2 can be set to be greater than or equal to t2, thereby completing most of the voltage regulation process within half a clock cycle corresponding to the voltage regulation frequency.

[0064] For example, the operating voltages output by voltage module 320, from smallest to largest, are V1, V2, V3, and V4. The maximum voltage change during the voltage regulation process is from V1 to V4, and the time taken from V1 to V4 is t14. One clock cycle corresponding to the voltage regulation frequency is T1. Therefore, T1 can be set to be greater than or equal to t14, or T1 / 2 can be set to be greater than or equal to t14.

[0065] As another implementation, multiple voltage regulation frequencies can be set, and the control module 330 selects the corresponding voltage regulation frequency according to the voltage change amplitude of the voltage regulation, so that the voltage regulation frequency matches the duration of the voltage regulation process.

[0066] In some embodiments, the control module 330 determines a voltage sequence for voltage regulation based on the voltage change amplitude between the current voltage and the target voltage, and controls the voltage module 320 to perform voltage regulation according to this voltage sequence to adjust the operating voltage signal to the target voltage. In some cases, the voltage sequence includes the target voltage, meaning the operating voltage signal is regulated from the current voltage to the target voltage in a single adjustment. In other cases, the voltage sequence includes the target voltage and one or more intermediate voltages with amplitudes between the current voltage and the target voltage. In this case, the voltage regulation is gradual, meaning that the current voltage is regulated to the target voltage in multiple stages via one or more intermediate voltages between the current voltage and the target voltage, rather than being regulated from the current voltage to the target voltage in one go, thereby reducing the voltage change amplitude of each voltage regulation. In this case, it is possible to avoid setting the voltage regulation frequency too low.

[0067] As an example, if the current operating voltage is V1 and the target operating voltage is V2, instead of directly adjusting the operating voltage from V1 to V2, in this example, the operating voltage can be adjusted sequentially to one or more intermediate voltages between V1 and V2. For example, if the intermediate voltage is V3, the voltage adjustment process includes V1 to V3 and V3 to V2; or if the intermediate voltages are V3 and V4, the voltage adjustment process includes V1 to V3, V3 to V4, and V4 to V2.

[0068] In one implementation, the target voltage is selected from a plurality of preset operating voltages. The intermediate voltages in the voltage sequence are selected from these preset operating voltages. For example, the control module 330 can be used to determine the number of voltage adjustments based on the number of preset operating voltages whose magnitudes fall between the current voltage and the target voltage, so as to progressively adjust the operating voltage signal to the target voltage.

[0069] As an example, when multiple preset operating voltages exist between the current voltage and the target voltage, voltage adjustment can be performed sequentially. Optionally, during voltage boosting, the current voltage is adjusted sequentially to adjacent preset operating voltages from lowest to highest until the target voltage is reached. Optionally, during voltage bucking, the current voltage is adjusted sequentially to adjacent preset operating voltages from highest to lowest until the target voltage is reached.

[0070] For example, the voltage levels supported by dynamic voltage regulation include sequentially increasing voltages V1, V2, V3, and V4. When adjusting the operating voltage from V1 to V2, there is no preset operating voltage between V1 and V2; the operating voltage is adjusted to V2 in one voltage adjustment. When adjusting the operating voltage from V1 to V4, there are two preset operating voltages between V1 and V4, namely V2 and V3. The voltage can be adjusted by first adjusting V1 to V2, then V2 to V3, and finally V3 to V4, thus adjusting the operating voltage from V1 to V4 in three voltage adjustments; or, it can be adjusted by first adjusting V1 to V3, then V3 to V4, thus adjusting the operating voltage from V1 to V4 in two voltage adjustments.

[0071] In some embodiments, the target frequency is selected from a plurality of preset operating frequencies, and the clock frequency of the operating clock signal is one of these preset operating frequencies. The target voltage is selected from a plurality of preset operating voltages, and the voltage of the operating voltage signal is one of these preset operating voltages. As one embodiment, the plurality of preset operating frequencies and the plurality of preset operating voltages have a corresponding relationship. For example, the preset operating frequencies include F0, F1, and F2, and the preset operating voltages include V0, V1, and V2, where F0 corresponds to V0, i.e., operation is performed at clock frequency F0 and operating voltage V0; similarly, F1 corresponds to V1, and F2 corresponds to V2.

[0072] The following describes an exemplary implementation of the control module 330 controlling the voltage module 310 and the clock module 320.

[0073] In some embodiments, as Figure 4 As shown, the control module 330 includes a first register 331, a second register 332, and a voltage regulation unit 333. The first register 331 and the second register 332 are read and written based on the operating clock signal. The voltage regulation unit 333 is used to write voltage data to the first register 331 and first control data to the second register 332. The second register 332 outputs a voltage regulation enable signal based on the first control data. Typically, voltage data is written to the first register 331 first, and then the first control data is written to the second register 332, so that the voltage module 310 correctly obtains the voltage to be regulated. The voltage module 310 is used to adjust the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the voltage regulation enable signal.

[0074] In one implementation, the voltage regulating unit 333 is configured to, when performing at least two voltage adjustments to progressively adjust the operating voltage signal to the target voltage: write voltage data corresponding to the current voltage adjustment to the first register 331 and write first control data to the second register 332, so that the voltage module 310 performs the current voltage adjustment; after detecting that the voltage module 310 outputs the voltage corresponding to the voltage data, write voltage data corresponding to the next voltage adjustment to the first register 331 and write first control data to the second register 332, so that the voltage module 310 performs the next voltage adjustment. This application embodiment does not limit the method of detecting the voltage corresponding to the voltage data output by the voltage module 310.

[0075] In another implementation, the voltage regulation unit 333 is configured to: write voltage data corresponding to the current voltage regulation to the first register 331 and write first control data to the second register 332 when performing at least two voltage adjustments to progressively adjust the operating voltage signal to the target voltage, so that the voltage module 310 performs the current voltage adjustment; after a delay of at least one clock cycle corresponding to the operating clock signal (whose clock frequency is the voltage regulation frequency), write voltage data corresponding to the next voltage adjustment to the first register 331 and write first control data to the second register 332, so that the voltage module 310 performs the next voltage adjustment. Since the voltage module 310 can perform a voltage adjustment once within one or half a clock cycle corresponding to the voltage regulation frequency, after a delay of at least one clock cycle corresponding to the voltage regulation frequency, the current voltage adjustment can be considered complete. Therefore, this implementation can control the timing of multiple voltage adjustments in a delayed manner.

[0076] As an implementation method, Figure 4 As shown, the control module 330 includes a third register 334, a fourth register 335, and a frequency modulation unit 336. The third register 334 and the fourth register 335 are read and written based on the operating clock signal. The frequency modulation unit 336 is used to write frequency data to the third register 334 and write second control data to the fourth register 335. The fourth register 335 outputs a frequency modulation enable signal based on the second control data. The clock module 320 is used to adjust the clock frequency of the operating clock signal to the frequency corresponding to the frequency data based on the frequency modulation enable signal.

[0077] In some embodiments, as Figure 4 As shown, the control module 330 further includes: a first delay unit 337, used to delay the voltage regulation enable signal for a first duration; and a voltage module 310, used to adjust the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the delayed voltage regulation enable signal. This implementation avoids voltage regulation at the rising edge of the clock.

[0078] In some embodiments, as Figure 4 As shown, the control module 330 further includes: a second delay unit 338, used to delay the frequency modulation enable signal for a second duration; and a clock module 320, used to adjust the clock frequency of the operating clock signal to the frequency corresponding to the frequency data based on the delayed frequency modulation enable signal. This implementation avoids frequency modulation at the rising edge of the clock.

[0079] In some embodiments, the control module 330 may delay the signal between the third register 334 and the clock module 320. In some embodiments, the control module 330 may delay the signal between the first register 331 and the voltage module 310. This application does not limit the scope of these embodiments.

[0080] Figure 5 This application illustrates an electronic system 500 including a dynamic voltage and frequency adjustment circuit, as provided in an embodiment of this application. The electronic system 500 may include a system-on-a-chip (SOC), etc., but this application does not limit this aspect. Figure 5 As shown, the electronic system 500 includes: a low dropout regulator (LDO) 510 (equivalent to voltage module 310), a clock generator (CG) 520 (equivalent to clock module 320), an LDO configuration register 531 (equivalent to first register 331), an LDO enable register 532 (equivalent to second register 332), a CG configuration register 541 (equivalent to third register 334), a CG enable register 542 (equivalent to fourth register 335), and a software system 550.

[0081] The LDO 510 is used to output the operating voltage signal of the core 560 (equivalent to the target module mentioned above). Figure 5 (The LDO output is shown). As one implementation, the operating voltage signal is selected from a plurality of preset operating voltages.

[0082] Clock generator 520 is used to output the operating clock signal of core 560 (i.e. Figure 5 (as shown in SYSCLK). In one implementation, the operating clock signal is selected from a voltage regulation frequency and multiple preset operating frequencies, wherein the voltage regulation frequency is different from the multiple preset operating frequencies and is less than any of the preset operating frequencies.

[0083] LDO configuration register 531, LDO enable register 532, CG configuration register 541, and CG enable register 542 are read and written based on the operating clock signal. LDO 510 operates using the operating clock signal.

[0084] like Figure 5As shown, the software system 550 includes an adjustment module 551 (equivalent to a voltage regulation unit 333 and a frequency regulation unit 336). The adjustment module 551 is used to control the LDO 510 and the clock generator 520. In this embodiment, the adjustment module 551 includes program instructions.

[0085] The adjustment module 551 can be used to: during voltage frequency adjustment, control the clock generator 520 to adjust the clock frequency of the working clock signal to the voltage regulation frequency based on the working clock signal, wherein the voltage regulation frequency is matched with the duration of one voltage adjustment performed by the voltage module; after adjustment to the voltage regulation frequency, control the LDO 510 to adjust the voltage of the working voltage signal to the target voltage based on the working clock signal (whose clock frequency is the voltage regulation frequency); after adjustment to the target voltage, control the clock generator 520 to adjust the clock frequency of the working clock signal to the target frequency based on the working clock signal.

[0086] In some embodiments, the adjustment module 551 may be used to: after adjusting to the voltage regulation frequency, determine a voltage sequence for voltage regulation based on the voltage change amplitude between the current voltage and the target voltage, wherein the voltage sequence includes the target voltage, or the target voltage and one or more intermediate voltages with amplitudes between the current voltage and the target voltage; and control the LDO 510 to perform voltage regulation a corresponding number of times according to the voltage sequence, so as to gradually adjust the operating voltage signal to the target voltage.

[0087] In one implementation, the target voltage is selected from a plurality of preset operating voltages, and the intermediate voltage in the voltage sequence is selected from the plurality of preset operating voltages.

[0088] For any voltage adjustment, the adjustment module 551 writes voltage data to the LDO configuration register 531 and writes voltage regulation enable data (equivalent to the first control data) to the LDO enable register 532. The LDO enable register 532 outputs an LDO enable signal (equivalent to the voltage regulation enable signal) based on the voltage regulation enable data. The LDO 510 is used to adjust the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the LDO enable signal. Generally, voltage data is written to the LDO configuration register 531 first, and then voltage regulation enable data is written to the LDO enable register 532. That is, the program instruction for writing voltage data is executed before the program instruction for writing voltage regulation enable data. The LDO 510 first obtains the voltage data, and then adjusts the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the LDO enable signal.

[0089] For any frequency adjustment, the adjustment module 551 writes frequency data to the CG configuration register 541 and frequency modulation enable data (equivalent to the second control data) to the CG enable register 542. The CG enable register 542 outputs a CG enable signal (equivalent to the frequency modulation enable signal) based on the frequency modulation enable data. The clock generator 520 adjusts the clock frequency of the working clock signal to the frequency corresponding to the frequency data based on the CG enable signal. Generally, frequency data is first written to the CG configuration register 541, and then frequency modulation enable data is written to the CG enable register 542. The clock generator 520 first obtains the frequency data, and then adjusts the clock frequency of the working clock signal to the frequency corresponding to the frequency data based on the CG enable signal.

[0090] In some implementations, the CG enable signal and the LDO enable signal may be delayed. For the sake of brevity, see the appendix. Figure 5 The corresponding delay module is not shown in the diagram; please refer to [link / reference]. Figure 4 A block diagram.

[0091] For the implementation methods of determining the target voltage and target frequency, see the foregoing description. Figure 1 Explanation. For example, Figure 5 An implementation method implemented in software is shown, such as... Figure 5 As shown, the software system 550 includes a load calculation module 552 and a target frequency and target voltage calculation module 553. For example, the load calculation module 552 can determine the system load by placing hooks in the kernel calls of the operating system, particularly the scheduler, based on the frequency of these calls. For example, the target frequency and target voltage calculation module 553 predicts the performance required by the system in the next time period based on the current system load, converts the predicted performance into the required frequency (i.e., the target frequency), and determines the target voltage based on the target frequency. This application does not limit the implementation method for determining the target voltage and target frequency.

[0092] The following is combined with Figures 6A to 6D right Figure 5 The signal and data timing during the voltage and frequency regulation process of the electronic system shown is illustrated by way of example.

[0093] The clock frequency of the operating clock signal is selected from F0, F1, and F2, and the voltage of the operating voltage signal is selected from V0, V1, and V2. The voltage regulation frequency is Fm. Figures 6A to 6D The process of reducing the clock frequency of the operating frequency signal from F0 to F2 and the voltage of the operating voltage signal from V0 to V2 is shown.

[0094] The current voltage is V0, and the current clock frequency is F0. The load calculation module 552 determines the system load, and the target frequency and target voltage calculation module 553 determines the target frequency as F2 and the target voltage as V2 based on the system load. That is, the clock frequency of the working clock signal is reduced from F0 to F2, and the voltage of the working voltage signal is reduced from V0 to V2.

[0095] refer to Figure 6A As shown, when the current voltage is V0, the voltage data in LDO configuration register 531 corresponds to V0; when the current clock frequency is F0, the frequency data in CG configuration register 541 corresponds to F0. Without voltage and frequency regulation, both the CG enable signal and the LDO enable signal are low. When voltage and frequency regulation are performed, the clock frequency of the working clock signal is first adjusted to the voltage regulation frequency (Fm), as follows: Figure 6A As shown, the adjustment module 551 writes the frequency data corresponding to Fm to the CG configuration register 541, and then writes frequency modulation enable data to the CG enable register 542, instructing the clock generator 520 to perform frequency modulation. After the frequency modulation enable data is written to the enable register 542, the CG enable signal changes from low to high, and the clock generator 520 performs frequency modulation while the CG enable signal is high. Based on the frequency data in the CG configuration register 541, the clock generator 520 adjusts the clock frequency of the working clock signal to the voltage modulation frequency, and thereafter the clock period of the working clock signal corresponds to the voltage modulation frequency. Furthermore, as... Figure 6A As shown, the voltage data in the LDO configuration register 531 is kept to correspond to V0, the LDO enable signal is kept low, and the voltage of the working voltage signal output by the LDO 510 is V0.

[0096] After adjusting the frequency to the voltage regulation frequency, the frequency data in the CG configuration register 541 remains corresponding to the voltage regulation frequency, the CG enable signal is low, and the clock generator 520 outputs a working clock signal with a clock frequency maintained at the voltage regulation frequency. Then, the voltage regulation process begins. The regulation module 551 determines the voltage sequence: the current voltage is V0, the target voltage is V2, and there exists a preset working voltage V1 between V0 and V2. Therefore, the voltage sequence includes both V1 and V2. In other words, the voltage regulation process is as follows: Figure 6B As shown, V0 is adjusted to V1, and as... Figure 6C The V1 shown is adjusted to V2.

[0097] Figure 6B The process of adjusting the working voltage signal from V0 to V1 is shown, as follows: Figure 6BAs shown, the regulation module 551 writes the voltage data corresponding to V1 to the LDO configuration register 531, and then writes the voltage regulation enable data to the LDO enable register 532, instructing the LDO 510 to perform voltage regulation. The LDO 510 starts voltage regulation when the LDO enable signal is high. Figure 6B As shown, the LDO 510 adjusts the LDO output from V0 to V1 within half a clock cycle corresponding to the voltage adjustment frequency. After adjusting the voltage from V0 to V1, voltage adjustment enable data is written to the LDO enable register 532, causing the LDO enable signal to change from high level to low level, and the LDO output of the LDO 510 is maintained at V1.

[0098] After confirming that the voltage adjustment from V0 to V1 is complete, the process of adjusting the voltage from V1 to V2 begins. The two processes can be separated by one or more clock cycles. The implementation method for determining whether the adjustment from V0 to V1 is complete is described above and will not be repeated here.

[0099] Figure 6C The process of adjusting the working voltage signal from V1 to V2 is shown, as follows: Figure 6C As shown, the adjustment module 551 writes the voltage data corresponding to V2 to the LDO configuration register 531, and then writes the voltage regulation enable data to the LDO enable register 532, instructing the LDO 510 to perform voltage regulation. The LDO enable register 532 outputs an LDO enable signal at a high level. The LDO 510 starts voltage regulation when the LDO enable signal is high. Figure 6B As shown, LDO 510 adjusts the LDO output from V1 to V2 within half a clock cycle corresponding to the voltage adjustment frequency. After adjusting the voltage from V1 to V2, voltage adjustment enable data is written to LDO enable register 532, causing the LDO enable signal to change from high level to low level, and the LDO output of LDO 510 remains at V2.

[0100] go through Figure 6B and Figure 6C The operating voltage signal is adjusted twice, from V0 to V2, and the LDO output is V2. After the voltage adjustment is completed, the clock frequency of the operating clock signal is adjusted from the voltage adjustment frequency to the target frequency, i.e., F2. Figure 6D The process of adjusting the frequency from the voltage regulation frequency Fm to F2 is shown, as follows: Figure 6DAs shown, the adjustment module 551 writes the frequency data corresponding to F2 to the CG configuration register 541, changing the frequency data in the CG configuration register 541 from corresponding to Fm to corresponding to F2. The adjustment module 551 writes frequency modulation enable data to the CG enable register 542, instructing the clock generator 520 to perform frequency modulation. The CG enable register 542 outputs a high-level CG enable signal. The clock generator 520 starts frequency modulation when the CG enable signal is high. The clock generator 520 adjusts the clock frequency of the working clock signal to F2. Afterward, the CG enable signal changes from high to low, and the clock frequency of the working clock signal remains at F2.

[0101] In addition, see Figures 6A to 6D As shown, the LDO enable signal and CG enable signal are delayed, i.e. Figures 6A to 6D As shown, the rising edges of the LDO enable signal and the CG enable signal have a certain delay relative to the rising edge of SYSCLK, and the falling edges of the LDO enable signal and the CG enable signal have a certain delay relative to the falling edge of SYSCLK.

[0102] This application also provides a dynamic voltage frequency regulation method. A voltage regulation frequency is set to match the duration of a single voltage regulation operation. Before voltage regulation, the clock frequency of the operating clock signal is adjusted to the voltage regulation frequency. At the voltage regulation frequency, the voltage of the operating voltage signal is regulated to the target voltage. After voltage regulation is completed, the clock frequency of the operating clock signal is adjusted to the target frequency. Since the voltage regulation is performed at the voltage regulation frequency, and the voltage regulation frequency matches the duration of a single voltage regulation operation, the voltage regulation process can avoid the rising edge of the clock, thus at least partially avoiding timing violations and voltage overshoot during voltage regulation.

[0103] Figure 7 A flowchart of the dynamic voltage frequency adjustment method provided in an embodiment of this application is shown, as follows: Figure 7 As shown, the method includes steps S701 to S703.

[0104] In step S701, during voltage frequency adjustment, the control clock module adjusts the clock frequency of the working clock signal to the voltage adjustment frequency, wherein the voltage adjustment frequency is matched with the duration of one voltage adjustment performed by the voltage module.

[0105] In step S702, after adjusting to the voltage regulation frequency, the voltage module is controlled to adjust the voltage of the working voltage signal to the target voltage based on the working clock signal.

[0106] In step S703, after adjusting to the target voltage, the clock module is controlled to adjust the clock frequency of the working clock signal to the target frequency based on the working clock signal.

[0107] In this embodiment, a single voltage regulation by the voltage module refers to the process of adjusting the operating voltage signal from one voltage to another, for example, adjusting the operating voltage from 5V to 3V. Matching the voltage regulation frequency with the duration of a single voltage regulation means that the duration of the clock cycle corresponding to the voltage regulation frequency is greater than or equal to the duration required for the voltage module to perform a single voltage regulation, so that a single voltage regulation is completed within one clock cycle corresponding to the voltage regulation frequency. That is, voltage regulation begins after the rising edge of the clock cycle and reaches the allowable operating voltage range before the rising edge of the next clock cycle.

[0108] In this embodiment, voltage regulation is performed at the voltage regulation frequency and can be completed within one clock cycle corresponding to the voltage regulation frequency. Therefore, the voltage regulation process can avoid the rising edge of the clock, avoiding timing violations and voltage overshoot during the voltage regulation process, and improving the reliability of the voltage regulation and frequency regulation process.

[0109] In some implementations, to avoid the falling edge of the clock during voltage regulation, the half-clock cycle corresponding to the voltage regulation frequency is matched with the duration of one voltage adjustment by the voltage module. That is, one voltage regulation process is completed within half a clock cycle corresponding to the voltage regulation frequency; that is, voltage regulation begins after the rising edge of the clock cycle and reaches the allowable operating voltage range before the falling edge of the same clock cycle. With this implementation, the voltage output can stabilize before the falling edge of the clock arrives, meaning the voltage corresponding to the falling edge is outside the allowable operating voltage range.

[0110] The larger the voltage change amplitude, the longer the voltage regulation time. In this embodiment, the voltage regulation frequency can be set according to the possible voltage change amplitude during the voltage regulation process.

[0111] In some implementations, the target frequency is selected from a plurality of preset operating frequencies, the voltage regulation frequency is different from the plurality of preset operating frequencies, and the voltage regulation frequency is less than any of the preset operating frequencies.

[0112] In one implementation, step S701 may include: after adjusting to the voltage regulation frequency, determining a voltage sequence for voltage regulation based on the voltage change amplitude between the current voltage and the target voltage; controlling the voltage module to perform voltage regulation a corresponding number of times according to the voltage sequence to adjust the working voltage signal to the target voltage. In some cases, the voltage sequence includes the target voltage, meaning the working voltage signal is regulated from the current voltage to the target voltage in one adjustment. In other cases, the voltage sequence includes the target voltage and one or more intermediate voltages with amplitudes between the current voltage and the target voltage. In this case, the voltage regulation is gradual, meaning that the current voltage is regulated to the target voltage multiple times via one or more intermediate voltages between the current voltage and the target voltage, rather than being regulated from the current voltage to the target voltage in one go, thereby reducing the voltage change amplitude of each voltage regulation. In this case, it is possible to avoid setting the voltage regulation frequency too low.

[0113] In one implementation, the target voltage is selected from a plurality of preset operating voltages, and the intermediate voltage in the voltage sequence is selected from the plurality of preset operating voltages. For example, the number of voltage adjustments can be determined based on the number of preset operating voltages whose magnitudes fall between the current voltage and the target voltage, so as to progressively adjust the operating voltage signal to the target voltage.

[0114] As an example, when multiple preset operating voltages exist between the current voltage and the target voltage, voltage adjustment can be performed sequentially. Optionally, during voltage boosting, the current voltage is adjusted sequentially to adjacent preset operating voltages from lowest to highest until the target voltage is reached. Optionally, during voltage bucking, the current voltage is adjusted sequentially to adjacent preset operating voltages from highest to lowest until the target voltage is reached.

[0115] In one implementation, step S702 may include: writing voltage data corresponding to the current voltage adjustment to a first register, and writing first control data to a second register; wherein the first register and the second register are read and written based on a working clock signal; the second register outputs a voltage regulation enable signal based on the first control data; and the voltage module is used to adjust the voltage of the working voltage signal to the voltage corresponding to the voltage data based on the voltage regulation enable signal.

[0116] In one implementation, when at least two voltage adjustments are performed, after writing the voltage data corresponding to the current voltage adjustment to the first register and writing the first control data to the second register in step S702, the method further includes: after detecting the voltage corresponding to the voltage data output by the voltage module, writing the voltage data corresponding to the next voltage adjustment to the first register and writing the first control data to the second register.

[0117] In another implementation where at least two voltage adjustments are performed, after writing the voltage data corresponding to the current voltage adjustment to the first register and writing the first control data to the second register in step S702, the method further includes: after delaying for at least one clock cycle corresponding to a working clock signal, writing the voltage data corresponding to the next voltage adjustment to the first register and writing the first control data to the second register.

[0118] In some implementations, performing a frequency adjustment includes: writing frequency data to a third register and writing second control data to a fourth register; wherein the third and fourth registers are read and written based on the working clock signal; the fourth register outputs a frequency modulation enable signal based on the second control data; and the clock module adjusts the clock frequency of the working clock signal to the frequency corresponding to the frequency data based on the frequency modulation enable signal.

[0119] Figure 8 A flowchart of the dynamic voltage frequency adjustment method provided in an embodiment of this application is shown, as follows: Figure 8 As shown, it includes steps S801 to S806.

[0120] Step S801: Collect signals related to system load and calculate system load.

[0121] Step S802: Determine the target frequency and target voltage based on the system load.

[0122] For example, based on the current load of the system, the required performance of the system in the next time period is predicted, the predicted performance is converted into a target frequency, and the target voltage is determined based on the target frequency.

[0123] The target frequency is selected from multiple preset operating frequencies.

[0124] The target voltage can be selected from multiple preset operating voltages.

[0125] After determining the target frequency and target voltage, the frequency and voltage regulation process begins.

[0126] Step S803: Adjust the clock frequency of the working clock signal to the voltage regulation frequency.

[0127] Specifically, after adjusting the clock frequency of the working clock signal to the voltage regulation frequency, the clock frequency of the working clock signal changes from the current frequency to the voltage regulation frequency, and the clock period corresponding to the working clock signal is the clock period corresponding to the voltage regulation frequency.

[0128] For example, when the clock frequency of the operating clock signal is detected to have changed to the voltage regulation frequency, it can be confirmed that the clock frequency adjustment of the operating clock signal to the voltage regulation frequency has been completed. For example, at least one clock cycle can be delayed.

[0129] Step S804: Determine the voltage sequence based on the voltage change amplitude between the current operating voltage and the target voltage.

[0130] The voltage sequence includes: a target voltage, or a target voltage and one or more intermediate voltages.

[0131] The one or more intermediate voltages are preset operating voltages that are between the target voltage and the current voltage.

[0132] In step S805, the voltage module is controlled to perform voltage adjustment a corresponding number of times according to the voltage sequence, so as to gradually adjust the working voltage signal to the target voltage.

[0133] The voltage module is controlled by the operating clock signal to perform a voltage regulation, including: writing the voltage data corresponding to this voltage regulation to the first register, and writing the first control data to the second register. The first and second registers are read and written based on the operating clock signal; the second register outputs a voltage regulation enable signal based on the first control data; and the voltage module adjusts the operating voltage signal to the voltage corresponding to the voltage data based on the voltage regulation enable signal.

[0134] For example, when controlling the voltage module via program instructions, the program instructions for writing voltage data are executed before the program instructions for writing first control data.

[0135] In the case of performing at least two voltage adjustments, after writing the voltage data corresponding to the current voltage adjustment to the first register and writing the first control data to the second register, the method further includes: after detecting the voltage corresponding to the voltage data output by the voltage module, or after delaying at least one clock cycle corresponding to the working clock signal, writing the voltage data corresponding to the next voltage adjustment to the first register and writing the first control data to the second register.

[0136] For example, when controlling the voltage module through program instructions, the program instructions can be used to determine whether the voltage output by the voltage module is the voltage corresponding to the voltage data, or the program instructions can be used to perform a delay, and after the delay is reached, the program instructions for the next voltage adjustment can be executed.

[0137] Step S806: After adjusting to the target voltage, the clock module is controlled to adjust the clock frequency of the working clock signal to the target frequency based on the working clock signal.

[0138] This application also provides a non-transient computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to execute the above-described dynamic voltage frequency adjustment method.

[0139] This application also provides a chip including the aforementioned dynamic voltage frequency adjustment circuit. The chip, also known as an integrated circuit (IC), can be, but is not limited to, a System-on-Chip (SOC) chip or a System-in-Package (SIP) chip. The chip sets a voltage regulation frequency that matches the duration of one voltage regulation operation. Before voltage regulation, the clock frequency of the operating clock signal is adjusted to the voltage regulation frequency. At the voltage regulation frequency, the voltage of the operating voltage signal is adjusted to the target voltage. After voltage regulation is completed, the clock frequency of the operating clock signal is adjusted to the target frequency. This can at least partially avoid timing violations and voltage overshoot during voltage regulation.

[0140] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. This chip sets a voltage regulation frequency that matches the duration of each voltage regulation operation. Before voltage regulation, the clock frequency of the operating clock signal is adjusted to the voltage regulation frequency. At the voltage regulation frequency, the voltage of the operating voltage signal is adjusted to the target voltage. After voltage regulation is completed, the clock frequency of the operating clock signal is adjusted to the target frequency. This can at least partially avoid timing violations and voltage overshoot during voltage regulation.

[0141] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A dynamic voltage-frequency regulation circuit, characterized in that, include: The voltage module is used to output the operating voltage signal of the target module; The clock module is used to output the operating clock signal of the target module; The control module is used for: During voltage frequency adjustment, the clock module is controlled to adjust the clock frequency of the working clock signal to the voltage adjustment frequency based on the working clock signal, wherein the voltage adjustment frequency is matched with the duration of one voltage adjustment performed by the voltage module; After adjusting to the voltage regulation frequency, the voltage module is controlled based on the working clock signal to adjust the voltage of the working voltage signal to the target voltage; After adjusting to the target voltage, the clock module is controlled based on the working clock signal to adjust the clock frequency of the working clock signal to the target frequency.

2. The dynamic voltage and frequency adjustment circuit as described in claim 1, characterized in that, The half-clock cycle corresponding to the voltage regulation frequency is matched with the duration of one voltage regulation operation performed by the voltage module.

3. The dynamic voltage and frequency adjustment circuit as described in claim 1, characterized in that, The target frequency is selected from a plurality of preset operating frequencies, the voltage regulation frequency is different from the plurality of preset operating frequencies, and the voltage regulation frequency is less than any of the preset operating frequencies.

4. The dynamic voltage and frequency adjustment circuit as described in claim 1, characterized in that, The control module is used for: After adjusting to the voltage regulation frequency, the voltage regulation voltage sequence is determined based on the voltage change amplitude between the current voltage and the target voltage; The voltage module is controlled to adjust the voltage according to the voltage sequence so as to adjust the working voltage signal to the target voltage. Wherein, the voltage sequence includes the target voltage; or The voltage sequence includes: the target voltage, and one or more intermediate voltages with amplitudes between the current voltage and the target voltage.

5. The dynamic voltage and frequency adjustment circuit as described in claim 4, characterized in that, The target voltage is selected from a plurality of preset operating voltages, and the intermediate voltage is selected from the plurality of preset operating voltages.

6. The dynamic voltage and frequency adjustment circuit as described in any one of claims 1 to 5, characterized in that, The control module includes: First register; Second register; A voltage regulation unit is used to write voltage data to the first register and write first control data to the second register; wherein the first register and the second register are read and written based on the working clock signal; the second register outputs a voltage regulation enable signal based on the first control data; The voltage module is used to adjust the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the voltage regulation enable signal.

7. The dynamic voltage frequency adjustment circuit as described in claim 6, characterized in that, The control module further includes: a first delay unit, used to delay the voltage regulation enable signal for a first duration; The voltage module is used to adjust the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the delayed voltage adjustment enable signal.

8. The dynamic voltage and frequency adjustment circuit as described in claim 6, characterized in that, The voltage regulating unit is configured to perform at least two voltage adjustments to progressively adjust the operating voltage signal to the target voltage: Write the voltage data corresponding to this voltage adjustment to the first register, and write the first control data to the second register; After detecting the voltage corresponding to the voltage data output by the voltage module, or after a delay of at least one clock cycle corresponding to the working clock signal, the voltage data corresponding to the next voltage adjustment is written to the first register, and the first control data is written to the second register.

9. The dynamic voltage and frequency adjustment circuit as described in any one of claims 1 to 5, characterized in that, The control module includes: Third register; Fourth register; A frequency modulation unit is used to write frequency data to the third register and write second control data to the fourth register; wherein the third register and the fourth register are read and written based on the working clock signal; the fourth register outputs a frequency modulation enable signal based on the second control data; The clock module is used to adjust the clock frequency of the working clock signal to the frequency corresponding to the frequency data based on the frequency modulation enable signal.

10. The dynamic voltage frequency adjustment circuit as described in claim 9, characterized in that, The control module further includes: The second delay unit is used to delay the frequency modulation enable signal for a second duration. The clock module is used to adjust the clock frequency of the working clock signal to the frequency corresponding to the frequency data based on the frequency modulation enable signal after a delay.

11. A dynamic voltage frequency regulation method, characterized in that, include: During voltage frequency adjustment, the control clock module adjusts the clock frequency of the working clock signal to the voltage adjustment frequency, wherein the voltage adjustment frequency is matched with the duration of one voltage adjustment performed by the voltage module; After adjusting to the voltage regulation frequency, the voltage module is controlled based on the working clock signal to adjust the voltage of the working voltage signal to the target voltage; After adjusting to the target voltage, the clock module is controlled based on the working clock signal to adjust the clock frequency of the working clock signal to the target frequency.

12. The dynamic voltage frequency adjustment method as described in claim 11, characterized in that, After adjusting to the voltage regulation frequency, controlling the voltage module to adjust the voltage of the working voltage signal to the target voltage based on the working clock signal includes: After adjusting to the voltage regulation frequency, the voltage regulation voltage sequence is determined based on the voltage change amplitude between the current voltage and the target voltage; The voltage module is controlled to adjust the voltage according to the voltage sequence so as to adjust the working voltage signal to the target voltage. Wherein, the voltage sequence includes the target voltage; or The voltage sequence includes the target voltage and one or more intermediate voltages with amplitudes between the current voltage and the target voltage.

13. The dynamic voltage frequency adjustment method as described in claim 12, characterized in that, Based on the operating clock signal, the voltage module is controlled to perform a voltage regulation, including: The voltage data corresponding to this voltage adjustment is written to the first register, and the first control data is written to the second register; wherein the first register and the second register are read and written based on the working clock signal; the second register outputs a voltage regulation enable signal based on the first control data; The voltage module is used to adjust the voltage of the operating voltage signal to the voltage corresponding to the voltage data based on the voltage regulation enable signal.

14. The dynamic voltage frequency adjustment method as described in claim 13, characterized in that, In the case of at least two voltage adjustments, after writing the voltage data corresponding to this voltage adjustment to the first register and writing the first control data to the second register, the method further includes: After detecting the voltage corresponding to the voltage data output by the voltage module, or after a delay of at least one clock cycle corresponding to the working clock signal, the voltage data corresponding to the next voltage adjustment is written to the first register, and the first control data is written to the second register.

15. A chip, characterized in that, Includes any one of the dynamic voltage frequency adjustment circuits in claims 1 to 10.

16. An electronic device, characterized in that, It includes a device body and a chip as described in claim 15 disposed on the device body.

17. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 11 to 14.

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