A low inductance silicon carbide power module

Abstract

The application discloses a low-inductance silicon carbide power module, which comprises a large-area current planning interconnection structure and a terminal direct-connection capacitor structure with a very short path, the mutual inductance between the large-area current planning interconnection structure and the conductive circuit of a ceramic substrate is used to greatly reduce the parasitic inductance in the silicon carbide power module, and the terminal direct-connection capacitor structure is used to shorten the path length from the terminal leading-out position in the power module to the external capacitor, thereby reducing the parasitic inductance of the external connecting circuit of the silicon carbide power module, reducing the parasitic inductance of the whole commutation loop, suppressing the switching voltage overshoot and oscillation, and reducing the working loss.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a low-inductance silicon carbide power module. BACKGROUND

[0002] A power module is a module formed by packaging and integrating a series of power semiconductor chips in a certain topology for the purpose of realizing a certain function. Compared with a topology composed of discrete power chips, the power module has high integration, and has great advantages in electrical performance, thermal performance, safety, chip life, cost, etc.

[0003] With the continuous development of semiconductor power chips, the application environment requirements of important fields such as new energy grid connection, high-voltage direct current transmission, electric vehicles, high-speed rail, aerospace, pulse power, and the like are continuously improved, and the influence of the energy-saving and "double carbon" slogan. The power module is continuously developing towards miniaturization, low loss, high power density, high reliability, and high integration. In particular, the emergence of a new generation of wide-bandgap semiconductor chips represented by silicon carbide and gallium nitride materials gradually replaces silicon-based chips in various industries, accelerating the development of power modules, so that power modules using wide-bandgap power semiconductor chips have smaller size, can work at higher temperature, and work at higher switching frequency, thereby further reducing the size of passive chips and improving the efficiency of the converter. Among them, the power chip represented by the silicon carbide MOSFET is expected to replace the traditional silicon IGBT in medium and high power conditions.

[0004] However, the traditional power module interconnection structure, i.e. aluminum bonding wire, cannot fully exert the performance advantages of silicon carbide. This is because the traditional power module interconnection structure has large parasitic parameters, which easily causes oscillation during high-speed switching of the silicon carbide chip, and aggravates the loss of the silicon carbide chip. At the same time, the traditional power module adopts a lead terminal bolt connection mode to connect with the external circuit, which results in a long path from the terminal to the external capacitor, introducing more line parasitic inductance, which makes it difficult to reduce the overall commutation loop parasitic inductance by optimizing the internal power module.

[0005] In summary, the excellent characteristics of the silicon carbide chip are limited by the packaging method, especially the parasitic inductance caused by the upper surface interconnection and the lead terminal of the silicon carbide chip. Therefore, a new type of packaging structure is needed to overcome the shortcomings of the traditional power module packaging method, and to reduce the overall commutation loop parasitic inductance by controlling the parasitic inductance of the internal and external circuits of the power module. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a low-inductance silicon carbide power module, which greatly reduces the parasitic inductance inside the silicon carbide power module by greatly reducing the mutual inductance between the large-area current planning interconnection structure and the conductive circuit of the ceramic substrate, and shortens the path length from the terminal lead-out position inside the power module to the external capacitor by using the terminal direct connection capacitor structure, thereby reducing the parasitic inductance of the external connection circuit of the silicon carbide power module, and reducing the overall parasitic inductance of the commutation loop, thereby solving the technical problem of large overall parasitic inductance of the commutation loop of the existing silicon carbide power module.

[0007] The present application adopts the following technical solutions:

[0008] A low-inductance silicon carbide power module, comprising a power substrate, the upper surface of the power substrate is provided with a silicon carbide power semiconductor chip, and a current planning interconnection structure with a current direction opposite to that of the power substrate is arranged above the silicon carbide power semiconductor chip, the current planning interconnection structure is connected with the conductive layer of the power substrate through the silicon carbide power semiconductor chip.

[0009] The current planning interconnection structure comprises a lower bridge arm current planning interconnection structure and an oppositely arranged upper bridge arm current planning interconnection structure, and the upper surfaces of the lower bridge arm current planning interconnection structure and the oppositely arranged upper bridge arm current planning interconnection structure are both provided with a chip connector and a substrate connector connected with the chip connector.

[0010] The upper bridge arm current planning interconnection structure is connected with an alternating current lead-out power terminal, and the lower bridge arm current planning interconnection structure is connected with a direct current lead-out power terminal, and the direct current lead-out power terminal is provided with a terminal direct connection capacitor structure.

[0011] Further, the terminal direct connection capacitor structure comprises a direct current circuit board electrically connected with the direct current lead-out power terminal, and a plurality of capacitors are arranged on the direct current circuit board.

[0012] Further, the capacitors with high capacitance among the plurality of capacitors are arranged outside the direct current lead-out power terminal.

[0013] Further, the outside of the upper bridge arm current planning interconnection structure is provided with an alternating current lead-out terminal connector, and the alternating current lead-out power terminal is connected with the alternating current lead-out terminal connector.

[0014] Further, the plane where the current planning interconnection structure is located is parallel to the upper surface of the power substrate.

[0015] Further, the current planning interconnection structure is provided with through holes with the same shape as the silicon carbide power semiconductor chip.

[0016] Further, the upper surface of the power substrate is slotted.

[0017] Further, the silicon carbide power semiconductor chip comprises an upper bridge arm chip and a lower bridge arm chip, the upper bridge arm current planning interconnection structure is arranged above the upper bridge arm chip, and the lower bridge arm current planning interconnection structure is arranged above the lower bridge arm chip.

[0018] The upper bridge arm chip is electrically connected with an upper bridge arm drain electrode on the power substrate, and the lower bridge arm chip is electrically connected with a lower bridge arm drain electrode on the power substrate.

[0019] Further, the power substrate and the current planning interconnection structure are externally wrapped with a bottom shell and a top shell.

[0020] Further, the power substrate is connected with a metal bottom plate.

[0021] Compared with the prior art, the present application has at least the following beneficial effects:

[0022] The present application provides a low-inductance silicon carbide power module, comprising a current planning interconnection structure arranged above a silicon carbide power semiconductor chip and a power substrate for mounting the silicon carbide power semiconductor chip, a conductive layer of the current planning interconnection structure and the power substrate are connected, the current planning interconnection structure is connected with the silicon carbide power semiconductor chip through a chip joint on a lower bridge arm current planning interconnection structure and an upper bridge arm current planning interconnection structure respectively, and is electrically connected with the power substrate through a substrate joint electrically connected with the chip joint, a current direction of the conductive layer on the power substrate is opposite to a current direction on the current planning interconnection structure, the use of a large-area current planning interconnection structure completes the electrical connection of the upper surface of the power semiconductor chip in the power module, and the parasitic inductance in the power module is greatly reduced; a terminal direct connection capacitor structure is adopted near a power terminal lead-out side of the power module, the parasitic inductance of a commutation loop is further reduced by reducing the distance from the terminal to the capacitor, so that the voltage overshoot and oscillation of the power module in the switching process are reduced, the switching speed is accelerated, the switching loss is reduced, and the working efficiency of the power converter is improved.

[0023] The current planning interconnection structure is arranged according to the current flow direction, so that the current flow direction of the upper conductive layer of the power substrate is opposite to the current flow direction on the current planning interconnection structure, thereby the mutual inductance is utilized to weaken the self-inductance value of the internal circuit of the power module, and the parasitic inductance in the power module is reduced.

[0024] Further, the plane where the current planning interconnection structure is located is parallel to the upper surface of the power substrate, the distance between the current planning interconnection structure and the upper conductive layer of the power substrate is ensured to be as close as possible under the condition of ensuring the necessary insulation gap, the mutual inductance between the lines is maximized, the mutual inductance value between the lines is close to the self-inductance value, and the parasitic inductance in the power module is greatly reduced.

[0025] Further, the terminal direct connection capacitor structure places the capacitance of the commutation loop near the end of the power module leading power terminal close to the power module, reducing the parasitic inductance of almost the entire length of the leading terminal compared to the traditional bolted leading terminal.

[0026] Further, the terminal direct connection capacitor structure allows low inductance capacitors to be placed near the leading power terminal, further reducing the parasitic inductance outside the power module.

[0027] Further, the power substrate, the silicon carbide power semiconductor chip mounted on the power substrate, and the current planning interconnection structure are collectively arranged in the bottom shell and the top shell, protecting the power module therein.

[0028] The technical solutions of the present application will be described in further detail below with the aid of the accompanying drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings used in the relative example description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other accompanying drawings can be obtained by those skilled in the art without any creative effort on the basis of these accompanying drawings.

[0030] Figure 1 Explosive schematic diagram of the low inductance silicon carbide power module of the present application;

[0031] Figure 2 Top surface circuit diagram of the power substrate of the silicon carbide power module of the present application and setting position schematic diagram of the silicon carbide power semiconductor chip;

[0032] Figure 3 Schematic diagram of the current planning interconnection structure of the present application;

[0033] Figure 4 Schematic diagram of the internal current flow direction of the silicon carbide power module of the present application;

[0034] Figure 5 Top view schematic diagram of the terminal direct connection capacitor structure of the present application;

[0035] Figure 6 Side view schematic diagram of the terminal direct connection capacitor structure of the present application.

[0036] Wherein: 100. power substrate; 111. first region of upper bridge leg drain on conductive layer on power substrate; 112. second region of upper bridge leg drain on conductive layer on power substrate; 113. lower bridge leg source region on conductive layer on power substrate; 114. upper bridge leg source region on conductive layer on power substrate; 115. first region of lower bridge leg drain on conductive layer on power substrate; 116. second region of lower bridge leg drain on conductive layer on power substrate; 200. current planning interconnect structure; 201. lower bridge leg current planning interconnect structure; 202. upper bridge leg current planning interconnect structure; 211. first chip terminal of lower bridge leg; 212. second chip terminal of lower bridge leg; 213. third chip terminal of lower bridge leg; 214. fourth chip terminal of lower bridge leg; 215. fifth chip terminal of lower bridge leg; 216. sixth chip terminal of lower bridge leg; 217. seventh chip terminal of lower bridge leg; 218. eighth chip terminal of lower bridge leg; 221. first chip terminal of upper bridge leg; 222. second chip terminal of upper bridge leg; 223. third chip terminal of upper bridge leg; 224. fourth chip terminal of upper bridge leg; 225. fifth chip terminal of upper bridge leg; 226. sixth chip terminal of upper bridge leg; 227. seventh chip terminal of upper bridge leg; 228. eighth chip terminal of upper bridge leg; 231. first substrate terminal of lower bridge leg; 232. second substrate terminal of lower bridge leg; 233. third substrate terminal of lower bridge leg; 241. first substrate terminal of upper bridge leg; 242. second substrate terminal of upper bridge leg; 251. first terminal of AC lead-out; 252. second terminal of AC lead-out; 300. silicon carbide power semiconductor chip; 311. first chip of lower bridge leg; 312. second chip of lower bridge leg; 313. third chip of lower bridge leg; 314. fourth chip of lower bridge leg; 315. fifth chip of lower bridge leg; 316. sixth chip of lower bridge leg; 317. seventh chip of lower bridge leg; 318. eighth chip of lower bridge leg; 321. first chip of upper bridge leg; 322. second chip of upper bridge leg; 323. third chip of upper bridge leg; 324. fourth chip of upper bridge leg; 325. fifth chip of upper bridge leg; 326. sixth chip of upper bridge leg; 327. seventh chip of upper bridge leg; 328. eighth chip of upper bridge leg; 400. AC lead-out power terminal; 410. DC lead-out power terminal; 411. first terminal of DC bus positive; 412. second terminal of DC bus positive; 413. terminal of DC bus negative; 501. metal base plate; 511. bottom housing; 512. top housing; 600. terminal direct connection capacitor structure; 610. direct connection circuit board; 620. low inductance capacitor; 630. high capacitance capacitor. DETAILED DESCRIPTION

[0037] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are some of the embodiments of the present application but not all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of the present application.

[0038] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "one side", "one end", "one edge" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can be explicitly or implicitly included one or more. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0039] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] It should be understood that when used in the present specification and the appended claims, the terms "comprise" and "include" indicate the presence of described features, whole, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, whole, steps, operations, elements, components and / or sets thereof.

[0041] It should also be understood that the terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, unless otherwise clear from the context, the singular form "a", "an" and "the" is intended to include the plural form.

[0042] It should be further understood that the term "and / or" as used herein in the specification and in the claims, if any, means any one of the associated listed items or a combination of any of the associated listed items.

[0043] The various structural diagrams according to the disclosed embodiments of the present application are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity and others omitted. The shapes and relative sizes of the various regions, layers, and their relative positions are shown for example only and can vary in actual implementation depending on manufacturing tolerances and technical limitations, and can be designed differently in terms of shape, size, and relative position by those skilled in the art according to actual needs.

[0044] The present application provides a low inductance silicon carbide power module, comprising a power substrate 100 and a current planning interconnection structure 200 connected with the conductive layer on the upper surface of the power substrate 100, a silicon carbide power semiconductor chip 300 is arranged between the power substrate 100 and the current planning interconnection structure 200, and the silicon carbide power semiconductor chip 300 is mounted on the upper surface of the power substrate 100.

[0045] The current direction on the power substrate 100 is opposite to the current direction on the current planning interconnection structure 200.

[0046] The current planning interconnection structure 200 comprises a lower bridge arm current planning interconnection structure 201 and an oppositely arranged upper bridge arm current planning interconnection structure 202, and both the lower bridge arm current planning interconnection structure 201 and the oppositely arranged upper bridge arm current planning interconnection structure 202 comprise a chip terminal and a substrate terminal, wherein the chip terminal and the substrate terminal are electrically connected, the chip terminal is used for connecting with the silicon carbide power semiconductor chip 300, the substrate terminal is used for connecting with the power substrate 100, and the current planning interconnection structure 200 realizes electrical connection with the conductive layer of the power substrate 100 through the silicon carbide power semiconductor chip 300.

[0047] An alternating current lead-out power terminal 400 is connected on the outer side of the upper bridge arm current planning interconnection structure 202, and correspondingly, a direct current lead-out power terminal 410 is arranged on the outer side of the lower bridge arm current planning interconnection structure 201, a terminal direct connection capacitor structure 600 is arranged on the upper surface of the direct current lead-out power terminal 410, and one end of the lead-out power terminal 410 is arranged on the power substrate 100.

[0048] In the embodiment, the terminal direct connection capacitor structure 600 is connected to the lead-out power terminal 410 in proximity through the lower part of the direct connection circuit board 610. Specifically, the terminal direct connection capacitor structure 600 includes a direct current circuit board 610, a low inductance capacitor 620 and a high capacitance capacitor 630. The direct current circuit board 610 is made of a printed circuit board or a laminated busbar according to the required working current. The direct current lead-out power terminal 410 is provided with a direct current bus positive first terminal 411, a direct current bus positive second terminal 412 and a direct current bus negative terminal 413. The direct current circuit board 610 is connected to the direct current bus positive first terminal 411, the direct current bus positive second terminal 412 and the direct current bus negative terminal 413 by soldering, micro-nano metal particle sintering or laser welding. The low inductance capacitor 620, such as a ceramic capacitor and a silicon chip capacitor, is arranged on the side close to the direct current lead-out power terminal 410. The high capacitance capacitor 630, such as a thin film capacitor and an electrolytic capacitor, is arranged on the side away from the direct current lead-out power terminal 410.

[0049] In one possible implementation, a slot is formed in the center of the upper surface of the power substrate 100 for mounting the silicon carbide power semiconductor chip 300.

[0050] The conductive layer on the upper surface of the power substrate 100 mainly includes an upper bridge arm drain first region 111, an upper bridge arm drain second region 112, a lower bridge arm source region 113, an upper bridge arm source region 114, and further includes a lower bridge arm drain first region 115 and a lower bridge arm drain second region 116. The lower bridge arm drain first region 115, the lower bridge arm drain second region 116 and the lower bridge arm source region 113 are arranged between the upper bridge arm drain first region 111 and the upper bridge arm drain second region 112. The lower bridge arm source region 113 and the upper bridge arm source region 114 are arranged at both ends of the power substrate 100.

[0051] In another embodiment, the lower surface of the silicon carbide power semiconductor chip 300 is arranged on the conductive layer on the upper surface of the power substrate 100 to complete electrical connection and transfer heat. The upper surface of the silicon carbide power semiconductor chip 300 is provided with a current planning interconnection structure 200 to complete electrical connection on the upper surface.

[0052] The silicon carbide power semiconductor chip 300 includes a lower bridge arm first chip 311, a lower bridge arm second chip 312, a lower bridge arm third chip 313, a lower bridge arm fourth chip 314, a lower bridge arm fifth chip 315, a lower bridge arm sixth chip 316, a lower bridge arm seventh chip 317 and a lower bridge arm eighth chip 318. Correspondingly, an upper bridge arm first chip 321, an upper bridge arm second chip 322, an upper bridge arm third chip 323, an upper bridge arm fourth chip 324, an upper bridge arm fifth chip 325, an upper bridge arm sixth chip 326, an upper bridge arm seventh chip 327 and an upper bridge arm eighth chip 328 are arranged in the upper bridge arm.

[0053] The current planning interconnection structure 200 is a one-piece high-conductivity metal structure, which connects one side or all of the parallel chips on the surface with the same potential. The overall structure includes three height layers, i.e., a substrate layer, a chip layer, and a wiring layer. The substrate layer is connected with the power substrate 100, the chip layer is connected with the silicon carbide power semiconductor chip 300, and the wiring layer completes the electrical wiring and provides a transition connection joint to the substrate layer and the chip layer.

[0054] The wiring layer layout of the current planning interconnection structure 200 is arranged according to the current flow direction in the internal commutation process of the power module, so that the current direction of the wiring layer of the current planning interconnection structure 200 is opposite to the current direction of the conductive layer on the power substrate 100 opposite to it.

[0055] Correspondingly, the chip joints connected with the lower arm chips are arranged on the lower arm current planning interconnection structure 201 of the current planning interconnection structure 200, including a lower arm first chip joint 211, a lower arm second chip joint 212, a lower arm third chip joint 213, a lower arm fourth chip joint 214, a lower arm fifth chip joint 215, a lower arm sixth chip joint 216, a lower arm seventh chip joint 217, and a lower arm eighth chip joint 218. The chip joints connected with the upper arm chips are arranged on the upper arm current planning interconnection structure 202 of the current planning interconnection structure 200, including an upper arm first chip joint 221, an upper arm second chip joint 222, an upper arm third chip joint 223, an upper arm fourth chip joint 224, an upper arm fifth chip joint 225, an upper arm sixth chip joint 226, an upper arm seventh chip joint 227, and an upper arm eighth chip joint 228. The chips on the silicon carbide power semiconductor chip 300 correspond to the chip joints on the current planning interconnection structure 200 one by one.

[0056] The height of the wiring layer of the current planning interconnection structure 200 is as small as possible in the premise of ensuring the necessary insulation gap and the spacing with the upper conductive layer of the power substrate 100.

[0057] In addition, the substrate joints electrically connected with the lower arm chip joints are arranged on the lower arm current planning interconnection structure 201, including a lower arm first substrate joint 231, a lower arm second substrate joint 232, and a lower arm third substrate joint 233. The substrate joints electrically connected with the upper arm chip joints are arranged on the upper arm current planning interconnection structure 202, including an upper arm first substrate joint 241 and an upper arm second substrate joint 242.

[0058] The outer side of the upper arm current planning interconnection structure 202 is connected with the alternating current lead-out power terminal 400 through an alternating current lead-out first joint 251 and an alternating current lead-out second joint 252.

[0059] In another embodiment of the present application, the power substrate 100, the silicon carbide power semiconductor chip 300 mounted on the power substrate 100, and the current planning interconnection structure 200 are collectively arranged in the bottom housing 511 and the top housing 512, and the bottom of the power substrate 100 is further connected with a metal bottom plate.

[0060] In still another embodiment of the present application, a low-inductance silicon carbide power module is provided, which includes a large-area current planning interconnection structure 200 and a terminal-directly-connected capacitor structure 600 with a very short path. The mutual inductance between the large-area current planning interconnection structure 200 and the conductive circuit of the ceramic substrate is greatly reduced, thereby greatly reducing the parasitic inductance inside the silicon carbide power module. Meanwhile, the terminal-directly-connected capacitor structure 600 is used to shorten the path length from the terminal leading-out position inside the power module to the external capacitor, thereby reducing the parasitic inductance of the external connection circuit of the silicon carbide power module, and further reducing the parasitic inductance of the entire commutation loop, thereby suppressing the switching voltage overshoot and oscillation, and reducing the operating loss.

[0061] Referring to Figure 1 , the low-inductance silicon carbide power module of the present application is of a single-face heat dissipation structure, which includes a power substrate 100, a current planning interconnection structure 200, a silicon carbide power semiconductor chip 300, an alternating-current leading-out power terminal 400, a direct-current leading-out power terminal 410, a metal bottom plate 501, a bottom housing 511, a top housing 512, and a terminal-directly-connected capacitor structure 600.

[0062] Referring to Figure 2 , the upper surface conductive area of the power substrate 100 mainly includes an upper bridge arm drain first region 111, an upper bridge arm drain second region 112, a lower bridge arm source region 113, and an upper bridge arm source region 114. The silicon carbide power semiconductor chip 300 is divided into two groups, the upper bridge arm chips are mounted on the upper bridge arm drain first region 111 and the upper bridge arm drain second region 112, and the lower bridge arm chips are mounted on the lower bridge arm drain first region 115 and the lower bridge arm drain second region 116.

[0063] Referring to Figure 3 , the current planning interconnection structure 200 includes a lower bridge arm current planning interconnection structure 201 and an upper bridge arm current planning interconnection structure 202. The lower bridge arm current planning interconnection structure 201 includes a chip joint and a substrate joint, and the upper bridge arm current planning interconnection structure 202 includes a chip joint, a substrate joint, and an alternating-current leading-out terminal joint.

[0064] Referring to Figure 4 , during the commutation process of the silicon carbide power module, the current flows from the upper bridge arm drain region, flows into the upper bridge arm current planning interconnection structure 202 after passing through the upper bridge arm chips, then flows into the lower bridge arm drain region, flows into the lower bridge arm current planning interconnection structure 201 after passing through the lower bridge arm chips, and finally reaches the lower bridge arm source region 113.

[0065] Please refer to Figure 5 , the terminal direct connection capacitor structure 600 is connected with the DC bus positive terminal 411, 412 and the DC bus negative terminal 413, including the direct connection circuit board 610, the low inductance capacitor 620 and the high capacitance capacitor 630.

[0066] Please refer to Figure 6 , the terminal direct connection capacitor structure 600 is connected with the DC lead-out power terminal 410 through the lower part of the direct connection circuit board 610, the low inductance capacitor 620 is arranged on the side close to the terminal, and the high capacitance capacitor 630 is arranged on the side away from the terminal.

[0067] In an optional embodiment, the embodiment includes one silicon carbide power module, including 16 silicon carbide power semiconductor chips, forming a half-bridge structure. In actual work, other topologies can be formed according to requirements, and the number of parallel chips can be increased or decreased to change the current-carrying capacity or the number of series chips can be increased or decreased to change the withstand voltage capacity, and diode chips can be added according to requirements.

[0068] 1. Adopting current planning interconnection structure 200 to control the internal parasitic inductance of the power module:

[0069] Please refer to Figure 2 , Figure 3 , the current planning interconnection structure 200 is arranged on the upper surface conductive layer corresponding to the power substrate 100 to complete the upper surface interconnection, the upper bridge arm chip of the silicon carbide power semiconductor chip 300 corresponds to the upper bridge arm current planning interconnection structure 202, and the lower bridge arm chip of the silicon carbide power semiconductor chip 300 corresponds to the lower bridge arm current planning interconnection structure 201.

[0070] The arrangement principle of the current planning interconnection structure 200 is that firstly, the current direction of the conductive layer on the power substrate 100 is opposite to the current direction on the current planning interconnection structure 200 in the commutation process, and secondly, the conductive path of the current planning interconnection structure 200 is as close as possible to the conductive layer on the power substrate 100.

[0071] Please refer to Figure 4 , the commutation loop current flows from the upper bridge arm drain region, flows into the upper bridge arm current planning interconnection structure 202 after the upper bridge arm chip, flows through the region opposite to the upper bridge arm drain region on the upper bridge arm current planning interconnection structure 202, the current direction is opposite to that of the upper bridge arm drain region, then flows into the lower bridge arm drain region, and after a very short current path, it flows into the lower bridge arm chip, then flows upward into the lower bridge arm current planning interconnection structure 201, the current direction on the lower bridge arm current planning interconnection structure 201 is still opposite to that of the upper bridge arm drain region, and finally flows into the lower bridge arm source region 113 and flows out of the power module.

[0072] In the whole conductive path, the longest upper bridge arm drain region on the power substrate 100 is weakened by the mutual inductance of the opposite direction current of the lower bridge arm current planning interconnection structure 201 and the upper bridge arm current planning interconnection structure 202, and the inductance of the current planning interconnection structure 200 is also reduced, thereby reducing the parasitic inductance inside the power module.

[0073] 2. Control the external parasitic inductance of the power module by using the terminal direct connection capacitor structure 600

[0074] Please refer to Figure 5 、 Figure 6 In the half-bridge structure, a capacitor needs to be installed between the DC bus positive first terminal 411, the DC bus positive second terminal 412 and the DC bus negative terminal 413 to complete the functions of stabilizing voltage and filtering. The terminal direct connection capacitor structure 600 is used above the DC lead-out power terminal 410 to directly connect the direct connection circuit board 610 with the DC bus positive first terminal 411, the DC bus positive second terminal 412 and the DC bus negative terminal 413, and a low-inductance capacitor 620 is placed near the DC lead-out power terminal 410, thereby limiting the area of the commutation loop outside the power module to a very small range, shortening the loop path and reducing the area of the loop outside the power module, and a high-capacitance capacitor 630 is placed away from the DC lead-out power terminal 410 to complete the requirement of reliably required stable voltage.

[0075] 3. Effect evaluation

[0076] Power module internal inductance control: After using the method of the present application, the power module internal parasitic inductance can be controlled from >8nH to <4nH, and the power module internal parasitic inductance is reduced by more than 50%;

[0077] Power module external inductance control: After using the method of the present application, the power module external loop parasitic inductance is controlled from >12nH to <2nH, and the power module external parasitic inductance is reduced by more than 80%;

[0078] Total parasitic inductance control of the commutation loop: After using the method of the present application, the total parasitic inductance of the commutation loop is controlled from >20nH to <5nH, and the total parasitic inductance of the commutation loop is reduced by more than 75%.

[0079] In summary, the present application is a low-inductance silicon carbide power module, which greatly reduces the parasitic inductance inside the silicon carbide power module by the mutual inductance between the large-area current planning interconnection structure 200 and the conductive circuit of the ceramic substrate, and at the same time, the terminal direct connection capacitor structure 600 is used to shorten the path length from the lead-out position of the internal terminal of the power module to the external capacitor, thereby reducing the parasitic inductance of the external connection circuit of the silicon carbide power module, and thus reducing the parasitic inductance of the whole commutation loop.

[0080] The above merely illustrates the technical idea of the present application, and cannot limit the protection scope of the present application. Any modification made according to the technical idea of the present application on the basis of the technical scheme falls within the protection scope of the present application.

Claims

1. A low inductance silicon carbide power module, characterized by, The power substrate (100) is provided with a silicon carbide power semiconductor chip (300) on the upper surface, and a current planning interconnection structure (200) is arranged above the silicon carbide power semiconductor chip (300) and has a current direction opposite to that of the power substrate (100); the current planning interconnection structure (200) is connected to the conductive layer of the power substrate (100) through the silicon carbide power semiconductor chip (300). The current planning interconnection structure (200) comprises a lower bridge arm current planning interconnection structure (201) and an oppositely arranged upper bridge arm current planning interconnection structure (202), and the lower bridge arm current planning interconnection structure (201) and the oppositely arranged upper bridge arm current planning interconnection structure (202) are both provided with a chip joint and a substrate joint electrically connected to the chip joint. The upper bridge arm current planning interconnection structure (202) is connected to an alternating current lead-out power terminal (400), and the lower bridge arm current planning interconnection structure (201) is provided with a direct current lead-out power terminal (410) on the outer side; the direct current lead-out power terminal (410) is provided with a terminal direct connection capacitor structure (600). The terminal direct connection capacitor structure (600) comprises a direct current circuit board (610) electrically connected to the direct current lead-out power terminal (410), and a plurality of capacitors are arranged on the direct current circuit board (610); the capacitors with high capacitance are arranged on the outer side of the direct current lead-out power terminal (410). The lower bridge arm current planning interconnection structure (201) is also provided with a substrate joint electrically connected to the lower bridge arm chip joint, comprising a lower bridge arm first substrate joint (231), a lower bridge arm second substrate joint (232) and a lower bridge arm third substrate joint (233); the upper bridge arm current planning interconnection structure (202) is provided with a substrate joint electrically connected to the upper bridge arm chip joint, comprising an upper bridge arm first substrate joint (241) and an upper bridge arm second substrate joint (242). The outer side of the upper bridge arm current planning interconnection structure (202) is connected to the alternating current lead-out power terminal (400) through an alternating current lead-out terminal first joint (251) and an alternating current lead-out terminal second joint (252).

2. The low inductance silicon carbide power module of claim 1, wherein, The plane where the current planning interconnection structure (200) is located is parallel to the upper surface of the power substrate.

3. The low inductance silicon carbide power module according to claim 1 or 2, characterized in that, The current planning interconnection structure (200) is provided with a through hole with the same shape as the silicon carbide power semiconductor chip (300).

4. The low inductance silicon carbide power module of claim 1, wherein, The upper surface of the power substrate (100) is slotted.

5. The low inductance silicon carbide power module of claim 1, wherein, The silicon carbide power semiconductor chip (300) comprises an upper bridge arm chip and a lower bridge arm chip, the upper bridge arm current planning interconnection structure (202) is arranged above the upper bridge arm chip, and the lower bridge arm current planning interconnection structure (201) is arranged above the lower bridge arm chip. The upper bridge arm chip is electrically connected to the upper bridge arm drain of the power substrate (100), and the lower bridge arm chip is electrically connected to the lower bridge arm drain of the power substrate (100).

6. The low inductance silicon carbide power module of claim 1, wherein, The power substrate (100) and the current planning interconnection structure (200) are wrapped with a bottom shell (511) and a top shell (512).

7. The low inductance silicon carbide power module of claim 6, wherein, The power substrate (100) is connected to a metal bottom plate (501).

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