A data transmission method based on FPGA
By using CDMA and state machine management technology in FPGA, the data transmission link and interrupt processing are optimized, and the problem of insufficient data transmission delay and stability in the existing technology is solved, efficient and reliable data transmission is achieved, and system performance is improved and flexibility.
Patent Information
- Application Number
- CN202411488937.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2044-10-24
AI Technical Summary
After the ADC sampling rate increases, the existing Ethernet port data acquisition and transmission scheme based on heterogeneous multi-core FPGA cannot effectively use PL terminal DDR for data buffering, resulting in insufficient data transmission delay and stability. .
The FPGA-based data transmission method is adopted to collect data through FIFO buffering ADC, and use CDMA to transmit data between the PL end and the PS end. The state machine manages the device behavior and optimizes the data transmission link and interrupt processing mechanism.
It significantly improves the real-time and stability of data transmission, improves system performance and resource utilization, enhances the response speed and reliability of equipment, reduces maintenance costs, and enhances the flexibility and scalability of the system.
Smart Images
Figure CN119003434B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission method based on FPGA. Background Art
[0002] The existing data collection and transmission scheme for Ethernet port based on heterogeneous multi-core FPGA, after sending the ADC collected data into the FPGA through JESD204, LVDS, SPI and other interfaces, first buffers the collected data through FIFO. When data is transmitted from the PL end to the PS end, two methods are generally adopted. One is to directly transmit the data to the PS end DDR through the HP interface between the PS end and the PL end, and then transmit the data back to the host computer through the network port. The other is to use the PL end DDR as the post-buffer between the PS end and the PL end, and send the data from the PL end DDR to the PS end DDR through memory copy or PS end DMA transfer, and then transmit it back to the host computer through the network port.
[0003] In the above two solutions, after the ADC sampling rate is increased, due to the data bandwidth of the HP interface, the PL-side DDR cannot be effectively utilized for data buffering in the entire data transmission process. In the later stage of the data flow, the network interface bandwidth cannot be fully utilized to ensure low latency and high stability of data transmission. Summary of the invention
[0004] In view of this, an embodiment of the present application provides an FPGA and FPGA-based data transmission, which can improve transmission efficiency.
[0005] The technical solution of the embodiment of the present application is implemented as follows:
[0006] In a first aspect, an embodiment of the present application provides a data transmission method based on FPGA, wherein the FPGA includes a PL end and a PS end, wherein the PL end collects data through a FIFO buffer ADC, the PL end transmits the collected data to the PS end, and the PS end transmits the collected data to a host computer through a network port; data is transmitted between the PL end and the PS end based on CDMA;
[0007] The method is applied to a lower computer, which includes a state machine for controlling a CDMA data transmission process; the state machine includes an idle state, an interrupt waiting state, a CDMA data transmission state, a network port data return state, and a transmission end state; the method includes:
[0008] Before an interrupt is generated, the idle state and the interrupt waiting state are cycled until a first type of interrupt is generated, the interrupt waiting state is entered, and the interrupt flag is set to True; wherein the first type of interrupt indicates that the collected data is buffered from the ADC to the PL end DDR via the FIFO;
[0009] In the interrupt waiting state, in response to detecting that the interrupt flag is True, switching to the CDMA data transmission state;
[0010] In the CDMA data transmission state, controlling the collected data of the PL-side DDR to be transmitted to the PS-side DDR based on CDMA;
[0011] Whenever data is moved from the DDR at the PL end to the DDR at the PS end, the state is switched to the network port data return state and the CDMA transmission state information is returned through the network port data return state, and after all the collected data are transmitted, the transmission end state is entered;
[0012] In the transmission end state, corresponding parameter and state reset is performed, and after the reset is completed, the system switches to the idle state.
[0013] In a second aspect, an embodiment of the present application provides a state machine, which includes an idle state, an interrupt waiting state, a CDMA data transmission state, a network port data return state and a transmission end state; the state machine controls the CDMA data transmission process between the PL end and the PS end in the FPGA through any FPGA-based data transmission method described in the first aspect.
[0014] In a third aspect, an embodiment of the present application provides a lower computer, which includes the state machine described in the second aspect.
[0015] In a fourth aspect, an embodiment of the present application provides an FPGA, wherein the FPGA includes a PL end and a PS end, wherein the PL end collects data by buffering ADC through a FIFO, the PL end transmits the collected data to the PS end, and the PS end transmits the collected data to a host computer through a network port; data transmission is performed between the PL end and the PS end based on CDMA; and the CDMA data transmission process is controlled by any FPGA-based data transmission method described in the first aspect.
[0016] In a fifth aspect, an embodiment of the present application provides a data transmission system, which includes an FPGA, a host computer and a slave computer, the FPGA includes a PL end and a PS end, the PL end collects data by buffering ADC through a FIFO, the PL end transmits the collected data to the PS end, and the PS end transmits the collected data to the host computer through a network port; data transmission is performed between the PL end and the PS end based on CDMA; the slave computer is used to respond to instructions from the host computer and control the CDMA data transmission process through any FPGA-based data transmission method described in the first aspect.
[0017] The embodiments of the present application have the following beneficial effects:
[0018] (1) Significantly improve system performance and resource utilization: Data transmission link reconstruction: By optimizing the data transmission link, the delay and packet loss rate of data transmission are reduced, thereby significantly improving the real-time and stability of data transmission. At the same time, link reconstruction also enables the system to use network resources more efficiently, avoid unnecessary bandwidth waste, and improve overall resource utilization.
[0019] (2) Enhance system response speed and efficiency: Interrupt self-processing: The introduction of interrupt self-processing mechanism enables the lower computer to respond and process interrupts immediately without relying on the polling check of the upper computer, which greatly shortens the interrupt response time and improves the efficiency of the system in handling emergencies. This not only reduces the burden on the upper computer, but also avoids the consumption of system resources caused by the polling mechanism, making the overall system run more smoothly.
[0020] (3) Improve the stability and reliability of equipment operation: Manage equipment behavior based on state machines: Use state machines to manage equipment status, ensuring that the behavior of equipment in different states can be accurately controlled. This management method effectively avoids equipment status confusion caused by program anomalies or logical errors, thereby significantly improving the stability and reliability of equipment operation. At the same time, the use of state machines also makes equipment behavior more predictable, facilitating troubleshooting and maintenance.
[0021] (4) Enhance the flexibility and scalability of the system: Customize the upper and lower computer interaction protocol: By formulating a private interaction protocol, the system can be more closely integrated with the actual application scenario to ensure the accuracy and efficiency of data transmission. This custom protocol approach also enables the system to be flexibly adjusted when facing different needs, enhancing the scalability of the system. At the same time, the private protocol also increases the security of the system and prevents unauthorized external access and interference.
[0022] (5) Reduce maintenance costs and difficulties: Based on the above improvements, the system architecture is clearer and the logic is more rigorous, making system maintenance easier. Due to the implementation of measures such as data transmission link optimization, interrupt self-processing, and state machine management, the system failure rate is greatly reduced, reducing downtime and maintenance costs caused by system failures. In addition, the use of custom interaction protocols also makes communication between systems clearer and easier for maintenance personnel to understand and operate.
[0023] In summary, these technical improvements not only improve the performance, stability and efficiency of the system, but also enhance the flexibility, scalability and maintainability of the system, providing a strong guarantee for the long-term stable operation of the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 It is a data flow diagram of the Ethernet transmission solution of the prior art provided by the embodiment of the present application;
[0026] Figure 2 It is a data flow diagram of the Ethernet transmission solution provided in an embodiment of the present application;
[0027] Figure 3 It is a schematic diagram of the state machine of the lower computer provided in the embodiment of the present application;
[0028] Figure 4 It is a software flow chart of the lower computer provided in the embodiment of the present application;
[0029] Figure 5 It is a flowchart of steps S101-S104 provided in an embodiment of the present application;
[0030] Figure 6 It is a flow chart of interaction between the upper computer and the lower computer provided in the embodiment of the present application;
[0031] Figure 7 It is an instruction definition diagram in the interaction process between the upper computer and the lower computer provided in the embodiment of the present application. DETAILED DESCRIPTION
[0032] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of order, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.
[0033] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0034] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0035] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.
[0036] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.
[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0038] See also Figure 1 , Figure 1It is a data flow diagram of the ADC acquisition Ethernet transmission solution in the prior art provided by the embodiment of the present application, such as Figure 1 As shown, in the prior art, after the ADC collected data is sent to the FPGA through interfaces such as JESD204, LVDS, and SPI, the collected data is first buffered through FIFO. When data is transmitted from the PL end to the PS end, two methods are generally adopted. One is to directly transmit the data to the PS end DDR through the HP interface between the PS end and the PL end, and then transmit the data back to the host computer through the network port. The other is to use the PL end DDR as the post-stage buffer between the PS end and the PL end, and the data is sent from the PL end DDR to the PS end DDR through memory copy or PS end DMA transfer, and then transmitted back to the host computer through the network port.
[0039] In the above two solutions, after the ADC sampling rate is increased, due to the data bandwidth of the HP interface, the PL-side DDR cannot be effectively utilized for data buffering in the entire data transmission process. In the later stage of the data flow, the network interface bandwidth cannot be fully utilized to ensure low latency and high stability of data transmission.
[0040] In view of this, an embodiment of the present application provides an FPGA, which includes a PL end and a PS end. The PL end receives the collected data of the ADC through a FIFO interface, and the PL end transmits the collected data to the PS end. The PS end transmits the collected data to a host computer through a network port; data is transmitted between the PL end and the PS end through AXI CDMA (abbreviated as CDMA, the same below).
[0041] See also Figure 2 , Figure 2 is a data flow diagram of the Ethernet transmission solution provided in the embodiment of the present application, such as Figure 2 As shown in the figure, the traditional ADC data acquisition Ethernet transmission data link is transformed. The main differences from the traditional implementation scheme are:
[0042] In the data flow between the PL and PS ends, CDMA is inserted to move data from memory to memory. Using CDMA for data movement solves the problem of limited bandwidth in traditional solutions for data transmission based on the HP interface. On the other hand, it can make full use of the DDR resources on the PL end to perform a second-level buffer on the data, ensuring high stability of data transmission.
[0043] When data is transmitted from the PS DDR to the host computer through the network port, in order to ensure the efficiency of the program and reduce the complexity of the solution, the network port program is developed completely in a bare metal environment and directly operates physical resources. Compared with the conventional network port program development based on RTOS or Linux operating system, the development difficulty is increased, but the resource overhead caused by system operation is reduced.
[0044] Based on the software concept of agile development, the software code is refactored. By abstracting the device behavior, two design modes, single instance and state machine, are introduced in program design. For decoupling between modules, a single instance shared parameter module is used to uniformly manage device parameters. For device exception handling and interaction with the host computer, a state machine is used for control, which specifies several states of device operation and increases the robustness and logic of the program.
[0045] See also Figure 3 and Figure 4 , Figure 3 is a schematic diagram of a lower computer state machine provided in an embodiment of the present application, Figure 4 is a software flow chart of the lower computer provided in the embodiment of the present application, such as Figure 3 , 4 As shown, the lower computer refines the equipment workflow and controls the data flow through state switching under certain conditions. The equipment operation status is specified as follows:
[0046] IDLE: Idle state:
[0047] In the idle state, the device will detect its own state. If an error is found during the internal state transfer, the device will send the corresponding abnormal state indication back to the upper computer. If there is no abnormality, it will switch to the interrupt waiting state.
[0048] WAIT_INTR: Interrupt waiting state:
[0049] In this solution, the interrupt is mainly used to notify the lower computer program that the ADC data collection and transmission to the PL-side DDR is completed. In the interrupt waiting state, if the upper computer does not issue the start collection command and the data cannot be transferred to the PL-side DDR, the interrupt will not be generated and the device state will switch back to the idle state.
[0050] Before an interrupt is generated, the device will cycle between the idle and interrupt waiting states. Until in the interrupt waiting state, the interrupt flag position is detected to be True, indicating that the ADC sampled data is sent to the DDR cache, and the program switches to the CDMA data transmission state. There are two types of interrupts, one is used to mark the completion of data from the ADC to the PL end DDR through the FIFO buffer; and the other is used to mark the completion of data from the PL end DDR to the PS DDR via CDMA.
[0051] CDMA_TRANSFER: CDMA data transmission status:
[0052] In the CDMA data transmission state, data is moved from the DDR at the PL end to the DDR at the PS end. During the data movement process, the address of the data movement needs to be confirmed, mainly the confirmation of the DDR address at the PL end.
[0053] For address confirmation, first distinguish according to the transmission mode. If it is a continuous transmission mode, the PL-side DDR address switching action needs to be automatically performed internally according to the interrupt count. If it is a single transmission mode, it is necessary to determine whether it exceeds the CDMA single transmission load capacity based on the amount of acquired data. If it exceeds, CDMA packet transmission is required, and during this period, the PL-side DDR address needs to be automatically offset according to the packet count.
[0054] After the CDMA single-packet data transmission is completed, the program switches to the network port data return state.
[0055] SEND_DATA: Network port data transmission status:
[0056] When transmitting data back through the network port, it should be noted that after the transmission of the data moved by CDMA is completed, it is necessary to determine whether it is necessary to return to the CDMA transmission state according to the transmission mode, execute the CDMA data packet operation, and then transmit the network port data again until the required data packet is completely transmitted and enter the transmission end state.
[0057] SEND_OVER: Transmission end status:
[0058] After the network port data is transmitted back, the device will enter the transmission end state. In this state, the device executes the corresponding parameter and state reset actions according to its own operation mode. After the reset is completed, the device returns to the idle state and waits for the next task to be executed.
[0059] The state machine is the core of this method, which defines the various stages and transition conditions in the data transmission process. On this basis, the lower computer executes the following methods:
[0060] Before an interrupt is generated, the idle state and the interrupt waiting state are cycled until a first type of interrupt is generated, the interrupt waiting state is entered, and the interrupt flag is set to True; wherein the first type of interrupt indicates that the collected data is buffered from the ADC to the PL end DDR via the FIFO;
[0061] In the interrupt waiting state, in response to detecting that the interrupt flag is True, switching to the CDMA data transmission state;
[0062] In the CDMA data transmission state, controlling the collected data of the PL-side DDR to be transmitted to the PS-side DDR based on CDMA;
[0063] Whenever data is moved from the DDR at the PL end to the DDR at the PS end, the state is switched to the network port data return state and the CDMA transmission state information is returned through the network port data return state, and after all the collected data are transmitted, the transmission end state is entered;
[0064] In the transmission end state, corresponding parameter and state reset is performed, and after the reset is completed, the system switches to the idle state.
[0065] In some embodiments, the cycling between the idle state and the interrupt wait state comprises:
[0066] In the idle state, the device state is detected, and if there is an abnormality in the internal state flow process, a corresponding abnormal state indication is sent to the upper computer; if there is no abnormality, it switches to the interrupt waiting state;
[0067] In the interrupt waiting state, if the host computer does not issue a start acquisition command and the acquisition data is not transmitted to the PL end DDR, an interrupt is not generated and the system switches to the idle state.
[0068] In some embodiments, controlling the collected data of the PL-side DDR to be transmitted to the PS-side DDR based on CDMA includes:
[0069] Determining a transmission mode, wherein the transmission mode includes a continuous transmission mode or a single transmission mode;
[0070] When the transmission mode is a continuous transmission mode, the DDR address switching of the PL side is automatically performed according to the interrupt count; when the transmission mode is a single transmission mode, it is determined whether the amount of acquired data exceeds the CDMA single transmission load capacity. If so, CDMA packet transmission is performed, wherein the DDR address of the PL side is automatically offset according to the packet count during the CDMA packet transmission.
[0071] In some embodiments, the interrupt waiting state is also used to determine a second type of interrupt, where the second type of interrupt indicates that the collected data is transferred from the PL-side DDR to the PS-side DDR via CDMA.
[0072] In combination with the above embodiments, it can be known that in the interrupt waiting state, once the interrupt of ADC data acquisition completion is detected, the data starts to be transmitted to the PL-side DDR and switches to the CDMA data transmission state. In the CDMA data transmission state, the CDMA mechanism is used to transmit data from the PL-side DDR to the PS-side DDR. After the transmission is completed, the system enters the transmission end state for reset, and finally returns to the idle state to wait for the next operation.
[0073] In the idle state, the system not only waits for the next operation, but also detects its own state. If an abnormality is found in the internal state flow (such as hardware failure, software error, etc.), an abnormal state indication is immediately sent to the host computer so that the host computer can perform remote monitoring and troubleshooting. If there is no abnormality in the detection, the system switches to the interrupt waiting state and prepares to receive new ADC data acquisition interrupts. In addition, the interrupt waiting state also adds response logic to the host computer command. If the host computer does not issue a start acquisition command, even if the ADC completes data acquisition, it will not trigger an interrupt, thereby avoiding invalid data transmission and wasting system resources. At this time, the system remains idle and waits for further instructions from the host computer.
[0074] During CDMA transmission, the selection of continuous transmission mode and single transmission mode is introduced. The continuous transmission mode is suitable for the transmission of large amounts of continuous data. It automatically switches the DDR address through interrupt count to achieve seamless data stream transmission. The single transmission mode is suitable for scenarios with small amounts of data or where the transmission process needs to be finely controlled. When the amount of data exceeds the single transmission load capacity of CDMA, the system will automatically perform packet transmission and automatically adjust the address offset of the DDR on the PL side according to the packet count during the transmission process to ensure the integrity and accuracy of the data.
[0075] In order to enhance the monitorability and debugging capabilities of the system, a mechanism for returning network port data transmission status and CDMA transmission status information is introduced. After completing a CDMA data transfer, the system will return the corresponding transmission status information to the host computer or monitoring system according to the current transmission mode. This information includes but is not limited to transmission speed, transmission data volume, whether an error occurred, etc. When all collected data are transmitted, the system enters the transmission end state and prepares for the next data transmission or enters the idle state to wait for new tasks.
[0076] Through the above embodiments, the FPGA-based data transmission method not only improves the efficiency and reliability of data transmission, but also enhances the flexibility and maintainability of the system.
[0077] In some embodiments, the state machine performs anomaly detection based on a preset state machine value mapping table; the state machine mapping table represents the mapping relationship between the state value corresponding to the state of the state machine and the state execution process; when an anomaly is detected, it switches to the transmission end state, resets the operating parameters and state quantities, and switches to the idle state after the reset is completed.
[0078] Here, please refer to Table 1, which is a state machine value mapping table provided in the embodiment of the present application. As shown in Table 1, for the abnormal monitoring of the device state caused by improper control of the host computer or hardware during the operation of the device, the state value is mapped to the state execution process for management. When an abnormality or error is detected inside the program, it will switch to the SEND_OVER state, reset the parameters and state quantities required for the operation of the device, and after the reset is completed, the program switches the device operation state to the IDLE state, and sends an abnormal alarm data packet to the host computer in this state.
[0079] Table 1
[0080]
[0081] The state machine value mapping table is a data structure used to store the numerical identifier (or state code) corresponding to each state in the state machine and the specific process or operation that should be performed in that state. The mapping table usually contains multiple entries, each of which corresponds to a state code and one or more execution processes. The state code can be an integer, an enumeration value, or any other unique identifier used to distinguish different states in the state machine. By querying the mapping table, the system can quickly determine the operation that should be performed in the current state, thereby ensuring the correctness and stability of the data transmission process.
[0082] At each cycle of the state machine or at a specific time point, the system checks the current state code and compares it with the entry in the state machine value mapping table. If the system finds that the current state code does not match any expected state code in the mapping table, or the state machine encounters a preset error condition (such as timeout, data error, etc.) during execution, it is determined that an exception has occurred. If an exception occurs, the system immediately switches to the transmission end state and stops the current data transmission operation. In the transmission end state, the system resets the operating parameters and state quantities to ensure that all resources are correctly released and reset. After the reset is completed, the system switches from the transmission end state back to the idle state, waiting for the next data transmission task or the host computer's instruction.
[0083] In some embodiments, see Figure 5 , Figure 5 It is a flow chart of steps S101-S104 provided in an embodiment of the present application. The lower computer is connected to the upper computer via TCP. The method also includes steps S101-S104, which will be described in combination with each step.
[0084] In step S101, in response to the connection request sent by the upper computer, the state of the lower computer is returned to the upper computer so that the upper computer can confirm the state of the lower computer.
[0085] In step S102, after the upper computer determines that the status of the lower computer is normal, it responds to the parameters and instructions sent by the upper computer, configures the parameters to the PL end user logic, and waits for an interrupt to be generated before performing data movement.
[0086] In step S103, in response to the interruption, the CDMA data transmission state and the network port data return state are entered; wherein, the upper computer and the lower computer reduce congestion by disabling the Nagle algorithm, and the upper computer side adjusts the sending and receiving buffer sizes based on the data receiving status and disables the interruption decision of the network card.
[0087] In step S104, in response to the completion of the data collection, the state is switched to the idle state, and the next parameter configuration and instruction are waited for.
[0088] For examples, see Figure 6 , Figure 6 is a flow chart of interaction between the host computer and the slave computer provided in the embodiment of the present application, such as Figure 6 As shown in the figure, after the device is powered on, the lower computer program automatically runs and is in a listening state. When the handshake signal sent by the upper computer is detected, the lower computer returns its own initialization state, and the upper computer confirms the device state.
[0089] After confirming that the device initialization status is normal, the host computer executes parameter configuration and command issuance through a private protocol in a specific format agreed upon with the slave computer. The command definition diagram during the interaction between the host computer and the slave computer is as follows: Figure 7 shown.
[0090] After receiving the parameters and instructions sent by the host computer, the lower computer configures the parameters to the PL end user logic and waits for the interrupt to generate before performing the data movement. After the interrupt is generated, the lower computer enters the CDMA data movement and network port data return stage. In this stage, the stability of data transmission is further guaranteed through the TCP connection. The Nagle algorithm is disabled on the upper and lower computers to avoid data buffering caused by the algorithm when a small amount of data is returned. On the upper computer side, adjust the size of the send and receive buffers, disable the interrupt arbitration of the network card, and ensure that the data transmitted by the lower computer is received in real time. The Nagle algorithm, whose full name is the Nagle algorithm proposed by John Nagle, is an algorithm used to reduce the number of small packets in network transmission and thus improve network efficiency. It is mainly used in the TCP protocol. The basic principle of the Nagle algorithm is: when there is data to be sent on a TCP connection, it is not sent out immediately, but waits for a short period of time (usually estimated by an RTT, i.e., round-trip delay) to see if there is more data to be sent. If additional data is generated during this period of time, then these data will be assembled into a larger message and sent together. Doing so can reduce congestion in the network caused by too many small packets.
[0091] After data collection is completed, the lower computer returns its state to the idle state and waits for the next parameter configuration and instruction to be issued.
[0092] In summary, the embodiments of the present application have the following beneficial effects:
[0093] (1) Significantly improve system performance and resource utilization: Data transmission link reconstruction: By optimizing the data transmission link, the delay and packet loss rate of data transmission are reduced, thereby significantly improving the real-time and stability of data transmission. At the same time, link reconstruction also enables the system to use network resources more efficiently, avoid unnecessary bandwidth waste, and improve overall resource utilization.
[0094] (2) Enhance system response speed and efficiency: Interrupt self-processing: The introduction of interrupt self-processing mechanism enables the lower computer to respond and process interrupts immediately without relying on the polling check of the upper computer, which greatly shortens the interrupt response time and improves the efficiency of the system in handling emergencies. This not only reduces the burden on the upper computer, but also avoids the consumption of system resources caused by the polling mechanism, making the overall system run more smoothly.
[0095] (3) Improve the stability and reliability of equipment operation: Manage equipment behavior based on state machines: Use state machines to manage equipment status, ensuring that the behavior of equipment in different states can be accurately controlled. This management method effectively avoids equipment status confusion caused by program anomalies or logical errors, thereby significantly improving the stability and reliability of equipment operation. At the same time, the use of state machines also makes equipment behavior more predictable, facilitating troubleshooting and maintenance.
[0096] (4) Enhance the flexibility and scalability of the system: Customize the upper and lower computer interaction protocol: By formulating a private interaction protocol, the system can be more closely integrated with the actual application scenario to ensure the accuracy and efficiency of data transmission. This custom protocol approach also enables the system to be flexibly adjusted when facing different needs, enhancing the scalability of the system. At the same time, the private protocol also increases the security of the system and prevents unauthorized external access and interference.
[0097] (5) Reduce maintenance costs and difficulties: Based on the above improvements, the system architecture is clearer and the logic is more rigorous, making system maintenance easier. Due to the implementation of measures such as data transmission link optimization, interrupt self-processing, and state machine management, the system failure rate is greatly reduced, reducing downtime and maintenance costs caused by system failures. In addition, the use of custom interaction protocols also makes communication between systems clearer and easier for maintenance personnel to understand and operate.
[0098] In summary, these technical improvements not only improve the performance, stability and efficiency of the system, but also enhance the flexibility, scalability and maintainability of the system, providing a strong guarantee for the long-term stable operation of the system.
[0099] Based on the same inventive concept, a state machine, a lower computer, an FPGA and a data transmission system are also provided in the embodiments of the present application. Since the principle of solving the problem is similar to the above-mentioned FPGA-based data transmission method, reference can be made to the implementation of the method, and the repeated parts will not be repeated.
[0100] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0101] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0102] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0103] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A data transmission method based on FPGA, wherein the FPGA includes a PL terminal and a PS terminal, the PL terminal collects data through a FIFO buffer ADC, the PL terminal transmits the collected data to the PS terminal, and the PS terminal transmits the collected data to a host computer through a network port; characterized in that: The PL end and the PS end perform data transmission based on CDMA; The method is applied to a lower computer, which includes a state machine for controlling a CDMA data transmission process; the state machine includes an idle state, an interrupt waiting state, a CDMA data transmission state, a network port data return state, and a transmission end state; the method includes: Before an interrupt is generated, the idle state and the interrupt waiting state are cycled until a first type of interrupt is generated, the interrupt waiting state is entered, and the interrupt flag is set to True; wherein the first type of interrupt indicates that the collected data is buffered from the ADC to the PL end DDR via the FIFO; In the interrupt waiting state, in response to detecting that the interrupt flag is True, switching to the CDMA data transmission state; In the CDMA data transmission state, controlling the collected data of the PL-side DDR to be transmitted to the PS-side DDR based on CDMA; Whenever data is moved from the DDR at the PL end to the DDR at the PS end, the state is switched to the network port data return state and the CDMA transmission state information is returned through the network port data return state, and after all the collected data are transmitted, the transmission end state is entered; In the transmission end state, corresponding parameter and state reset is performed, and after the reset is completed, the system switches to the idle state.
2. The method according to claim 1, characterized in that The step of cycling between the idle state and the interrupt waiting state comprises: In the idle state, the device state is detected, and if there is an abnormality in the internal state flow process, a corresponding abnormal state indication is sent to the upper computer; if there is no abnormality, it switches to the interrupt waiting state; In the interrupt waiting state, if the host computer does not issue a start acquisition command and the acquisition data is not transmitted to the PL end DDR, an interrupt is not generated and the system switches to the idle state.
3. The method according to claim 1, characterized in that The controlling the collected data of the PL-side DDR to be transmitted to the PS-side DDR based on CDMA includes: Determining a transmission mode, wherein the transmission mode includes a continuous transmission mode or a single transmission mode; When the transmission mode is a continuous transmission mode, the DDR address switching of the PL side is automatically performed according to the interrupt count; when the transmission mode is a single transmission mode, it is determined whether the amount of acquired data exceeds the CDMA single transmission load capacity. If so, CDMA packet transmission is performed, wherein the DDR address of the PL side is automatically offset according to the packet count during the CDMA packet transmission.
4. The method according to claim 1, characterized in that: The state machine performs anomaly detection based on a preset state machine value mapping table; the state machine mapping table represents a mapping relationship between a state value corresponding to the state of the state machine and a state execution process; When an abnormality is detected, the state is switched to the transmission end state, and the operating parameters and state quantities are reset, and after the reset is completed, the state is switched to the idle state.
5. The method according to claim 1, characterized in that The lower computer is connected to the upper computer via TCP, and the method further comprises: In response to the connection request sent by the upper computer, return its own status to the upper computer so that the upper computer can confirm the status of the lower computer; After the upper computer determines that the state of the lower computer is normal, it responds to the parameters and instructions sent by the upper computer, configures the parameters to the PL end user logic, and waits for an interrupt to be generated before performing data movement; In response to the interruption, the CDMA data transmission state and the network port data return state are entered; wherein the host computer and the slave computer reduce congestion by disabling the Nagle algorithm, and the host computer side adjusts the sending and receiving buffer sizes and disables the interruption decision of the network card based on the data receiving state; In response to the completion of the data collection, the state of the device is switched to the idle state, and the next parameter configuration and instruction are waited for.
6. The method according to claim 1, characterized in that The interrupt waiting state is also used to determine a second type of interrupt, where the second type of interrupt indicates that the collected data is transferred from the PL-side DDR to the PS-side DDR via CDMA.
7. A state machine, characterized in that: The state machine includes an idle state, an interrupt waiting state, a CDMA data transmission state, a network port data return state and a transmission end state; the state machine controls the CDMA data transmission process between the PL end and the PS end in the FPGA through the FPGA-based data transmission method described in any one of claims 1 to 6.
8. A lower computer, characterized in that: The lower computer includes the state machine described in claim 7.
9. An FPGA, characterized in that: The FPGA includes a PL end and a PS end, the PL end buffers ADC collected data through a FIFO, the PL end transmits the collected data to the PS end, and the PS end transmits the collected data to a host computer through a network port; it is characterized in that data transmission between the PL end and the PS end is based on CDMA; the CDMA data transmission process is controlled by the FPGA-based data transmission method described in any one of claims 1 to 6.
10. A data transmission system, characterized in that: The data transmission system includes an FPGA, a host computer and a slave computer, the FPGA includes a PL terminal and a PS terminal, the PL terminal collects data by buffering ADC through a FIFO, the PL terminal transmits the collected data to the PS terminal, and the PS terminal transmits the collected data to the host computer through a network port; The PL end and the PS end perform data transmission based on CDMA; the lower computer is used to respond to the instructions of the upper computer and control the CDMA data transmission process through the FPGA-based data transmission method described in any one of claims 1 to 6.