A method for preparing a self-aligned gate GaN HEMT device

Abstract

The present invention discloses a method for fabricating a self-aligned gate GaN HEMT device, comprising: providing a wafer; forming a first regrown region and a second regrown region on the wafer surface; using the silicon nitride layer in the middle region as a mask, etching both sides of the silicon dioxide layer in the middle region with an etching solution, so that the silicon nitride layer and the silicon dioxide layer form a T-shaped structure; forming a source electrode on the first N+GaN layer, and a drain electrode on the second N+GaN layer; depositing silicon nitride dielectric layers in the first region, the middle region, and the second region, and polishing them to flatten the device top surface and expose the silicon dioxide layer in the middle region; etching away the silicon dioxide layer in the middle region to form a groove, and fabricating a gate electrode in the groove; and etching the silicon nitride dielectric layers in the first and second regions of the device using the gate electrode as a mask to expose the source and drain electrodes. The present invention can improve the performance of GaN HEMT devices.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a method for preparing a self-aligned gate GaN HEMT device. Background Art

[0002] GaN HEMT devices, with their excellent material properties, have become a key device technology for millimeter-wave applications. Driven by emerging fields such as 6G communications, automotive radar, and medical imaging, demand for GaN RF devices is growing. Consequently, GaN HEMT devices must continuously improve their frequency characteristics to meet the demands of RF applications. For example, in 6G wireless communications, equipment operating frequencies can reach the terahertz range, requiring GaN RF devices to achieve characteristic frequencies exceeding 100G. While there are scientific research reports on high-frequency GaN HEMT devices, their device structures and processes are extremely complex, resulting in poor feasibility. Device technology capable of mass production at these frequencies has yet to emerge.

[0003] Improving the frequency characteristics of GaN millimeter-wave devices requires scaling both the lateral and longitudinal dimensions of the devices. Vertical scaling shortens the gate-to-channel distance by using a thin, strongly polarized AlN barrier, mitigating short-channel effects. Lateral scaling requires reducing both the gate length and the source-drain spacing. Simply reducing the device gate length, while increasing the frequency, can produce negative parasitic effects. For example, it generates source-drain parasitic resistance. More importantly, the depletion region near the drain, which expands with increasing source-drain voltage, blocks the enhancement of the lateral electric field beneath the gate. This results in a decrease in the macroscopic average electron drift velocity, an increase in drain delay, and thus hinders frequency performance improvement. Therefore, it is necessary to reduce contact resistance and the source-drain spacing. Due to the difficulty of GaN ion implantation, the contact resistance is typically reduced by growing N+GaN. After growth, the N+GaN outside the source-drain region is removed by etching or etching masking. The gate is then fabricated between the source and drain regions, and the source-drain spacing is directly determined by the overlay accuracy of the photolithography. To address this issue, HRL Laboratories pioneered self-aligned gate technology. However, existing self-aligned gate technology is complex and has a low yield rate. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a method for preparing a self-aligned gate GaN HEMT device. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a method for preparing a self-aligned gate GaN HEMT device, comprising:

[0006] Providing a wafer, the wafer comprising a substrate, a gallium nitride layer, a barrier layer, a silicon dioxide layer, and a silicon nitride layer stacked in sequence;

[0007] Etching away the silicon nitride layer, the silicon dioxide layer, the barrier layer, and at least a portion of the gallium nitride layer in the first region and the second region of the device to form a first regrown region and a second regrown region, respectively;

[0008] Using the silicon nitride layer in the middle region of the device as a mask, an etching solution is used to etch both sides of the silicon dioxide layer in the middle region of the device, so that the silicon nitride layer and the silicon dioxide layer in the middle region of the device form a T-shaped structure;

[0009] Growing N+GaN in the first region, the middle region, and the second region of the device, forming a first N+GaN layer in the first regrown region, forming a second N+GaN layer in the second regrown region, and forming a polycrystalline GaN layer on the silicon nitride layer; forming a source electrode on the first N+GaN layer, and forming a drain electrode on the second N+GaN layer;

[0010] Depositing a silicon nitride dielectric layer in the first region, the middle region, and the second region of the device to cover the source electrode, the drain electrode, and the polycrystalline GaN layer, and polishing the first region, the middle region, and the second region of the device to flatten the upper surfaces of the first region, the middle region, and the second region of the device and expose the silicon dioxide layer in the middle region of the device;

[0011] The silicon dioxide layer in the middle area of ​​the device is etched away to form a groove, and a gate electrode is formed in the groove and on the upper surface of the silicon nitride dielectric layer in the first area and the silicon nitride dielectric layer in the second area of ​​the device;

[0012] Using the gate electrode as a mask, etching the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device to expose the source electrode and the drain electrode;

[0013] The middle region of the device is located between the first region and the second region.

[0014] Optionally, etching away the silicon nitride layer, the silicon dioxide layer, the barrier layer, and at least a portion of the gallium nitride layer in the first region and the second region of the device to form a first regrown region and a second regrown region, respectively, includes:

[0015] Coating a layer of photoresist on the upper surface of the silicon nitride layer, and etching the photoresist, silicon dioxide layer, and silicon nitride layer in the first and second regions of the device using F-based plasma;

[0016] The photoresist in the middle region of the device is removed using a degumming solvent. The silicon dioxide layer and silicon nitride layer in the middle region of the device are used as masks. Cl-based plasma is used to etch the barrier layer and at least a portion of the gallium nitride layer in the first region of the device to form a first regrown region. The barrier layer and at least a portion of the gallium nitride layer in the second region of the device are also etched using Cl-based plasma to form a second regrown region.

[0017] Optionally, before forming the gate electrode in the groove and on the upper surface of the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device, the method further includes:

[0018] A silicon nitride film is deposited in the groove and on the upper surface of the silicon nitride dielectric layer, and then the silicon nitride film on the upper surface of the silicon nitride dielectric layer and the silicon nitride film at the bottom of the groove are etched away, leaving the silicon nitride film on the sidewall of the groove.

[0019] Optionally, etching away the silicon nitride film on the upper surface of the silicon nitride dielectric layer and etching away the silicon nitride film at the bottom of the groove includes:

[0020] The silicon nitride film on the upper surface of the silicon nitride dielectric layer and the silicon nitride film at the bottom of the groove are etched away using F-based plasma.

[0021] Optionally, the etching solution is a buffered oxide etching solution.

[0022] Optionally, growing N+GaN in the first region, the middle region, and the second region of the device includes:

[0023] Using molecular beam epitaxy, N+GaN is grown in the first, middle, and second regions of the device.

[0024] Optionally, a silicon nitride dielectric layer is deposited in the first region, the middle region, and the second region of the device, and the silicon nitride dielectric layer at least covers two sides of the silicon dioxide layer.

[0025] Optionally, polishing the first region, the middle region, and the second region of the device includes:

[0026] The first region, the middle region and the second region of the device are polished by chemical mechanical polishing.

[0027] Optionally, etching the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device using the gate electrode as a mask includes:

[0028] The silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device are etched using F-based plasma.

[0029] Beneficial effects of the present invention:

[0030] 1. The selectivity ratios of silicon nitride and silicon dioxide layers for wet etching using a buffered oxide etchant are different. After reducing the lateral width of silicon dioxide, a T-shaped structure is formed. During the growth of N+GaN, the silicon nitride layer shields the gate electrode area. The silicon nitride layer is subsequently removed during the planarization process to achieve selective growth of N+GaN, thus overcoming the process complexity and difficulty of using wet etching to remove polycrystalline GaN on the mask surface.

[0031] 2. Use the gate electrode as a mask to etch the silicon nitride dielectric, exposing the source and drain electrodes while forming a support layer for the gate electrode. This reduces parasitic capacitance and avoids the step of photolithography and hole opening. The formed gate electrode support is also conducive to improving the yield rate.

[0032] 3. Compatible with molecular beam epitaxy and metal organic chemical vapor deposition N+GaN processes; among them, molecular beam epitaxy is carried out in an ultra-high vacuum environment, and the mean free path of molecules (atoms) is very large, making it difficult to reach the inner side of the T-shaped structure; metal organic chemical vapor deposition is heteroepitaxial on silicon nitride and silicon dioxide, and is also not easy to adhere to the T-shaped structure. Therefore, both processes can achieve selective growth of N+GaN.

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a flow chart of a method for preparing a self-aligned gate GaN HEMT device provided by an embodiment of the present invention;

[0035] FIG2(a) to (i) are schematic diagrams of a method for fabricating a self-aligned gate GaN HEMT device according to an embodiment of the present invention;

[0036] Figures 3(a) to 3(c) is another schematic diagram of a method for fabricating a self-aligned gate GaN HEMT device provided by an embodiment of the present invention;

[0037] Figures 4(a) to 4(h) This is another schematic diagram of a method for preparing a self-aligned gate GaN HEMT device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0039] To increase the operating frequency of GaN HEMT (gallium nitride high electron mobility transistor) devices, reducing device size is the most direct and important approach. When gate lengths are reduced below 100nm, severe short-channel effects, large source-drain parasitic resistance, and increased drain delay with increasing source-drain voltage become significant factors limiting the frequency characteristics of HEMT devices. The impact of short-channel effects can be mitigated using thin AlN (aluminum nitride) barrier layers, while the effects of parasitic resistance and drain delay must be addressed by using N+GaN (heavily N-type doped GaN) and reducing the source-drain spacing. Compared to silicon-based MOSFETs (metal oxide semiconductor field-effect transistors), which use polysilicon gates and ion implantation to achieve self-aligned source-drain alignment, GaN HEMTs require high ion implantation activation temperatures and low activation efficiency. Furthermore, the mask materials used for implantation and activation pose compatibility issues with subsequent processes, making their application difficult. Usually, the parasitic resistance is reduced by growing N+GaN, but source and drain lithography selection and gate lithography are required before or after growth, and alignment and overlay are required between the two lithography processes. For example, taking a gate length of 150nm as an example, in order to successfully produce a device with a source-drain spacing of less than 250nm, the overlay error needs to be kept within 50nm. Due to the limitations of the current GaN process and the capacity of mainstream production lines for III-V compound semiconductors, such conditions are difficult to achieve. In response to such difficulties, HRL Laboratories proposed gate self-alignment technology, which can effectively shorten the source-drain spacing. However, the complex process steps and high production difficulty of this technology also bring problems of high cost and low yield for large-scale applications.

[0040] In light of this, the present invention provides a method for fabricating a self-aligned gate GaN HEMT device. Using silicon nitride and silicon dioxide as masks, the device forms a T-shaped structure through etching and wet etching, enabling selective growth of N+GaN. This method also simplifies the fabrication steps for source / drain electrodes and gate electrode supports, improving yield and reducing costs. Furthermore, the process is compatible with the capabilities of current mainstream GaN and III-V compound semiconductor production lines, enabling lower parasitic resistance, higher gain, and higher frequency characteristics for GaN HEMT devices.

[0041] See Figure 1 , Figure 1 FIG2 is a flow chart of a method for fabricating a self-aligned gate GaN HEMT device according to an embodiment of the present invention. FIG2(a) to (i) are schematic diagrams of a method for fabricating a self-aligned gate GaN HEMT device according to an embodiment of the present invention. The method for fabricating a self-aligned gate GaN HEMT device according to the present invention includes:

[0042] S101. Provide a wafer, wherein the wafer includes a substrate, a gallium nitride layer, a barrier layer, a silicon dioxide layer, and a silicon nitride layer stacked in sequence, as shown in FIG2(a).

[0043] Specifically, in this embodiment, a substrate is first provided, which includes a substrate, a gallium nitride layer and a barrier layer, and a silicon dioxide layer and a silicon nitride layer are deposited on the upper surface of the barrier layer to form a wafer; optionally, the substrate can be any one of a silicon carbide substrate, an aluminum oxide substrate or a silicon substrate, and the material of the barrier layer is AlN.

[0044] S102 , etching away the silicon nitride layer, silicon dioxide layer, barrier layer, and at least a portion of the gallium nitride layer in the first region and the second region of the device to form a first regrown region and a second regrown region, respectively, as shown in FIG2( b ).

[0045] Specifically, in this embodiment, the silicon nitride layer, the silicon dioxide layer, the barrier layer, and at least a portion of the gallium nitride layer in the first region and the second region of the device are etched away to form a first regrown region and a second regrown region, respectively, including:

[0046] A layer of photoresist is coated on the upper surface of the silicon nitride layer. Using the photoresist in the middle region of the device as a mask, F-based plasma is used to etch the photoresist, silicon dioxide layer, and silicon nitride layer in the first and second regions of the device. Due to the lateral etching effect, the silicon nitride layer and silicon dioxide layer shrink slightly in the lateral direction. It should be noted that due to different material properties, the F-based plasma does not etch the barrier layer.

[0047] The photoresist in the middle area of ​​the device is removed using a degumming solvent. The silicon dioxide layer and silicon nitride layer in the middle area of ​​the device are used as masks. Cl-based plasma is used to etch the barrier layer and at least a portion of the gallium nitride layer in the first area of ​​the device to form a first regrown area. The barrier layer and at least a portion of the gallium nitride layer in the second area of ​​the device are also etched using Cl-based plasma to form a second regrown area. The formed first and second regrown areas provide contact for subsequently formed N+GaN and two-dimensional electron gas channels.

[0048] S103 , using the silicon nitride layer in the middle region of the device as a mask, and using an etching solution to etch both sides of the silicon dioxide layer in the middle region of the device, so that the silicon nitride layer and the silicon dioxide layer in the middle region of the device form a T-shaped structure, as shown in FIG2( c ).

[0049] Specifically, in this embodiment, the etching solution is a buffered oxide etching solution, wherein the etching rate of silicon nitride by the buffered oxide etching solution is much lower than the etching rate of silicon dioxide. Therefore, silicon nitride is used as a mask.

[0050] S104. Grow N+GaN in the first region, the middle region, and the second region of the device, form a first N+GaN layer in the first regrown region, form a second N+GaN layer in the second regrown region, and form a polycrystalline GaN layer on the silicon nitride layer; prepare a source electrode on the first N+GaN layer, and prepare a drain electrode on the second N+GaN layer, as shown in Figure 2(d).

[0051] Specifically, in this embodiment, growing N+GaN in the first region, the middle region, and the second region of the device includes:

[0052] N+GaN is grown in the first, middle and second regions of the device using molecular beam epitaxy or metal organic chemical vapor deposition.

[0053] It should be noted that, due to the lattice mismatch between N+GaN and the silicon nitride layer, polycrystalline GaN is grown on the silicon nitride layer.

[0054] S105. Depositing a silicon nitride dielectric layer in the first region, the middle region, and the second region of the device to cover the source electrode, the drain electrode, and the polycrystalline GaN layer, and polishing the first region, the middle region, and the second region of the device to flatten the upper surfaces of the first region, the middle region, and the second region of the device, and exposing the silicon dioxide layer in the middle region of the device, as shown in Figures 2(e) and (f).

[0055] Specifically, in this embodiment, a silicon nitride dielectric layer is deposited in the first region, the middle region, and the second region of the device, and the silicon nitride dielectric layer at least covers both sides of the silicon dioxide layer.

[0056] S106, etching the silicon dioxide layer in the middle area of ​​the device to form a groove, and preparing a gate electrode in the groove and on the upper surface of the silicon nitride dielectric layer in the first area and the silicon nitride dielectric layer in the second area of ​​the device, as shown in Figures 2(g) and (h).

[0057] Specifically, in this embodiment, Figures 3(a) to 3(c) is another schematic diagram of a method for preparing a self-aligned gate GaN HEMT device provided by an embodiment of the present invention, such as Figure 3(a) and 3(b) As shown, before forming the gate electrode in the groove and on the upper surface of the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device, the method further includes:

[0058] A silicon nitride film is deposited in the groove and on the upper surface of the silicon nitride dielectric layer, and then the silicon nitride film on the upper surface of the silicon nitride dielectric layer and the silicon nitride film at the bottom of the groove are etched away, leaving the silicon nitride film on the sidewall of the groove.

[0059] It should be noted that silicon nitride has good conformal coverage and can cover the steps of the gate electrode groove;

[0060] Forming a silicon nitride film on the sidewalls of the groove can reduce the gate length.

[0061] Further, etching away the silicon nitride film on the upper surface of the silicon nitride dielectric layer and etching away the silicon nitride film at the bottom of the groove, including:

[0062] The silicon nitride film on the upper surface of the silicon nitride dielectric layer and the silicon nitride film at the bottom of the groove are etched away using F-based plasma.

[0063] In this embodiment, polishing the first region, the middle region, and the second region of the device includes:

[0064] The first region, the middle region and the second region of the device are polished by chemical mechanical polishing.

[0065] S107, using the gate electrode as a mask, etching the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device to expose the source electrode and the drain electrode, as shown in FIG2(i);

[0066] The middle region of the device is located between the first region and the second region.

[0067] Specifically, in this embodiment, etching the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device using the gate electrode as a mask includes:

[0068] The silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device are etched using F-based plasma to reduce parasitic capacitance and form gate electrode support at the same time.

[0069] In summary, the method for preparing a self-aligned gate GaN HEMT device provided by the present invention has the following beneficial effects:

[0070] 1. The selectivity ratios of silicon nitride and silicon dioxide layers for wet etching using a buffered oxide etchant are different. After reducing the lateral width of silicon dioxide, a T-shaped structure is formed. During the growth of N+GaN, the silicon nitride layer shields the gate electrode area. The silicon nitride layer is subsequently removed during the planarization process to achieve selective growth of N+GaN, thus overcoming the process complexity and difficulty of using wet etching to remove polycrystalline GaN on the mask surface.

[0071] 2. Use the gate electrode as a mask to etch the silicon nitride dielectric, exposing the source and drain electrodes while forming a support layer for the gate electrode. This reduces parasitic capacitance and avoids the step of photolithography and hole opening. The formed gate electrode support is also conducive to improving the yield rate.

[0072] 3. Compatible with molecular beam epitaxy and metal organic chemical vapor deposition N+GaN processes; among them, molecular beam epitaxy is carried out in an ultra-high vacuum environment, and the mean free path of molecules (atoms) is very large, making it difficult to reach the inner side of the T-shaped structure; metal organic chemical vapor deposition is heteroepitaxial on silicon nitride and silicon dioxide, and is also not easy to adhere to the T-shaped structure. Therefore, both processes can achieve selective growth of N+GaN.

[0073] In an optional embodiment of the present invention, see Figures 4(a) to 4(h) , Figures 4(a) to 4(h) FIG. 1 is another schematic diagram of a method for fabricating a self-aligned gate GaN HEMT device according to an embodiment of the present invention. The GaN HEMT device is fabricated by the following process, specifically:

[0074] Providing a wafer, the wafer comprising a substrate, a gallium nitride layer, a barrier layer, and a silicon dioxide layer stacked in sequence;

[0075] The silicon dioxide layer, the barrier layer, and at least a portion of the gallium nitride layer in the first and second regions of the device are etched away to form a first regrown region and a second regrown region, respectively. It should be noted that the first and second regrown regions are formed by etching the regrown regions using silicon dioxide as a mask.

[0076] N+GaN is grown in the first, middle, and second regions of the device, a first N+GaN layer is formed in the first regrown region, a second N+GaN layer is formed in the second regrown region, and a polycrystalline GaN layer is formed on the silicon dioxide layer; a source electrode is formed on the first N+GaN layer, and a drain electrode is formed on the second N+GaN layer, as shown in FIG4(a);

[0077] A silicon nitride dielectric layer is deposited on the first, middle, and second regions of the device to cover the source electrode, drain electrode, and polycrystalline GaN layer. The first, middle, and second regions of the device are then polished to flatten the upper surfaces of the first, middle, and second regions of the device and expose the silicon dioxide layer in the middle region of the device, as shown in Figures 4(b) and (c);

[0078] After the polycrystalline GaN is etched away by Cl-based plasma, silicon dioxide is removed by BOE to form a gate groove. A silicon nitride film is deposited to cover the groove, and the silicon nitride at the bottom is etched to form a sidewall to isolate the source and drain. Finally, the gate is formed, as shown in Figures 4(d), (e), and (f).

[0079] Using the gate electrode as a mask, the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device are etched to expose the source electrode and the drain electrode, as shown in FIG4(h).

[0080] In an optional embodiment of the present invention, a GaN HEMT device is prepared by the following process, specifically:

[0081] The wafer material uses a silicon carbide substrate, the barrier layer is composed of aluminum nitride, and the barrier layer thickness is 3 to 5 nm;

[0082] Plasma-enhanced chemical vapor deposition was used to deposit 250nm of silicon dioxide and 50nm of silicon nitride on the wafer surface;

[0083] A negative photoresist is coated on the surface of the wafer, and a photoresist mask with a length of 200 nm is formed on the surface by photolithography and development;

[0084] Using F-based inductively coupled plasma etching with carbon tetrafluoride and oxygen as the etching gases, both sides of the photoresist mask were etched to form silicon nitride and silicon dioxide patterns with a height of 300 nm and a length of 200 nm;

[0085] Use a stripping solution to clean and remove the remaining photoresist mask;

[0086] The barrier layer and the gallium nitride layer are etched using Cl-based gas inductively coupled plasma, with chlorine and boron trichloride as the etching gases, and the etching depth is about 50nm;

[0087] Use BOE to etch silicon dioxide, shrinking it by 60nm on both sides. At this point, the length of silicon oxide is 80nm, and the length of silicon nitride is about 200nm.

[0088] Use organic metal chemical vapor deposition (MOCVD) to deposit 80nm of N+GaN to contact the two-dimensional electron gas channel below the barrier layer.

[0089] Photolithography of source and drain patterns on both sides of the middle area, evaporation of Ti and Au, stripping of metal, and fabrication of source and drain electrodes;

[0090] 500nm silicon nitride was deposited using plasma-enhanced chemical vapor deposition;

[0091] Chemical mechanical polishing is used to flatten the wafer surface while exposing the silicon dioxide;

[0092] Use BOE to etch silicon dioxide to form gate grooves;

[0093] Photolithography of the gate pattern is performed above the gate groove, Ni and Au are evaporated, and the metal is stripped off to form the gate. The gate has a T-shaped structure with a top length of 600nm and a bottom length of 80nm.

[0094] F-based inductively coupled plasma etching is used, with carbon tetrafluoride and oxygen as etching gases, to expose the source and drain electrodes.

[0095] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0096] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0097] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for preparing a self-aligned gate GaN HEMT device, characterized in that: include: Providing a wafer, the wafer comprising a substrate, a gallium nitride layer, a barrier layer, a silicon dioxide layer, and a silicon nitride layer stacked in sequence; Etching the silicon nitride layer, the silicon dioxide layer, the barrier layer, and at least a portion of the gallium nitride layer in the first and second regions of the device to form a first regrown region and a second regrown region, respectively; Using the silicon nitride layer in the middle region of the device as a mask, etching the two sides of the silicon dioxide layer in the middle region of the device with an etching solution, so that the silicon nitride layer and the silicon dioxide layer in the middle region of the device form a T-shaped structure; Growing N+GaN in the first region, the middle region, and the second region of the device, forming a first N+GaN layer in the first regrown region, forming a second N+GaN layer in the second regrown region, and forming a polycrystalline GaN layer on the silicon nitride layer; forming a source electrode on the first N+GaN layer, and forming a drain electrode on the second N+GaN layer; Depositing a silicon nitride dielectric layer in the first region, the middle region, and the second region of the device to cover the source electrode, the drain electrode, and the polycrystalline GaN layer, and polishing the first region, the middle region, and the second region of the device to flatten the upper surfaces of the first region, the middle region, and the second region of the device and expose the silicon dioxide layer in the middle region of the device; Etching the silicon dioxide layer in the middle region of the device to form a groove, and preparing a gate electrode in the groove and on the upper surface of the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device; Using the gate electrode as a mask, etching the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device to expose the source electrode and the drain electrode; The middle region of the device is located between the first region and the second region.

2. The method for preparing a self-aligned gate GaN HEMT device according to claim 1, wherein: The step of etching the silicon nitride layer, the silicon dioxide layer, the barrier layer, and at least a portion of the gallium nitride layer in the first and second regions of the device to form a first regrown region and a second regrown region, respectively, comprises: Coating a layer of photoresist on the upper surface of the silicon nitride layer, and etching the photoresist, the silicon dioxide layer, and the silicon nitride layer in the first and second regions of the device using F-based plasma; The photoresist in the middle region of the device is removed using a degumming solvent, and the silicon dioxide layer and the silicon nitride layer in the middle region of the device are used as masks. The barrier layer and at least a portion of the gallium nitride layer in the first region of the device are etched using a Cl-based plasma to form a first regrown region. The barrier layer and at least a portion of the gallium nitride layer in the second region of the device are etched using a Cl-based plasma to form a second regrown region.

3. The method for preparing a self-aligned gate GaN HEMT device according to claim 1, wherein: Before forming gate electrodes in the groove and on the upper surfaces of the silicon nitride dielectric layer in the first region and the second region of the device, the method further includes: A silicon nitride film is deposited in the groove and on the upper surface of the silicon nitride dielectric layer, and then the silicon nitride film on the upper surface of the silicon nitride dielectric layer is etched away, and the silicon nitride film at the bottom of the groove is etched away, leaving the silicon nitride film on the sidewall of the groove.

4. The method for preparing a self-aligned gate GaN HEMT device according to claim 3, wherein: The etching of the silicon nitride film on the upper surface of the silicon nitride dielectric layer and the etching of the silicon nitride film at the bottom of the groove include: The silicon nitride film on the upper surface of the silicon nitride dielectric layer is etched away using F-based plasma, and the silicon nitride film at the bottom of the groove is also etched away.

5. The method for preparing a self-aligned gate GaN HEMT device according to claim 1, wherein: The etching solution is a buffered oxide etching solution.

6. The method for preparing a self-aligned gate GaN HEMT device according to claim 1, wherein: The method of growing N+GaN in the first region, the middle region, and the second region of the device includes: Using molecular beam epitaxy, N+GaN is grown in the first, middle, and second regions of the device.

7. The method for preparing a self-aligned gate GaN HEMT device according to claim 1, wherein: A silicon nitride dielectric layer is deposited in the first region, the middle region and the second region of the device, and the silicon nitride dielectric layer at least covers two sides of the silicon dioxide layer.

8. The method for preparing a self-aligned gate GaN HEMT device according to claim 1, wherein: The polishing of the first region, the middle region, and the second region of the device comprises: The first region, the middle region and the second region of the device are polished by chemical mechanical polishing.

9. The method for preparing a self-aligned gate GaN HEMT device according to claim 1, wherein: The etching of the silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device using the gate electrode as a mask comprises: The silicon nitride dielectric layer in the first region and the silicon nitride dielectric layer in the second region of the device are etched using F-based plasma.

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