A calibration test system for a chip testing and sorting device

Abstract

The present invention discloses a calibration test system for a chip test and sorting device, which relates to the technical field of semiconductor sorting. The system includes: a real-time path acquisition module for deploying real-time position sensors to obtain real-time path position information; a speed information extraction module for interacting with the device action control end to obtain path speed information; a positioning comparison and calibration module for obtaining ideal path position information based on the path speed information and comparing and calibrating it with the real-time path position information; an image acquisition calibration module for obtaining standard chips, collecting images with the calibrated device to obtain calibrated chip images, and performing image acquisition calibration; a sorting discrimination optimization module for obtaining typical chip series, performing typical detection tests, optimizing sorting discrimination based on the results, and using the optimized device for chip test and sorting. Furthermore, the technical effects of improving the calibration efficiency, providing an adaptive calibration cycle, and improving the sorting quality are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor sorting, and particularly relates to a calibration test system for a chip test and sorting device. Background Art

[0002] In the semiconductor manufacturing process, the testing and sorting of chips are important links to ensure product quality and performance. With the continuous progress of chip technology, the complexity and precision requirements of chip test and sorting devices are also increasing. Due to the complexity of cameras, light sources, and mechanical systems, the introduction of a calibration test system is particularly important. Existing calibration test methods for chip test and sorting devices mostly adopt periodic calibration methods, which have technical problems such as complex calibration processes, large fluctuations in calibration levels, and affecting sorting consistency. Summary of the Invention

[0003] The present invention provides a calibration test system for a chip test and sorting device to solve the technical problems of complex calibration processes, large fluctuations in calibration levels, and affecting sorting consistency in the prior art, and achieve the technical effects of improving calibration efficiency, providing an adaptive calibration cycle, and improving sorting quality.

[0004] The present invention also provides a calibration test system for a chip test and sorting device, wherein the system includes:

[0005] A real-time path acquisition module, which is used to deploy real-time position sensors and run the chip test and sorting device based on a preset movement strategy to obtain real-time path position information.

[0006] A speed information extraction module, which is used to interact with the action control end of the chip test and sorting device to obtain path speed information corresponding to the real-time path position information, wherein the path speed information includes speed vector information associated with position markers.

[0007] A positioning comparison and calibration module, which is used to obtain ideal path position information based on the path speed information and perform positioning comparison and calibration with the real-time path position information.

[0008] An image acquisition and calibration module, which is used to obtain a standard chip, perform image acquisition on the chip test and sorting device after positioning comparison and calibration to obtain a calibrated chip image, and perform image acquisition calibration based on the calibrated chip image.

[0009] Sorting discrimination optimization module, which is used to obtain typical chip series, perform typical detection tests using the chip test sorting device after image acquisition calibration, and perform sorting discrimination optimization based on the typical detection test results. The chip test sorting device after discrimination optimization is used for chip test sorting.

[0010] In a feasible implementation, a real-time position sensor is deployed, and the chip test sorting device is operated based on a preset movement strategy to obtain real-time path position information. The execution steps include:

[0011] Deploy and calibrate the real-time position sensor. Based on the movement strategy, operate the conveying mechanism of the chip test sorting device to perform a conveying action, and synchronously activate the real-time position sensor to collect conveying trajectory information. Analyze the conveying trajectory information, determine multiple key control points, and segment the conveying trajectory information based on the multiple key control points, and output the segmented result as the real-time path position information.

[0012] In a feasible implementation, based on the path speed information, obtain ideal path position information and perform positioning comparison and calibration with the real-time path position information. The execution steps include:

[0013] Traverse the path speed information for position matching to obtain multiple speed control points corresponding to the multiple key control points. Perform sectional velocity vector integration based on the multiple speed control points to obtain multiple ideal paths, establish the sequence relationship of the multiple ideal paths, and output it as the ideal path position information. Perform sectional matching on the ideal path position information and the real-time path position information to obtain multiple sectional comparison groups. Traverse the multiple sectional comparison groups, align the starting speed control point and the starting key control point within the group respectively, analyze and calculate the deviation vector between the ending speed control point and the ending starting key control point, and output it as the positioning comparison deviation. Correct the speed calibration information of the action control end according to the positioning comparison deviation to perform positioning comparison and calibration.

[0014] In a feasible implementation, obtain a standard chip, perform image acquisition using the chip test sorting device after positioning comparison and calibration to obtain a calibrated chip image, and perform image acquisition calibration based on the calibrated chip image. The execution steps include:

[0015] Obtain a standard chip image, and perform image registration on the calibrated chip image and the standard chip image. Based on the image registration result, compare and calculate the image difference to obtain a difference metric. Adjust the acquisition parameters of the image acquisition component according to the difference metric, and perform image reconstruction on the calibrated chip image according to the adjusted acquisition parameters to verify the image acquisition calibration effect.

[0016] In a feasible implementation, obtain a typical chip series, and use the chip test and sorting device after image acquisition calibration to perform typical detection tests. The execution steps include:

[0017] Interact with the target test scenario to obtain a sorting sample set of the target chips. Analyze the sorting sample set to obtain the defect probability and detection difficulty, and configure the proportion of typical chips based on the defect probability and the detection difficulty. According to the proportion of typical chips, extract a chip image set of typical defective chips and output it as the typical chip series. Use the typical chip series as a sorting discrimination verification set, input it into the sorting discrimination component for typical detection tests, and obtain typical detection test results, where the typical detection test results include defect categories and corresponding sorting grades.

[0018] In a feasible implementation, based on the typical detection test results, perform sorting discrimination optimization. The execution steps further include:

[0019] Compare the typical detection test results with the sorting mark information of the typical chip series to obtain an inspection error set. Analyze the error defect frequency distribution in the inspection error set, and based on the error defect frequency distribution, perform extended acquisition of defect images to obtain an extended sample set. Based on the extended sample set and the inspection error set, perform feedback optimization on the sorting discrimination component.

[0020] In a feasible implementation, the execution steps of the system further include:

[0021] Configure a trigger constraint with the continuous defect count as the first constraint dimension. Configure a statistical constraint with the defect proportion change rate as the second constraint dimension. Use the trigger constraint and the statistical constraint as calibration trigger constraints to perform adaptive triggering of calibration tests.

[0022] In a feasible implementation, the execution steps of the system further include:

[0023] Collect historical calibration test records and construct a calibration record knowledge base. Based on the calibration record knowledge base, perform calibration trend analysis and calibration fluctuation analysis within a preset time window to construct a progressive error model. Perform error prediction according to the progressive error model. When the predicted error is greater than the preset error limit, mark the time point corresponding to the predicted error as a periodic calibration node. Perform forward calibration based on the periodic calibration node.

[0024] The present invention discloses a calibration test system for a chip testing and sorting device, including: a real-time path acquisition module for deploying a real-time position sensor, operating the chip testing and sorting device based on a preset movement strategy, and acquiring real-time path position information; a speed information extraction module for interacting with the action control end of the chip testing and sorting device to acquire path speed information corresponding to the real-time path position information, where the path speed information includes speed vector information associated with position markers; a positioning comparison and calibration module for acquiring ideal path position information based on the path speed information and performing positioning comparison and calibration with the real-time path position information; an image acquisition and calibration module for acquiring a standard chip, performing image acquisition on the chip testing and sorting device after positioning comparison and calibration to obtain a calibrated chip image, and performing image acquisition calibration based on the calibrated chip image; a sorting discrimination and optimization module for acquiring a typical chip series, performing typical detection tests on the chip testing and sorting device after image acquisition calibration, and performing sorting discrimination optimization based on the typical detection test results. The sorted and discriminated chip testing and sorting device is used for chip testing and sorting. The calibration test system for a chip testing and sorting device disclosed by the present invention solves the technical problems of complex calibration process, large fluctuation in calibration level, and influence on sorting consistency, and achieves the technical effects of improving calibration efficiency, providing an adaptive calibration cycle, and improving sorting quality. Brief Description of the Drawings

[0025] Figure 1 It is a schematic structural diagram of a calibration test system for a chip testing and sorting device of the present invention;

[0026] Figure 2 It is a schematic flow diagram of the steps for acquiring real-time path position information in a calibration test system for a chip testing and sorting device of the present invention.

[0027] Description of the reference numerals: real-time path acquisition module, speed information extraction module, positioning comparison and calibration module, image acquisition and calibration module, sorting discrimination and optimization module. Detailed Embodiments

[0028] In the embodiments of the present invention, the overall idea adopted for solving the technical problems of complex calibration process, large fluctuation in calibration level, and influence on sorting consistency existing in the prior art is as follows:

[0029] First, the real-time path acquisition module deploys real-time position sensors and runs the chip testing and sorting device based on a preset movement strategy to obtain real-time path position information. Next, the speed information extraction module is enabled. The speed information extraction module is used to interact with the action control end of the chip testing and sorting device to obtain the path speed information corresponding to the real-time path position information. Among them, the path speed information includes speed vector information associated with position markers. Then, the positioning comparison and calibration module is used. The positioning comparison and calibration module is used to obtain ideal path position information based on the path speed information and perform positioning comparison and calibration with the real-time path position information. Subsequently, the image acquisition and calibration module is activated. The image acquisition and calibration module is used to obtain a standard chip, perform image acquisition with the chip testing and sorting device after positioning comparison and calibration to obtain a calibrated chip image, and perform image acquisition calibration based on the calibrated chip image. Finally, the sorting discrimination and optimization module is run. The sorting discrimination and optimization module is used to obtain a typical chip series, perform typical detection tests with the chip testing and sorting device after image acquisition calibration, and perform sorting discrimination and optimization based on the results of the typical detection tests. The chip testing and sorting device after discrimination and optimization is used for chip testing and sorting.

[0030] The above technical solutions will be described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments to better understand the above technical solutions. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention. It should be understood that the present invention is not limited to the example embodiments that are only used to explain the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. In addition, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings, not all of them.

[0031] Figure 1 It is a schematic structural diagram of a calibration test system for a chip testing and sorting device of the present invention, which includes:

[0032] The real-time path acquisition module 11 is used to deploy real-time position sensors and run the chip testing and sorting device based on a preset movement strategy to obtain real-time path position information.

[0033] Specifically, the real-time position sensor is used to obtain the position information of the chip picking and delivering component of the conveying mechanism of the chip testing and sorting equipment in real time. Among them, the real-time position sensor can be a single sensor or a sensor array composed of multiple sensors.

[0034] Optionally, deploying a real-time position sensor means deploying a real-time position sensor on or around the target chip testing and sorting device to obtain the position information of the device. The preset movement strategy refers to a conveying mechanism movement plan with a predetermined known desired trajectory, and this movement strategy can be a movement path or a numerical control code or program (such as G-code) readable by the chip testing and sorting device.

[0035] Specifically, the real-time path position information is used to characterize the detailed trajectory information of the chip pick-up and delivery component in the conveying mechanism of the chip testing and sorting equipment. Exemplarily, this real-time path position information includes serialized spatial point coordinates and corresponding time stamps.

[0036] In some embodiments, such as Figure 2 shown, deploy a real-time position sensor, and run the chip testing and sorting device based on the preset movement strategy to obtain real-time path position information. The execution steps of the real-time path acquisition module 11 include:

[0037] Deploy and calibrate the real-time position sensor.

[0038] Based on the movement strategy, run the conveying mechanism of the chip testing and sorting device to perform a conveying action, and synchronously activate the real-time position sensor to collect the conveying trajectory information.

[0039] Analyze the conveying trajectory information, determine multiple key control points, and segment the conveying trajectory information based on the multiple key control points, and output the segmented result as the real-time path position information.

[0040] Specifically, when deploying a real-time position sensor, first, select a suitable real-time position sensor, such as a laser rangefinder, a millimeter-wave radar, an inertial sensor, etc. Then, install the real-time position sensor at the key positions of the chip testing and sorting device to ensure that the entire conveying path can be covered and the position information can be monitored in real time.

[0041] Furthermore, after the sensor is installed, calibrate the sensor to determine its precise position and angle in the conveying path. Specifically, calibrate the sensor by using a calibration board or markers with known positions to ensure the accuracy of the sensor data. Exemplarily, based on the relative position of the real-time position sensor and the control coordinate system of the chip testing and sorting device, calibrate the real-time position sensor to ensure that the position coordinates obtained by this real-time position sensor can be accurately represented as coordinate values consistent with the control coordinate system of the chip testing and sorting device.

[0042] Specifically, the preset movement strategy is a reasonable movement strategy designed and determined according to the requirements of the chip testing and sorting device, which includes a starting point, a conveying path, a speed, intermediate control points, a stopping point, etc. Optionally, the preset movement strategy also includes the rotation of the conveying mechanism.

[0043] Specifically, start the conveying mechanism of the chip testing and sorting device, and perform the conveying action according to the preset movement strategy. At the same time, synchronously activate the real-time position sensor to collect the conveying trajectory information in real time. Among them, the real-time position sensor collects positions based on the preset collection frequency. The higher the accuracy requirement of the target chip testing and sorting device, the higher the preset collection frequency of the real-time position sensor, so as to provide accurate conveying trajectory information.

[0044] Optionally, the real-time position sensor collects the conveying trajectory information and generates a continuous data stream of position information. Then, preprocess the collected data, including operations such as denoising and smoothing, to ensure the accuracy and continuity of the data.

[0045] Specifically, analyze the conveying trajectory information to identify the key control points in the trajectory. Among them, the key control points usually include the turning points, stop points or speed mutation points of the trajectory, etc. Exemplarily, methods such as inflection point detection and clustering analysis (based on speed) are used to automatically identify and extract the key control points. Then, based on the identified key control points, divide the conveying trajectory information into segments. Each segment represents an independent part of the conveying path, and output the segmentation result as the real-time path position information. By dividing the conveying trajectory information into multiple relatively independent trajectory segments, the relatively complex complete task is transformed into relatively simple decomposed tasks, which helps to reduce the difficulty of subsequent positioning comparison and calibration.

[0046] The speed information extraction module 12 is used to interact with the action control end of the chip testing and sorting device to obtain the path speed information corresponding to the real-time path position information, where the path speed information includes speed vector information associated with position marks.

[0047] Specifically, the action control end of the chip testing and sorting device refers to the control unit or component used to control the operation of the conveying mechanism. This action control end completes the execution of the conveying action by executing the preset movement strategy. Among them, the path speed information is collected by sensors set on the conveying mechanism. Exemplarily, it includes resolver sensors or encoders set on the motors of the conveying mechanism, acceleration sensors set on the chip picking and delivering components, etc.

[0048] Specifically, the path speed information is a set of serialized speed vector information, and each speed vector information is marked with the corresponding spatial position. The position mark represents the ideal spatial position generated based on the preset movement strategy. This path speed information represents the desired control result of the action control end. If the path trajectory corresponding to this path speed information is consistent with the actually collected real-time path position information, it can be considered that the operation of the conveying component in the target chip testing and sorting device is accurate.

[0049] The positioning comparison and calibration module 13 is used to obtain the ideal path position information based on the path speed information and perform positioning comparison and calibration with the real-time path position information.

[0050] In some embodiments, to obtain the ideal path position information based on the path speed information and perform positioning comparison and calibration with the real-time path position information, the execution steps of the positioning comparison and calibration module 13 include:

[0051] Traverse the path speed information for position matching to obtain multiple speed control points corresponding to the multiple key control points.

[0052] Perform partitioned speed vector integration based on the multiple speed control points to obtain multiple segments of ideal paths, establish the sequence relationship of the multiple segments of ideal paths, and output it as the ideal path position information.

[0053] Perform segmented matching on the ideal path position information and the real-time path position information to obtain multiple sets of segmented comparison groups.

[0054] Traverse the multiple sets of segmented comparison groups, align the starting speed control point and the starting key control point within each group respectively, analyze and calculate the deviation vector between the ending speed control point and the ending starting key control point, and output it as the positioning comparison deviation.

[0055] Correct the speed calibration information of the motion control end according to the positioning comparison deviation to perform positioning comparison and calibration.

[0056] Specifically, first, based on multiple previous key control points, traverse the path speed information to find the speed control points corresponding to the key control points. Then, take the path speed information between two speed control points as a segment, and integrate the speed vectors within each segment to calculate and obtain each segment of the ideal path. Next, serialize the multiple segments of ideal paths and connect them end to end, and output it as the ideal path position information.

[0057] Furthermore, according to the correspondence of multiple key control points, match the ideal path position information and the real-time path position information by segment to form multiple sets of segmented comparison groups, where each set of segmented comparison groups includes ideal path segments and real-time path segments with the same starting and ending targets.

[0058] Specifically, align the starting speed control points and starting key control points within each group, analyze and calculate the deviation vector between the ending speed control points and the ending starting key control points within each group, and output it as the positioning comparison deviation. Among them, aligning the starting speed control points and starting key control points within each group is used to eliminate the influence of the previous path segmentation on the starting position of the current path segmentation. In other words, the ideal path segment and the real-time path segment in the current segmentation comparison group of the task start from the same starting point. Then, calculate the deviation vector between the aligned ending speed control points and the ending starting key control points. This deviation vector is the partial path deviation under the current segmentation comparison group. Through the above steps, the deviation analysis task of the complex complete path is transformed into multiple relatively simple partial path deviation analysis tasks, which helps to reduce the difficulty of error analysis and improve the analysis and calculation efficiency.

[0059] Specifically, the final deviation of the real-time path position information is expressed as the vector sum of the deviation vectors of multiple segmentation comparison groups.

[0060] Further, according to the positioning comparison deviation, adjust the speed calibration information of the motion control end, including decomposing the deviation vectors of multiple segmentation comparison groups into the control parameters of multiple power components of the conveying mechanism respectively, and adjusting the speed ratio coefficient. Among them, the speed calibration information is expressed as the speed ratio coefficient, and this speed ratio coefficient reflects the proportional relationship between the control speed and the actual running speed in the motion control end.

[0061] Exemplarily, the multiple power components include stepper motors, servo motors, etc.

[0062] Specifically, through the corrected speed calibration information, perform positioning comparison calibration to make the control speed in the motion control end consistent with the actual running speed, thereby ensuring the accuracy of the conveying mechanism.

[0063] The image acquisition calibration module 14 is used to obtain a standard chip, perform image acquisition on the chip testing and sorting device after positioning comparison calibration, obtain a calibrated chip image, and perform image acquisition calibration based on the calibrated chip image.

[0064] Specifically, due to the optical characteristics of the image acquisition device or component, the acquired image information may be distorted. Therefore, use distortion correction algorithms (such as perspective transformation, radial distortion correction, etc.) to correct the image to ensure the accuracy of the image.

[0065] Specifically, the quality of the image output by the image acquisition device or component is affected by its internal parameter matrix and external parameter matrix. Among them, the internal parameter matrix determines the internal optical characteristics of the image acquisition device, such as focal length, principal point position (the intersection of the optical axis and the image plane), and lens distortion coefficient, etc. The external parameter matrix describes the position and orientation of the image acquisition device in the world coordinate system, that is, the translation and rotation matrices.

[0066] In some embodiments, a standard chip is obtained to perform image acquisition on the calibrated chip testing and sorting device for positioning and comparison, and a calibrated chip image is obtained. Image acquisition calibration is performed based on the calibrated chip image. The execution steps of the image acquisition calibration module 14 include:

[0067] A standard chip image is obtained, and image registration is performed on the calibrated chip image and the standard chip image.

[0068] Based on the image registration result, the image differences are compared and calculated to obtain a difference metric.

[0069] According to the difference metric, the acquisition parameters of the image acquisition component are adjusted, and image reconstruction is performed on the calibrated chip image according to the adjusted acquisition parameters to verify the image acquisition calibration effect.

[0070] Optionally, for image acquisition calibration, first, a standard chip and a standard chip image are obtained. The standard chip is a standard chip with known characteristics and dimensions for image acquisition and calibration. The standard chip image refers to the image of the standard chip in an ideal state, and this standard chip image can be manually corrected image information or simulation image information generated based on chip design data. Then, the standard chip is placed in the working area of the chip testing and sorting device, and the image acquisition device is started to perform image acquisition on the standard chip, and the acquisition result is stored as the calibrated chip image.

[0071] Furthermore, an image registration algorithm (such as feature point matching, phase correlation method, or gradient-based registration method) is used to register the calibrated chip image and the standard chip image. A pair of registered images is generated to ensure that the two images are aligned in the same coordinate system. Then, an image difference metric algorithm (such as mean square error (MSE), structural similarity (SSIM), or other image quality evaluation metrics) is used to calculate the difference between the pair of registered images, and the distortion category and degree of the calibrated chip image are discriminated to obtain a difference metric.

[0072] Furthermore, according to the obtained difference metric, an image processing algorithm (such as the camera calibration module in OpenCV) is used to calculate the distortion parameters of the image acquisition device. Among them, the distortion parameters include the internal parameter matrix and the external parameter matrix.

[0073] Optionally, based on the distortion parameters, the acquisition parameters of the image acquisition device or component are recalibrated and adjusted, and image reconstruction is performed on the calibrated chip image based on the adjusted acquisition parameters, including re-acquiring images or performing distortion calibration on the existing calibrated images, to verify the image acquisition calibration effect. If the difference metric between the reconstructed image and the standard chip image is less than a preset difference control limit, it can be considered that the image acquisition calibration effect is good.

[0074] The sorting discrimination optimization module 15 is used to obtain a typical chip series, perform typical detection tests using the chip test sorting device after image acquisition calibration, and perform sorting discrimination optimization based on the typical detection test results. The chip test sorting device after discrimination optimization is used for chip test sorting.

[0075] In some embodiments, to obtain a typical chip series and perform typical detection tests using the chip test sorting device after image acquisition calibration, the execution steps of the sorting discrimination optimization module 15 include:

[0076] Interact with the target test scenario to obtain a sorting sample set of the target chips.

[0077] Analyze the sorting sample set to obtain the defect probability and detection difficulty, and configure the typical chip ratio based on the defect probability and the detection difficulty.

[0078] Extract the chip image set of typical defective chips according to the typical chip ratio and output it as the typical chip series.

[0079] Use the typical chip series as a sorting discrimination verification set, input it into the sorting discrimination component for typical detection tests, and obtain the typical detection test results, where the typical detection test results include the defect category and the corresponding sorting grade.

[0080] Specifically, first, connect to the target chip test scenario and collect the sorting sample set of the target chips. This sorting sample set includes chip images corresponding to various possible defects and detection difficulty data. Then, analyze the sorting sample set and extract the defect probability and detection difficulty of each defect. Among them, the defect probability is the possibility of a certain type of defect appearing on the target batch or target model of chips, and the detection difficulty refers to the difficulty of detecting this defect.

[0081] Furthermore, configure the typical chip ratio based on the defect probability and detection difficulty. This typical chip ratio is a representative typical chip sample ratio configured according to the defect probability and detection difficulty. Among them, the higher the defect probability and the greater the defect detection difficulty, the larger the corresponding sample ratio (the number of samples). In other words, the defect types with higher defect probabilities require higher attention, and the defect types with greater defect detection difficulties require more abundant samples to ensure the detection rate. Exemplarily, the possible defect types of chips include: surface scratches, pin damage, internal defects, impurity contamination, functional defects, etc.

[0082] Subsequently, based on the above-mentioned typical chip ratios, representative typical defective chip images are extracted from the sorting sample set to form a typical chip series. Among them, the typical chip series includes multiple sub-series corresponding to various types of defects, and the length (i.e., the sample size) of each sub-series corresponds to the above-mentioned typical chip ratio. Through the above method, it helps to ensure that the extracted image set covers various common defect types and detection difficulties, and at the same time conforms to the performance characteristics of the defects.

[0083] Among them, the chip images with multiple defect levels are included in the multiple sub-series included in the typical chip series, which further helps to improve the defect level discrimination ability of the subsequent optimized sorting discrimination component.

[0084] Specifically, taking the typical chip series as the sorting discrimination verification set, input it into the sorting discrimination component for typical detection tests to obtain test results. Among them, the test results include the defect category and the corresponding sorting level. In other words, the test results characterize the sorting discrimination ability of the sorting discrimination component. The closer the defect category and the corresponding sorting level in the test results are to the true values, the higher the accuracy rate, and the stronger the sorting discrimination ability of the sorting discrimination component.

[0085] In some embodiments, based on the typical detection test results, sorting discrimination optimization is performed. The execution steps of the sorting discrimination optimization module 15 further include:

[0086] Compare the typical detection test results with the sorting mark information of the typical chip series to obtain an inspection error set.

[0087] Analyze the error defect frequency distribution in the obtained inspection error set, and based on the error defect frequency distribution, perform extended acquisition of defect images to obtain an extended sample set.

[0088] Based on the extended sample set and the inspection error set, perform feedback optimization on the sorting discrimination component.

[0089] Specifically, for sorting discrimination optimization, first, obtain the typical detection test results, including the defect category discrimination results and defect level discrimination results for each typical defective chip image. Subsequently, obtain the sorting mark information of the typical chip series. This sorting mark information reflects the actual defect category and defect level of the chip, which is the true value of the sorting discrimination. Then, compare the typical detection test results with the sorting mark information to identify the errors in the detection results and generate an inspection error set. This inspection error set contains the difference part between the recorded detection results and the sorting mark information, that is, the incorrect test results in the typical detection test results.

[0090] Further, the error frequency of each defect in the inspection error set is counted to generate an error defect frequency distribution table. Then, based on the error defect frequency distribution, the defect types that need to be supplemented and collected are determined. Exemplarily, the error categories with an error defect frequency greater than the preset frequency control threshold are considered as the defect categories that need to be discriminated and optimized. Furthermore, for the defect types with a higher error frequency, additional image acquisitions are performed to obtain more defect images. Thus, the newly acquired defect images are added to the augmented sample set, which contains richer defect image information.

[0091] Specifically, the augmented sample set is combined with the inspection error set for feedback optimization, where the augmented sample set is the positive sample in the feedback optimization, and the inspection error set is the negative sample set in the feedback optimization. Exemplarily, the augmented sample set (positive sample) and the inspection error set (negative sample) are merged to form a new training data set. Then, duplicate and invalid samples are removed to ensure data quality. At the same time, data augmentation (such as rotation, scaling, flipping, etc.) is performed on the images in the training data set to increase data diversity and improve the robustness of the sorting and discrimination component. Next, the merged training data set is used to perform enhanced training on the sorting and discrimination component to improve the model's ability to effectively distinguish positive and negative samples, thereby achieving feedback optimization of the sorting and discrimination component.

[0092] Further, the execution steps of the system further include:

[0093] Configure a trigger constraint with the consecutive defect count as the first constraint dimension.

[0094] Configure a statistical constraint with the defect ratio change rate as the second constraint dimension.

[0095] Use the trigger constraint and the statistical constraint as the calibration trigger constraint for adaptive triggering of the calibration test.

[0096] Specifically, the trigger constraint is defined as the number of consecutive defective chips detected, which is used to trigger the calibration test when the number of consecutive predictions of defective chips in the sorting and discrimination result reaches the set threshold.

[0097] Specifically, the statistical constraint is defined as the upper limit of the defect ratio change rate of defective chips within a certain time window. It is used to trigger the calibration test when the defect ratio change rate exceeds the set threshold. Among them, the statistical constraint includes the rising rate threshold and the falling rate threshold of the defect ratio change rate, and the two may not be equal.

[0098] Specifically, when the number of consecutive defects reaches a set threshold or the change rate of the defect ratio exceeds the set threshold, a calibration test is triggered to retrain or adjust the parameters of the sorting and discrimination component to ensure the accuracy and robustness of chip test sorting. By defining and configuring the number of consecutive defects (trigger constraint) and the change rate of the defect ratio (statistical constraint), and combining these two constraints for calibration triggering, the adaptive trigger calibration of the sorting and discrimination component is achieved. This ensures the accuracy and robustness of the sorting and discrimination component in the actual production environment, and improves the detection efficiency and reliability.

[0099] Furthermore, the execution steps of the system further include:

[0100] Collect historical calibration test records and build a calibration record knowledge base.

[0101] Based on the calibration record knowledge base, perform calibration trend analysis and calibration fluctuation analysis within a preset time window to build a progressive error model.

[0102] Predict errors according to the progressive error model. When the predicted error is greater than the preset error limit, mark the time point corresponding to the predicted error as the periodic calibration node.

[0103] Perform forward-looking calibration based on the periodic calibration node.

[0104] Optionally, on the basis of the system execution steps, further introduce historical calibration test records, calibration trend analysis, progressive error model, and forward-looking calibration to better predict and manage the errors of the sorting and discrimination system.

[0105] Specifically, first, collect all historical calibration test records, including calibration time, error conditions before and after calibration, calibration parameters, etc., and organize the collected calibration test records. Store the organized data in a structured calibration record knowledge base. Then, set a preset time window (for example, monthly or quarterly), analyze the calibration test records within each time window, and identify the trend of error change and the fluctuation of calibration. Among them, calibration fluctuation analysis is used to obtain the fluctuation of errors and identify the periodicity and fluctuation amplitude of errors.

[0106] Furthermore, based on the results of calibration trend analysis and calibration fluctuation analysis, build a progressive error model. This progressive error model obtains the ability to predict future error changes by learning the results of calibration trend analysis and calibration fluctuation analysis.

[0107] Optionally, a preset error limit is set as the criterion for determining whether calibration is required, and a progressive error model is used for error prediction to predict the error change in a future period. When the predicted error is greater than the preset error limit, this time point is marked as a periodic calibration node. Then, based on the periodic calibration node, a forward-looking calibration plan is formulated to ensure that forward-looking calibration is performed before the periodic calibration node arrives, thereby ensuring the sorting quality of the chip sorting device.

[0108] In summary, the calibration test system for a chip test sorting device provided by the present invention has the following technical effects:

[0109] By deploying real-time position sensors through the real-time path acquisition module and operating the chip test sorting device based on a preset movement strategy to obtain real-time path position information; the speed information extraction module interacts with the action control end of the chip test sorting device to obtain the path speed information corresponding to the real-time path position information, and the path speed information includes speed vector information associated with position markers; the positioning comparison and calibration module obtains ideal path position information based on the path speed information and performs positioning comparison and calibration with the real-time path position information; the image acquisition and calibration module obtains standard chips and performs image acquisition through the chip test sorting device after positioning comparison and calibration to obtain calibrated chip images, and performs image acquisition calibration based on the calibrated chip images; the sorting discrimination optimization module obtains a typical chip series, uses the chip test sorting device after image acquisition calibration to perform typical detection tests, and performs sorting discrimination optimization based on the typical detection test results. The optimized chip test sorting device is used for chip test sorting. Thus, the technical effects of improving the calibration efficiency, providing an adaptive calibration cycle, and improving the sorting quality are achieved.

[0110] It should be understood that the disclosed embodiments of the present invention and the above descriptions enable those skilled in the art to implement the present invention using the present invention. At the same time, the present invention is not limited to the above-mentioned part of the embodiments. It should be understood that ordinary skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A calibration test system for a chip testing and sorting device, characterized in that, The system includes: A real-time path acquisition module, which is used to deploy real-time position sensors and operate the chip test and sorting device based on a preset movement strategy to obtain real-time path position information; A speed information extraction module, which is used to interact with the action control end of the chip test and sorting device to obtain the path speed information corresponding to the real-time path position information, wherein the path speed information includes speed vector information associated with position markers; A positioning comparison and calibration module, which is used to obtain ideal path position information based on the path speed information and perform positioning comparison and calibration with the real-time path position information; An image acquisition and calibration module, which is used to obtain a standard chip, perform image acquisition with the chip test and sorting device after positioning comparison and calibration to obtain a calibrated chip image, and perform image acquisition calibration based on the calibrated chip image; A sorting discrimination and optimization module, which is used to obtain a typical chip series, perform typical detection tests with the chip test and sorting device after image acquisition calibration, and perform sorting discrimination and optimization based on the typical detection test results. The chip test and sorting device after discrimination and optimization is used for chip test and sorting.

2. The calibration test system of a chip testing and sorting device as described in claim 1, wherein Deploy real-time position sensors and operate the chip test and sorting device based on a preset movement strategy to obtain real-time path position information. The execution steps include: Deploy and calibrate the real-time position sensors; Based on the movement strategy, operate the conveying mechanism of the chip test and sorting device to perform a conveying action, and simultaneously activate the real-time position sensors to collect conveying trajectory information; Analyze the conveying trajectory information, determine multiple key control points, and segment the conveying trajectory information based on the multiple key control points, and output the segmented result as the real-time path position information.

3. The calibration test system of a chip testing and sorting device as described in claim 2, characterized in that, Obtain ideal path position information based on the path speed information and perform positioning comparison and calibration with the real-time path position information. The execution steps include: Traverse the path speed information for position matching to obtain multiple speed control points corresponding to the multiple key control points; Perform zonal speed vector integration according to the multiple speed control points to obtain multiple ideal paths, and establish a sequence relationship of the multiple ideal paths, and output it as the ideal path position information; Perform segmented matching on the ideal path position information and the real-time path position information to obtain multiple segmented comparison groups; Traverse the multiple segmented comparison groups, align the starting speed control point and the starting key control point within each group respectively, analyze and calculate the deviation vector between the ending speed control point and the ending starting key control point, and output it as the positioning comparison deviation; Correct the speed calibration information of the action control end according to the positioning comparison deviation to perform positioning comparison and calibration.

4. The calibration test system of a chip test and sorting device according to claim 3, characterized in that, Obtain a standard chip, perform image acquisition with the chip test and sorting device after positioning comparison and calibration to obtain a calibrated chip image, and perform image acquisition calibration based on the calibrated chip image. The execution steps include: Obtain a standard chip image, and perform image registration on the calibrated chip image and the standard chip image; Based on the image registration result, compare and calculate the image difference to obtain a difference metric; Adjust the acquisition parameters of the image acquisition component according to the difference metric, and perform image reconstruction on the calibrated chip image according to the adjusted acquisition parameters to verify the image acquisition calibration effect.

5. The calibration test system of a chip test and sorting device according to claim 4, characterized in that, Obtain a typical chip series, and use the chip test and sorting device after image acquisition calibration to perform typical detection tests. The execution steps include: Interact with the target test scenario to obtain a sorting sample set of the target chip; Analyze the sorting sample set to obtain the defect probability and detection difficulty, and configure the proportion of typical chips based on the defect probability and the detection difficulty; Extract the chip image set of typical defective chips according to the proportion of typical chips and output it as the typical chip series; Use the typical chip series as a sorting discrimination verification set, input it into the sorting discrimination component for typical detection tests, and obtain the typical detection test results. The typical detection test results include the defect category and the corresponding sorting grade.

6. The calibration test system of a chip test and sorting device according to claim 5, characterized in that, Based on the typical detection test results, perform sorting discrimination optimization. The execution steps further include: Compare the typical detection test results with the sorting mark information of the typical chip series to obtain an inspection error set; Analyze and obtain the error defect frequency distribution in the inspection error set, and based on the error defect frequency distribution, perform extended acquisition of defective images to obtain an extended sample set; Based on the extended sample set and the inspection error set, perform feedback optimization on the sorting discrimination component.

7. The calibration test system of a chip test and sorting device according to claim 1, characterized in that, The execution steps of the system further include: Configure a trigger constraint with the continuous defect count as the first constraint dimension; Configure a statistical constraint with the defect proportion change rate as the second constraint dimension; Use the trigger constraint and the statistical constraint as calibration trigger constraints to perform adaptive triggering of calibration tests.

8. The calibration test system of a chip test and sorting device as described in claim 1, characterized in that, The execution steps of the system: Collect historical calibration test records and build a calibration record knowledge base; Based on the calibration record knowledge base, perform calibration trend analysis and calibration fluctuation analysis within a preset time window to build a progressive error model; Perform error prediction according to the progressive error model. When the predicted error is greater than the preset error limit, mark the time point corresponding to the predicted error as the periodic calibration node; Perform forward-looking calibration based on the periodic calibration node.

Images