Method and device for multi-level support of near-end atomic operations and far-end atomic operations

Abstract

The embodiments of this specification provide a method and apparatus for multi-level support of near-end atomic operations and far-end atomic operations, including: the LSU receives an atomic operation request and determines whether the requested data is in the first-level data cache and whether the first-level data cache has exclusive modification permission; if both are yes, the LSU executes and completes the near-end atomic operation; if not, the LSU sends the atomic operation request to the intermediate-level cache; the intermediate-level cache determines whether the requested data is in the intermediate-level cache or the local cache consistency domain to which the intermediate-level cache belongs, and whether the intermediate-level cache and its cache consistency domain have exclusive modification permission; if both are yes, the required data is sent to the LSU to execute the near-end atomic operation; if not, the intermediate-level cache sends the atomic operation request to the CSA; the CSA receives the atomic operation request, executes the far-end atomic operation, and sends a completion signal to the LSU. The embodiments of this specification can improve the performance of multi-core systems.

Description

Technical Field

[0001] The embodiments of this specification relate to the field of atomic operations, and in particular, to a method and apparatus for multi-level support of near-end atomic operations and far-end atomic operations. Background Art

[0002] The existing technology uses proximal and remote operations in multi-core systems to implement atomic operation instructions. The proximal atomic operation component is placed in the load store unit LSU (Load Store Unit). The LSU is the module of the CPU responsible for processing memory access operations, usually including the first-level data cache (L1D). The remote atomic operation component is placed on the consistency slave node CSA (Coherent Slave Agent) close to the main memory side. When the data that needs to perform an atomic operation is cached in the L1D and has exclusive modification permissions, the proximal atomic operation is performed, and the LSU locks the cache bar to implement the Read-Modify-Write operation to complete the atomic operation; when the data that needs to be modified is not in the L1D cache in the memory access unit or does not have exclusive modification permissions, the LSU converts the atomic operation request into a remote atomic operation and sends it directly to the downstream cache system, and the atomic operation is completed at the consistency maintenance point CSA on the main memory side.

[0003] In multi-core systems, atomic operation instructions are often used to construct lock-free algorithms. The data modified by these atomic operations needs to be shared between multiple threads. After a local thread modifies data using an atomic operation, it generally does not access the data again (for a short period of time), while expecting the modified data to be immediately accessible to other threads. In the prior art, atomic operation requests are pushed to a remote CSA for execution. This means that when other threads in the local coherence domain want to access the data operated on by the atomic operation, they must transfer the latest data from the target CSA to the requesting thread. The CSA is located close to main memory within the system coherence domain and may even be separated from the core where the requesting thread resides by the distance between the die (the smallest slicable unit on a wafer in chip manufacturing, consisting of a fully designed single chip and the adjacent horizontal and vertical scribe grooves) and the physical socket that connects to the processor (CPU). This distance is typically long, increasing access latency and degrading system performance.

[0004] Therefore, there is an urgent need for a multi-level method to support near-end atomic operations and far-end atomic operations, which can avoid the performance degradation of the multi-core system caused by pushing data in the local cache consistency domain to the far-end CSA side and improve the performance of the multi-core system. Summary of the Invention

[0005] The purpose of the embodiments of this specification is to provide a method and apparatus for multi-level support of proximal atomic operations and distal atomic operations to improve the performance of a multi-core system.

[0006] To achieve the above objectives, on the one hand, embodiments of this specification provide a method for supporting near-end atomic operations and far-end atomic operations at multiple levels, including:

[0007] The LSU receives an atomic operation request and determines whether the data required by the request is in the first-level data cache and whether the first-level data cache has exclusive modification permission;

[0008] If both are true, the LSU performs the proximal atomic operation to complete the atomic operation request;

[0009] If yes, the LSU sends the atomic operation request to the intermediate level cache;

[0010] The intermediate cache receives an atomic operation request, and the intermediate cache determines whether the data required by the request is in the intermediate cache, and whether the intermediate cache has exclusive modification permission;

[0011] If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0012] If yes, the intermediate level cache sends the atomic operation request to the CSA;

[0013] CSA receives the atomic operation request, performs the remote atomic operation, and sends a completion signal to LSU after completing the atomic operation request.

[0014] Preferably, the intermediate level cache includes a second level cache and a third level cache.

[0015] Preferably, the intermediate level cache determines whether the requested data is in the intermediate level cache, and whether the intermediate level cache has exclusive modification authority further includes:

[0016] The secondary cache determines whether the requested data is in the secondary cache and whether the secondary cache has exclusive modification permission;

[0017] If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0018] If yes, the L2 cache sends the atomic operation request to the L3 cache;

[0019] The third-level cache determines whether the data required by the request is in the third-level cache and whether the third-level cache has exclusive modification permission;

[0020] If both are yes, the required data is sent to the secondary cache, the secondary cache sends it to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0021] If no, the L3 cache sends the atomic operation request to the CSA.

[0022] Preferably, the intermediate level cache determines whether the requested data is in the intermediate level cache, and whether the intermediate level cache has exclusive modification authority further includes:

[0023] The intermediate level cache determines step by step through the improved six pipeline stages whether the required data of the request is in the intermediate level cache, and whether the intermediate level cache has exclusive modification authority.

[0024] Preferably, the intermediate cache determines whether the requested data is in the intermediate cache step by step through six pipeline stages, and whether the intermediate cache has exclusive modification authority further includes:

[0025] The first pipeline stage selects the request according to the set rules and sends it to the second pipeline stage;

[0026] The second pipeline stage reads the tag and coherence status of the cache bar in the middle pipeline stage, and sends the obtained tag information and status information of the cache bar to the third pipeline stage;

[0027] The third pipeline stage matches the request address of the request with the tag information of the cache bar to obtain a matching result, wherein the matching result indicates whether the required data is in the cache bar of the intermediate cache; and determines whether the state information of the cache bar is in the E state or the M state to obtain a status result; and sends the matching result and the status result to the fourth pipeline stage;

[0028] The fourth pipeline stage drives the fifth pipeline stage and the sixth pipeline stage to send the required data in the cache bar to the LSU or the previous level cache based on the matching result and the status result; or sends the atomic operation request to the CSA or the next level cache based on the matching result and the status result.

[0029] Preferably, the first pipeline stage selects the request according to a set rule and sends it to the second pipeline stage further includes:

[0030] The first pipeline stage treats the atomic operation request and other requests as a full request;

[0031] Processing each request in the full request one by one according to the order in which each request in the full request arrives at the intermediate cache and the priority of each request;

[0032] When processing the atomic operation request, the atomic operation request is sent to the second pipeline stage.

[0033] Preferably, the fourth pipeline stage drives the fifth pipeline stage and the sixth pipeline stage to send the required data in the cache bar to the previous level cache according to the matching result and the status result; or sends the atomic operation request to the CSA or the next level cache according to the matching result and the status result further includes:

[0034] When the matching result is a successful match and the state result is E state or M state, driving the fifth pipeline stage to select the required data in the cache bar and sending the required data to the sixth pipeline stage;

[0035] If the intermediate level cache is a secondary cache, the sixth pipeline stage sends the required data to the LSU;

[0036] If the intermediate level cache is a level 3 cache, the sixth pipeline stage sends the required data to the level 2 cache, and the level 2 cache sends the required data to the LSU;

[0037] When the matching result is a matching failure or the status result is neither E nor M,

[0038] If the intermediate cache is a level 2 cache, sending the atomic operation request to a level 3 cache;

[0039] If the intermediate level cache is a level 3 cache, the atomic operation request is sent to the CSA.

[0040] Preferably, it also includes:

[0041] The local consistency domain of the third-level cache defines a special state of a cache bar: the cache bar only exists in the current third-level cache, or only exists in the first-level data cache or second-level cache of at least one core in the local consistency domain to which the current third-level cache belongs.

[0042] Preferably, it also includes:

[0043] The LSU receives the atomic operation request and sends the atomic operation request to the third-level cache;

[0044] The third-level cache determines whether there is a cache bar in a special state in the local coherence domain, and the data required by the atomic operation request is in the cache bar in the special state;

[0045] The third-level cache selects the cache bar in the special state and sends the required data in the cache bar in the special state to the LSU. The state information of the cache bar in the special state is E state or M state.

[0046] The LSU performs the proximal atomic operation and completes the atomic operation request.

[0047] On the other hand, an embodiment of this specification provides a device for supporting near-end atomic operations and far-end atomic operations at multiple levels, the device comprising:

[0048] An LSU judgment module, configured for the LSU to receive an atomic operation request, and the LSU to judge whether the data required by the request is in the first-level data cache, and whether the first-level data cache has exclusive modification permission;

[0049] If both are true, the LSU performs the proximal atomic operation to complete the atomic operation request;

[0050] If yes, the LSU sends the atomic operation request to the intermediate level cache;

[0051] An intermediate cache judgment module is configured to receive an atomic operation request from an intermediate cache, and to judge whether the data required by the request is in the intermediate cache, and whether the intermediate cache has exclusive modification permission;

[0052] If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0053] If yes, the intermediate level cache sends the atomic operation request to the CSA;

[0054] The CSA execution module is used for the CSA to receive atomic operation requests, execute remote atomic operations, and send a completion signal to the LSU after completing the atomic operation request.

[0055] On the other hand, an embodiment of this specification further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory, wherein when the computer program is run by the processor, the computer program executes instructions according to any one of the above methods.

[0056] On the other hand, an embodiment of the present specification further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor of a computer device, executes instructions of any one of the above methods.

[0057] On the other hand, the embodiments of this specification further provide a computer program product, which, when executed by a processor of a computer device, executes instructions of any one of the above methods.

[0058] It can be seen from the technical solutions provided by the above embodiments of this specification that, through the methods of the embodiments of this specification, the permission check of each level of cache is performed to ensure that the data of the operation is consistent and correct, to avoid concurrency conflicts and to ensure data consistency. And through the layered processing strategy, it is ensured that even if the local cache cannot process the request, the system can still complete the task through remote operation, thereby improving the robustness and flexibility of the system. It also maximizes the use of local cache levels, reduces the delay of atomic operations, improves the response speed of the overall system, avoids the performance degradation of the multi-core system caused by pushing data in the local cache consistency domain to the remote CSA side, and improves the performance of the multi-core system.

[0059] In order to make the above and other purposes, features and advantages of this specification more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0061] Figure 1 A schematic flow chart of a method for multi-level support of near-end atomic operations and far-end atomic operations provided by an embodiment of this specification is shown;

[0062] Figure 2 A schematic diagram of a process for determining whether requested data is in the intermediate-level cache and whether the intermediate-level cache has exclusive modification permission is shown in an embodiment of the present specification;

[0063] Figure 3 A schematic diagram shows a flow chart of the intermediate-level cache according to an embodiment of the present specification, which determines whether the requested data is in the intermediate-level cache and whether the intermediate-level cache has exclusive modification rights through six pipeline stages;

[0064] Figure 4 A schematic diagram of a process in which the first pipeline stage according to an embodiment of the present specification selects a request according to a set rule and sends the request to the second pipeline stage is shown;

[0065] Figure 5 A schematic diagram of a process in which the fourth pipeline stage drives the fifth and sixth pipeline stages to send required data in a cache bar to the previous level cache, or to send an atomic operation request to the CSA or the next level cache, according to an embodiment of the present specification;

[0066] Figure 6Another flowchart of a method for multi-level support of near-end atomic operations and far-end atomic operations provided by an embodiment of this specification is shown;

[0067] Figure 7 A schematic diagram of the module structure of a multi-level device supporting near-end atomic operations and far-end atomic operations provided by an embodiment of this specification is shown;

[0068] Figure 8 A schematic diagram of the structure of a computer device provided in an embodiment of this specification is shown.

[0069] Description of the accompanying symbols:

[0070] 100. LSU judgment module;

[0071] 200, intermediate cache judgment module;

[0072] 300, CSA execution module;

[0073] 802. Computer equipment;

[0074] 804, processor;

[0075] 806, memory;

[0076] 808, driving mechanism;

[0077] 810, input / output module;

[0078] 812. Input devices;

[0079] 814. Output device;

[0080] 816. Presentation equipment;

[0081] 818. Graphical User Interface;

[0082] 820, network interface;

[0083] 822, communication link;

[0084] 824. Communication bus. DETAILED DESCRIPTION

[0085] The following will clearly and completely describe the technical solutions in the embodiments of this specification in conjunction with the drawings in the embodiments of this specification. Obviously, the embodiments described are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the embodiments of this specification.

[0086] In multi-core systems, atomic operation instructions are often used to construct lock-free algorithms. The data modified by these atomic operations needs to be shared between multiple threads. After a local thread modifies data using an atomic operation, it generally does not access the data again (for a short period of time), while expecting the modified data to be immediately accessible to other threads. In the prior art, atomic operation requests are pushed to a remote CSA for execution. This means that when other threads in the local coherence domain want to access the data operated on by the atomic operation, they must transfer the latest data from the target CSA to the requesting thread. The CSA is located close to main memory within the system coherence domain and may even be separated from the core where the requesting thread resides by the distance between the die (the smallest slicable unit on a wafer in chip manufacturing, consisting of a fully designed single chip and the adjacent horizontal and vertical scribe grooves) and the physical socket that connects to the processor (CPU). This distance is typically long, increasing access latency and degrading system performance.

[0087] In order to solve the above problems, the embodiments of this specification provide a multi-level method for supporting near-end atomic operations and far-end atomic operations, in which the data that originally needs to perform atomic operations on the far-end CSA will be further judged in the intermediate-level cache system. If the data on which the atomic operation is performed only exists in the local cache consistency domain, the data will be sent to the requesting core LSU, and the far-end atomic operation will be converted into a near-end atomic operation and executed on the requesting core LSU. Figure 1 This is a flowchart of a method for multi-level support of proximal atomic operations and remote atomic operations provided by an embodiment of this specification. This specification provides method operation steps as described in the embodiment or flowchart, but may include more or fewer operation steps based on conventional or non-creative labor. The order of steps listed in the embodiment is only one way of executing the steps among many steps and does not represent the only execution order. When the actual system or device product is executed, it can be executed in the order of the method shown in the embodiment or the accompanying drawings or in parallel.

[0088] It should be noted that the terms "first", "second", etc. in the description and claims of the embodiments of this specification and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of this specification described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0089] Reference Figure 1 The embodiments of this specification disclose a method for supporting near-end atomic operations and far-end atomic operations at multiple levels, including:

[0090] S101: The LSU receives an atomic operation request, and determines whether the data required by the request is in the first-level data cache, and whether the first-level data cache has exclusive modification permission;

[0091] S102: If both are yes, the LSU performs the proximal atomic operation to complete the atomic operation request;

[0092] S103: If no, the LSU sends the atomic operation request to the intermediate level cache;

[0093] S104: The intermediate-level cache receives the atomic operation request, and the intermediate-level cache determines whether the data required by the request is in the intermediate-level cache, and whether the intermediate-level cache has exclusive modification permission;

[0094] S105: If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0095] S106: If no, the intermediate level cache sends the atomic operation request to the CSA;

[0096] S107: The CSA receives the atomic operation request, performs the remote atomic operation, and sends a completion signal to the LSU after completing the atomic operation request.

[0097] For example, a "yes" response for the first-level data cache indicates that the requested data is in the first-level data cache and has exclusive modification permissions. A "no" response indicates that the requested data is not in the first-level data cache or the first-level data cache does not have exclusive modification permissions. The determination for intermediate-level caches is similar to that for the first-level data cache and will not be further detailed in this specification.

[0098] The core memory access unit (LSU) is the CPU module responsible for handling memory access operations. It typically includes the Level 1 data cache (L1D). In a multi-core processor system, multiple processors may access and modify the same data simultaneously. If these operations are not atomic, data contention may occur, leading to data inconsistency or errors. Atomic operations ensure the correctness of data access in concurrent environments, guaranteeing data consistency and correct system functionality.

[0099] The LSU determines whether the requested data is in the first-level data cache and whether the first-level data cache has exclusive modification permissions. If the requested data is in the first-level data cache and the first-level data cache has exclusive modification permissions, the LSU retrieves the required data from the first-level data cache and performs a proximal atomic operation to complete the atomic operation request. If the requested data is not in the first-level data cache, or the first-level data cache does not have exclusive modification permissions, the LSU sends the atomic operation request to the intermediate-level cache.

[0100] Generally speaking, the intermediate cache includes a second-level cache and a third-level cache, and may also include a second-level cache, a third-level cache, and a fourth-level cache. In the embodiments of this specification, there is no specific limitation on how many levels of cache the intermediate cache includes.

[0101] The intermediate cache receives an atomic operation request. The intermediate cache determines whether the requested data is in the intermediate cache and whether the intermediate cache has exclusive modification permission. If the requested data is in the intermediate cache and the intermediate cache has exclusive modification permission, the intermediate cache obtains the required data from the intermediate cache and sends it to the LSU to perform a local atomic operation, completing the atomic operation request. If the requested data is not in the intermediate cache, or the intermediate cache does not have exclusive modification permission, the intermediate cache sends the atomic operation request to the CSA. The CSA receives the atomic operation request, performs the remote atomic operation, and sends a completion signal to the LSU after completing the atomic operation request.

[0102] The remote system coherence node (CSA) is a component or agent in a computer system used to manage and ensure cache coherence. It is often used in complex multi-processor or multi-core systems to coordinate access to shared memory across multiple processor cores or devices, ensuring that data in the cache remains consistent.

[0103] Generally speaking, whether it is a first-level data cache or an intermediate-level cache, the cache is divided into multiple groups, each group contains multiple cache bars, each cache bar stores a piece of data, and the cache bar usually contains a data block, a tag, and a consistency state. In the embodiments of this specification, the required data requested is in the first-level data cache or the required data requested is in the intermediate-level cache, which means that the required data is stored in the cache bar of the first-level data cache or the required data is stored in the cache bar of the intermediate-level cache. The first-level data cache has exclusive modification permission or the intermediate-level cache has exclusive modification permission, which means that the consistency state of the cache bar is E state (the cache bar has not been modified and only exists in the current cache) or M state (the cache bar has been modified and only exists in the current cache).

[0104] In the embodiments of this specification, the intermediate-level cache includes the second-level cache and the third-level cache as an example for further explanation. For the case where the intermediate-level cache includes the second-level cache, the third-level cache and the fourth-level cache, as well as other intermediate-level caches, please refer to the examples in this application.

[0105] The example is as follows, refer to Figure 2 The intermediate level cache determines whether the requested data is in the intermediate level cache, and whether the intermediate level cache has exclusive modification permission further includes:

[0106] S201: The L2 cache determines whether the requested data is in the L2 cache, and whether the L2 cache has exclusive modification permission;

[0107] S202: If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0108] S203: If no, the L2 cache sends the atomic operation request to the L3 cache;

[0109] S204: The third-level cache determines whether the requested data is in the third-level cache, and whether the third-level cache has exclusive modification permission;

[0110] S205: If both are yes, the required data is sent to the L2 cache, and the L2 cache sends it to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0111] S206: If no, the L3 cache sends the atomic operation request to the CSA.

[0112] If the intermediate cache includes a second-level cache, a third-level cache, and a fourth-level cache, the intermediate cache determines whether the requested data is in the intermediate cache, and whether the intermediate cache has exclusive modification permission further includes:

[0113] S1: The L2 cache determines whether the requested data is in the L2 cache and whether the L2 cache has exclusive modification permission;

[0114] S2: If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0115] S3: If no, the L2 cache sends the atomic operation request to the L3 cache;

[0116] S4: The third-level cache determines whether the requested data is in the third-level cache and whether the third-level cache has exclusive modification permission;

[0117] S5: If both are yes, the required data is sent to the L2 cache, and the L2 cache sends it to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0118] S6: If no, the L3 cache sends the atomic operation request to the L4 cache;

[0119] S4: The L4 cache determines whether the requested data is in the L4 cache and whether the L4 cache has exclusive modification permission;

[0120] S5: If both are yes, the required data is sent to the L3 cache, the L3 cache sends the required data to the L2 cache, the L2 cache sends the data to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request;

[0121] S6: If no, the L4 cache sends the atomic operation request to the CSA.

[0122] For the middle-level cache, the middle-level cache gradually determines whether the required data of the request is in the middle-level cache through the improved six pipeline stages, and whether the middle-level cache has exclusive modification authority.

[0123] Specifically, refer to Figure 3 The intermediate cache determines whether the requested data is in the intermediate cache through six pipeline stages, and whether the intermediate cache has exclusive modification permission further includes:

[0124] S301: The first pipeline stage selects the request according to the set rules and sends it to the second pipeline stage;

[0125] S302: The second pipeline stage reads the tag and coherence status of the cache bar in the middle pipeline stage, and sends the obtained tag information and status information of the cache bar to the third pipeline stage;

[0126] S303: The third pipeline stage matches the request address of the request with the tag information of the cache bar to obtain a matching result, which indicates whether the required data is in the cache bar of the intermediate cache; and determines whether the state information of the cache bar is in the E state or the M state to obtain a status result; and sends the matching result and the status result to the fourth pipeline stage;

[0127] S304: The fourth pipeline stage drives the fifth pipeline stage and the sixth pipeline stage to send the required data in the cache bar to the LSU or the previous level cache based on the matching result and the status result; or sends the atomic operation request to the CSA or the next level cache based on the matching result and the status result.

[0128] The intermediate cache may be a level 2 cache or a level 3 cache. If the intermediate cache includes a level 2 cache, a level 3 cache and a level 4 cache, the intermediate cache may also be a level 4 cache.

[0129] Among them, reference Figure 4 The first pipeline stage selects the request according to the set rules and sends it to the second pipeline stage, further comprising:

[0130] S401: The first pipeline stage treats the atomic operation request and other requests as a full request;

[0131] S402: Processing each request in the full request one by one according to the order in which each request in the full request arrives at the intermediate cache and the priority of each request;

[0132] S403: When processing the atomic operation request, send the atomic operation request to the second pipeline stage.

[0133] Other requests refer to requests other than atomic operation requests, including data read / write requests, instruction access requests, and so on. Generally speaking, requests that arrive at the intermediate cache first and have higher priority are processed first, following this order of precedence. Each request in the full pipeline is processed one by one according to this rule. When an atomic operation request is encountered, it is sent to the second pipeline stage.

[0134] The second pipeline stage can read the tag and consistency status of the cache bar in the middle pipeline stage to obtain tag information and status information. The tag information is used to mark the high-order address of the cache bar. Since the cache of the middle pipeline stage is divided into multiple groups, different cache bars in the same group are distinguished by different tags. The status information is used to characterize the consistency state of the cache bar, such as one of the M state, E state, S state, and I state in MESI. Each cache bar has corresponding tag information and status information, and the tag information and status information of different cache bars are sent to the third pipeline stage.

[0135] The third pipeline stage matches the request address of the atomic operation request with the tag information of the cache bar. For the atomic operation request, it includes the request type and request address. The request address is the data address for performing the atomic operation on the required data. If the match is successful, it means that the required data is in the cache bar of the intermediate level cache. If the match fails, it means that the required data is not in the cache bar of the intermediate level cache.

[0136] And determine whether the status information of the cache bar (the cache bar that is matched above) is in the E state or the M state. The status results include the cache bar being in the E state or the M state, and also include the cache bar being not in the E state or the M state. These two states ensure the consistency and effectiveness of the cache in the multi-core system in the MESI protocol. By clarifying the status and behavior of the cache bar, data inconsistency and redundant access are avoided, and then the matching results and status results are sent to the fourth pipeline stage.

[0137] Further explanation is still given by taking the example of the intermediate level cache including the second level cache and the third level cache. For the case where the intermediate level cache includes the second level cache, the third level cache and the fourth level cache, as well as other intermediate level caches, please refer to the examples in this application.

[0138] The following is an example: For further information, refer to Figure 5 The fourth pipeline stage drives the fifth pipeline stage and the sixth pipeline stage to send the required data in the cache bar to the previous level cache according to the matching result and the status result; or sends the atomic operation request to the CSA or the next level cache according to the matching result and the status result, further comprising:

[0139] S501: When the matching result is a successful match and the status result is E state or M state, driving the fifth pipeline stage to select required data in the cache bar and sending the required data to the sixth pipeline stage;

[0140] S502: If the intermediate cache is a secondary cache, the sixth pipeline stage sends the required data to the LSU;

[0141] S503: If the intermediate cache is a level 3 cache, the sixth pipeline stage sends the required data to the level 2 cache, and the level 2 cache sends the required data to the LSU;

[0142] S504: When the matching result is a matching failure or the status result is neither E nor M,

[0143] S505: If the intermediate cache is a level 2 cache, the atomic operation request is sent to a level 3 cache;

[0144] S506: If the intermediate level cache is a level 3 cache, the atomic operation request is sent to the CSA.

[0145] When the matching result is successful and the status result is E or M, the fifth pipeline stage selects the required data in the cache bar corresponding to the matching result and the status result is E or M, and sends the required data to the sixth pipeline stage.

[0146] For the intermediate-level cache including the second-level cache, the third-level cache and the fourth-level cache, if the intermediate-level cache is the second-level cache, the sixth pipeline stage sends the required data to the LSU; if the intermediate-level cache is the third-level cache, the sixth pipeline stage sends the required data to the second-level cache, and from the second-level cache to the LSU; if the intermediate-level cache is the fourth-level cache, the sixth pipeline stage sends the required data to the third-level cache, from the third-level cache to the second-level cache, and from the second-level cache to the LSU.

[0147] When the matching result is a matching failure or the status result is neither in the E state nor in the M state, if the intermediate-level cache is a secondary cache, the atomic operation request is sent to the third-level cache, and the third-level cache executes the above steps S301-S304 as an intermediate-level cache, and gradually determines through six pipeline stages whether the required data of the request is in the third-level cache, and whether the third-level cache has exclusive modification permissions.

[0148] For the intermediate-level cache including the second-level cache, the third-level cache and the fourth-level cache, if the intermediate-level cache is the second-level cache, the atomic operation request is sent to the third-level cache, and the third-level cache executes the above steps S301-S304 as the intermediate-level cache. If the intermediate-level cache is the third-level cache, the atomic operation request is sent to the fourth-level cache, and the fourth-level cache executes the above steps S301-S304 as the intermediate-level cache. If the intermediate-level cache is the fourth-level cache, the atomic operation request is sent to the CSA.

[0149] In addition, in order to improve the efficiency of data access, the intermediate-level cache including the second-level cache and the third-level cache is still taken as an example for further explanation. For the case where the intermediate-level cache includes the second-level cache, the third-level cache and the fourth-level cache, as well as other intermediate-level caches, please refer to the examples in this application.

[0150] The embodiments of this specification also include:

[0151] The local consistency domain of the third-level cache defines a special state of a cache bar: the cache bar only exists in the current third-level cache, or only exists in the first-level data cache or second-level cache of at least one core in the local consistency domain to which the current third-level cache belongs.

[0152] The cache bar exists only in the current L3 cache, or only in the L1 data cache or L2 cache of at least one core in the local coherence domain to which the current L3 cache belongs, but not in other L3 caches or other cores.

[0153] Generally speaking, the local coherence domain of the lowest level cache in the intermediate level cache defines a special state of the cache bar, where the cache bar only exists in the current lowest level cache, or only exists in the upper level cache of at least one core in the local coherence domain to which the current lowest level cache belongs.

[0154] For the intermediate-level cache including the second-level cache, the third-level cache and the fourth-level cache, the local consistency domain of the fourth-level cache defines the special state of the cache bar as the cache bar only exists in the current fourth-level cache, or only exists in the first-level data cache, the second-level cache or the third-level cache of at least one core in the local consistency domain to which the current fourth-level cache belongs.

[0155] Based on this, refer to Figure 6 , the embodiments of this specification also include:

[0156] S601: The LSU receives an atomic operation request and sends the atomic operation request to the L3 cache;

[0157] S602: The L3 cache determines whether there is a cache bar in a special state in the local coherence domain, and the data required by the atomic operation request is in the cache bar in the special state;

[0158] S603: The L3 cache selects a cache bar in the special state and sends the required data in the cache bar in the special state to the LSU. The state information of the cache bar in the special state is E state or M state.

[0159] S604: The LSU performs a proximal atomic operation to complete the atomic operation request.

[0160] In practical applications, this mechanism can significantly improve the performance of multi-core systems, especially when frequent atomic operations are required. By optimizing data access paths and ensuring data consistency, the system can respond to and process requests more quickly, reducing latency and increasing throughput. The local consistency domain mechanism optimizes the processing flow of atomic operations, thereby improving the efficiency and performance of multi-core systems.

[0161] Through the method of the embodiment of this specification, the permission check of each level of cache is used to ensure that the data being operated is consistent and correct, avoid concurrency conflicts, and ensure data consistency. And through the layered processing strategy, it is ensured that even if the local cache cannot process the request, the system can still complete the task through remote operation, thereby improving the robustness and flexibility of the system. It also maximizes the use of local cache levels, reduces the delay of atomic operations, improves the response speed of the overall system, avoids the performance degradation of the multi-core system caused by pushing data in the local cache consistency domain to the remote CSA side, and improves the performance of the multi-core system.

[0162] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of relevant data comply with the relevant laws, regulations and standards of relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0163] This application provides users with corresponding big data analysis (such as personal biometrics, identity data, consumption data, asset data, electronic terminal operation data, etc.) operation entrances for users to choose to agree or reject automated decision-making results; if the user chooses to reject, the expert decision-making process will be entered.

[0164] Based on the above-mentioned method of multi-level support for proximal atomic operations and remote atomic operations, the embodiments of this specification also provide a corresponding device for multi-level support for proximal atomic operations and remote atomic operations. The device may include a system (including a distributed system), software (application), module, component, server, client, etc. using the method described in the embodiments of this specification and combined with the necessary implementation hardware. Based on the same innovative concept, the devices in one or more embodiments provided in the embodiments of this specification are as described in the following embodiments. Since the implementation scheme and method for solving the problem of the device are similar, the implementation of the specific device in the embodiments of this specification can refer to the implementation of the aforementioned method, and the repetitions will not be repeated. As used below, the term "unit" or "module" can implement a combination of software and / or hardware for predetermined functions. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceived.

[0165] Specifically, Figure 7 This is a schematic diagram of the module structure of an embodiment of a multi-level device supporting near-end atomic operations and far-end atomic operations provided by the embodiment of this specification, with reference to Figure 7 As shown, an embodiment of this specification provides a multi-level device for supporting near-end atomic operations and far-end atomic operations, including: an LSU judgment module 100, an intermediate cache judgment module 200, and a CSA execution module 300.

[0166] An LSU determination module 100 is configured to receive an atomic operation request from the LSU, and determine whether the data required by the request is in the first-level data cache and whether the first-level data cache has exclusive modification permission. If both are yes, the LSU performs a proximal atomic operation to complete the atomic operation request. If not, the LSU sends the atomic operation request to the intermediate-level cache.

[0167] The intermediate cache judgment module 200 is configured to receive an atomic operation request from the intermediate cache, and to judge whether the data required by the request is in the intermediate cache and whether the intermediate cache has exclusive modification permission. If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request. If no, the intermediate cache sends the atomic operation request to the CSA.

[0168] The CSA execution module 300 is used for the CSA to receive an atomic operation request, execute a remote atomic operation, and send a completion signal to the LSU after completing the atomic operation request.

[0169] Reference Figure 8 As shown, based on the above-mentioned method of multi-level support for near-end atomic operations and far-end atomic operations, an embodiment of this specification further provides a computer device 802, wherein the above-mentioned method runs on the computer device 802. The computer device 802 may include one or more processors 804, such as one or more central processing units (CPUs) or graphics processing units (GPUs), each of which may implement one or more hardware threads. The computer device 802 may also include any memory 806, which is used to store any type of information such as code, settings, data, etc. In a specific embodiment, a computer program on the memory 806 and executable on the processor 804, when the computer program is executed by the processor 804, can execute instructions according to the above-mentioned method. For example, without limitation, the memory 806 may include any one or more combinations of the following: any type of RAM, any type of ROM, a flash memory device, a hard disk, an optical disk, etc. More generally, any memory may use any technology to store information. Further, any memory may provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of the computer device 802. In one embodiment, when the processor 804 executes the associated instructions stored in any memory or combination of memories, the computer device 802 can perform any operation of the associated instructions. The computer device 802 also includes one or more drive mechanisms 808 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0170] The computer device 802 may also include an input / output module 810 (I / O) for receiving various inputs (via input devices 812) and for providing various outputs (via output devices 814). A specific output mechanism may include a presentation device 816 and an associated graphical user interface 818 (GUI). In other embodiments, the input / output module 810 (I / O), input devices 812, and output devices 814 may not be included, and the computer device 802 may simply be a computer device in a network. The computer device 802 may also include one or more network interfaces 820 for exchanging data with other devices via one or more communication links 822. One or more communication buses 824 couple the components described above together.

[0171] The communication link 822 may be implemented in any manner, for example, via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, etc., or any combination thereof. The communication link 822 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0172] Corresponding to Figures 1-6 The method in this specification also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the above method are executed.

[0173] The embodiment of this specification also provides a computer-readable instruction, wherein when the processor executes the instruction, the program therein causes the processor to execute the following Figures 1 to 6 The method shown.

[0174] The embodiment of the present specification also provides a computer program product, wherein the computer program product is executed by a processor of a computer device to perform the following Figures 1 to 6 The method shown.

[0175] The computer program product described in this specification is a software product that mainly implements the method described in this specification through a computer program.

[0176] It should be understood that in the various embodiments of this specification, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0177] It should also be understood that in the embodiments of this specification, the term "and / or" is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent three situations: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, in the embodiments of this specification, the character " / " generally indicates that the associated objects are in an "or" relationship.

[0178] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of this specification can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this specification.

[0179] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0180] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or can be an electrical, mechanical or other form of connection.

[0181] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of this specification.

[0182] In addition, the functional units in the various embodiments of this specification may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0183] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of this specification is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of this specification. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0184] Specific embodiments are used in this specification to illustrate the principles and implementation methods of the embodiments of this specification. The description of the above embodiments is only used to help understand the methods and core ideas of the embodiments of this specification. At the same time, for those skilled in the art, based on the ideas of the embodiments of this specification, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the embodiments of this specification.

Claims

1. A method for supporting near-end atomic operations and far-end atomic operations at multiple levels, characterized in that: include: The LSU receives an atomic operation request and determines whether the data required by the request is in the first-level data cache and whether the first-level data cache has exclusive modification permission; If both are true, the LSU performs the proximal atomic operation to complete the atomic operation request; If yes, the LSU sends the atomic operation request to the intermediate level cache; The intermediate-level cache receives an atomic operation request, and the intermediate-level cache determines whether data required by the request is in the intermediate-level cache, and whether the intermediate-level cache has exclusive modification permission, wherein the intermediate-level cache includes a second-level cache and a third-level cache, and the second-level cache determines whether the data required by the request is in the second-level cache, and whether the second-level cache has exclusive modification permission; If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request; If yes, the L2 cache sends the atomic operation request to the L3 cache; The third-level cache determines whether the data required by the request is in the third-level cache and whether the third-level cache has exclusive modification permission; If both are yes, the required data is sent to the secondary cache, the secondary cache sends it to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request; If yes, the L3 cache sends the atomic operation request to the CSA; If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request; If yes, the intermediate level cache sends the atomic operation request to the CSA; CSA receives the atomic operation request, performs the remote atomic operation, and sends a completion signal to LSU after completing the atomic operation request.

2. The method according to claim 1, characterized in that The intermediate level cache determines whether the required data of the request is in the intermediate level cache, and whether the intermediate level cache has exclusive modification permission further includes: The intermediate level cache determines step by step through the improved six pipeline stages whether the required data of the request is in the intermediate level cache, and whether the intermediate level cache has exclusive modification authority.

3. The method according to claim 2, characterized in that The intermediate cache determines whether the requested data is in the intermediate cache through six pipeline stages, and whether the intermediate cache has exclusive modification authority further includes: The first pipeline stage selects the request according to the set rules and sends it to the second pipeline stage; The second pipeline stage reads the tag and coherence status of the cache bar in the middle pipeline stage, and sends the obtained tag information and status information of the cache bar to the third pipeline stage; The third pipeline stage matches the request address of the request with the tag information of the cache bar to obtain a matching result, wherein the matching result indicates whether the required data is in the cache bar of the intermediate cache; and determines whether the state information of the cache bar is in the E state or the M state to obtain a status result; and sends the matching result and the status result to the fourth pipeline stage; The fourth pipeline stage drives the fifth pipeline stage and the sixth pipeline stage to send the required data in the cache bar to the LSU or the previous level cache based on the matching result and the status result; or sends the atomic operation request to the CSA or the next level cache based on the matching result and the status result.

4. The method according to claim 3, characterized in that The first pipeline stage selects the request according to the set rule and sends it to the second pipeline stage further comprising: The first pipeline stage treats the atomic operation request and other requests as a full request; Processing each request in the full request one by one according to the order in which each request in the full request arrives at the intermediate cache and the priority of each request; When processing the atomic operation request, the atomic operation request is sent to the second pipeline stage.

5. The method according to claim 3, characterized in that The fourth pipeline stage drives the fifth pipeline stage and the sixth pipeline stage to send the required data in the cache bar to the upper level cache according to the matching result and the status result; Alternatively, sending the atomic operation request to the CSA or the next-level cache according to the matching result and the status result further includes: When the matching result is a successful match and the state result is E state or M state, driving the fifth pipeline stage to select the required data in the cache bar and sending the required data to the sixth pipeline stage; If the intermediate level cache is a secondary cache, the sixth pipeline stage sends the required data to the LSU; If the intermediate level cache is a level 3 cache, the sixth pipeline stage sends the required data to the level 2 cache, and the level 2 cache sends the required data to the LSU; When the matching result is a matching failure or the status result is neither E nor M, If the intermediate cache is a level 2 cache, sending the atomic operation request to a level 3 cache; If the intermediate level cache is a level 3 cache, the atomic operation request is sent to the CSA.

6. The method according to claim 2, characterized in that Also includes: The local consistency domain of the third-level cache defines a special state of a cache bar: the cache bar only exists in the current third-level cache, or only exists in the first-level data cache or second-level cache of at least one core in the local consistency domain to which the current third-level cache belongs.

7. The method according to claim 6, characterized in that Also includes: The LSU receives the atomic operation request and sends the atomic operation request to the third-level cache; The third-level cache determines whether there is a cache bar in a special state in the local coherence domain, and the data required by the atomic operation request is in the cache bar in the special state; The third-level cache selects the cache bar in the special state and sends the required data in the cache bar in the special state to the LSU. The state information of the cache bar in the special state is E state or M state. The LSU performs the proximal atomic operation and completes the atomic operation request.

8. A device that supports multi-level proximal atomic operations and distal atomic operations, characterized in that: The device comprises: An LSU judgment module, configured for the LSU to receive an atomic operation request, and the LSU to judge whether the data required by the request is in the first-level data cache, and whether the first-level data cache has exclusive modification permission, wherein the intermediate-level cache includes the second-level cache and the third-level cache, and the second-level cache judges whether the data required by the request is in the second-level cache, and whether the second-level cache has exclusive modification permission; If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request; If yes, the L2 cache sends the atomic operation request to the L3 cache; The third-level cache determines whether the data required by the request is in the third-level cache and whether the third-level cache has exclusive modification permission; If both are yes, the required data is sent to the secondary cache, the secondary cache sends it to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request; If yes, the L3 cache sends the atomic operation request to the CSA; If both are true, the LSU performs the proximal atomic operation to complete the atomic operation request; If yes, the LSU sends the atomic operation request to the intermediate level cache; An intermediate cache judgment module is configured to receive an atomic operation request from an intermediate cache, and to judge whether the data required by the request is in the intermediate cache, and whether the intermediate cache has exclusive modification permission; If both are yes, the required data is sent to the LSU, and the LSU performs a proximal atomic operation to complete the atomic operation request; If yes, the intermediate level cache sends the atomic operation request to the CSA; The CSA execution module is used for the CSA to receive atomic operation requests, execute remote atomic operations, and send a completion signal to the LSU after completing the atomic operation request.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: When the computer program is executed by the processor, the computer program executes the instructions of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor of a computer device, the computer program executes the instructions of the method according to any one of claims 1 to 7.

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