Chip diagnosis coverage calculation method and device

Abstract

The application relates to the technical field of chip diagnosis coverage, and discloses a chip diagnosis coverage calculation method and device, which comprises the following steps: according to a safety mechanism design in an RTL code stage, different types of faults are injected into a specified chip module through an EDA tool to test the diagnosis coverage of the chip module; test results of the diagnosis coverage of the chip module according to the different types of faults are obtained and classified; the proportion of each classified test result in the overall test result is calculated, and the diagnosis coverage of the safety mechanism in a working state is judged based on an ISO26262 standard. In view of the characteristics that the simulation evaluation diagnosis coverage is not reasonable and accurate, various test conditions are designed for the simulation evaluation diagnosis coverage, and multiple diagnosis coverage calculation formulas are set according to the test conditions; simulation data is obtained through fault injection simulation; the simulation data is brought into a more reasonable calculation model; and more accurate and reasonable simulation coverage is calculated.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip diagnosis coverage rate technical field, and particularly relates to a chip diagnosis coverage rate calculation method and device. BACKGROUND

[0002] The content of the automotive semiconductor functional safety is proposed in the 11th part of ISO 26262:2018 version in 2018, which highlights the importance of the automotive semiconductor functional safety. The safety mechanism diagnosis coverage rate in the functional safety design of the automotive chip can provide methods and guidance for verifying the integrity and correctness of the development of the functional safety of the automotive chip, and provide the chip user with the basis and reference of the chip application layer.

[0003] The safety mechanism efficiency mainly refers to the diagnosis coverage rate of the safety mechanism. The coverage rate describes the probability that the safety mechanism can discover in time and make the system respond effectively when the real physical risk is found, that is, the fault is injected in the chip design simulation test. The diagnosis coverage rate (DC) is the core test index of the functional safety mechanism design. The diagnosis coverage rate calculation method for the automotive chip usually adopts simulation test. In the simulation test, the diagnosis coverage rate can be evaluated only for a single test excitation or a single safety mechanism. Under the conventional condition, only one fault injection simulation test case exists for the tested module. The diagnosis coverage rate can be directly calculated through simulation, that is:

[0004] However, in actual application, the tested module generally has multiple safety mechanisms and multiple simulation environments. Therefore, multiple fault injection simulation test excitations are required. The above conventional DC calculation model cannot meet the DC calculation demand any more. Moreover, the result calculated only through the above conventional DC calculation model is not reasonable and accurate. SUMMARY

[0005] In order to solve the problem that the result of the diagnosis coverage rate of the automotive chip is not reasonable and accurate in the prior art, the present application provides a chip diagnosis coverage rate calculation method and device.

[0006] The technical content of the present application is as follows:

[0007] The present application provides a chip diagnosis coverage rate calculation method, which comprises the following steps:

[0008] According to the safety mechanism design in the RTL code stage, different types of faults are injected into the specified chip module through the EDA tool, and the diagnosis coverage rate of the chip module is tested;

[0009] The test results of the diagnosis coverage rate of the chip module according to the different types of faults are obtained and classified;

[0010] The proportion of each classified test result in the overall test result is calculated, and the diagnostic coverage of the safety mechanism in the working state is evaluated based on the ISO26262 standard.

[0011] Further, when the EDA tool injects different types of faults into the specified chip module, the diagnostic coverage test of the chip module includes:

[0012] The fault injection simulation is simulation data, and the simulation data is brought into different fault models to realize the diagnostic coverage test.

[0013] Further, injecting the different types of faults includes:

[0014] Different test stimuli are designed for different chip modules and fault models, and different test stimuli output different test results.

[0015] Further, the test results of the diagnostic coverage test of the chip module according to the injection of different types of faults are obtained and classified, including:

[0016] The test results are divided into safe and risky based on whether the results of fault injection change the standard function output results.

[0017] Further, the test results of the diagnostic coverage test of the chip module according to the injection of different types of faults are obtained and classified, including:

[0018] Based on whether the results of fault injection can be captured by the safety mechanism, it is divided into monitorable and unmonitorable.

[0019] Further, the fault model is established based on the same or multiple simulation environments.

[0020] Further, the diagnostic coverage when the fault model is established based on the same simulation environment includes:

[0021] Under multiple safety mechanisms, the diagnostic coverage is calculated in a combined and insufficient manner, and is calculated by formula (1):

[0022] DC ME (%) = DC1 + DC2*(1-DC1) + DC3*(1-DC1-DC2*(1-DC1))... (1);

[0023] Under multiple safety mechanisms, the diagnostic coverage is calculated by taking the average value, and is calculated by formula (2):

[0024]

[0025] Under multiple safety mechanisms, the diagnostic coverage adopts a conservative result, and the calculation is realized through formula (3):

[0026] DC eff =DC lowest (3);

[0027] Wherein, DC1, DC2, DC3 refer to the diagnostic coverage of the measured module under different safety mechanisms, DC eff is the diagnostic coverage, DC lowest is the lowest safety mechanism diagnostic coverage.

[0028] Further, the fault model is based on the diagnostic coverage when multiple simulation environments are established, and includes:

[0029] Under multiple different diagnostic coverage, the overall average is calculated through formula (4):

[0030]

[0031] Under different diagnostic coverage of a single safety mechanism, the calculation is obtained through formula (5):

[0032]

[0033] The application also provides a chip diagnostic coverage calculation device, at least including: a compiler, a simulator, a fault injection script module and a comparator, the simulator is connected with the compiler, the fault injection script module and the comparator respectively, the chip diagnostic coverage calculation method injects faults into the simulator through the fault injection script module, and obtains simulation data by comparing the injected fault simulation and normal simulation through the comparator.

[0034] The application has at least the following beneficial effects: multiple test conditions are designed for the characteristics that the simulation evaluation diagnostic coverage is not reasonable and accurate, multiple diagnostic coverage calculation formulas are set accordingly, simulation data is obtained through fault injection simulation, more reasonable simulation data is brought into the simulation data through a more reasonable calculation model, more accurate and more reasonable simulation coverage is calculated, the integrity and correctness of the functional safety design of the chip design stage calculation evaluation are improved, and the application provides a basis for subsequent chip functional safety quantitative analysis. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 A fault injection result classification schematic diagram of a chip diagnostic coverage calculation method provided by the application.

[0036] Figure 2 A fault injection architecture of a chip diagnostic coverage calculation device provided by the application.

[0037] Figure 3This invention discloses an operating architecture of a chip diagnosis coverage calculation device. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] The present invention provides a chip diagnostic coverage calculation method, comprising the following steps:

[0040] During the chip design phase, fault injection simulation is required to verify the correctness and effectiveness of the security mechanism. This involves injecting different types of faults into the specified chip module using EDA tools based on the security mechanism designed in the RTL code phase to test the diagnostic coverage of the chip module.

[0041] Obtaining and classifying test results of diagnostic coverage of the chip module according to different types of faults injected;

[0042] Calculate the proportion of each categorized test result in the overall test result, and judge the diagnostic coverage of the safety mechanism in the working state based on the ISO26262 standard.

[0043] Furthermore, when different types of faults are injected into a designated chip module through the EDA tool, the diagnostic coverage test of the chip module is performed, including:

[0044] The fault injection simulation is performed as simulation data, and the simulation data is introduced into different fault models to implement diagnostic coverage testing.

[0045] Furthermore, injecting the different types of faults includes:

[0046] Different test stimuli are designed for different chip modules under test and fault models. Different test stimuli output different test results and fault models (constant 0 / 1 stuck and flipped).

[0047] like Figure 1 As shown, the fault injection results are divided into 4 categories, which are classified as follows:

[0048] Obtain and classify the diagnostic coverage test results of the chip module based on different types of injected faults, including:

[0049] The test results are divided into safe and risky based on whether the results of fault injection change the standard functional output results.

[0050] The test results of diagnostic coverage of the chip module according to different types of injected faults are acquired and classified, including:

[0051] The test results are divided into monitorable and unmonitorable based on whether the results of fault injection can be captured by the security mechanism.

[0052] In practical applications, the tested module generally has multiple security mechanisms and multiple simulation environments, so the application is matched with multiple fault injection simulation test excitations, which cannot further meet the DC calculation demand through a conventional DC calculation model, in which case, the application proposes five DC calculation models applicable to the case that the tested module has multiple fault injection simulation test excitations and multiple fault injection simulation results.

[0053] Further, the fault model is established based on the same or multiple simulation environments.

[0054] Further, the diagnostic coverage when the fault model is established based on the same simulation environment includes:

[0055] Under multiple security mechanisms, the diagnostic coverage is calculated in a combined and insufficient manner, and the calculation is realized through formula (1):

[0056] DC ME (%) = DC1 + DC2*(1-DC1) + DC3*(1-DC1-DC2*(1-DC1))... (1);

[0057] Under multiple security mechanisms, the diagnostic coverage takes an average value, and the calculation is realized through formula (2):

[0058]

[0059] Under multiple security mechanisms, the diagnostic coverage takes a conservative result, and the calculation is realized through formula (3):

[0060] DC eff = DC lowest (3);

[0061] Wherein, DC1, DC2 and DC3 refer to the diagnostic coverage of different security mechanisms for the tested module, DC eff is the diagnostic coverage, and DC lowest is the lowest security mechanism diagnostic coverage.

[0062] Further, the diagnostic coverage when the fault model is established based on multiple simulation environments includes:

[0063] The overall average is calculated by formula (4) in the case of different diagnostic coverage of multiple different security mechanisms:

[0064]

[0065] The result is calculated by formula (5) in the case of different diagnostic coverage of a single security mechanism:

[0066]

[0067] According to Figure 2 The chip diagnostic coverage calculation device also includes a compiler, an emulator, a fault injection script module, and a comparator. The emulator is connected to the compiler, the fault injection script module, and the comparator. The chip diagnostic coverage calculation method injects faults into the emulator through the fault injection script module and obtains simulation data by comparing the injected fault simulation and normal simulation through the comparator.

[0068] Linux system: As the basic operating system of the test environment, it provides the platform and tools needed to run the test system. The compiler is responsible for converting source code into executable code. The emulator simulates the software running environment, allowing developers to test the code without actually running the software. The fault injection script is used to inject specific faults into the emulator to simulate the behavior of the software under abnormal conditions. The test limit injection compiler adds specific limitations during compilation to test the performance of the software under resource-limited conditions. Through the comparator, the actual running result can be compared with the expected result to verify the stability and reliability of the software. This process not only helps to find potential problems, but also optimizes the performance of the software to ensure its normal operation under various conditions.

[0069] Among them, Figure 2 The structure also includes test vectors: input data sets used to test software, which can be normal operation required data or special data used to trigger potential defects of the software;

[0070] Simulation results: the output results obtained after the emulator runs simulation according to the test vectors.

[0071] Starting from the compiler, passing through the emulator and fault injection simulation, the test results are finally output by the comparator. The entire process embodies the complete cycle from code compilation to result verification in software testing, ensuring that the software can run normally under various conditions and timely discover and repair potential problems.

[0072] According to Figure 3As shown, the application utilizes a PC end to connect with a measured target board through a CAN communication device, the measured chip is arranged on the measured target board, the PC end also controls a power supply and an oscilloscope on the measured target board, and the PC end exchanges signals with the measured target board through the oscilloscope.

[0073] The application proposes a board-level vehicle regulation level control chip function safety test, a diagnosis coverage rate calculation method based on fault injection simulation results, and more calculation models are designed, compared with the traditional calculation method, more safety mechanisms are considered, and the complex situation of multiple test incentives is considered, which provides a new scheme for evaluating the integrity and correctness of chip function safety development, and provides a more accurate and more reasonable method for evaluating whether the chip function safety development meets the application requirements.

[0074] The above is only an embodiment of the application, and does not limit the patent range of the application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection range of the application.

Claims

1. A chip diagnostic coverage calculation method, characterized by: The following steps are involved: Based on the safety mechanism design at the RTL code stage, different types of faults are injected into the specified chip modules through EDA tools to test the diagnostic coverage of the chip modules. Obtaining and classifying test results of diagnostic coverage of the chip module according to different types of faults injected; Calculate the proportion of each categorized test result in the overall test result, and evaluate the diagnostic coverage of the safety mechanism in working condition based on the ISO26262 standard; Among them, when injecting different types of faults, they include: Fault injection simulation is used as simulation data, and the simulation data is brought into different fault models to achieve diagnostic coverage testing; The fault model is established based on the same or multiple simulation environments; Design different test stimuli for different chip modules and fault models under test, and different test stimuli output different test results; The step of obtaining and classifying the test results of the diagnostic coverage of the chip module according to different types of injected faults includes: Based on whether the results of fault injection can be captured by the safety mechanism, they are divided into monitorable and unmonitorable; Among them, there are 5 DC calculation models that can be applied to the test module with multiple fault injection simulation test stimuli and multiple fault injection simulation results; The diagnostic coverage when the fault models are established based on the same simulation environment includes: Under multiple safety mechanisms, the calculation of diagnostic coverage is performed by combining insufficient calculations, and the calculation is realized through formula (1): DC ME (%)=DC1+DC2*(1-DC1)+DC3*(1-DC1-DC2*(1-DC1))...(1); Under multiple safety mechanisms, the diagnostic coverage rate takes the average value and is calculated using formula (2): Under multiple safety mechanisms, the diagnostic coverage adopts conservative results and is calculated by formula (3): DC eff =DC lowest (3); Among them, DC1, DC2, and DC3 refer to the diagnostic coverage of different safety mechanisms for the module under test. eff is the diagnostic coverage, DC lowest Provides the lowest diagnostic coverage for safety mechanisms; The diagnostic coverage when the fault model is established based on multiple simulation environments includes: In the case of multiple different diagnostic coverages, the overall average value is calculated using formula (4): When different diagnostic coverages occur under a single safety mechanism, the following formula (5) is used to calculate:

2. The chip diagnostic coverage calculation method according to claim 1, characterized in that: Obtain and classify the diagnostic coverage test results of the chip module based on different types of injected faults, including: The test results are classified as safe or risky based on whether the results of the fault injection change the standard functional output results.

3. A chip diagnostic coverage calculation device, according to the chip diagnostic coverage calculation method of claim 1, characterized in that: At least: A compiler, a simulator, a fault injection script module and a comparator are provided. The simulator is connected to the compiler, the fault injection script module and the comparator respectively. The chip diagnostic coverage calculation method injects faults into the simulator through the fault injection script module, and obtains simulation data by comparing the injected fault simulation with the normal simulation through the comparator.

Images