Oxide semiconductor 2T0C DRAM non-volatile power-off test circuit and verification method

Abstract

The present invention discloses a non-volatile power-off test circuit and verification method for oxide semiconductor 2T0C DRAMs, belonging to the field of information materials and device technology. The test circuit includes an oxide semiconductor 2T0C DRAM cell, a transmission gate, an input data buffer, a current-mode sense amplifier, and a bootstrap write wordline driver. After a write operation on the oxide semiconductor 2T0C DRAM cell, a high-resistance node is introduced via the transmission gate, achieving complete power-off of the oxide semiconductor 2T0C DRAM cell and isolation from external circuits. The present invention effectively performs non-volatile testing and verification on oxide semiconductor 2T0C DRAM cells, thereby broadening the application scope of oxide semiconductor 2T0C DRAM non-volatility and having important implications for its development in the post-Moore era.

Description

Technical Field

[0001] The patent of this invention relates to an oxide semiconductor 2T0C DRAM non-volatile power-off test circuit and verification method, which belongs to the field of information materials and device technology. Background Art

[0002] Oxide semiconductor materials are widely used in the display field due to their advantages of high transmittance, high mobility and large-area uniformity. In recent years, with the continuous development of the integrated circuit industry, oxide semiconductor materials with low thermal budget processes have shown great potential in the fields of logic, storage and radio frequency compatible with the back-end. Thanks to the wide bandgap of oxide semiconductors, a 10-μm CMOS process has been achieved in oxide semiconductor transistors. -20 Ultra-low off-state current of A / μm. Based on this unique advantage, 2T0C-structured oxide semiconductor DRAM cells and systems have been thoroughly and meticulously studied. Its excellent leakage characteristics reduce the requirements for storage capacitor size, enabling a 2T0C design that uses the gate capacitance of the read transistor to store charge. This structure not only offers the unique advantage of lossless read operations, but also provides a viable solution for high-density 3D-DRAM by eliminating the need for high-aspect ratio capacitors. Recent work has demonstrated that data retention times in 2T0C DRAM cells based on oxide semiconductor materials can exceed thousands of seconds with storage capacitance values ​​below a few femtofarads.

[0003] The excellent data retention characteristics of 2T0C DRAM cells based on oxide semiconductor materials change the data volatility of traditional silicon-based DRAM cells. The internal structure of 2T0C DRAM cells, made of oxide semiconductor materials, isolates read and write operations from each other. This lossless read operation makes them non-volatile. Even in the event of a power outage, the data stored in the DRAM cell is not lost, and the data can be read again after power is restored. This characteristic ensures that non-volatile memory protects data from loss in the event of a sudden power outage. Summary of the Invention

[0004] The present invention provides an oxide semiconductor 2T0C DRAM non-volatile power-off test circuit and verification method, which can improve the reliability of the oxide semiconductor 2T0C DRAM system.

[0005] The technical solutions provided by the present invention are as follows:

[0006] An oxide semiconductor 2T0C DRAM non-volatile power-off test circuit, characterized in that the 2T0C DRAM unit is connected to four transmission gates, wherein the RBL port of the 2T0C DRAM unit is connected to the OUT port of the first transmission gate, the IN port of the first transmission gate is connected to the power supply, and the V EN port and V sense Signal connection, V of the first transmission gate EN *Port and V sense *Signal connection, the RWL port of the 2T0C DRAM cell is connected to the IN port of the second transmission gate, and the OUT port of the second transmission gate is connected to the I IN port connection, the second transmission gate's V EN port and V sense Signal connection, V of the second transmission gate EN *Port and V sense * signal connections; PEQ* of the current mode sense amplifier is connected to the PEQ* signal, VDD is connected to the power supply, PEQ is connected to the PEQ signal, VASEN* is connected to the VASEN* signal, VSAEN is connected to the VSAEN signal, CSAEN* is connected to the CSAEN* signal, SA and SA* ports are output ports, the WWL port of the 2T0C DRAM cell is connected to the OUT port of the fourth transmission gate, the IN port of the fourth transmission gate is connected to the OUT port of the bootstrap write word line driver, and the V EN port and V write Signal connection, V of the fourth transmission gate EN *Port and V write *Signal connection; the VDD port of the bootstrap write word line driver is connected to the power supply, the Phase port is connected to the Phase signal, the DEC* port is connected to the WWL*Bus signal, the DEC port is connected to the WWL Bus signal, the WBL port of the 2T0CDRAM unit is connected to the OUT port of the third transmission gate, the IN port of the third transmission gate is connected to the DOUT* port of the input data buffer, and the V EN port and V write Signal connection, V of the third transmission gate EN *Port and V write * signal connection, the VDD port of the input data buffer is connected to the power supply, the DATA port is connected to the WBL Bus signal, the TRAP* port is connected to the TRAP* signal, and the EN* port is connected to the EN* signal.

[0007] Furthermore, the 2T0C DRAM cell is composed of a first transistor and a second transistor, the active layers of the first transistor and the second transistor are a layer of oxide semiconductor thin film or a composite material of a stack of multiple oxide thin films, wherein the d-port of the first transistor is the WBL port of the 2T0C DRAM cell, the g-port of the first transistor is the WWL port of the 2T0C DRAM cell, the s-port of the first transistor is connected to the g-port of the second transistor, the d-port of the second transistor is the RBL port of the 2T0C DRAM cell, and the s-port of the second transistor is the RWL port of the 2T0C DRAM cell.

[0008] Furthermore, the transmission gate is composed of two transistors, wherein the d port of the first transistor is connected to the s port of the second transistor, the s port of the first transistor is connected to the d port of the second transistor, the d port of the first transistor and the s port of the second transistor together constitute the IN port of the transmission gate, the s port of the first transistor and the d port of the second transistor together constitute the OUT port of the transmission gate, and the g port of the first transistor is the V of the transmission gate. EN port, the g port of the second transistor is the V of the transmission gate EN *port.

[0009] Furthermore, the bootstrap write word line driver is composed of three transistors, wherein the d port of the first transistor is the DEC port of the bootstrap write word line driver, the g port of the first transistor is the VDD port of the bootstrap write word line driver, the s port of the first transistor is connected to the g port of the second transistor, the d port of the second transistor is the Phase port of the bootstrap write word line driver, the s port of the second transistor is connected to the d port of the third transistor, the g port of the third transistor is the DEC* port of the bootstrap write word line driver, the s port of the third transistor is connected to GND, and the s port of the second transistor and the d port of the third transistor together constitute the OUT port of the bootstrap write word line driver.

[0010] Furthermore, the input data buffer is composed of four transistors, two inverters, and four NAND gates, wherein the s port of the first transistor is connected to GND, the g port of the first transistor is connected to the g port of the third transistor, the d port of the first transistor is connected to the d port of the third transistor, the g port of the first transistor and the g port of the third transistor together constitute the DATA port of the input data buffer, the s port of the third transistor is connected to the d port of the fourth transistor, the g port of the fourth transistor is the EN* port of the input data buffer, the s port of the fourth transistor is the VDD port of the input data buffer, the g port of the second transistor is the EN* port of the input data buffer, the s port of the second transistor is connected to GND, the d port of the second transistor is connected to the d port of the third transistor and the d port of the first transistor The g port of the second transistor is connected to the IN port of the first inverter, the OUT port of the first inverter is connected to the B port of the third NAND gate, the A port of the third NAND gate is connected to the A port of the first NAND gate, and together constitute the TRAP* port of the input data buffer, the OUT port of the third NAND gate is connected to the B port of the fourth NAND gate, and at the same time, the OUT port of the third NAND gate is connected to the B port of the first NAND gate, the OUT port of the first NAND gate is connected to the A port of the second NAND gate, the B port of the second NAND gate is connected to the OUT port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the A port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the IN port of the second inverter, and the OUT port of the second inverter is the DOUT* port in the input data buffer.

[0011] Further, the NAND gate is composed of four transistors, the g port of the first transistor in the NAND gate is connected to the g port of the fourth transistor, the d port of the first transistor in the NAND gate is connected to the s port of the fourth transistor, the g port of the second transistor in the NAND gate is connected to the g port of the third transistor, the d port of the second transistor in the NAND gate is connected to the s port of the first transistor, the d port of the third transistor in the NAND gate is connected to the d port of the fourth transistor, the s port of the third transistor in the NAND gate and the s port of the fourth transistor together constitute the VDD port of the NAND gate, which is connected to the power supply, the s port of the second transistor in the NAND gate is connected to GND, and the d port of the first transistor and the s port of the fourth transistor together constitute the OUT port of the NAND gate.

[0012] Furthermore, the inverter is composed of two transistors, the g port of the first transistor in the inverter is connected to the g port of the second transistor in the inverter, the d port of the first transistor in the inverter is connected to the d port of the second transistor in the inverter, the g port of the first transistor in the inverter and the g port of the second transistor in the inverter together constitute the IN port of the inverter, and the d port of the first transistor in the inverter and the d port of the second transistor in the inverter together constitute the OUT port of the inverter.

[0013] Furthermore, the current mode sense amplifier is composed of 12 transistors. Among them, the g port of the first transistor is connected to the g port of the second transistor, together forming the VDD port of the current mode sense amplifier, the s port of the first transistor is connected to the s port of the second transistor, and together connected to GND, the d port of the first transistor is connected to the s port of the third transistor, the d port of the second transistor is connected to the s port of the fourth transistor, and the reference current source I REF Connected to the d-port of the first transistor, the d-port of the second transistor and the s-port of the fourth transistor together form the I of the current mode sense amplifier INThe d port of the third transistor is connected to the g port of the fourth transistor, the g port of the third transistor is connected to the d port of the fourth transistor, the d port of the third transistor is connected to the d port of the fifth transistor, the d port of the fourth transistor is connected to the d port of the sixth transistor, the g port of the fifth transistor is connected to the g port of the sixth transistor, the s port of the fifth transistor is connected to the s port of the sixth transistor, the g port of the fifth transistor and the g port of the sixth transistor together constitute the VSAEN port of the current mode sense amplifier, the s port of the fifth transistor and the s port of the sixth transistor are commonly connected to the d port of the seventh transistor, the g port of the seventh transistor is the CSAEN* port of the current mode sense amplifier, the s port of the seventh transistor is the VDD port of the current mode sense amplifier, the d port of the eighth transistor is connected to the s port of the ninth transistor, and the s port of the eighth transistor is connected to the d port of the ninth transistor The g port of the eighth transistor is connected to the PEQ port of the current mode sense amplifier, the g port of the ninth transistor is the PEQ* port of the current mode sense amplifier, the d port of the eighth transistor is connected to the d port of the fourth transistor, the s port of the eighth transistor is connected to the d port of the third transistor, the d port of the tenth transistor is connected to the s port of the eleventh transistor, the g port of the tenth transistor is connected to the d port of the eleventh transistor, the s port of the tenth transistor is connected to the g port of the eleventh transistor, the d port of the twelfth transistor is connected to the d port of the tenth transistor, the g port of the twelfth transistor is the VSAEN* port of the current mode sense amplifier, the s port of the twelfth transistor is the VDD port of the current mode sense amplifier, the s port of the tenth transistor is the SA output port of the current mode sense amplifier, and the d port of the eleventh transistor is the SA* output port of the current mode sense amplifier.

[0014] The present invention further provides a non-volatile power-off test and verification method for an oxide semiconductor 2TOC DRAM, which is characterized by being divided into three steps: a write operation, a hold operation, and a read operation. The test waveforms of the three operations are all based on the CLK signal provided by an external programmable gate array as a reference. The specific steps include:

[0015] 1) During write operation, V sense The signal always remains at a low level; V write The signal becomes high level at time t2, V writeThe signal becomes low when it reaches time t5; the EN* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the TRAP* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the WWL Bus, that is, the DEC signal becomes high when it reaches time t2, and becomes low when it reaches time t5; the DEC* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the Phase signal becomes high when it reaches time t3, and becomes low when it reaches time t4; for the WBL Bus, that is, the DATA signal, if the data written to the oxide semiconductor 2T0C DRAM unit is 1, it becomes high when it reaches time t2, and becomes low when it reaches time t5; for the WBL Bus, that is, the DATA signal, if the data written to the oxide semiconductor 2T0C DRAM unit is 0, the signal is always low;

[0016] 2) During the operation, V sense The signal always remains at a low level; V write The signal always remains at a low level. sense signal and V write When the signals are all in the low level state, due to the high resistance characteristics of transmission gates 1, 2, 3, and 4, the WWL, WBL, RBL, and RWL ports of the oxide semiconductor 2T0C DRAM unit are all in the floating state, except for V sense signal and V write Except for the signal, no other signals are operated, and the oxide semiconductor 2T0C DRAM unit is in the power-off hold state;

[0017] 3) During the read operation, V sense The signal always maintains a high level state; V write The signal always maintains a low level state. For the CSAEN* signal, it becomes a low level when it reaches time t1 and becomes a high level when it reaches time t2; for the PEQ signal, it becomes a low level when it reaches time t1 and becomes a high level when it reaches time t4; for the PEQ* signal, it becomes a high level when it reaches time t1 and becomes a low level when it reaches time t4; for the VSAEN signal, it becomes a high level when it reaches time t2 and becomes a low level when it reaches time t3; for the VSAEN* signal, it becomes a low level when it reaches time t2 and becomes a high level when it reaches time t3.

[0018] The beneficial effects of the present invention are as follows:

[0019] To comprehensively and completely test the non-volatility of oxide semiconductor 2T0C DRAM, this invention patent proposes a new oxide semiconductor 2T0C DRAM non-volatile power-off test circuit. This circuit introduces a high-resistance node, designed as a transmission gate external to the memory cell, after a write operation in the oxide semiconductor 2T0C DRAM. This complete power-off of the oxide semiconductor 2T0C DRAM cell and its isolation from external circuits is achieved. The introduction of the high-resistance node enables effective non-volatility testing and verification of the oxide semiconductor 2T0C DRAM cell, thereby broadening the application scope of oxide semiconductor 2T0C DRAM non-volatility and having significant implications for its development in the post-Moore era. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the oxide semiconductor 2TOC DRAM non-volatile power-off test circuit module of the present invention;

[0021] Figure 2 Schematic diagram of an oxide semiconductor 2TOC DRAM unit circuit in a specific embodiment of the present invention;

[0022] Figure 3 Schematic diagram of a transmission gate in a specific embodiment of the present invention, wherein (1) and (2) are the module symbol and structure of the transmission gate respectively;

[0023] Figure 4 Schematic diagram of a bootstrap write word line driver circuit in a specific embodiment of the present invention;

[0024] Figure 5 Schematic diagram of an input data buffer circuit in a specific embodiment of the present invention;

[0025] Figure 6 A schematic diagram of a NAND gate circuit in a specific embodiment of the present invention;

[0026] Figure 7 Schematic diagram of an inverter in a specific embodiment of the present invention, wherein (1) and (2) are module symbols and structures respectively;

[0027] Figure 8 Schematic diagram of a current mode sense amplifier circuit in a specific embodiment of the present invention;

[0028] Figure 9 This is a timing diagram of a non-volatile test verification circuit in a verification method for a test circuit of the present invention;

[0029] Figure 10 A circuit timing diagram of a write operation in a verification method for a test circuit of the present invention;

[0030] Figure 11A circuit timing diagram of the power-off hold operation in the verification method of the test circuit of the present invention;

[0031] Figure 12 This is a circuit timing diagram of a read operation in the verification method of the test circuit of the present invention. DETAILED DESCRIPTION

[0032] The present invention provides an oxide semiconductor 2T0C DRAM non-volatile power-off test circuit, such as Figure 1 As shown, the structure is as follows: the RBL port of the 2T0C DRAM unit is connected to the OUT port of the transmission gate No. 1, the IN port of the transmission gate No. 1 is connected to the power supply, and the V EN port and V sense Signal connection, V of transmission gate 1 EN *Port and V sense *Signal connection. The RWL port of the 2T0C DRAM cell is connected to the IN port of the transmission gate 2, and the OUT port of the transmission gate 2 is connected to the I IN Port connection, V of transmission gate 2 EN port and V sense Signal connection, V of transmission gate 2 EN *Port and V sense * Signal connections; PEQ* of the current mode sense amplifier is connected to PEQ* signals, VDD is connected to the power supply, PEQ is connected to PEQ signals, VASEN* is connected to VASEN* signals, VSAEN is connected to VSAEN signals, CSAEN* is connected to CSAEN* signals, and SA and SA* ports are output ports. The WWL port of the 2T0C DRAM cell is connected to the OUT port of the No. 4 transmission gate, the IN port of the No. 4 transmission gate is connected to the OUT port of the bootstrap write word line driver, and the V EN port and V write Signal connection, V of transmission gate 4 EN *Port and V write *Signal connections: The VDD port of the bootstrap write word line driver is connected to the power supply, the Phase port is connected to the Phase signal, the DEC* port is connected to the WWL*Bus signal, and the DEC port is connected to the WWL Bus signal. The WBL port of the 2T0CDRAM unit is connected to the OUT port of the No. 3 transmission gate, the IN port of the No. 3 transmission gate is connected to the DOUT* port of the input data buffer, and the V EN port and V write Signal connection, V of transmission gate 3 EN *Port and V write*Signal connections. The VDD port of the input data buffer is connected to the power supply, the DATA port is connected to the WBL Bus signal, the TRAP* port is connected to the TRAP* signal, and the EN* port is connected to the EN* signal.

[0033] like Figure 2 As shown, a 2T0C DRAM cell is composed of transistor No. 1 and transistor No. 2. The active layers of transistors No. 1 and No. 2 include, but are not limited to, all oxide semiconductor thin films of various doping compositions and proportions, and a composite channel formed by stacking multiple oxide thin films. The transistor structures include, but are not limited to, bottom-gate, top-gate, dual-gate, fin-type, surround-gate, ring-channel, and vertical-channel structures. The d-port of transistor No. 1 serves as the WBL port of the 2T0C DRAM cell, the g-port of transistor No. 1 serves as the WWL port of the 2T0C DRAM cell, the s-port of transistor No. 1 is connected to the g-port of transistor No. 2, the d-port of transistor No. 2 serves as the RBL port of the 2T0C DRAM cell, and the s-port of transistor No. 2 serves as the RWL port of the 2T0C DRAM cell.

[0034] like Figure 3 As shown, the transmission gate consists of two transistors, where the d port of transistor No. 1 is connected to the s port of transistor No. 2, and the s port of transistor No. 1 is connected to the d port of transistor No. 2. The d port of transistor No. 1 and the s port of transistor No. 2 together constitute the IN port of the transmission gate, and the s port of transistor No. 1 and the d port of transistor No. 2 together constitute the OUT port of the transmission gate. The g port of transistor No. 1 is the V EN Port, the g port of transistor 2 is the V of the transmission gate EN *port.

[0035] like Figure 4 As shown, the bootstrap write word line driver consists of three transistors, wherein the d port of transistor No. 1 is the DEC port of the bootstrap write word line driver, the g port of transistor No. 1 is the VDD port of the bootstrap write word line driver, the s port of transistor No. 1 is connected to the g port of transistor No. 2, the d port of transistor No. 2 is the Phase port of the bootstrap write word line driver, the s port of transistor No. 2 is connected to the d port of transistor No. 3, the g port of transistor No. 3 is the DEC* port of the bootstrap write word line driver, the s port of transistor No. 3 is connected to GND, and the s port of transistor No. 2 and the d port of transistor No. 3 together constitute the OUT port of the bootstrap write word line driver.

[0036] like Figure 5 As shown in Figure 1, the input data buffer consists of four transistors, two inverters, and four NAND gates. Figure 6As shown, the g port of transistor No. 1 in the NAND gate is connected to the g port of transistor No. 4, the d port of transistor No. 1 in the NAND gate is connected to the s port of transistor No. 4, the g port of transistor No. 2 in the NAND gate is connected to the g port of transistor No. 3, the d port of transistor No. 2 in the NAND gate is connected to the s port of transistor No. 1, the d port of transistor No. 3 in the NAND gate is connected to the d port of transistor No. 4, the s port of transistor No. 3 in the NAND gate and the s port of transistor No. 4 together constitute the VDD port of the NAND gate, which is connected to the power supply, the s port of transistor No. 2 in the NAND gate is connected to GND, and the d port of transistor No. 1 and the s port of transistor No. 4 together constitute the OUT port of the NAND gate. The inverter is composed of two transistors, as shown in FIG. Figure 7 As shown, the g port of transistor No. 1 in the inverter is connected to the g port of transistor No. 2 in the inverter, the d port of transistor No. 1 in the inverter is connected to the d port of transistor No. 2 in the inverter, the g port of transistor No. 1 in the inverter and the g port of transistor No. 2 in the inverter together constitute the IN port of the inverter, and the d port of transistor No. 1 in the inverter and the d port of transistor No. 2 in the inverter together constitute the OUT port of the inverter.

[0037] In the input data buffer, the s-port of transistor #1 in the input data buffer is connected to GND, the g-port of transistor #1 in the input data buffer is connected to the g-port of transistor #3 in the input data buffer, and the d-port of transistor #1 in the input data buffer is connected to the d-port of transistor #3 in the input data buffer. Together, the g-port of transistor #1 and the g-port of transistor #3 form the DATA port of the input data buffer. The s-port of transistor #3 in the input data buffer is connected to the d-port of transistor #4, the g-port of transistor #4 serves as the EN* port of the input data buffer, and the s-port of transistor #4 serves as the VDD port of the input data buffer. The g-port of transistor #2 in the input data buffer serves as the EN* port of the input data buffer. The s-port of transistor #2 is connected to GND, and the d-port of transistor #2 is connected to the d-port of transistor #3 and the d-port of transistor #1. The g-port of transistor #2 in the input data buffer is connected to the IN port of inverter #1 in the input data buffer, and the OUT port of inverter #1 in the input data buffer is connected to the B-port of NAND gate #3. The A port of NAND gate #3 in the input data buffer is connected to the A port of NAND gate #1, together forming the TRAP* port of the input data buffer. The OUT port of NAND gate #3 in the input data buffer is connected to the B port of NAND gate #4, and the OUT port of NAND gate #3 is also connected to the B port of NAND gate #1. The OUT port of NAND gate #1 in the input data buffer is connected to the A port of NAND gate #2, the B port of NAND gate #2 is connected to the OUT port of NAND gate #4, the OUT port of NAND gate #2 is connected to the A port of NAND gate #4, and the OUT port of NAND gate #2 is connected to the IN port of inverter #2. The OUT port of inverter #2 constitutes the DOUT* port of the input data buffer.

[0038] like Figure 8 As shown, the current mode sense amplifier consists of 12 transistors. Among them, the g port of transistor No. 1 in the current mode sense amplifier is connected to the g port of transistor No. 2, together forming the VDD port of the current mode sense amplifier. The s port of transistor No. 1 in the current mode sense amplifier is connected to the s port of transistor No. 2, and both are connected to GND. The d port of transistor No. 1 in the current mode sense amplifier is connected to the s port of transistor No. 3, and the d port of transistor No. 2 in the current mode sense amplifier is connected to the s port of transistor No. 4. The reference current source I REF Connected to the d port of transistor 1, the d port of transistor 2 and the s port of transistor 4 together form the I of the current mode sense amplifier INThe d-port of transistor 3 in the current-mode sense amplifier is connected to the g-port of transistor 4, and the g-port of transistor 3 is connected to the d-port of transistor 4. The d-port of transistor 3 in the current-mode sense amplifier is connected to the d-port of transistor 5, and the d-port of transistor 4 is connected to the d-port of transistor 6. The g-port of transistor 5 in the current-mode sense amplifier is connected to the g-port of transistor 6, and the s-port of transistor 5 is connected to the s-port of transistor 6. The g-port of transistor 5 and the g-port of transistor 6 together constitute the VSAEN port of the current-mode sense amplifier. The s-port of transistor 5 and the s-port of transistor 6 are connected to the d-port of transistor 7. The g-port of transistor 7 in the current-mode sense amplifier serves as the CSAEN* port of the current-mode sense amplifier, and the s-port of transistor 7 serves as the VDD port of the current-mode sense amplifier. The d-port of transistor 8 in the current-mode sense amplifier is connected to the s-port of transistor 9, the s-port of transistor 8 is connected to the d-port of transistor 9, the g-port of transistor 8 is the PEQ port of the current-mode sense amplifier, and the g-port of transistor 9 is the PEQ* port of the current-mode sense amplifier. The d-port of transistor 8 in the current-mode sense amplifier is connected to the d-port of transistor 4, and the s-port of transistor 8 is connected to the d-port of transistor 3. The d-port of transistor 10 in the current-mode sense amplifier is connected to the s-port of transistor 11, the g-port of transistor 10 is connected to the d-port of transistor 11, and the s-port of transistor 10 is connected to the g-port of transistor 11. The d-port of transistor 12 in the current-mode sense amplifier is connected to the d-port of transistor 10, the g-port of transistor 12 is the VSAEN* port of the current-mode sense amplifier, and the s-port of transistor 12 is the VDD port of the current-mode sense amplifier. The s port of transistor No. 10 in the current mode sense amplifier is the SA output port of the current mode sense amplifier, and the d port of transistor No. 11 is the SA* output port of the current mode sense amplifier.

[0039] The verification method of the oxide semiconductor 2TOC DRAM non-volatile power-off test circuit of the present invention is divided into three steps: write operation, hold operation, and read operation. Figure 9 The test waveforms of the three operations are all based on the CLK signal provided by the external programmable gate array. This patent does not limit the amplitude and frequency of the CLK signal.

[0040] like Figure 10 As shown, during the write operation, V sense The signal always remains at a low level; V write The signal becomes high level at time t2, V writeThe signal becomes low when it reaches time t5; the EN* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the TRAP* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the WWL Bus, that is, the DEC signal becomes high when it reaches time t2, and becomes low when it reaches time t5; the DEC* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the Phase signal becomes high when it reaches time t3, and becomes low when it reaches time t4; for the WBLBus, that is, the DATA signal, if the data written to the oxide semiconductor 2T0C DRAM unit is 1, it becomes high when it reaches time t2, and becomes low when it reaches time t5; for the WBL Bus, that is, the DATA signal, if the data written to the oxide semiconductor 2T0C DRAM unit is 0, the signal is always low.

[0041] like Figure 11 As shown, in the hold operation, V sense The signal always remains at a low level; V write The signal always remains at a low level. sense signal and V write When the signals are all in the low level state, due to the high resistance characteristics of transmission gates 1, 2, 3, and 4, the WWL, WBL, RBL, and RWL ports of the oxide semiconductor 2T0C DRAM unit are all in a floating state. Therefore, this patent does not apply to the operation except for V sense signal and V write At this time, the oxide semiconductor 2TOC DRAM unit is in a power-off hold state.

[0042] like Figure 12 As shown, during the read operation, V sense The signal always maintains a high level state; V write The signal always remains in a low state. For the CSAEN* signal, it becomes low at time t1 and becomes high at time t2. For the PEQ signal, it becomes low at time t1 and becomes high at time t4. For the PEQ* signal, it becomes high at time t1 and becomes low at time t4. For the VSAEN signal, it becomes high at time t2 and becomes low at time t3. For the VSAEN* signal, it becomes low at time t2 and becomes high at time t3.

[0043] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. An oxide semiconductor 2TOC DRAM non-volatile power-off test circuit, characterized in that: The 2T0C DRAM unit is connected to four transmission gates, wherein the RBL port of the 2T0C DRAM unit is connected to the OUT port of the first transmission gate, the IN port of the first transmission gate is connected to the power supply, and the V EN port and V sense Signal connection, V of the first transmission gate EN *Port and V sense *Signal connection, the RWL port of the 2T0C DRAM cell is connected to the IN port of the second transmission gate, and the OUT port of the second transmission gate is connected to the I IN port connection, the second transmission gate's V EN port and V sense Signal connection, V of the second transmission gate EN *Port and V sense * signal connections; PEQ* of the current mode sense amplifier is connected to the PEQ* signal, VDD is connected to the power supply, PEQ is connected to the PEQ signal, VASEN* is connected to the VASEN* signal, VSAEN is connected to the VSAEN signal, CSAEN* is connected to the CSAEN* signal, SA and SA* ports are output ports, the WWL port of the 2T0C DRAM cell is connected to the OUT port of the fourth transmission gate, the IN port of the fourth transmission gate is connected to the OUT port of the bootstrap write word line driver, and the V EN port and V write Signal connection, V of the fourth transmission gate EN *Port and V write * Signal connection; the VDD port of the bootstrap write word line driver is connected to the power supply, the Phase port is connected to the Phase signal, the DEC* port is connected to the WWL* Bus signal, the DEC port is connected to the WWL Bus signal, the WBL port of the 2T0C DRAM unit is connected to the OUT port of the third transmission gate, the IN port of the third transmission gate is connected to the DOUT* port of the input data buffer, and the V EN port and V write Signal connection, V of the third transmission gate EN *Port and V write * signal connection, the VDD port of the input data buffer is connected to the power supply, the DATA port is connected to the WBL Bus signal, the TRAP* port is connected to the TRAP* signal, the EN* port is connected to the EN* signal, the bootstrap write word line driver is composed of 3 transistors, wherein the d port of the first transistor is the DEC port of the bootstrap write word line driver, the g port of the first transistor is the VDD port of the bootstrap write word line driver, the s port of the first transistor is connected to the g port of the second transistor, the d port of the second transistor is the Phase port of the bootstrap write word line driver, the s port of the second transistor is connected to the d port of the third transistor, the g port of the third transistor is the DEC* port of the bootstrap write word line driver, the s port of the third transistor is connected to GND, and the s port of the second transistor and the d port of the third transistor together constitute the OUT port of the bootstrap write word line driver.

2. The oxide semiconductor 2TOC DRAM non-volatile power-off test circuit according to claim 1, wherein: The 2T0C DRAM cell is composed of a first transistor and a second transistor, wherein the active layers of the first transistor and the second transistor are a single oxide semiconductor thin film or a composite material of a stack of multiple oxide thin films, wherein the d-port of the first transistor is the WBL port of the 2T0C DRAM cell, the g-port of the first transistor is the WWL port of the 2T0C DRAM cell, the s-port of the first transistor is connected to the g-port of the second transistor, the d-port of the second transistor is the RBL port of the 2T0C DRAM cell, and the s-port of the second transistor is the RWL port of the 2T0C DRAM cell.

3. The oxide semiconductor 2TOC DRAM non-volatile power-off test circuit according to claim 1, wherein: The transmission gate is composed of two transistors, wherein the d port of the first transistor is connected to the s port of the second transistor, the s port of the first transistor is connected to the d port of the second transistor, the d port of the first transistor and the s port of the second transistor together constitute the IN port of the transmission gate, the s port of the first transistor and the d port of the second transistor together constitute the OUT port of the transmission gate, and the g port of the first transistor is the V of the transmission gate EN port, the g port of the second transistor is the V of the transmission gate EN *port.

4. The oxide semiconductor 2TOC DRAM non-volatile power-off test circuit according to claim 1, wherein: The input data buffer is composed of four transistors, two inverters, and four NAND gates, wherein the s port of the first transistor is connected to GND, the g port of the first transistor is connected to the g port of the third transistor, the d port of the first transistor is connected to the d port of the third transistor, the g port of the first transistor and the g port of the third transistor together constitute the DATA port of the input data buffer, the s port of the third transistor is connected to the d port of the fourth transistor, the g port of the fourth transistor is the EN* port of the input data buffer, the s port of the fourth transistor is the VDD port of the input data buffer, the g port of the second transistor is the EN* port of the input data buffer, the s port of the second transistor is connected to GND, the d port of the second transistor is connected to the d port of the third transistor and the d port of the first transistor. The g port of the second transistor is connected to the IN port of the first inverter, the OUT port of the first inverter is connected to the B port of the third NAND gate, the A port of the third NAND gate is connected to the A port of the first NAND gate, and together they constitute the TRAP* port of the input data buffer. The OUT port of the third NAND gate is connected to the B port of the fourth NAND gate. At the same time, the OUT port of the third NAND gate is connected to the B port of the first NAND gate, the OUT port of the first NAND gate is connected to the A port of the second NAND gate, the B port of the second NAND gate is connected to the OUT port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the A port of the fourth NAND gate, the OUT port of the second NAND gate is connected to the IN port of the second inverter, and the OUT port of the second inverter is the DOUT* port in the input data buffer.

5. The oxide semiconductor 2TOC DRAM non-volatile power-off test circuit according to claim 4, characterized in that: The NAND gate is composed of four transistors. The g port of the first transistor in the NAND gate is connected to the g port of the fourth transistor, the d port of the first transistor in the NAND gate is connected to the s port of the fourth transistor, the g port of the second transistor in the NAND gate is connected to the g port of the third transistor, the d port of the second transistor in the NAND gate is connected to the s port of the first transistor, the d port of the third transistor in the NAND gate is connected to the d port of the fourth transistor, the s port of the third transistor in the NAND gate and the s port of the fourth transistor together constitute the VDD port of the NAND gate, which is connected to the power supply, the s port of the second transistor in the NAND gate is connected to GND, and the d port of the first transistor and the s port of the fourth transistor together constitute the OUT port of the NAND gate.

6. The oxide semiconductor 2TOC DRAM non-volatile power-off test circuit according to claim 4, characterized in that: The inverter is composed of two transistors, the g port of the first transistor in the inverter is connected to the g port of the second transistor in the inverter, the d port of the first transistor in the inverter is connected to the d port of the second transistor in the inverter, the g port of the first transistor in the inverter and the g port of the second transistor in the inverter together constitute the IN port of the inverter, and the d port of the first transistor in the inverter and the d port of the second transistor in the inverter together constitute the OUT port of the inverter.

7. The oxide semiconductor 2TOC DRAM non-volatile power-off test circuit according to claim 1, wherein: The current mode sense amplifier is composed of 12 transistors, wherein the g port of the first transistor is connected to the g port of the second transistor, together forming the VDD port of the current mode sense amplifier, the s port of the first transistor is connected to the s port of the second transistor, and together connected to GND, the d port of the first transistor is connected to the s port of the third transistor, the d port of the second transistor is connected to the s port of the fourth transistor, and the reference current source I REF Connected to the d-port of the first transistor, the d-port of the second transistor and the s-port of the fourth transistor together form the I of the current mode sense amplifier IN The d port of the third transistor is connected to the g port of the fourth transistor, the g port of the third transistor is connected to the d port of the fourth transistor, the d port of the third transistor is connected to the d port of the fifth transistor, the d port of the fourth transistor is connected to the d port of the sixth transistor, the g port of the fifth transistor is connected to the g port of the sixth transistor, the s port of the fifth transistor is connected to the s port of the sixth transistor, the g port of the fifth transistor and the g port of the sixth transistor together constitute the VSAEN port of the current mode sense amplifier, the s port of the fifth transistor and the s port of the sixth transistor are commonly connected to the d port of the seventh transistor, the g port of the seventh transistor is the CSAEN* port of the current mode sense amplifier, the s port of the seventh transistor is the VDD port of the current mode sense amplifier, the d port of the eighth transistor is connected to the s port of the ninth transistor, and the s port of the eighth transistor is connected to the d port of the ninth transistor The g port of the eighth transistor is connected to the PEQ port of the current mode sense amplifier, the g port of the ninth transistor is the PEQ* port of the current mode sense amplifier, the d port of the eighth transistor is connected to the d port of the fourth transistor, the s port of the eighth transistor is connected to the d port of the third transistor, the d port of the tenth transistor is connected to the s port of the eleventh transistor, the g port of the tenth transistor is connected to the d port of the eleventh transistor, the s port of the tenth transistor is connected to the g port of the eleventh transistor, the d port of the twelfth transistor is connected to the d port of the tenth transistor, the g port of the twelfth transistor is the VSAEN* port of the current mode sense amplifier, the s port of the twelfth transistor is the VDD port of the current mode sense amplifier, the s port of the tenth transistor is the SA output port of the current mode sense amplifier, and the d port of the eleventh transistor is the SA* output port of the current mode sense amplifier.

8. The verification method of the oxide semiconductor 2TOC DRAM non-volatile power-off test circuit according to claim 1, wherein: It is divided into three steps: write operation, hold operation, and read operation. The test waveforms of the three operations are all based on the CLK signal provided by the external programmable gate array as the benchmark. The specific steps include: 1) During write operation, V sense The signal always remains at a low level; V write The signal becomes high level at time t2, V write The signal becomes low when it reaches time t5; the EN* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the TRAP* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the WWL Bus, that is, the DEC signal becomes high when it reaches time t2, and becomes low when it reaches time t5; the DEC* signal becomes low when it reaches time t2, and becomes high when it reaches time t5; the Phase signal becomes high when it reaches time t3, and becomes low when it reaches time t4; for the WBL Bus, that is, the DATA signal, if the data written to the oxide semiconductor 2T0C DRAM unit is 1, it becomes high when it reaches time t2, and becomes low when it reaches time t5; for the WBL Bus, that is, the DATA signal, if the data written to the oxide semiconductor 2T0C DRAM unit is 0, the signal is always low; 2) During the operation, V sense The signal always remains at a low level; V write The signal always remains at a low level. sense signal and V write When the signals are all in the low level state, due to the high resistance characteristics of the first transmission gate to the fourth transmission gate, the WWL, WBL, RBL, and RWL ports of the oxide semiconductor 2T0C DRAM unit are all in the floating state, except for V sense signal and V write Except for the signal, no other signals are operated, and the oxide semiconductor 2T0C DRAM unit is in the power-off hold state; 3) During the read operation, V sense The signal always maintains a high level state; V write The signal always maintains a low level state. For the CSAEN* signal, it becomes a low level when it reaches time t1 and becomes a high level when it reaches time t2; for the PEQ signal, it becomes a low level when it reaches time t1 and becomes a high level when it reaches time t4; for the PEQ* signal, it becomes a high level when it reaches time t1 and becomes a low level when it reaches time t4; for the VSAEN signal, it becomes a high level when it reaches time t2 and becomes a low level when it reaches time t3; for the VSAEN* signal, it becomes a low level when it reaches time t2 and becomes a high level when it reaches time t3.

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