Semiconductor device and preparation method thereof

Abstract

The present application provides a semiconductor device and a method for manufacturing the same, relating to the field of integrated circuit technology. The method comprises providing a base wafer having multiple chips formed thereon and a first heat dissipation structure formed within the chips; providing a carrier wafer having a second heat dissipation structure formed therein; aligning the second heat dissipation structure of the carrier wafer with the first heat dissipation structure of the base wafer so that the carrier wafer is bonded to the multiple chips on the base wafer; forming a lead-out structure on a side of the chip away from the first heat dissipation structure for connecting the chip to a printed circuit board; thinning the carrier wafer so that the second heat dissipation structure is exposed on a side of the carrier wafer away from the first heat dissipation structure; and forming a heat conductive layer on one side of the exposed second heat dissipation structure. The first and second heat dissipation structures conduct heat away from the chips; thinning the carrier wafer and forming a heat conductive layer on one side of the second heat dissipation structure. The heat conductive layer and the second heat dissipation structure are aligned to conduct heat quickly, dissipating heat from the chips and improving their performance and reliability.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development of large-scale integrated circuits (ICs), circuit feature sizes continue to shrink, and chips are evolving in three dimensions, entering the post-Moore era. This approach meets the demands for high integration, high transmission speeds, and low power consumption. Among these three-dimensional structures is chip-to-wafer (C2W) heterogeneous integration. By bonding known-good chips to wafers, C2W significantly improves yield when stacking multiple chips. Multiple chips are heterogeneously integrated onto a single chip, which is then bonded to a silicon carrier to form a complete new chip.

[0003] The existing C2W structure is bonded to the silicon carrier on the back side through melt bonding, which results in poor heat dissipation of the C2W structure. The device generates a large amount of heat during operation that cannot be dissipated. The heterogeneous integration of multiple core particles on one core particle will cause the chip to heat up more, affecting the chip's performance and reliability. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a semiconductor device and a method for manufacturing the same, which can effectively dissipate heat and improve product performance and reliability.

[0005] In one aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising providing a base wafer, wherein a plurality of chips are formed on the base wafer, and a first heat dissipation structure is formed within the chips;

[0006] providing a carrier wafer, and forming a second heat dissipation structure within the carrier wafer;

[0007] The second heat dissipation structure of the carrier wafer is aligned with the first heat dissipation structure of the bottom wafer, so that the carrier wafer is bonded to the multiple chips on the bottom wafer;

[0008] A lead-out structure is formed on a side of the chip away from the first heat dissipation structure, for connecting the chip and a printed circuit board;

[0009] Thinning the carrier wafer so that the second heat dissipation structure is exposed on a side of the carrier wafer away from the first heat dissipation structure;

[0010] A heat conducting layer is formed on the exposed side of the second heat dissipation structure.

[0011] Optionally, providing a base wafer, forming a plurality of chips on the base wafer, and forming a first heat dissipation structure within the chips, includes:

[0012] forming a first heat dissipation hole in the chip in a direction from the chip to the bottom wafer;

[0013] The first heat dissipation hole is filled with a first heat conductive metal to form the first heat dissipation structure.

[0014] Optionally, providing a carrier wafer and forming a second heat dissipation structure in the carrier wafer includes:

[0015] forming a second heat dissipation hole along the thickness direction of the carrier wafer;

[0016] The second heat dissipation hole is filled with a second heat conductive metal to form the second heat dissipation structure.

[0017] Optionally, forming a lead-out structure on a side of the chip away from the first heat dissipation structure for connecting the chip and a printed circuit board includes:

[0018] Holes are opened and wired in sequence on a side of the bottom wafer away from the chip to form the lead-out structure.

[0019] Optionally, thinning the carrier wafer so that the second heat dissipation structure is exposed on a side of the carrier wafer away from the first heat dissipation structure includes:

[0020] forming a temporary bond on a side of the lead-out structure away from the carrier wafer;

[0021] With temporary bonding as support, the carrier wafer is thinned along the thickness direction of the carrier wafer until the second heat dissipation structure is exposed.

[0022] On the other hand, an embodiment of the present application provides a semiconductor device, which is prepared using the above-mentioned method for preparing a semiconductor device, and includes a bottom wafer, a chip layer and a carrier wafer stacked in sequence, the chip layer includes a plurality of chips, a first heat dissipation structure is provided in the chip layer, and a second heat dissipation structure is provided in the carrier wafer. The chip and the carrier wafer are bonded through the corresponding connection of the first heat dissipation structure and the second heat dissipation structure, and the bottom wafer is also provided with a lead-out structure for connecting the chip and a printed circuit board.

[0023] Optionally, the first heat dissipation structure includes a first heat dissipation hole and a first heat dissipation metal filled in the first heat dissipation hole, and the second heat dissipation structure includes a second heat dissipation hole and a second heat dissipation metal filled in the second heat dissipation hole.

[0024] Optionally, a heat-conducting layer is further provided on a side of the second heat dissipation structure away from the first heat dissipation structure, and the thermal conductivity of the heat-conducting layer is at least 10 times that of the second heat-conducting metal.

[0025] Optionally, a plurality of the first heat dissipation holes are arranged in a matrix in the chip, or the first heat dissipation holes include a plurality of slots distributed in the chip, and the second heat dissipation holes are provided corresponding to the first heat dissipation holes.

[0026] Optionally, a depth of the first heat dissipation structure along the bonding direction is 3 um to 5 um, and a depth of the second heat dissipation structure along the bonding direction is 100 um to 200 um.

[0027] The semiconductor device and preparation method provided in the embodiments of the present application provide a first heat dissipation structure in the chip and a second heat dissipation structure in the carrier wafer. After the chip and the carrier wafer are bonded, the heat of the chip can be conducted away through the first heat dissipation structure and the second heat dissipation structure. After the carrier wafer is subsequently thinned, a heat conductive layer is formed on one side of the second heat dissipation structure. The heat conductive layer and the second heat dissipation structure are bonded together to quickly conduct heat away, thereby completing the heat dissipation of the chip and the entire semiconductor device, and improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0029] Figures 1 to 9 is a diagram of the preparation process of the semiconductor device provided in this embodiment;

[0030] Figure 10 Schematic diagram of the connection between the semiconductor device and the printed circuit board provided in this embodiment.

[0031] Icons: 10-bottom wafer; 11-barrier layer; 12-metal block; 13-oxidation area; 14-chip; 15-first heat dissipation structure; 16-lead structure; 20-carrier wafer; 21-second heat dissipation structure; 22-thermal conductive layer; 30-printed circuit board; 31-metal bump; F-bonding direction. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application.

[0033] In the description of this application, it should be noted that the terms "inner" and "outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships in which the product of this application is typically placed when in use. These terms are intended solely to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" and the like are used solely for distinction and should not be construed as indicating or implying relative importance.

[0034] It should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0035] The main three-dimensional structures include wafer-to-wafer (W2W) stacking, chip-to-wafer (C2W) heterogeneous integration, and chip-to-chip (C2C) heterogeneous integration. With the development of semiconductor process equipment, C2W technology is currently the primary method of application. However, C2W devices have poor heat dissipation performance, resulting in poor chip performance and reliability.

[0036] Based on this, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0037] S100 : providing a base wafer 10 , on which a plurality of chips 14 are formed, and a first heat dissipation structure 15 is formed within the chips 14 .

[0038] Specifically, if Figure 1 As shown, a plurality of oxidation regions 13 are formed on the bottom wafer 10, and a barrier layer 11 is formed between adjacent oxidation regions 13; a plurality of metal blocks 12 are formed in the barrier layer 11, which are arranged at intervals and penetrate the barrier layer 11; a plurality of chips 14 are respectively formed on the barrier layer 11 between the plurality of oxidation regions 13, and the surface of the chip 14 is flush with the surface of the oxidation region 13.

[0039] The barrier layer 11 may be made of silicon carbon nitride (SiCN) material. Silicon carbon nitride is a dense material with high thermal stability and chemical stability, as well as high thermal conductivity.

[0040] The metal block 12 can be made of metal such as copper and is used to electrically connect to the subsequent lead structure 16 .

[0041] like Figure 2As shown, a first heat dissipation hole is formed in the chip 14 from the surface of the chip 14 toward the bottom wafer 10. Specifically, the through silicon via (TSV) technology can be used. The depth of the first heat dissipation hole is 3um to 5um. It can be seen from the figure that the depth is approximately 1 / 3 of the thickness of the chip 14, 1 / 2 of the thickness of the barrier layer 11, and 1 / 6 of the thickness of the bottom wafer 10. The depth and thickness are the dimensions of the same bonding direction F.

[0042] Then, a first heat-conducting metal is filled into the first heat-dissipating hole to form a first heat-dissipating structure 15 . For example, the first heat-conducting metal may be copper (Cu). The first heat-conducting metal has a heat-conducting function and can be used for heat conduction and heat dissipation after the chip 14 and the carrier wafer 20 are bonded.

[0043] This application discloses two forms of the first heat dissipation structure 15. In one embodiment, as shown in FIG. Figure 3 As shown, a plurality of first heat dissipation holes are arranged in a dot matrix in the chip 14; in a second embodiment, the first heat dissipation holes are arranged in a plurality of rectangular slots in the chip 14. Figure 4 1 shows two rectangular grooves arranged on the left and right, and rectangular grooves of different sizes are sequentially arranged in each rectangular groove. Of course, grooves of other shapes or other structural forms can also be arranged to form the first heat dissipation holes.

[0044] like Figure 5 As shown, S110 : providing a carrier wafer 20 , and forming a second heat dissipation structure 21 in the carrier wafer 20 .

[0045] A second heat dissipation hole is formed along the thickness direction of the carrier wafer 20; wherein, the second heat dissipation hole can also be formed by using through silicon via (TSV) technology, and the depth of the second heat dissipation hole is 100um to 200um, which is approximately 1 / 4 of the thickness of the carrier wafer 20. The depth and thickness are the dimensions of the same bonding direction F.

[0046] A second heat-conducting metal is filled into the second heat-dissipating hole to form a second heat-dissipating structure 21. The second heat-conducting metal can also be made of copper (Cu). The second heat-conducting metal has a heat-conducting function and is used to bond the chip 14 and the carrier wafer 20 to the corresponding first heat-conducting metal. The heat of the chip 14 is conducted through the first heat-conducting metal and the second heat-conducting metal to dissipate the heat of the chip 14.

[0047] Correspondingly, the second heat dissipation structure 21 may also have different forms, and the second heat dissipation structure 21 needs to be matched with the first heat dissipation structure 15. For example, when the plurality of first heat dissipation holes are arranged in a dot matrix, the second heat dissipation holes are correspondingly arranged in a dot matrix. The second heat dissipation holes and the first heat dissipation holes may correspond one to one, or may be arranged in a dot matrix. Figure 6 As shown, one second heat dissipation hole corresponds to multiple first heat dissipation holes, and can also conduct heat.

[0048] like Figure 7As shown, S120 : the second heat dissipation structure 21 of the carrier wafer 20 is aligned with the first heat dissipation structure 15 of the base wafer 10 , so that the carrier wafer 20 is bonded to the multiple chips 14 on the base wafer 10 .

[0049] The carrier wafer 20 is flipped over so that the second heat dissipation structure 21 of the carrier wafer 20 faces the first heat dissipation structure 15 of the base wafer 10. The second heat conductive metal and the first heat conductive metal are aligned with each other, and the carrier wafer 20 is bonded to the multiple chips 14 on the base wafer 10. The heat of the chips 14 is transferred from the first heat conductive metal to the second heat conductive metal within the chips 14, and then discharged through the second heat conductive metal, completing the heat dissipation of the chips 14.

[0050] like Figure 8 As shown, S130: forming a lead structure 16 on a side of the chip 14 away from the first heat dissipation structure 15 to connect the chip 14 and the printed circuit board 30.

[0051] The semi-finished device is flipped over as a whole so that the side of the bottom wafer 10 away from the chip 14 faces upward. On the side of the bottom wafer 10 away from the chip 14, specifically on the side of the barrier layer 11 away from the chip 14, the first layer (M1) of metal wires, openings (through silicon vias TSV), wiring (redistribution layer RDL), and aluminum pads (AL Pad) are formed in sequence to form a lead-out structure 16. One end of the lead-out structure 16 is connected to the chip 14 through the metal block 12 of the barrier layer 11, and the other end is connected to the printed circuit board 30 through the metal bump 31 process (bump).

[0052] S140 : thinning the carrier wafer 20 so that the second heat dissipation structure 21 is exposed on a side of the carrier wafer 20 away from the first heat dissipation structure 15 .

[0053] like Figure 9 As shown, the semi-finished device is flipped over again so that the side of the carrier wafer 20 away from the second heat dissipation structure 21 faces upward, and a temporary bond (BGTap) is formed at the lower part of the lead-out structure 16 below (i.e., the side of the lead-out structure 16 away from the carrier wafer 20) to facilitate the support of the semi-finished device for thinning the carrier wafer 20. The carrier wafer 20 is thinned along the thickness direction until the second heat dissipation structure 21 is exposed.

[0054] S150 : forming a heat conducting layer 22 on one side of the exposed second heat dissipation structure 21 .

[0055] After the carrier wafer 20 is thinned, a thermal conductive layer 22 is formed on the exposed second thermal conductive metal. The thermal conductive layer 22 can be made of graphene material or other heat-conducting materials. The thermal conductive layer 22 and the second thermal conductive metal are bonded to transfer the heat of the chip 14 through the first thermal conductive metal, the second thermal conductive metal and the thermal conductive layer 22, so that the chip 14 can dissipate heat faster.

[0056] After forming the heat-conducting layer 22, the temporary bonding is removed to form the semiconductor device of the present application; the semiconductor device is connected to the printed circuit board 30 through a metal bump 31 (31) process (bump) to adapt to different application scenarios.

[0057] Among them, the carrier wafer 20 and the thermal conductive layer 22 can play a supporting role in the hot pressing bonding of the metal bump 31 (31) process and the printed circuit board 30. Along the bonding direction F, the total thickness t3 of the thinned carrier wafer 20 and the thermal conductive layer 22 is 100um~200um; the thickness of the oxidation area 13 is 10um~20um, and the thickness t1 of the bottom wafer 10 is 20um~50um.

[0058] Therefore, the preparation method of the semiconductor device provided in the embodiment of the present application is to set a first heat dissipation structure 15 in the chip 14 and a second heat dissipation structure 21 in the carrier wafer 20. After the chip 14 and the carrier wafer 20 are bonded, the heat of the chip 14 can be dissipated through the first heat dissipation structure 15 and the second heat dissipation structure 21; after the carrier wafer 20 is subsequently thinned, a heat conductive layer 22 is also formed on one side of the second heat dissipation structure 21. The heat conductive layer 22 and the second heat dissipation structure 21 are bonded to quickly dissipate heat, completing the heat dissipation of the chip 14 and the entire semiconductor device, thereby improving the performance and reliability of the semiconductor device.

[0059] On the other hand, refer to Figure 10 The embodiment of the present application also discloses a semiconductor device, which is prepared using the above-mentioned method for preparing a semiconductor device. The semiconductor device includes a bottom wafer 10, a chip 14 layer and a carrier wafer 20 stacked in sequence. The chip 14 layer includes multiple chips 14. A first heat dissipation structure 15 is provided in the chip 14 layer, and a second heat dissipation structure 21 is provided in the carrier wafer 20. The chip 14 and the carrier wafer 20 are bonded through the corresponding connection between the first heat dissipation structure 15 and the second heat dissipation structure 21. The bottom wafer 10 is also provided with a lead-out structure 16 for connecting the chip 14 and the printed circuit board 30.

[0060] The first heat dissipation structure 15 includes a first heat dissipation hole and a first heat dissipation metal filled in the first heat dissipation hole, and the second heat dissipation structure 21 includes a second heat dissipation hole and a second heat dissipation metal filled in the second heat dissipation hole; the first heat conductive metal is located in the chip 14, and the first heat conductive metal and the second heat conductive metal are bonded to conduct the heat generated by the chip 14 to the second heat conductive metal through the first heat conductive metal, thereby dissipating the heat from the chip 14.

[0061] Generally, the first heat dissipation metal and the second heat dissipation metal can be made of the same metal, for example, copper can be used for heat dissipation; of course, the first heat dissipation metal and the second heat dissipation metal can also be made of different metals, as long as they are metals that are conducive to heat dissipation.

[0062] On this basis, a heat conducting layer 22 is further provided on the side of the second heat dissipation structure 21 away from the first heat dissipation structure 15 . The thermal conductivity of the heat conducting layer 22 is at least 10 times that of the second heat conducting metal.

[0063] The heat conducting layer 22 is provided to guide the heat transferred to the second heat conducting metal to the heat conducting layer 22 and then out of the semiconductor device, thereby further improving the heat dissipation capability of the chip 14 .

[0064] For example, the heat conducting layer 22 may be made of materials such as graphene, which has a much greater thermal conductivity than the second heat conducting metal copper, so as to enhance the heat conduction and heat dissipation speed.

[0065] The first heat dissipation structure 15 of the present application may have various forms, and correspondingly, the second heat dissipation structure 21 is matched with the first heat dissipation structure 15 .

[0066] For example, the first heat dissipation holes may be distributed in a dot matrix within the chip 14 , and the first heat dissipation holes may also be formed in a rectangular groove connection or sleeve connection manner; the second heat dissipation holes are correspondingly provided.

[0067] The depth of the first heat dissipation structure 15 along the bonding direction F is 3um-5um, and the depth of the second heat dissipation structure 21 along the bonding direction F is 100um-200um, so as to meet the heat dissipation requirements of the semiconductor device structure.

[0068] The semiconductor device has the same structure and benefits as the method for manufacturing the semiconductor device in the aforementioned embodiment. The method for manufacturing the semiconductor device and the benefits have been described in detail in the aforementioned embodiment and will not be repeated here.

[0069] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: Providing a bottom wafer, wherein a plurality of chips are formed on the bottom wafer, and a first heat dissipation structure is formed within the chips; providing a carrier wafer, and forming a second heat dissipation structure within the carrier wafer; The second heat dissipation structure of the carrier wafer is aligned with the first heat dissipation structure of the bottom wafer, so that the carrier wafer is bonded to the multiple chips on the bottom wafer; A lead-out structure is formed on a side of the chip away from the first heat dissipation structure, for connecting the chip and a printed circuit board; Thinning the carrier wafer so that the second heat dissipation structure is exposed on a side of the carrier wafer away from the first heat dissipation structure; A heat conducting layer is formed on the exposed side of the second heat dissipation structure.

2. The method for preparing a semiconductor device according to claim 1, wherein: The method provides a bottom wafer, wherein a plurality of chips are formed on the bottom wafer, and a first heat dissipation structure is formed within the chips, including: forming a first heat dissipation hole in the chip in a direction from the chip to the bottom wafer; The first heat dissipation hole is filled with a first heat conductive metal to form the first heat dissipation structure.

3. The method for preparing a semiconductor device according to claim 2, wherein: The providing of a carrier wafer and forming a second heat dissipation structure in the carrier wafer includes: forming a second heat dissipation hole along the thickness direction of the carrier wafer; The second heat dissipation hole is filled with a second heat conductive metal to form the second heat dissipation structure.

4. The method for preparing a semiconductor device according to claim 1, wherein: The lead-out structure is formed on a side of the chip away from the first heat dissipation structure for connecting the chip and a printed circuit board, comprising: Holes are opened and wired in sequence on a side of the bottom wafer away from the chip to form the lead-out structure.

5. The method for preparing a semiconductor device according to any one of claims 1 to 4, wherein: The thinning of the carrier wafer so that the second heat dissipation structure is exposed on a side of the carrier wafer away from the first heat dissipation structure includes: forming a temporary bond on a side of the lead-out structure away from the carrier wafer; With temporary bonding as support, the carrier wafer is thinned along the thickness direction of the carrier wafer until the second heat dissipation structure is exposed.

6. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: It includes a bottom wafer, a chip layer and a carrier wafer stacked in sequence, the chip layer includes multiple chips, a first heat dissipation structure is provided in the chip layer, and a second heat dissipation structure is provided in the carrier wafer. The chip and the carrier wafer are bonded through the corresponding connection of the first heat dissipation structure and the second heat dissipation structure. The bottom wafer is also provided with a lead-out structure for connecting the chip and a printed circuit board.

7. The semiconductor device according to claim 6, wherein: The first heat dissipation structure includes a first heat dissipation hole and a first heat conductive metal filled in the first heat dissipation hole, and the second heat dissipation structure includes a second heat dissipation hole and a second heat conductive metal filled in the second heat dissipation hole.

8. The semiconductor device according to claim 7, wherein: A heat-conducting layer is further provided on a side of the second heat-dissipating structure away from the first heat-dissipating structure. The thermal conductivity of the heat-conducting layer is at least 10 times that of the second heat-conducting metal.

9. The semiconductor device according to claim 7, wherein: A plurality of the first heat dissipation holes are arranged in a matrix in the chip, or the first heat dissipation holes include a plurality of slots distributed in the chip, and the second heat dissipation holes are arranged corresponding to the first heat dissipation holes.

10. The semiconductor device according to claim 6, wherein The depth of the first heat dissipation structure along the bonding direction is 3um to 5um, and the depth of the second heat dissipation structure along the bonding direction is 100um to 200um.

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