A calibration system and calibration method for a receiver signal link

Abstract

The present invention discloses a calibration system and a calibration method for a receiver signal link, and belongs to the technical field of receiver signal link. The calibration system includes a TIA and an ADC connected to the output end of the TIA; the input end of the TIA includes a conventional input end and a calibration input end; the calibration input end is respectively connected to a link gain calibration current input circuit, a conventional load current input circuit, and a TIA calibration voltage input circuit. The present invention first eliminates the error of the device itself, and then calibrates the link error, thereby systematically calibrating the entire receiver link, greatly improving the accuracy of the entire link.

Description

Technical Field

[0001] The present invention relates to the technical field of receiver signal links, and in particular to a calibration system and a calibration method for a receiver signal link. Background Art

[0002] In a receiver (RX) signal chain consisting of a TIA (transimpedance amplifier) ​​and an ADC (analog-to-digital converter) circuit, non-ideal factors in the circuit will affect the accuracy of the data converted by the ADC, such as the offset voltage (offset voltage) of the SARADC (successive approximation register analog-to-digital converter), the offset voltage of the TIA circuit, the residual offset voltage of the RX chain, and the gain error caused by the limited gain of the op amp and circuit mismatch.

[0003] In the prior art, the TIA and ADC are generally calibrated separately, but no systematic calibration is performed on the entire link, so that the output structure of the entire link still has large errors. Summary of the invention

[0004] The object of the present invention is to provide a calibration system and calibration method for a receiver signal link, to partially solve or alleviate the above-mentioned deficiencies in the prior art, to perform a systematic calibration on the entire link, and to improve the accuracy of the system link output.

[0005] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions: a calibration system for a receiver signal chain, comprising a TIA and an ADC connected to an output end of the TIA;

[0006] The input end of the TIA includes a conventional input end and a calibration input end; the calibration input end is respectively connected to a link gain calibration current input circuit, a conventional load current input circuit and a TIA calibration voltage input circuit;

[0007] When the TIA calibration voltage input line is connected to the calibration input terminal of the TIA, the TIA input offset voltage calibration can be performed; when the link gain calibration current input line is connected to the calibration input terminal of the TIA, the link gain calibration can be performed; when the normal load current input line is connected to the calibration input terminal of the TIA, the TIA operates normally; when the link gain calibration current input line, the normal load current input line and the TIA calibration voltage input circuit are all disconnected from the calibration input terminal of the TIA, the link residual deviation calibration and the ADC offset voltage calibration can be performed.

[0008] As an improvement, the TIA is arranged in a TIA input offset voltage calibration circuit; the TIA input offset voltage calibration circuit comprises a TIA and a first comparator;

[0009] The output end of the TIA includes a load output stage and a calibration output stage; the load output stage is connected to the ADC and is connected to the calibration input end of the TIA using a feedback circuit;

[0010] In normal operation, the load output stage is a circuit and the calibration output stage is an open circuit; when performing TIA input offset voltage calibration, the load output stage is an open circuit and the calibration output stage is a circuit;

[0011] The first comparator includes a first input terminal and a second input terminal; the output terminal of the calibration output stage is connected to the first input terminal of the first comparator, and the second input terminal of the first comparator is externally connected to a standard voltage, so that the output voltage of the calibration output stage is compared with the standard voltage through the comparator; the output terminal of the comparator is connected to the TIA.

[0012] As an improvement, the TIA includes two outputs, which are respectively connected to the input ends of the first group of field effect transistors and the input ends of the second group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors form the load output stage and the calibration output stage in parallel.

[0013] As an improvement, the first group of field effect transistors includes a first field effect transistor MOS-1 and a second field effect transistor MOS-2, whose gates G are respectively connected to two outputs of the TIA, wherein a source S of the first field effect transistor MOS-1 is externally connected to a voltage through a first switch SW1, a source S of the second field effect transistor MOS-2 is grounded through a second switch SW2, and a drain D of the first field effect transistor MOS-1 is connected to a drain D of the second field effect transistor MOS-2 as a load output terminal externally connected to a load;

[0014] The second group of field effect transistors includes a third field effect transistor MOS-3 and a fourth field effect transistor MOS-4, whose gates G are respectively connected to the two outputs of the TIA, wherein the source S of the third field effect transistor MOS-3 is externally connected to a voltage through a third switch SW3, the source S of the fourth field effect transistor MOS-4 is grounded through a fourth switch SW4, and the drain D of the third field effect transistor MOS-3 is connected to the drain D of the fourth field effect transistor MOS-4 as a calibration output stage connected to the first input terminal of the comparator.

[0015] The present invention also provides a receiver signal link calibration method, which is applied to the above receiver signal link calibration system, comprising:

[0016] Calibrate the offset voltage of ADC;

[0017] Calibrate the input offset voltage of TIA;

[0018] Obtain link residual deviation;

[0019] Calibrate the gain error of the link;

[0020] When the link is operating normally, the difference between the ADC output value and the link residual deviation is taken as the link output result.

[0021] As an improvement, the step of calibrating the offset voltage of the ADC includes:

[0022] Disconnect the link gain calibration current input circuit, the normal load current input circuit, and the TIA calibration voltage input circuit from the calibration input terminal of the TIA;

[0023] Applying a common mode voltage Vcm to the two input terminals of the second comparator inside the ADC;

[0024] The input offset voltage of the second comparator is adjusted according to the output of the second comparator.

[0025] As an improvement, the steps for calibrating the input offset voltage of the TIA include:

[0026] Connect the TIA calibration voltage input circuit to the TIA calibration input terminal; put the TIA load output stage in an open circuit state, and put the TIA calibration output stage in a closed circuit state;

[0027] By applying a common mode voltage Vcm to both the calibration input terminal and the regular input terminal of the TIA, and comparing the calibration output voltage Vout_cal of the calibration output stage with the standard voltage Vref;

[0028] The difference between the calibrated output voltage Vout_cal and the standard voltage Vref is input into the TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the calibrated output voltage Vout_cal.

[0029] As an improvement, the step of inputting the difference between the calibrated output voltage Vout_cal and the standard voltage Vref into the TIA for adjustment so that the calibrated output voltage Vout_cal approaches the standard voltage Vref specifically includes:

[0030] Comparing the calibrated output voltage Vout_cal with the standard voltage Vref,

[0031] If the calibrated output voltage Vout_cal is higher than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal is reduced;

[0032] If the calibrated output voltage Vout_cal is lower than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal increases;

[0033] Repeat the above steps until the adjustment times reach the set value;

[0034] The current adjustment step size for adjusting the TIA parameters is 1 / 2 of the previous adjustment step size.

[0035] As an improvement, the step of obtaining the link residual deviation includes:

[0036] Disconnect the link gain calibration current input circuit, the normal load current input circuit, and the TIA calibration voltage input circuit from the calibration input terminal of the TIA;

[0037] Apply input voltage Vcm to the conventional input terminal of TIA;

[0038] Get the ADC output dout0;

[0039] The ADC output dout0 is compared with the theoretical value 2 N-1 The difference is taken as the link residual deviation, where N is the number of bits of the ADC.

[0040] As an improvement, the steps of calibrating the gain error of the link include:

[0041] Connect the link gain calibration current input line to the calibration input terminal of the TIA;

[0042] The calibration currents Ical1 and Ical2 are respectively loaded to the calibration input terminal of the TIA through the link gain calibration current input circuit, so that the load output stage of the TIA outputs voltages Vcal1 and Vcal2 respectively and inputs them to the ADC; wherein the absolute value of the difference between Ical1 and Ical2 is 1 / 2 of the ADC reference current Iref;

[0043] Get the outputs dout1 and dout2 of the ADC under the input voltages Vcal1 and Vcal2;

[0044] The absolute value of the difference between the ADC outputs dout1 and dout2 is compared with the theoretical value, and the reference voltage Vref_adc of the ADC is adjusted according to the comparison result; the theoretical value is 2 N-1 , generated according to 1 / 2 of the reference current Iref, where N is the number of bits of the ADC.

[0045] The invention is beneficial in that: in the invention, firstly, the TIA and ADC of the link device are calibrated separately to eliminate the error of the device itself, then the link residual error is obtained and the link gain error is calibrated, and finally, when the link is in normal operation, the link residual error is subtracted from the output result as the final output, thereby eliminating the link residual error.

[0046] The present invention first eliminates the error of the device itself and then calibrates the link error, thereby systematically calibrating the entire receiver link and greatly improving the accuracy of the entire link.

[0047] In addition, in the calibration circuit of the existing receiver, during normal operation, the switch on the feedback circuit (including a feedback resistor and a switch) is closed, so the resistance value on the feedback circuit is the sum of the resistance value of the feedback resistor and the resistance value of the switch. During the calibration process, the switch on the feedback circuit is in an open state, making the feedback circuit open. That is, in the above calibration method, since the calibration process does not cover the switch on the feedback circuit, during normal operation, the resistance value of the switch will change the resistance value of the feedback circuit, thereby causing measurement errors. Therefore, if it is applied to a photon computing chip with high-precision and high-speed computing, on the one hand, the error of the TIA itself will reduce the accuracy of the link, and on the other hand, the output of the TIA is directly used as the input of the ADC. If there is an error in the output of the TIA, even if the ADC is calibrated, it will reduce the accuracy of the entire link, thereby reducing the accuracy of the photon computing chip.

[0048] In the present invention, the switch SW5 on the feedback circuit is cancelled, and a special calibration output stage is set at the output end of the TIA. The calibration output stage and the load output stage conventionally used by the TIA are both connected to the output end of the TIA, and the calibration output stage is disconnected during normal operation and is only connected to the circuit during calibration. When the calibration output stage is connected to the circuit, the load output stage is disconnected from the output end of the TIA, and the feedback circuit connected to the load output stage is also disconnected, entering the calibration state. Since the switch SW5 on the feedback circuit is cancelled, the resistance value on the feedback circuit will not change, thereby avoiding the generation of other measurement errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0050] Figure 1 Schematic diagram of a calibration system for a receiver signal link in Embodiment 1 of the present invention;

[0051] Figure 2 A schematic diagram of an existing TIA input offset voltage calibration circuit;

[0052] Figure 3 Schematic diagram of a TIA input offset voltage calibration circuit in Embodiment 1 of the present invention;

[0053] Figure 4 This is a flow chart of a method for calibrating a receiver signal link in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0055] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0056] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0057] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0058] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0059] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0060] Embodiment 1: Prior art CN202210665363.1 discloses a radio frequency receiving system and an output third-order intercept point OIP3 calibration method, which relates to the field of signal processing. The system includes a radio frequency receiving end, a low noise amplifier LNA, a mixer Mixer, a local oscillator LO, a digital-to-analog converter ADC, an operational amplifier OPA, a feedback circuit and a negative resistance circuit, wherein the circuit constituting the operational amplifier OPA includes a transimpedance amplifier TIA, a low-pass filter LPF, and a variable gain amplifier PGA, and the negative resistance circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a variable P tube current source and a variable N tube current source; a negative resistance circuit is connected between the in-phase input terminal and the inverting input terminal of the transimpedance amplifier TIA, and the output terminal of the variable gain amplifier PGA is connected to the negative resistance circuit through a feedback circuit.

[0061] The above-mentioned prior art mainly solves the problem of insufficient linearity in the radio frequency receiver and realizes automatic calibration of OIP3 in the radio frequency receiver, but does not calibrate the entire receiver signal chain.

[0062] like Figure 1 As shown, the present invention provides a calibration system for a receiver signal chain, including a TIA and an ADC connected to an output terminal of the TIA;

[0063] The input end of the TIA includes a normal input end and a calibration input end; wherein the calibration input end is respectively connected to a link gain calibration current input circuit, a normal load current input circuit and a TIA calibration voltage input circuit.

[0064] When the TIA calibration voltage input circuit is connected to the calibration input terminal of the TIA, that is, the switch SW6 is closed, the TIA input offset voltage calibration can be performed.

[0065] When the link gain calibration current input line is connected to the calibration input terminal of the TIA, that is, the switch SW7 is closed, the link gain calibration can be performed.

[0066] When the normal load current input line is connected to the calibration input terminal of the TIA, that is, the switch SW8 is closed, the TIA operates normally;

[0067] When the link gain calibration current input line, the normal load current input line and the TIA calibration voltage input circuit are all disconnected from the calibration input terminal of the TIA, that is, switches SW6, SW7 and SW9 are all disconnected, link residual deviation calibration and ADC offset voltage calibration can be performed.

[0068] In the above calibration system, ADC offset voltage calibration, TIA input offset voltage calibration, link residual deviation calibration and link gain calibration can be performed separately, that is, systematic calibration is performed on the device (TIA and ADC) and the link respectively, thereby ensuring the accuracy of the entire receiver signal link.

[0069] Figure 1 In order to facilitate reading, the TIA is simplified. In fact, the TIA is set in the TIA input offset voltage calibration circuit, such as Figure 3 Specifically, the TIA input offset voltage calibration circuit includes a TIA and a first comparator;

[0070] The output end of the TIA includes a load output stage and a calibration output stage; the load output stage is connected to the calibration input end of the TIA using a feedback circuit; and only a feedback resistor is connected to the feedback circuit;

[0071] Furthermore, switches are provided on both the calibration output stage and the load output stage. During normal operation, the switch on the calibration output stage is opened and the switch on the load output stage is closed, so that the load output stage is a circuit and the calibration output stage is an open circuit. During calibration, the switch on the calibration output stage is closed and the switch on the load output stage is opened, so that the load output stage is an open circuit and the calibration output stage is a circuit.

[0072] The output terminal of the calibration output stage is connected to the first comparator, so that the output voltage of the calibration output stage is compared with a preset standard voltage through the first comparator; and the output terminal of the first comparator is connected to the TIA.

[0073] like Figure 2 In the conventional calibration circuit shown, in normal operation, the switch SW5 on the feedback circuit is closed, so the resistance value on the feedback circuit is the sum of the resistance value of the feedback resistor and the switch resistance value. During the calibration process, the switch SW5 on the feedback circuit is in an open state, making the feedback circuit open circuit. That is, during Figure 2 In the prior art shown, the calibration process does not cover the switch SW5 and during normal operation, the resistance value of the switch SW5 will change the resistance value of the feedback circuit, thereby causing measurement errors.

[0074] In the present invention, the switch SW5 on the feedback circuit is cancelled, and a special calibration output stage is set at the output end of the TIA. The calibration output stage and the load output stage conventionally used by the TIA are both connected to the output end of the TIA, and the calibration output stage is disconnected during normal operation and is only connected to the circuit during calibration. When the calibration output stage is connected to the circuit, the load output stage is disconnected from the output end of the TIA, and the feedback circuit connected to the load output stage is also disconnected, entering the calibration state.

[0075] Since the switch SW5 on the feedback circuit is cancelled, the resistance value on the feedback circuit will not change, thereby avoiding the generation of other measurement errors.

[0076] More specifically, in this embodiment, the first comparator includes a first input terminal and a second input terminal; the output terminal of the calibration output stage is connected to the first input terminal of the first comparator, and the second input terminal of the first comparator is externally connected to a standard voltage.

[0077] The specific structure of the calibration output stage and the load output stage is as follows: TIA includes two outputs, and the two outputs are respectively connected to the input ends of the first group of field effect transistors and the input ends of the second group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors form a parallel load output stage and a calibration output stage.

[0078] In some embodiments, the specific structure of the load output stage includes: a first group of field effect transistors includes a first field effect transistor MOS-1 and a second field effect transistor MOS-2, whose gates G are respectively connected to two outputs of the TIA, wherein the source S of the first field effect transistor MOS-1 is externally connected to a voltage through a first switch SW1, the source S of the second field effect transistor MOS-2 is grounded through a second switch SW2, and the drain D of the first field effect transistor MOS-1 is connected to the drain D of the second field effect transistor MOS-2 as an external load at the load output terminal; and a common point where the drain D of the first field effect transistor MOS-1 and the drain D of the second field effect transistor MOS-2 are connected is connected to the calibration input terminal of the TIA through a feedback resistor.

[0079] In some embodiments, the specific structure of the calibration output stage includes: the second group of field effect transistors includes a third field effect transistor MOS-3 and a fourth field effect transistor MOS-4, whose gates G are respectively connected to the two outputs of the TIA, wherein the source S of the third field effect transistor MOS-3 is externally connected to a voltage through a third switch SW3, the source S of the fourth field effect transistor MOS-4 is grounded through a fourth switch SW4, and the drain D of the third field effect transistor MOS-3 is connected to the drain D of the fourth field effect transistor MOS-4 as a calibration output stage connected to the first input terminal of the first comparator.

[0080] Example 2: Figure 4 As shown, the present invention also provides a calibration method for a receiver signal link, which is applied to the calibration system of the above receiver signal link, comprising:

[0081] S1 calibrates the offset voltage of the ADC.

[0082] S2 calibrates the input offset voltage of the TIA.

[0083] S3 obtains the link residual deviation.

[0084] S4 calibrates the gain error of the link.

[0085] When the link is running normally, S5 takes the difference between the ADC output value and the link residual deviation as the link output result.

[0086] It should be noted that the execution order of step S1 and step S2 in the present invention can be swapped, and the execution order of step S3 and step S4 can also be swapped, and the swapping does not affect the overall calibration effect. Among them, steps S1 and S2 calibrate the device itself, and steps S3 to S5 are used to calibrate the link.

[0087] Specifically, the specific steps of calibrating the offset voltage of the ADC in S1 include:

[0088] S11 disconnects the link gain calibration current input circuit, the normal load current input circuit and the TIA calibration voltage input circuit from the calibration input terminal of the TIA; that is, disconnects switches SW6, SW7 and SW8.

[0089] S12 applies a common mode voltage Vcm to two input terminals of the second comparator inside the ADC.

[0090] The comparator is a key component in the ADC, which can compare the voltages of two input terminals and output 0 or 1 based on the comparison result. In this step, the same common-mode voltage Vcm is loaded on the two input terminals.

[0091] S13 adjusts the input offset voltage of the second comparator according to the output of the second comparator.

[0092] After the common mode voltage Vcm is applied, the comparator is adjusted according to the output (high or low) of the second comparator. Step S12 and step S13 may be executed repeatedly (for example, by binary division).

[0093] The adjustment of the input offset voltage of the second comparator can be achieved by adjusting the W / L ratio (width / length ratio) of the second comparator input MOSFET (field effect transistor), which will not be described in detail in this embodiment.

[0094] The specific steps for calibrating the input offset voltage of the TIA in S2 include:

[0095] S21 connects the TIA verification voltage input circuit to the calibration input terminal of the TIA; the load output stage of the TIA is in an open circuit state, and the calibration output stage of the TIA is in a closed circuit state.

[0096] See also Figure 1 and Figure 3 During calibration, the switch SW6 is closed so that the TIA calibration voltage input circuit is connected to the calibration input terminal of the TIA.

[0097] In addition, it is necessary to disconnect switches SW1 and SW2 on the load output stage to disconnect the entire load output stage from the TIA output terminal, and also disconnect the feedback circuit from the TIA. Close switches SW3 and SW4 on the calibration output stage to connect the calibration output stage to the TIA output terminal.

[0098] S22 connects the input voltage Vcm to both the calibration input terminal and the normal input terminal of the TIA, and compares the calibration output voltage Vout_cal of the calibration output stage with the standard voltage Vref.

[0099] After the voltage Vcm is input to the calibration input terminal and the regular input terminal, the calibration output voltage Vout_cal is output at the TIA calibration output stage. The calibration output voltage Vout_cal is then input to the first input terminal of the first comparator. The second input terminal of the first comparator is externally connected to the standard voltage Vref, and the calibration output voltage Vout_cal can be compared with the standard voltage Vref through the first comparator.

[0100] S23 inputs the difference between the calibrated output voltage Vout_cal and the standard voltage Vref into the TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the calibrated output voltage Vout_cal.

[0101] The purpose of calibration is to make the output voltage of the TIA equal to the standard voltage under ideal conditions. Of course, in actual calibration, it is difficult to make the output voltage of the TIA completely equal to the standard voltage, and it can only be gradually approached to the standard voltage. Through one of the binary method, gradient descent method, genetic algorithm, and particle swarm optimization method, the difference between the calibrated output voltage Vout_cal and the standard voltage Vref is input into the TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the calibrated output voltage Vout_cal. In this embodiment, the binary method is used for adjustment, and the specific steps include:

[0102] S231 compares the calibrated output voltage Vout_cal with the standard voltage Vref. If the calibrated output voltage Vout_cal is higher than the standard voltage Vref, the TIA parameters are adjusted to reduce the calibrated output voltage Vout_cal. If the calibrated output voltage Vout_cal is lower than the standard voltage Vref, the TIA parameters are adjusted to increase the calibrated output voltage Vout_cal.

[0103] In this embodiment, the TIA parameter that affects the calibrated output voltage Vout_cal may be the number of MOS transistors inside the TIA. The calibrated output voltage Vout_cal is adjusted by changing the number of MOS transistors in the access circuit. When the input voltage Vcm does not change, the purpose of adjusting the calibrated output voltage Vout_cal is achieved by adjusting the parameters of the TIA itself.

[0104] The specific adjustment rule is that the current adjustment step of the TIA parameter is 1 / 2 of the previous adjustment step.

[0105] Through continuous adjustment, the quasi-output voltage Vout_cal gradually approaches the standard voltage Vref.

[0106] S232 repeats the above step S231 until the adjustment times reaches the set value.

[0107] For example, after the first comparison, if the calibrated output voltage Vout_cal is higher than the standard voltage Vref, the TIA parameters are adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step is S. After the second comparison, if the calibrated output voltage Vout_cal is still higher than the standard voltage Vref, the TIA parameters need to be further adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step is S / 2. After the third comparison, if the calibrated output voltage Vout_cal is still higher than the standard voltage Vref, the TIA parameters need to be further adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step is S / 4. After the fourth comparison, if the calibrated output voltage Vout_cal is lower than the standard voltage Vref, the TIA parameters need to be adjusted to increase the calibrated output voltage Vout_cal, and the adjustment step is S / 8. After the fifth comparison, if the calibrated output voltage Vout_cal is higher than the standard voltage Vref again, the TIA parameters need to be adjusted to reduce the calibrated output voltage Vout_cal, and the adjustment step is S / 16... and so on.

[0108] Through continuous adjustment, the quasi-output voltage Vout_cal gradually approaches the standard voltage Vref.

[0109] It can be foreseen that the more times the adjustment is performed, the closer the calibrated output voltage Vout_cal will be to the standard voltage Vref. Of course, in actual engineering applications, there will not be unlimited adjustment, and a certain number of adjustment times will be set. When the number of adjustment times reaches the set value, the adjustment will stop.

[0110] In fact, the setting value of the number of adjustments is adjusted according to the circuit design accuracy. The higher the design accuracy, the larger the setting value of the number of adjustments, so that the calibrated output voltage Vout_cal will be closer to the standard voltage Vref, thereby achieving the corresponding design accuracy; and the lower the design accuracy, the smaller the setting value of the number of adjustments, thereby reducing system overhead.

[0111] In some other embodiments, in order to further reduce the overhead, before the number of adjustments reaches the number threshold, if the difference between the calibrated output voltage Vout_cal and the standard voltage Vref is less than the difference threshold, it means that the design accuracy has been met, and the adjustment can be stopped at this time.

[0112] After the TIA and ADC are calibrated separately, there will still be deviations in the entire link that will eventually affect the output. Therefore, the purpose of step S3 is to obtain the residual deviation of the entire link after eliminating the TIA and ADC deviations, so as to facilitate the subsequent steps to calibrate the deviation. Step S3 specifically includes:

[0113] S31 disconnects the link gain calibration current input circuit, the normal load current input circuit and the TIA calibration voltage input circuit from the calibration input terminal of the TIA, that is, the switch SW6, the switch SW7 and the switch SW8 are all disconnected.

[0114] During this process, the calibration output stage of the TIA itself is also disconnected from the TIA and the load output stage is connected to the TIA, so that the output signal of the TIA can be transmitted to the ADC.

[0115] S32 applies input voltage Vcm to the normal input terminal of the TIA.

[0116] S33 obtains the output dout0 of the ADC.

[0117] S34 compares the ADC output dout0 with the theoretical value 2 N-1 The difference is taken as the link residual deviation, where N is the number of bits of the ADC.

[0118] After both the TIA and ADC are calibrated, the output of this link should theoretically be 2 N-1 The actual output will deviate from the theoretical value. Therefore, the actual output dout0 is compared with the theoretical value 2 N-1 The difference is the residual deviation of the entire link.

[0119] In the field of electronic engineering and signal processing, "gain" refers to the ratio between the output signal and the input signal. Specifically, gain can be used to describe the amplification effect of an amplifier, mixer or other signal processor. In the ideal design, each component in the signal chain has its predetermined gain value, such as the transimpedance gain of the TIA, or the open-loop gain of the op amp. Due to the non-ideal characteristics of circuit components, changes in environmental conditions and other factors, the actual gain will deviate from this ideal value. Therefore, step S4 of the present invention also calibrates the gain error of the link, specifically including:

[0120] S41 connects the link gain calibration current input line to the calibration input terminal of the TIA, that is, the switch SW7 is closed. In this process, the calibration output stage of the TIA itself is also disconnected from the TIA and the load output stage is connected to the TIA, so that the output signal of the TIA can be transmitted to the ADC.

[0121] S42 loads calibration currents Ical1 and Ical2 to the calibration input terminal of TIA through the link gain calibration current input circuit, so that the load output stage of TIA outputs voltages Vcal1 and Vcal2 respectively and inputs them to ADC; wherein the absolute value of the difference between Ical1 and Ical2 is 1 / 2 of the ADC reference current Iref.

[0122] Through the link gain calibration current input line, two currents, Ical1 and Ical2, are loaded to the calibration input of the TIA. The absolute value of the difference between the two currents Ical1 and Ical2 is 1 / 2 of the ADC reference current Iref. The purpose is to determine the difference between the actual gain and the theoretical gain.

[0123] S43 obtains the outputs dout1 and dout2 of the ADC under the input voltages Vcal1 and Vcal2.

[0124] S44 compares the absolute value of the difference between the ADC outputs dout1 and dout2 with the theoretical value, and adjusts the ADC reference voltage Vref_adc according to the comparison result; the theoretical value is 2 N-1 , generated according to 1 / 2 of the reference current Iref, where N is the number of bits of the ADC.

[0125] The ADC contains a variable resistor Rref. By changing the value of the variable resistor Rref, the ADC reference voltage Vref_adc can be changed. The two loaded currents Ical1 and Ical2 will eventually output two signals dout1 and dout2 after passing through the TIA and ADC gain. Since the absolute value of the difference between Ical1 and Ical2 is 1 / 2 of the reference current Iref, theoretically, the absolute value of the difference between the two signals dout1 and dout2 output by the ADC should be the value generated by 1 / 2 of the reference current Iref, that is, 2 N -1 If the final difference is 2 N-1 If there is a deviation, it means that a gain error has occurred. It is necessary to adjust the variable resistor Rref to change the ADC reference voltage Vref_adc, thereby changing the ADC output value. The specific method of adjustment can also use the binary method. After multiple adjustments, the absolute value of the difference between the output values ​​generated by the two currents Ical1 and Ical2 is close to 2 N -1 .

[0126] In step S5, when the link is operating normally, the normal load current input line is connected to the calibration input terminal of the TIA, that is, the switch SW8 is closed. The input signal is transmitted to the ADC through the load output stage of the TIA, and the ADC outputs a digital signal. At this time, the link residual deviation obtained in step S3 needs to be subtracted from the output digital signal to eliminate the influence of the link residual deviation on the final output result.

[0127] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0129] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A calibration system for a receiver signal link, characterized in that: including a TIA and an ADC connected to an output terminal of the TIA; The input end of the TIA includes a conventional input end and a calibration input end; the calibration input end is respectively connected to a link gain calibration current input circuit, a conventional load current input circuit and a TIA calibration voltage input circuit; When the TIA calibration voltage input line is connected to the calibration input terminal of the TIA, the TIA input offset voltage calibration can be performed; When the link gain calibration current input line is connected to the calibration input terminal of the TIA, link gain calibration can be performed; When the normal load current input line is connected to the calibration input terminal of the TIA, the TIA operates normally; when the link gain calibration current input line, the normal load current input line and the TIA calibration voltage input circuit are disconnected from the calibration input terminal of the TIA, the link residual deviation calibration and ADC offset voltage calibration can be performed; The calibration steps include: Calibrate the offset voltage of ADC; Calibrate the input offset voltage of TIA; Obtaining the link residual deviation, specifically comprising: disconnecting the link gain calibration current input circuit, the normal load current input circuit, and the TIA calibration voltage input circuit from the calibration input terminal of the TIA; Load the input voltage Vcm at the conventional input terminal of TIA; obtain the output dout0 of ADC; compare the output dout0 of ADC with the theoretical value 2 N-1 The difference is taken as the link residual deviation, where N is the number of bits of ADC; Calibrate the gain error of the link; When the link is running normally, the difference between the ADC output value and the link residual deviation is taken as the link output result.

2. A receiver signal chain calibration system according to claim 1, characterized in that: The TIA is arranged in a TIA input offset voltage calibration circuit; the TIA input offset voltage calibration circuit comprises a TIA and a first comparator; The output end of the TIA includes a load output stage and a calibration output stage; the load output stage is connected to the ADC and is connected to the calibration input end of the TIA using a feedback circuit; In normal operation, the load output stage is a circuit and the calibration output stage is an open circuit; when performing TIA input offset voltage calibration, the load output stage is an open circuit and the calibration output stage is a circuit; The first comparator includes a first input terminal and a second input terminal; the output terminal of the calibration output stage is connected to the first input terminal of the first comparator, and the second input terminal of the first comparator is externally connected to a standard voltage, so that the output voltage of the calibration output stage is compared with the standard voltage through the first comparator; the output terminal of the first comparator is connected to the TIA.

3. A receiver signal chain calibration system according to claim 2, characterized in that: The TIA includes two outputs, which are respectively connected to the input ends of the first group of field effect transistors and the input ends of the second group of field effect transistors, so that the first group of field effect transistors and the second group of field effect transistors form the load output stage and the calibration output stage in parallel.

4. A receiver signal chain calibration system according to claim 3, characterized in that: The first group of field effect transistors includes a first field effect transistor MOS-1 and a second field effect transistor MOS-2, whose gates G are respectively connected to two outputs of the TIA, wherein a source S of the first field effect transistor MOS-1 is externally connected to a voltage through a first switch SW1, a source S of the second field effect transistor MOS-2 is grounded through a second switch SW2, and a drain D of the first field effect transistor MOS-1 is connected to a drain D of the second field effect transistor MOS-2 as a load output terminal externally connected to a load; The second group of field effect transistors includes a third field effect transistor MOS-3 and a fourth field effect transistor MOS-4, whose gates G are respectively connected to the two outputs of the TIA, wherein the source S of the third field effect transistor MOS-3 is externally connected to a voltage through a third switch SW3, the source S of the fourth field effect transistor MOS-4 is grounded through a fourth switch SW4, and the drain D of the third field effect transistor MOS-3 is connected to the drain D of the fourth field effect transistor MOS-4 as a calibration output stage connected to the first input terminal of the comparator.

5. A receiver signal chain calibration system according to claim 1, characterized in that The step of calibrating the offset voltage of the ADC comprises: Disconnect the link gain calibration current input circuit, the normal load current input circuit, and the TIA calibration voltage input circuit from the calibration input terminal of the TIA; Applying a common mode voltage Vcm to the two input terminals of the second comparator inside the ADC; The input offset voltage of the second comparator is adjusted according to the output of the second comparator.

6. A receiver signal chain calibration system according to claim 1, characterized in that The steps to calibrate the input offset voltage of the TIA include: Connect the TIA calibration voltage input circuit to the TIA calibration input terminal; put the TIA load output stage in an open circuit state, and put the TIA calibration output stage in a closed circuit state; By applying a common mode voltage Vcm to both the calibration input terminal and the regular input terminal of the TIA, and comparing the calibration output voltage Vout_cal of the calibration output stage with the standard voltage Vref; The difference between the calibrated output voltage Vout_cal and the standard voltage Vref is input into the TIA for adjustment, so that the calibrated output voltage Vout_cal approaches the calibrated output voltage Vout_cal.

7. A receiver signal chain calibration system according to claim 6, characterized in that The step of inputting the difference between the calibrated output voltage Vout_cal and the standard voltage Vref into the TIA for adjustment so that the calibrated output voltage Vout_cal approaches the standard voltage Vref specifically includes: Comparing the calibrated output voltage Vout_cal with the standard voltage Vref, If the calibrated output voltage Vout_cal is higher than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal is reduced; If the calibrated output voltage Vout_cal is lower than the standard voltage Vref, adjusting the TIA parameters so that the calibrated output voltage Vout_cal increases; Repeat the above steps until the adjustment times reach the set value; The current adjustment step size for adjusting the TIA parameters is 1 / 2 of the previous adjustment step size.

8. A receiver signal chain calibration system according to claim 1, characterized in that The steps to calibrate the gain error of the link include: Connect the link gain calibration current input line to the calibration input terminal of the TIA; The calibration currents Ical1 and Ical2 are respectively loaded to the calibration input terminal of the TIA through the link gain calibration current input circuit, so that the load output stage of the TIA outputs voltages Vcal1 and Vcal2 respectively and inputs them to the ADC; wherein the absolute value of the difference between Ical1 and Ical2 is 1 / 2 of the ADC reference current Iref; Get the outputs dout1 and dout2 of the ADC under the input voltages Vcal1 and Vcal2; The absolute value of the difference between the ADC outputs dout1 and dout2 is compared with the theoretical value, and the reference voltage Vref_adc of the ADC is adjusted according to the comparison result; the theoretical value is 2 N-1 , generated according to 1 / 2 of the reference current Iref, where N is the number of bits of the ADC.

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