Storage array structure

Abstract

The disclosed embodiments relate to the field of semiconductor technology and provide a memory array structure comprising: a substrate; a plurality of first transistors arranged in a square pattern and a plurality of second transistors arranged in a hexagonal pattern, located on the surface of the substrate; the first transistors comprising a first semiconductor layer, a first gate, and a first electrode and a second electrode electrically connected to different regions of the first semiconductor layer, the first electrode being located on the surface of the substrate, the second electrode being located on a side of the first electrode away from the substrate, and adjacent second electrodes being insulated; the second transistors comprising a second semiconductor layer, a second gate and a third gate located on opposite sides of the second semiconductor layer, and a third electrode and a fourth electrode electrically connected to different regions of the second semiconductor layer, the second electrode also being electrically connected to the second gate. The disclosed embodiments are at least beneficial for improving the electrical performance of the memory array structure and increasing the storage density of the memory array structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a storage array structure. Background Art

[0002] Common dynamic random access memory (DRAM) is a 1T1C type, where a single transistor source or drain is electrically connected to a capacitor to form a single memory cell. This structure uses capacitors to store data, but reading data consumes the capacitor's charge, and the capacitor itself leaks electricity, requiring constant refreshing. This results in high DRAM power consumption and unstable electrical performance. Furthermore, the large area required to manufacture the capacitor makes scaling down the capacitor challenging.

[0003] To overcome the problem caused by capacitance, a 2T0C type memory cell structure is used, that is, the source or drain of a transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a memory array structure that is at least advantageous for improving the storage density of the memory array structure while improving the electrical performance of the memory array structure.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a storage array structure, comprising: a substrate; a plurality of first transistors and a plurality of second transistors located on the surface of the substrate, the plurality of first transistors being arranged in a square, the plurality of second transistors being closely packed in a hexagonal pattern, a second transistor and two adjacent first transistors being connected to form a triangle, and a second transistor and a second transistor constituting a storage unit structure; wherein the first transistor comprises a first semiconductor layer, a first gate, and a first electrode and a second electrode electrically connected to different regions of the first semiconductor layer, the first electrode being located on the surface of the substrate, the second electrode being located on a side of the first electrode away from the substrate, the first gate, the first electrode and the second electrode being insulated from each other in pairs, and adjacent second electrodes being insulated from each other; the second transistor comprises a second semiconductor layer, a second gate and a third gate located on opposite sides of the second semiconductor layer, and a third electrode and a fourth electrode electrically connected to different regions of the second semiconductor layer, the second gate, the third gate, the third electrode and the fourth electrode being insulated from each other in pairs, and the second electrode being also electrically connected to the second gate.

[0006] In some embodiments, a plurality of the first transistors are arranged at intervals along a first direction and a second direction, the first direction and the second direction are both parallel to the surface of the substrate, and the first direction and the second direction intersect; the storage array structure also includes: a first word line extending along the first direction, the first word line is electrically contacted with a plurality of the first gates arranged at intervals along the first direction, and the first word line is insulated from the second gate; a bit line extending along the second direction, the bit line including a plurality of the first electrodes arranged at intervals along the second direction.

[0007] In some embodiments, the memory array structure further includes: a first isolation layer located between the bit lines adjacent along the first direction, the first isolation layer having a gap therein, and the gap passes through the first isolation layer in a direction perpendicular to the substrate surface.

[0008] In some embodiments, the memory array structure further includes: a second isolation layer located between the first isolation layer and the second electrode, between the first electrode and the second electrode, and between adjacent first semiconductor layers, and the second isolation layer is a stacked structure.

[0009] In some embodiments, along a direction perpendicular to the surface of the substrate, the second isolation layer includes a first sub-isolation layer, a second sub-isolation layer, and a third sub-isolation layer stacked in sequence, wherein the material of the first sub-isolation layer and the material of the third sub-isolation layer both include silicon nitride, and the material of the second sub-isolation layer includes silicon oxide.

[0010] In some embodiments, the first semiconductor layer encloses a first chamber, the first chamber is a chamber having a first opening, or the first chamber is a chamber having two first openings arranged opposite to each other; the first semiconductor layer has a first inner side and a first outer side relative to each other, and the first gate is opposite to a partial area of ​​the first inner side; the first transistor also includes: a first gate dielectric layer, located between the first gate and the first semiconductor layer.

[0011] In some embodiments, along a direction perpendicular to the surface of the substrate, the first semiconductor layer includes a first part, a second part and a third part; the second electrode is located on at least a portion of the first outer side of the third part; along a direction perpendicular to the surface of the substrate, the first electrode surrounds at least a portion of the height of the first outer side of the first part, and / or the first electrode is in contact and connected with the first bottom surface of the first semiconductor layer near the substrate.

[0012] In some embodiments, along a direction perpendicular to the surface of the substrate, the second semiconductor layer has a first surface and a second surface relative to each other, and along the first direction, the second semiconductor layer has a third surface and a fourth surface relative to each other; the second gate is opposite to the first surface, the third gate is opposite to the second surface, the third electrode is in contact with the third surface, and the fourth electrode is in contact with the fourth surface; the storage array structure also includes: a third isolation layer, located between the second gate and the first surface, between the third gate and the second surface, and between adjacent second transistors.

[0013] In some embodiments, the second semiconductor layer encloses a second chamber, the second chamber is a chamber having a second opening, or the second chamber is a chamber having two second openings arranged opposite to each other; the second semiconductor layer has a second inner side and a second outer side opposite to each other, the third gate is opposite to at least a portion of the second inner side, and the second gate is opposite to at least a portion of the second outer side; the second transistor further includes: a second gate dielectric layer, located between the second gate and the second semiconductor layer; and a third gate dielectric layer, located between the third gate and the second semiconductor layer.

[0014] In some embodiments, the potential at the third gate is adjusted according to the usage time of the memory cell structure.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] On the one hand, the first transistor and the second transistor together constitute a memory cell structure, without the need for a capacitor device, which is conducive to reducing the size of the memory cell structure itself, thereby improving the integration density of the memory array structure composed of multiple memory cell structures. Moreover, the multiple first transistors are arranged in a square and the multiple second transistors are closely packed in a hexagonal manner, which is conducive to reducing the spacing between adjacent memory cell structures, thereby further improving the integration density of the memory array structure. On the other hand, the second transistor is a dual-gate transistor, that is, the threshold voltage of the second transistor is controlled by the second gate and the third gate, which is conducive to flexible control of the conduction or shutdown of the second transistor to improve the electrical performance of the memory cell structure, thereby improving the electrical performance of the memory array structure. On the other hand, the first transistor can be used as a write transistor and the second transistor can be used as a read transistor. The second electrode is electrically connected to the second gate, so that the first transistor can affect the potential at the second gate. The second transistor is affected by the second gate and the third gate and presents different threshold voltages for representing data 1 and data 0, respectively, thereby realizing a 2TOC type memory cell structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of a partial top view of a storage array structure provided in one embodiment of the present disclosure;

[0019] Figure 2 for Figure 1 A schematic diagram of a partial cross-sectional structure of the storage array structure shown along the cross-sectional direction AA1;

[0020] Figure 3 for Figure 2 A schematic diagram of a partial cross-sectional structure of a first word line, a first gate, and a second gate in the memory array structure shown;

[0021] Figure 4 for Figure 2 An enlarged structural diagram of the box in the storage array structure shown;

[0022] Figure 5 for Figure 2 A schematic cross-sectional structure diagram of the first semiconductor layer and the second semiconductor layer in the memory array structure shown;

[0023] Figure 6 for Figure 1 Another partial cross-sectional structural schematic diagram of the memory array structure along the cross-sectional direction AA1 is shown;

[0024] Figure 7 Two partially enlarged cross-sectional structural schematic diagrams of the second transistor in the memory array structure provided in one embodiment of the present disclosure;

[0025] Figure 8 for Figure 1 Another partial cross-sectional structural schematic diagram of the memory array structure shown along the cross-sectional direction AA1;

[0026] Figure 9 Two other partially enlarged cross-sectional structural schematic diagrams of the second transistor in the memory array structure provided in one embodiment of the present disclosure;

[0027] Figure 10Three schematic diagrams of partial top views of the first transistor in the memory array structure provided in one embodiment of the present disclosure;

[0028] Figure 11 Two schematic diagrams of partial top views of the second transistor in the memory array structure provided in one embodiment of the present disclosure;

[0029] Figure 12 A simplified circuit diagram of operating a storage array structure according to another embodiment of the present disclosure;

[0030] Figures 13 to 20 A schematic cross-sectional structure diagram corresponding to each step in a method for manufacturing a memory cell structure provided in yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] As can be seen from the background art, both the electrical performance and integration density of the memory array structure need to be improved.

[0032] The present disclosure provides a memory array structure. On the one hand, a first transistor and a second transistor together constitute a memory cell structure, eliminating the need for a capacitor device, thereby reducing the size of the memory cell structure itself and improving the integration density of the memory array structure composed of multiple memory cell structures. Furthermore, the multiple first transistors are arranged in a square pattern and the multiple second transistors are closely packed in a hexagonal pattern, which helps reduce the spacing between adjacent memory cell structures, further improving the integration density of the memory array structure. On the other hand, the second transistor is a dual-gate transistor, that is, the threshold voltage of the second transistor is controlled by the second gate and the third gate, which helps flexibly control the conduction or shutdown of the second transistor to improve the electrical performance of the memory cell structure, thereby improving the electrical performance of the memory array structure. On the other hand, the first transistor can be used as a write transistor and the second transistor can be used as a read transistor. The second electrode is electrically connected to the second gate, so that the first transistor can affect the potential at the second gate. The second transistor, affected by the second gate and the third gate, exhibits different threshold voltages for representing data 1 and data 0, respectively, thereby realizing a 2TOC type memory cell structure.

[0033] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0034] An embodiment of the present disclosure provides a storage array structure, which will be described in detail below with reference to the accompanying drawings. Figure 1A schematic diagram of a partial top view of a storage array structure provided in one embodiment of the present disclosure; Figure 2 for Figure 1 A schematic diagram of a partial cross-sectional structure of the storage array structure shown along the cross-sectional direction AA1; Figure 3 for Figure 2 A schematic diagram of a partial cross-sectional structure of a first word line WWL, a first gate, and a second gate in the memory array structure shown; Figure 4 for Figure 2 An enlarged structural diagram of the box in the storage array structure shown; Figure 5 for Figure 2 A schematic cross-sectional structure diagram of the first semiconductor layer and the second semiconductor layer in the memory array structure shown; Figure 6 for Figure 1 Another partial cross-sectional structural schematic diagram of the memory array structure along the cross-sectional direction AA1 is shown; Figure 7 Two partially enlarged cross-sectional structural schematic diagrams of the second transistor in the memory array structure provided in one embodiment of the present disclosure; Figure 8 for Figure 1 Another partial cross-sectional structural schematic diagram of the memory array structure shown along the cross-sectional direction AA1; Figure 9 Two other partially enlarged cross-sectional structural schematic diagrams of the second transistor in the memory array structure provided in one embodiment of the present disclosure; Figure 10 Three schematic diagrams of partial top views of the first transistor in the memory array structure provided in one embodiment of the present disclosure; Figure 11 Two schematic diagrams of partial top views of the second transistor in the memory array structure provided in one embodiment of the present disclosure are provided.

[0035] refer to Figures 1 to 11The memory array structure includes: a substrate 100; a plurality of first transistors 101 and a plurality of second transistors 102 located on the surface of the substrate 100, wherein the plurality of first transistors 101 are arranged in a square pattern, and the plurality of second transistors 102 are closely packed in a hexagonal pattern, a second transistor 102 and two adjacent first transistors 101 are connected to form a triangle, and a second transistor 102 and a second transistor 102 constitute a memory cell structure 103; wherein the first transistor 101 includes a first semiconductor layer 111, a first gate 121, and a first electrode 131 and a second electrode 141 electrically connected to different regions of the first semiconductor layer 111, and the first electrode 131 is located on the surface of the substrate 100. The second electrode 141 is located on the side of the first electrode 131 away from the substrate 100, and the first gate 121, the first electrode 131 and the second electrode 141 are insulated from each other in pairs, and adjacent second electrodes 141 are insulated from each other; the second transistor 102 includes a second semiconductor layer 112, a second gate 122 and a third gate 132 located on opposite sides of the second semiconductor layer 112, and a third electrode 142 and a fourth electrode 152 electrically connected to different regions of the second semiconductor layer 112, the second gate 122, the third gate 132, the third electrode 142 and the fourth electrode 152 are insulated from each other in pairs, and the second electrode 141 is also electrically connected to the second gate 122.

[0036] It can be understood that compared to the second transistor 102, the first transistor 101 is closer to the substrate 100, and the electrical connection relationship between the first transistor 101 and the second transistor 102 is that the second electrode 141 is electrically connected to the second gate 122. In order to reduce the distance between the second electrode 141 and the second gate 122, the multiple first transistors 101 are designed to be arranged in a square and the multiple second transistors 102 are designed to be closely packed in a hexagonal manner. This is also beneficial to reducing the spacing between adjacent memory cell structures, thereby further improving the integration density of the memory array structure.

[0037] In addition, the second transistor 102 is a dual-gate transistor, that is, the threshold voltage of the second transistor 102 is jointly controlled by the second gate 122 and the third gate 132. The second transistor 102 exhibits different threshold voltages under the joint influence of the second gate 122 and the third gate 132. The second transistor 102 at different threshold voltages can be used to represent data 1 and data 0, respectively.

[0038] In this way, the second transistor 102 can be a read transistor and the first transistor 101 is a write transistor. Since the second electrode 141 of the first transistor 101 is electrically connected to the second gate 122 of the second transistor 102, that is, the first transistor 101 can affect the threshold voltage of the second transistor 102 through the second gate 122. In addition, the third gate 132 will also affect the threshold voltage of the second transistor 102. Therefore, during a period of time when the storage unit structure 103 is used, the voltage provided to the third gate 132 is kept unchanged. The difference in the voltage provided to the second electrode 141, that is, the voltage provided to the second gate 122, is changed by the first transistor 101, so that the threshold voltage of the second transistor 102 is changed, so that the second transistor 102 can store data. Subsequently, the current flowing through the second transistor 102 is read through the third electrode 142 and the fourth electrode 152 of the second transistor 102 to realize the reading of data. Among them, different voltages of the second gate 122 result in different threshold voltages of the second transistor 102, and thus different currents flowing through the first transistor 101 read from the third electrode 142 and the fourth electrode 152 are different. The different magnitudes of the currents can be used to represent data 1 and data 0, respectively.

[0039] In addition, the threshold voltage of the second transistor 102 will also be affected by the use time. For example, in the early stage of using the second transistor 102, when the potential at the second gate 122 is A1 and the potential at the third gate 132 is B1, the second transistor 102 is in a critical state of conduction, that is, the current read through the second transistor 102 is large at this time, and it can be judged that data 1 is read; after using the second transistor 102 for a period of time, when the potential at the second gate 122 is A1 and the potential at the third gate 132 is B1, the second transistor 102 may not be turned on, so that the current read through the second transistor 102 is small or 0 at this time, and it will be judged that data 0 is read. There will be a deviation between writing and reading data. At this time, since the second transistor 102 is a dual-gate transistor, by adjusting the potential at the third gate 132, for example, making the potential at the third gate 132 B2, so that the potential at the second gate 122 is still A1, when the potential at the third gate 132 is B2, the second transistor 102 is in a critical state of conduction to avoid the deviation between writing and reading data, so as to ensure the normal operation of the storage unit structure 103. It can be understood that by designing the second transistor 102 as a dual-gate transistor, it is beneficial to more flexibly control the storage unit structure 103 through the third gate 132, which is beneficial to improve the service life of the storage unit structure 103.

[0040] It should be noted that Figure 1In the example, four first transistors 101 are arranged at intervals along the first direction X and four first transistors 101 are arranged along the second direction Y. In actual applications, there is no limit on the number of first transistors 101 arranged at intervals along the first direction X, and there is no limit on the number of first transistors 101 arranged along the second direction Y.

[0041] The memory cell structure provided by an embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0042] In some embodiments, reference Figure 1 , a plurality of first transistors 101 are arranged at intervals along a first direction X and a second direction Y, the first direction X and the second direction Y are both parallel to the surface of the substrate 100, and the first direction X and the second direction Y intersect; the memory array structure further includes: a first word line WWL extending along the first direction X, the first word line WWL electrically contacting a plurality of first gates 121 arranged at intervals along the first direction X, and the first word line WWL is insulated from the second gate 122; a bit line BL extending along the second direction Y, the bit line BL including a plurality of first electrodes 131 arranged at intervals along the second direction Y.

[0043] It should be noted that, in order to illustrate the positional relationship among the first word line WWL, the bit line BL, the first transistor 101 and the second transistor 102, Figure 1 The main position of the first transistor 101 is indicated by a circle, and the main position of the second transistor 102 is indicated by a rectangle. Except for the first word line WWL, the bit line BL, the first transistor 101 and the second transistor 102, other parts of the memory array structure are not drawn. Among them, the second transistor 102 is hexagonally closely packed, that is, the second transistor 102 is arranged in a honeycomb shape. In addition, Figure 1 The memory cell structure 103 is marked by a combination of a first transistor 101 and a second transistor 102 enclosed in a box.

[0044] In some embodiments, in conjunction with reference Figure 1 and Figure 2 The bit line BL extends along the second direction Y, and a portion of the bit line BL itself serves as the first electrode 131 in the first transistor 101, so that a plurality of first transistors 101 spaced apart along the second direction Y share the same bit line BL.

[0045] In some embodiments, in conjunction with reference Figure 2 and Figure 3The first word line WWL as a whole tends to extend along the first direction X. Moreover, along the direction Z perpendicular to the surface of the substrate 100, the first word line WWL surrounds a portion of the first gate 121 at a height, so that the first word line WWL is electrically in contact with the multiple first gates 121 arranged at intervals along the first direction X. In addition, the first word line WWL has multiple grooves corresponding to the second gates 122, so that a gap is formed between the first word line WWL and the second gate 122, so that the first word line WWL and the second gate 122 are insulated.

[0046] In some embodiments, reference Figure 2 The memory array structure may further include a first isolation layer 104 located between adjacent bit lines BL along a first direction X. The first isolation layer 104 may include a gap 114 extending through the first isolation layer 104 in a direction perpendicular to the surface of the substrate 100. Thus, the gap 114 may increase the overall dielectric constant of the first isolation layer 104 between adjacent bit lines BL, thereby reducing the coupling effect between adjacent bit lines BL and improving the electrical performance of the memory array structure.

[0047] In some embodiments, continue to refer to Figure 2 The first isolation layer 104 between adjacent bit lines BL has at least two gaps 114 , which is beneficial for further reducing the coupling effect between adjacent bit lines BL.

[0048] In some embodiments, continue to refer to Figure 2 The storage array structure may further include: a second isolation layer 105, located between the first isolation layer 104 and the second electrode 141, between the first electrode 131 and the second electrode 141, and between adjacent first semiconductor layers 111, and the second isolation layer 105 is a stacked structure.

[0049] It can be understood that the second isolation layer 105 is located between the first isolation layer 104 and the second electrode 141, that is, the second isolation layer 105 is located between the bit line BL and the first word line WWL. The second isolation layer 105 is a stacked structure, which is beneficial to improving the dielectric constant of the second isolation layer 105 itself through changes in the material of the second isolation layer 105 itself or the interface performance of its own film layer, thereby reducing the coupling effect between the bit line BL and the first word line WWL, so as to improve the electrical performance of the storage array structure.

[0050] In some embodiments, continue to refer to Figure 2Along a direction Z perpendicular to the surface of the substrate 100, the second isolation layer 105 includes a first sub-isolating layer 115, a second sub-isolating layer 125, and a third sub-isolating layer 135 stacked in sequence. The first sub-isolating layer 115 and the third sub-isolating layer 135 are both made of silicon nitride, while the second sub-isolating layer 125 is made of silicon oxide. This structure, on the one hand, facilitates improving the dielectric constant of the second isolation layer 105 through the NON structure (i.e., the combined film structure of the silicon nitride layer, the silicon oxide layer, and the silicon nitride layer), thereby further reducing the coupling effect between the bit line BL and the first word line WWL. On the other hand, the silicon nitride layer is relatively hard and not prone to collapse, which helps to improve the stability of the second isolation layer 105, thereby improving the stability of the memory array structure.

[0051] In some embodiments, along the direction Z, the thickness of the first sub-isolating layer 115 and the thickness of the third sub-isolating layer 135 are both less than the thickness of the second sub-isolating layer 125. It can be understood that the dielectric constant of the second sub-isolating layer 125 including silicon oxide is greater than the dielectric constant of the first sub-isolating layer 115 and the third sub-isolating layer 135 including silicon nitride, and the hardness of the second sub-isolating layer 125 including silicon oxide is less than the hardness of the first sub-isolating layer 115 and the third sub-isolating layer 135 including silicon nitride. Therefore, the second sub-isolating layer 125 is designed to be thinner than the first sub-isolating layer 115 and the third sub-isolating layer 135. The thickness of layer 125 is relatively thick, while the thickness of the first sub-isolation layer 115 and the third sub-isolation layer 135 are relatively thin, which is beneficial to improving the overall dielectric constant of the second isolation layer 105, and a film layer containing silicon nitride is designed on the opposite sides of the second sub-isolation layer 125 along the direction Z, which is beneficial to using the film layer containing silicon nitride to avoid deformation of the second sub-isolation layer 125, that is, the first sub-isolation layer 115 and the third sub-isolation layer 135 play a supporting and shaping role for the second sub-isolation layer 125, so as to improve the overall stability of the second isolation layer 105.

[0052] It should be noted that Figure 2 In the example, the second isolation layer 105 includes three sub-isolation layers. In practical applications, in order to meet the corresponding requirements, the second isolation layer 105 can be designed to have a multi-layer structure such as NONO or NONON. Among them, N represents a sub-isolation layer including silicon nitride, and O represents a sub-isolation layer including silicon oxide. In addition, for the clarity of the diagram, Figure 2 The first word line WWL is not shown.

[0053] In some embodiments, reference Figure 2 , the gap 114 in the first isolation layer 104 penetrates the first isolation layer 104 along the direction Z. In practical applications, the gap can also be a blind hole in the first isolation layer. Figure 2 and Figure 4 The bottom surface of the second isolation layer 105 corresponding to the gap 114 is recessed toward the substrate 100 .

[0054] The specific structure of the first transistor 101 includes at least the following embodiments:

[0055] In some embodiments, reference Figure 2 or Figure 6 The first semiconductor layer 111 forms a first chamber 117 , and the first chamber 117 is a chamber having a first opening 127 .

[0056] In other embodiments, reference Figure 8 The first chamber 117 is a chamber having two first openings 127 disposed opposite each other. For example, the two first openings 127 of the first chamber 117 are disposed opposite each other along direction Z. It is understood that the first gate 121 is located within the first chamber 117, and one of the first openings 127 in the first chamber 117 is used to expose the top surface of the first gate 121 away from the substrate 100.

[0057] In the above two embodiments, reference Figure 2 、 Figures 5 to 9 The first semiconductor layer 111 has a first inner side 111a and a first outer side 111b relative to each other, and the first gate 121 is opposite to a portion of the first inner side 111a; the first transistor 101 also includes: a first gate dielectric layer 151, located between the first gate 121 and the first semiconductor layer 111.

[0058] Understandably, the reference Figure 8 When the first chamber 117 is a chamber having two first openings 127 opposite to each other, the first gate dielectric layer 151 is also located between the first gate 121 and the first electrode 131 .

[0059] In some embodiments, in conjunction with reference Figure 5 and Figure 2 、 Figure 6 or Figure 8 Along a direction Z perpendicular to the surface of the substrate 100 , the first semiconductor layer 111 includes a first portion 161 , a second portion 171 and a third portion 181 ; the second electrode 141 is located at least partially on the first outer side 111 b of the third portion 181 .

[0060] It can be understood that, in one example, the second electrode 141 can surround the first outer side 111b of the third part 181, which is beneficial to increase the contact area between the second electrode 141 and the first semiconductor layer 111, so as to reduce the contact resistance between the second electrode 141 and the first semiconductor layer 111, thereby facilitating the improvement of the electrical performance of the first transistor 101; in another example, the second electrode 141 may also be located only on part of the first outer side 111b of the third part 181.

[0061] In some embodiments, in conjunction with reference Figure 5 and Figure 2 ,or Figure 5 and Figure 8 In the direction Z perpendicular to the surface of the substrate 100, the first electrode 131 surrounds at least a portion of the first outer side 111b of the first portion 161. This helps to increase the contact area between the first electrode 131 and the first semiconductor layer 111, thereby reducing the contact resistance between the first electrode 131 and the first semiconductor layer 111, thereby improving the electrical performance of the first transistor 101. It should be noted that Figure 2 In the example, the first electrode 131 surrounds the entire first outer side 111b of the first portion 161. Figure 8 The first electrode 131 is also in contact with and connected to the first bottom surface 111 d of the first semiconductor layer 111 close to the substrate 100 .

[0062] In other embodiments, reference Figure 6 The first electrode 131 is only in contact with and connected to the first bottom surface 111 d of the first semiconductor layer 111 close to the substrate 100 .

[0063] In the above various embodiments, reference Figure 2 、 Figure 6 and Figure 8 The second isolation layer 105 may surround the first outer side 111 b of the second portion 171 , so that the first electrode 131 and the second electrode 141 are electrically insulated by the second isolation layer 105 .

[0064] In the above various embodiments, reference Figure 2 、 Figure 6 and Figure 8 The first gate dielectric layer 151 may also be located on the first top surface 111 c of the first semiconductor layer 111 away from the substrate 100 , and the first gate 121 also faces the first top surface 111 c .

[0065] In the above various embodiments, reference Figure 10 In 10a, the orthographic projection of the first semiconductor layer 111 in the first transistor 101 on the substrate 100 is a ring, that is, the first semiconductor layer 111 is a hollow cylinder; or, referring to Figure 10 In FIG10c , the orthographic projection of the first semiconductor layer 111 in the first transistor 101 on the substrate 100 is a square ring. In practical applications, the orthographic projection of the first semiconductor layer 111 in the first transistor 101 on the substrate 100 may also be a ring of other shapes.

[0066] In the above various embodiments, in combination with reference Figure 2 and Figure 10 10b, or Figure 6 and Figure 10In FIG10b, the cross-sectional shape of the first semiconductor layer 111 in the first transistor 101 on a plane perpendicular to the second direction Y may be similar to a U shape. Alternatively, in combination with reference Figure 8 and Figure 10 In FIG10b , the cross-sectional shape of the first semiconductor layer 111 in the first transistor 101 on a plane perpendicular to the second direction Y may also be two rectangles spaced apart along the first direction X, and the cross-sectional shape of the first gate dielectric layer 151 on a plane perpendicular to the second direction Y is similar to a U-shape.

[0067] It can be understood that in the various embodiments described above, in the first transistor 101, the first semiconductor layer 111 itself forms a first cavity, which is beneficial to increasing the surface area of ​​the first semiconductor layer 111 while ensuring that the first semiconductor layer 111 itself occupies a smaller layout space, thereby facilitating increasing the facing area between the first gate 121 and the first semiconductor layer 111, as well as increasing the facing area between the first gate 121 and the first semiconductor layer 111, so as to improve the control ability of the first gate 121 over the first semiconductor layer 111, thereby facilitating improving the electrical performance of the first transistor 101.

[0068] In the above various embodiments, the cross-section of the first gate 121 on a plane perpendicular to the second direction Y may be T-shaped. It is understood that, depending on the manufacturing process, the first gate 121 may be a single-layer structure or a multi-layer structure.

[0069] The specific structure of the second transistor 102 includes at least the following embodiments:

[0070] Example 1: In some embodiments, reference Figure 5 Along the direction Z perpendicular to the surface of the substrate 100, the second semiconductor layer 112 has a first surface 112a and a second surface 112b opposite to each other. Along the first direction X, the second semiconductor layer 112 has a third surface 112c and a fourth surface 112d opposite to each other.

[0071] Combined with reference Figure 2 and Figure 5The second gate 122 is directly opposite to the first surface 112a, the third gate 132 is directly opposite to the second surface 112b, the third electrode 142 is in contact with the third surface 112c, and the fourth electrode 152 is in contact with the fourth surface 112d. The memory array structure may further include: a third isolation layer 106, located between the second gate 122 and the first surface 112a, between the third gate 132 and the second surface 112b, and between adjacent second transistors 102. It is understood that the third isolation layer 106 located between the second gate 122 and the first surface 112a can serve as a gate dielectric layer between the second gate 122 and the second semiconductor layer 112, and the third isolation layer 106 located between the third gate 132 and the second surface 112b can serve as a gate dielectric layer between the third gate 132 and the second semiconductor layer 112.

[0072] Example 2: In some embodiments, reference Figures 6 to 9 The second semiconductor layer 112 forms a second chamber 137 , and the second chamber 137 is a chamber having a second opening 147 .

[0073] In some other embodiments, the second chamber 137 is a chamber having two second openings 147 disposed opposite to each other. For example, the two second openings 147 of the second chamber 137 are disposed opposite to each other along the Z direction.

[0074] It should be noted that Figure 7 The second chamber 137 is framed by a thick dashed line, and the range of the second opening 147 is drawn by a dashed line.

[0075] It can be understood that the third gate 132 is located in the second cavity 137 , and a second opening 147 in the second cavity 137 is used to expose the third gate 132 to facilitate electrical connection of the third gate 132 to other electrical connection layers.

[0076] In the above two embodiments, reference Figures 6 to 9 The second semiconductor layer 112 has a second inner side 112e and a second outer side 112f opposite to each other, the third gate 132 is directly opposite to at least a portion of the second inner side 112e, and the second gate 122 is directly opposite to at least a portion of the second outer side 112f. The second transistor 102 may further include: a second gate dielectric layer 162 located between the second gate 122 and the second semiconductor layer 112; and a third gate dielectric layer 172 located between the third gate 132 and the second semiconductor layer 112. It should be noted that the second gate dielectric layer 162 is located at least between the second gate 122 and the second semiconductor layer 112, and the third gate dielectric layer 172 is located at least between the third gate 132 and the second semiconductor layer 112. In actual applications, the second gate dielectric layer 162 or the third gate dielectric layer 172 may also be located at other locations as required to achieve insulation between the other two film layers.

[0077] It can be understood that in the various embodiments described above, the second semiconductor layer 112 itself forms a second chamber, which is beneficial to increasing the surface area of ​​the second semiconductor layer 112 while ensuring that the second semiconductor layer 112 itself occupies a smaller layout space, and increasing the length of the channel formed in the second semiconductor layer 112, thereby facilitating increasing the area facing the second gate 122 and the second semiconductor layer 112, as well as increasing the area facing the third gate 132 and the second semiconductor layer 112, so as to improve the control ability of the second gate 122 and the third gate 132 over the second semiconductor layer 112, thereby facilitating improving the electrical performance of the second transistor 102.

[0078] In the above various embodiments, reference Figure 6 and Figure 8 The memory array structure may further include a conductive pillar 107. Along direction Z, one end of the conductive pillar 107 is electrically in contact with the second electrode 141, and the other end of the conductive pillar 107 is electrically in contact with the second gate 122. In other words, the conductive pillar 107 provides electrical connection between the second electrode 141 and the second gate 122. It is understood that the first word line WWL is electrically insulated from the conductive pillar 107.

[0079] Due to the different positional relationships between the third electrode 142 and the fourth electrode 152 and the second semiconductor layer 112, the specific structure of the second transistor 102 includes at least the following various embodiments:

[0080] First, in some embodiments, reference Figure 6 and Figure 7 The second gate dielectric layer 162 is located in a partial area of ​​the second outer side 112f, and the third electrode 142 and the fourth electrode 152 are respectively in contact with different areas of other areas of the second outer side 112f.

[0081] In some embodiments, continue to refer to Figure 6 and Figure 7 , a partial area of ​​the second outer side 112f extending along the third Z is not covered by the second gate dielectric layer 162, and this partial area is in contact with the third electrode 142, the fourth electrode 152 and the third isolation layer 106, and the third electrode 142, the fourth electrode 152 and the second gate 122 are electrically insulated from each other by the third isolation layer 106.

[0082] In some embodiments, continue to refer to Figure 6 and Figure 7 , the third electrode 142 and the fourth electrode 152 are facing each other along the first direction X. It should be noted that, referring to Figure 11In FIG. 11 a , the orthographic projection of the second chamber surrounded by the second semiconductor layer 112 on the substrate 100 may be a circular ring. In practical applications, the orthographic projection of the second chamber surrounded by the second semiconductor layer on the substrate may also be a square ring or a ring of other shapes.

[0083] The second transistor 102 in which both the third electrode 142 and the fourth electrode 152 are in contact with the second semiconductor layer 112 will be described in detail below.

[0084] In one example, in conjunction with reference Figure 6 The second semiconductor layer 112 is a second chamber 137 including a second opening 147, the second outer side 112f includes an area extending along the direction Z and an area extending along the first direction X, the second gate dielectric layer 162 covers the area of ​​the second outer side 112f extending along the first direction X and is located at a partial area of ​​the second outer side 112f extending along the direction Z, and the second gate 122 covers the side of the second gate dielectric layer 162 away from the second semiconductor layer 112.

[0085] In another example, refer to Figure 7 In Figure 7a, the second semiconductor layer 112 is a second chamber 137 including a second opening 147, the second outer side 112f includes an area extending along the direction Z and an area extending along the first direction X, the second gate dielectric layer 162 only covers the area of ​​the second outer side 112f extending along the first direction X, and the second gate 122 covers the side of the second gate dielectric layer 162 away from the second semiconductor layer 112.

[0086] In yet another example, reference Figure 7 In Figure 7b, the second semiconductor layer 112 is a second chamber 137 including a second opening 147, the second outer side 112f includes an area extending along the direction Z and an area extending along the first direction X, the second gate dielectric layer 162 is only located in a partial area of ​​the second outer side 112f extending along the direction Z, and the second gate 122 covers a side of the second gate dielectric layer 162 away from the second semiconductor layer 112, that is, the area of ​​the second outer side 112f extending along the first direction X is not covered by the second gate dielectric layer 162.

[0087] In another example, the second semiconductor layer is a second cavity including two second openings. In addition to having a second inner side and a second outer side opposite to each other along the first direction, the second semiconductor layer further has a second top surface and a second bottom surface opposite to each other along the direction Z. The second gate dielectric layer is located only in a portion of the second outer side.

[0088] Second, in other embodiments, reference Figure 8In addition to FIG9 , the second gate dielectric layer 162 covers the area of ​​the second outer side 112f extending in a direction Z perpendicular to the surface of the substrate 100. Along the direction Z perpendicular to the surface of the substrate 100, the third electrode 142 directly faces a portion of the sidewall of the second gate dielectric layer 162, and the fourth electrode 152 directly faces other portions of the sidewall of the second gate dielectric layer 162. For example, the third electrode 142 and the fourth electrode 152 may directly face each other along a first direction X, where the first direction X is parallel to the surface of the substrate 100. In practical applications, to meet other requirements, the third electrode 142 and the fourth electrode 152 only need to directly face different areas of the sidewall of the second gate dielectric layer 162, and the third electrode 142 and the fourth electrode 152 can be insulated from each other.

[0089] Continue to refer Figure 8 and Figure 9 The storage cell structure may further include: a first electrical connection layer 118, one end of the first electrical connection layer 118 is electrically contacted with the third electrode 142, and the other end is electrically contacted with a portion of the second top surface of the second semiconductor layer 112, so as to realize electrical connection between the third electrode 142 and the second semiconductor layer 112 through the first electrical connection layer 118; a second electrical connection layer 128, one end of the second electrical connection layer 128 is electrically contacted with the fourth electrode 152, and the other end is electrically contacted with a portion of the other second top surface of the second semiconductor layer 112, so as to realize electrical connection between the fourth electrode 152 and the second semiconductor layer 112 through the second electrical connection layer 128.

[0090] It should be noted that the reference Figure 11 In Figure 11a, the orthographic projection of the second cavity enclosed by the second semiconductor layer 112 on the substrate 100 is a circular ring, that is, the second top surface of the second semiconductor layer 112 is a circular ring, the first electrical connection layer 118 is in contact with and connected to a portion of the length of the circular ring, and the second electrical connection layer 128 is in contact with and connected to the remaining portion of the length of the circular ring. In practical applications, the orthographic projection of the second cavity enclosed by the second semiconductor layer on the substrate 100 can also be a square ring or other ring shape, that is, the second top surface of the second semiconductor layer is a square ring or other ring shape.

[0091] In addition, the first electrical connection layer 118 is electrically insulated from the second gate 122 and the third gate 132 , and the second electrical connection layer 128 is electrically insulated from the second gate 122 and the third gate 132 .

[0092] The second transistor 102 including the first electrical connection layer 118 and the second electrical connection layer 128 will be described in detail below.

[0093] In one example, reference Figure 8The second semiconductor layer 112 is a second cavity 137 including a second opening 147. The second outer side 112f includes an area extending along the direction Z and an area extending along the first direction X. The second gate dielectric layer 162 not only covers the area of ​​the second outer side 112f extending along the direction Z, but also covers the area of ​​the second outer side 112f extending along the first direction X, that is, the second gate dielectric layer 162 covers the entire second outer side 112f, and the second gate 122 covers the side of the second gate dielectric layer 162 away from the second semiconductor layer 112.

[0094] In another example, in conjunction with reference Figure 9 9a, the second semiconductor layer 112 is a second chamber 137 including a second opening 147, the second outer side 112f includes an area extending along the direction Z and an area extending along the first direction X, and the second gate dielectric layer 162 only covers the area of ​​the second outer side 112f extending along the direction Z, that is, the second outer side 112f extending along the first direction X in the second semiconductor layer 112 is not in contact with the second gate dielectric layer 162, and the second gate 122 covers the side of the second gate dielectric layer 162 away from the second semiconductor layer 112.

[0095] In yet another example, reference Figure 9 9b, the second semiconductor layer 112 is a second cavity 137 including two second openings 147. In addition to having a second inner side 112e and a second outer side 112f opposite to each other along the first direction X, the second semiconductor layer 112 further has a second top surface 112g and a second bottom surface 112h opposite to each other along the direction Z. The second gate dielectric layer 162 covers the region of the second outer side 112f extending along the direction Z, that is, covers the entire second outer side 112f. The second gate electrode 122 covers the side of the second gate dielectric layer 162 away from the second semiconductor layer 112.

[0096] In the above various embodiments, reference Figures 5 to 9 The third gate dielectric layer 172 covers the second inner side 112 e , and the third gate electrode 132 covers a side of the third gate dielectric layer 172 away from the second semiconductor layer 112 .

[0097] In the above various embodiments, reference Figure 11 In FIG11b, the cross-sectional shape of the second semiconductor layer 112 on a plane perpendicular to the second direction Y is U-shaped. Thus, any one of the second gate dielectric layer 162, the third gate dielectric layer 172 and the second gate electrode 122 can be two long strip structures spaced apart along the first direction X, or have a U-shaped cross-sectional shape on a plane perpendicular to the second direction Y.

[0098] In the various embodiments described above, the third electrode 142 and the fourth electrode 152 are arranged to surround a portion of the side wall of the second semiconductor layer 112 extending in the direction Z. This is beneficial for increasing the cross-sectional area of ​​the third electrode 142 and the fourth electrode 152 in a plane perpendicular to the direction Z while ensuring that the layout space occupied by the third electrode 142 and the fourth electrode 152 themselves is small, so as to increase the contact area between the third electrode 142 and the fourth electrode 152 and other conductive structures (for example, the first electrical connection layer 118 or the second electrical connection layer 128), and is beneficial for improving the capacitive coupling effect between the third electrode 142 and the fourth electrode 152 and the second gate 122.

[0099] In some embodiments, the third isolation layer 106 may be a multi-layer structure, and the materials of different layers in the multi-layer structure may be the same or different.

[0100] In some embodiments, the potential at the third gate 132 can be adjusted based on the age of the memory cell structure. It is understood that the threshold voltage of the second transistor 102 will also be affected by age. By adjusting the potential at the third gate 132, the threshold voltage of the second transistor 102 at this time is guaranteed to be consistent with the threshold voltage of the second transistor 102 not affected by age, while the potential at the second gate 122 remains unchanged, thereby avoiding deviations between data writing and reading, and ensuring the normal operation of the memory cell structure. In this way, by designing the second transistor 102 as a dual-gate transistor, it is beneficial to more flexibly control the memory cell structure through the third gate 132, thereby increasing the service life of the memory cell structure, thereby increasing the service life of the memory array structure.

[0101] In some embodiments, the memory array structure may further include: a second word line RWL extending along a first direction X, and a plurality of third gates 132 spaced apart along the first direction X electrically connected to the same second word line RWL. In other embodiments, the memory array structure may further include: a second word line RWL extending along a second direction Y, and a plurality of third gates 132 spaced apart along the second direction Y electrically connected to the same second word line RWL. It will be appreciated that when the second word line RWL in the memory array structure is electrically linked to the third gates 132 in the second transistor 102, the current flowing through the second word line RWL is of very low magnitude and can be considered to be zero. Therefore, the current flowing through the second word line RWL does not affect the number of second transistors 102 electrically connected to the same second word line RWL, thereby facilitating an improvement in the storage density of the memory array structure.

[0102] In some further embodiments, the potential of the third gate 132 in each second transistor 102 can be controlled individually.

[0103] In some embodiments, the material of the first semiconductor layer 111 includes one or more of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide), or ITO (Indium Tin Oxide), and the material of the second semiconductor layer 112 includes one or more of IGZO, IWO, or ITO.

[0104] It can be understood that when the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 are composed of the above materials, it is beneficial to improve the carrier mobility of the first semiconductor layer 111 and the second semiconductor layer 112, thereby helping the first semiconductor layer 111 and the second semiconductor layer 112 to transmit electrical signals more efficiently.

[0105] In one example, the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 are both IGZO. The carrier mobility of IGZO is 20 to 50 times that of polysilicon, which helps to improve the carrier mobility of the channel region formed in the first semiconductor layer 111 and the second semiconductor layer 112, thereby helping to reduce the leakage current of the first transistor 101 and the second transistor 102 during operation, thereby reducing the power consumption of the memory cell structure and improving the operating efficiency of the memory cell structure. In addition, the retention time of the memory cell structure configured by the first transistor 101 and the second transistor 102 including IGZO can exceed 300 seconds, which helps to reduce the refresh rate and power consumption of the memory cell structure.

[0106] It should be noted that for the sake of clarity of the diagram, Figures 1 to 11 The first semiconductor layer 111 and the second semiconductor layer 112 are filled in the same filling manner. It can be understood that the material of the first semiconductor layer 111 and the material of the second semiconductor layer 112 can be the same or different; Figures 1 to 11 The first gate 121 and the third gate 132 are filled in the same filling manner. It can be understood that the material of the first gate 121 and the material of the third gate 132 can be the same or different; Figure 2 、 Figure 6 and Figure 8 The first isolation layer 104, the second sub-isolation layer 125 and the third isolation layer 106 are filled in the same filling manner. It can be understood that the material of the first isolation layer 104, the material of the second sub-isolation layer 125 and the material of the third isolation layer 106 can be the same or different.

[0107] also, Figure 1 The filling method of the median line BL is the same as Figure 2 、 Figure 6 and Figure 8The filling method of the first electrode 131 is the same. It can be understood that the local area of ​​the bit line BL is the first electrode 131.

[0108] The second direction Y and the first direction X are both parallel to the surface of the substrate 100 , that is, the second direction Y and the first direction X are both perpendicular to the direction Z, and, Figures 1 to 11 In the examples, the first direction X and the second direction Y are perpendicular to each other. In actual applications, the first direction X and the second direction Y can intersect.

[0109] In summary, the first transistor 101 and the second transistor 102 together constitute the memory cell structure 103, which does not require a capacitor device, which is beneficial to reducing the size of the memory cell structure 103 itself, thereby improving the integration density of the memory array structure composed of multiple memory cell structures 103. Moreover, the multiple first transistors 101 are arranged in a square and the multiple second transistors 102 are closely packed in a hexagonal pattern, which is beneficial to reducing the spacing between adjacent memory cell structures 103, thereby further improving the integration density of the memory array structure. On the other hand, the second transistor 102 is a dual-gate transistor, that is, the threshold voltage of the second transistor 102 is jointly controlled by the second gate 122 and the third gate 132, which is beneficial to flexibly control the conduction or shutdown of the second transistor 102, thereby improving the electrical performance of the memory cell structure 103, thereby improving the electrical performance of the memory array structure. On the other hand, the first transistor 101 can be used as a write transistor, the second transistor 102 can be used as a read transistor, and the second electrode 141 is electrically connected to the second gate 122. Then, the first transistor 101 can affect the potential at the second gate 122, and the second transistor 102 is affected by the second gate 122 and the third gate 132 to present different threshold voltages for representing data 1 and data 0, respectively, thereby realizing a 2T0C type storage cell structure.

[0110] Another embodiment of the present disclosure further provides a method for operating a storage array structure, which is used to operate the storage array structure provided by an embodiment of the present disclosure. Figure 12 A simplified circuit diagram of operating a storage array structure according to another embodiment of the present disclosure.

[0111] Combined with reference Figure 2 and Figure 12 The operating method of the storage array structure includes: providing the aforementioned storage array structure, and performing a write operation or a read operation on any storage cell structure 103 in the storage array structure.

[0112] It should be noted that Figure 12 In the example, a memory array structure includes a plurality of first word lines WWL arranged at intervals along the second direction Y, a plurality of bit lines BL arranged at intervals along the first direction X, and a plurality of second word lines RWL arranged at intervals along the second direction Y. Figure 12The example shown details the write operation or read operation of the memory cell structure 103. In practical applications, the plurality of second word lines RWL may also be arranged at intervals along the first direction X, or the third gate 132 of each second transistor 102 may be controlled individually.

[0113] It can be understood that the second transistor 102 is a read transistor and the first transistor 101 is a write transistor. From a circuit perspective, the second transistor 102 is a dual-gate transistor, and the first transistor 101 and the second transistor 102 together form a 2T0C type memory cell structure 103. This facilitates utilizing the two gates of the second transistor 102 to respectively complete data storage and read and write operation control. Based on the advantages of gate-controlled read and write operations, the read and write operations of the constructed 2T0C type memory cell structure are more flexible.

[0114] In addition, it can be seen from the above analysis that the threshold voltage of the second transistor 102 will also be affected by the usage time. By adjusting the potential at the third gate 132, the first transistor 101 can still be in a critical state of conduction when the potential at the second gate 122 remains unchanged, so as to avoid the deviation between data writing and reading, so as to ensure the normal operation of the memory cell structure 103. It can be understood that by designing the second transistor 102 as a dual-gate transistor, it is beneficial to more flexibly control the memory cell structure 103 through the third gate 132, so as to improve the service life of the memory array structure.

[0115] The following describes in detail how to use the two gates of the second transistor 102 to respectively complete data storage and read / write operation control.

[0116] In some embodiments, performing a write operation on any memory cell structure 103 in the memory array structure may include the following steps:

[0117] A first voltage V1 is provided to a first word line WWL, and a second voltage V2 is provided to a bit line BL to select a memory cell structure. Figure 12 The memory cell structure composed of the marked first transistor 101 and the second transistor 102 is taken as the selected memory cell structure.

[0118] A third voltage V3 is supplied to the third electrode 142 in the selected memory cell structure, and a fourth voltage V4 is supplied to the fourth electrode 152 in the selected memory cell structure to perform a write operation on the selected memory cell structure. The first voltage V1 is the turn-on voltage of the first transistor 101 in the selected memory cell structure, and the difference in potential at the storage node SN results in a difference in the threshold voltage of the second transistor 102. It should be noted that the electrically connected second electrode 141 and second gate 122 constitute the storage node SN.

[0119] In some embodiments, during the write operation on the selected memory cell structure, no voltage signal is provided to all second word lines RWL, no voltage is provided to the remaining first word lines WWL and the remaining bit lines BL, and no voltage is provided to the third electrode 142 and the fourth electrode 152 in other memory cell structures.

[0120] In some embodiments, the higher the potential at the storage node SN, the lower the threshold voltage of the second transistor 102. Thus, when writing data 1 to a selected memory cell structure, the second voltage V2 and the third voltage V3 are both high, the fourth voltage V4 is grounded, and after the first voltage V1 is supplied to a first word line WWL, the first transistor 101 in the selected memory cell structure is turned on, causing the potential at the storage node SN to approach the second voltage V2, i.e., the potential at the storage node SN is high. When writing data 0 to a selected memory cell structure, the second voltage V2 and the third voltage V3 are both low, the fourth voltage V4 is grounded, and after the first voltage V1 is supplied to a first word line WWL, the first transistor 101 in the selected memory cell structure is turned on, causing the potential at the storage node SN to approach the second voltage V2, i.e., the potential at the storage node SN is low.

[0121] In practical applications, the second voltage V2 and the third voltage V3 may be provided by the same bit line BL, or the third voltage V3 may be provided by another potential control line.

[0122] In some embodiments, reference Figure 2 and Figure 12 In step 12b, performing a read operation on any memory cell structure in the memory array structure may include the following steps:

[0123] A fifth voltage V5 is provided to a second word line RWL, and a fourth voltage V4 is provided to the fourth electrode 152 in the selected memory cell structure. The current in the second transistor 102 is detected through the third electrode 142 to determine the potential stored at the storage node SN, so as to perform a read operation on the storage node SN.

[0124] In some embodiments, during a read operation on a selected memory cell structure, no voltage signal is provided to all first word lines WWL, no voltage is provided to the remaining second word lines RWL, and no voltage is provided to all bit lines BL.

[0125] It can be understood that after the fifth voltage V5 is provided to the second gate 122 in the selected memory cell structure, when the potential at the storage node SN is a high level, the threshold voltage of the second transistor 102 in the selected memory cell structure is low, so that the conduction degree of the second transistor 102 is relatively high. In this way, the current in the second transistor 102 detected by the third electrode 142 in the selected memory cell structure is relatively large, and the data stored at the storage node SN is determined to be 1 based on the larger current value read; when the potential at the storage node SN is a low level, the threshold voltage of the second transistor 102 in the selected memory cell structure is relatively high, so that the conduction degree of the second transistor 102 is relatively small, or the second transistor 102 will not be turned on. In this way, the current in the second transistor 102 detected by the third electrode 142 in the selected memory cell structure is relatively small, or there is no current, and the data stored at the storage node SN is determined to be 0 based on the smaller current value read.

[0126] In some embodiments, the level of the fifth voltage V5 is adjusted according to the usage time of the memory cell structure.

[0127] It can be understood that the threshold voltage of the second transistor 102 will also be affected by the usage time. By adjusting the potential at the third gate 132, that is, adjusting the level value of the fifth voltage V5, the threshold voltage of the second transistor 102 at this time is guaranteed to be consistent with the threshold voltage of the second transistor 102 that is not affected by the usage time when the potential at the storage node SN remains unchanged, so as to avoid the deviation between the writing and reading of data, so as to ensure the normal operation of the storage cell structure. In this way, by designing the second transistor 102 as a dual-gate transistor, it is beneficial to more flexibly control the storage cell structure through the third gate 132, so as to improve the service life of the storage cell structure.

[0128] It should be noted that in the above description of high level and low level, the high level can be a level value greater than or equal to the power supply voltage, and the low level can be a level value less than or equal to the ground voltage. Moreover, the high level and the low level are relative, and the specific level value ranges included in the high level and the low level can be determined according to the specific device. For example, for an NMOS transistor, the high level refers to the level value range of the gate voltage that can turn on the NMOS transistor, and the low level refers to the level value range of the gate voltage that can turn off the NMOS transistor; for a PMOS transistor, the low level refers to the level value range of the gate voltage that can turn on the PMOS transistor, and the high level refers to the level value range of the gate voltage that can turn off the PMOS transistor. In addition, the high level can be the data 1 in the above description, and the low level can be the data 0 in the above description.

[0129] In summary, the second transistor 102 is a dual-gate transistor, which facilitates utilizing the two gates of the second transistor 102 to separately perform data storage and read / write operation control. Based on the advantages of gate-controlled read / write operations, the read / write operations of the constructed 2TOC type memory cell structure are more flexible. In addition, by adjusting the potential at the third gate 132, the threshold voltage of the second transistor 102 remains unchanged when the potential at the storage node SN remains unchanged, thereby avoiding deviations between data writing and reading, achieving more flexible control of the memory cell structure, and improving the service life of the memory cell structure.

[0130] Yet another embodiment of the present disclosure provides a method for manufacturing a memory array structure, which is used to prepare the memory array structure provided by an embodiment of the present disclosure. Figures 13 to 20 This is a schematic diagram of the cross-sectional structures corresponding to each step in the manufacturing method of the storage cell structure provided in another embodiment of the present disclosure. The manufacturing method of the semiconductor structure provided in this embodiment will be described in detail in conjunction with the accompanying drawings. The parts that are the same or corresponding to the above embodiments will not be described in detail below.

[0131] It should be noted that Figures 13 to 20 To form Figure 2 The memory array structure shown is an example. In actual applications, the method and method for forming various memory array structures provided by an embodiment of the present disclosure are as follows: Figures 13 to 20 The manufacturing steps shown are similar and can be flexibly adjusted according to existing manufacturing process technology.

[0132] refer to Figure 13 , providing a substrate 100, forming a first isolation layer 104 and an initial bit line 133 on the surface of the substrate 100, wherein a plurality of initial bit lines are arranged at intervals along a first direction X, and the first isolation layer 104 is located in the intervals between adjacent initial bit lines 133.

[0133] Continue to refer Figure 13 The first isolation layer 104 has a first trench 124 . It is understandable that the first trench 124 is subsequently used to form a gap in the first isolation layer 104 .

[0134] refer to Figure 14 An initial second isolation layer 145 is formed on a top surface of the first isolation layer 104 and the initial bit line 133 away from the substrate 100 to form a gap 114 in the first isolation layer 104 .

[0135] In some embodiments, continue to refer to Figure 14Along the direction Z, the initial second isolation layer 145 includes an initial first sub-isolation layer 155, an initial second sub-isolation layer 165, and an initial third sub-isolation layer 175 stacked in sequence. In one example, the material of the initial first sub-isolation layer 155 and the material of the initial third sub-isolation layer 175 may include silicon oxide, and the material of the initial second sub-isolation layer 165 may include silicon nitride.

[0136] Continue to refer Figure 14 , forming an initial second electrode 123 , the initial second electrode 123 is located on the top surface of the initial second isolation layer 145 away from the substrate 100 .

[0137] Combined with reference Figure 14 and Figure 15 The initial second electrode 123, the initial second isolation layer 145 and the initial bit line 133 are all patterned to form a first through hole 109, and the remaining initial second isolation layer 145 serves as the second isolation layer 105, and the remaining initial bit line 133 serves as the bit line BL.

[0138] It is understood that a portion of the bit line BL serves as the first electrode 131. It is understood that the orthographic projection of the first through hole 109 on the substrate 100 can be circular, rectangular, or other shapes. In addition, the multi-layer structure of the initial second isolation layer 145 helps prevent the collapse of the remaining initial second isolation layer 145 during the step of forming the first through hole 109, ensuring the accuracy of the formed first through hole 109, thereby improving the yield of the first transistor subsequently formed based on the first through hole.

[0139] In some embodiments, reference Figure 15 The first through hole 109 penetrates the entire thickness of the initial second electrode 123, the entire thickness of the initial second isolation layer 145, and a portion of the thickness of the initial bit line 133 along the direction Z. In practical applications, the first through hole may only penetrate the entire thickness of the initial second electrode and the entire thickness of the initial first isolation layer along the direction Z, exposing the top surface of the initial bit line away from the substrate, that is, the entire initial bit line serves as a bit line.

[0140] Combined with reference Figure 15 and Figure 16 , an initial first semiconductor layer 143, an initial first gate dielectric layer 153 and an initial first gate electrode 163 are formed in sequence to conformally cover the first through hole 109, and the initial first semiconductor layer 143, the initial first gate dielectric layer 153 and the initial first gate electrode 163 together fill the first through hole 109, and the initial first semiconductor layer 143, the initial first gate dielectric layer 153 and the initial first gate electrode 163 all cover the top surface of the initial second electrode 123 away from the substrate 100 in sequence.

[0141] Combined with reference Figure 16 and Figure 17The initial first semiconductor layer 143, the initial first gate dielectric layer 153 and the initial first gate electrode 163 are patterned to form a plurality of first semiconductor layers 111, first gate dielectric layers 151 and first gate electrodes 121 spaced apart along the first direction X.

[0142] Continue to combine references Figure 16 and Figure 17 The initial second electrode 123 is patterned again to remove a portion of the initial second electrode 123 located on the surface of the second isolation layer 105, thereby forming a plurality of second electrodes 141 spaced apart along the first direction X. It is understood that the second electrodes 141 correspond one-to-one to the first semiconductor layers 111, and a first electrode 131, a first semiconductor layer 111, a first gate dielectric layer 151, a first gate electrode 121, and a second electrode 141 constitute a first transistor 101.

[0143] Combined with reference Figure 17 and Figure 18 , forming an initial fourth sub-isolation layer (not shown) covering the top surface of the substrate 100 and formed by the first transistor 101 and the second isolation layer 105, and patterning the initial fourth sub-isolation layer to form a second through hole 119 exposing a portion of the second electrode 141, and the remaining initial fourth sub-isolation layer serves as the fourth sub-isolation layer. It can be understood that in the step of patterning the initial fourth sub-isolation layer, the second electrode 141 can also be patterned, that is, along the direction Z, the second through hole 119 not only penetrates a portion of the thickness of the initial fourth sub-isolation layer, but also penetrates a portion of the thickness of the second electrode 141, which is conducive to increasing the contact area between the conductive structure subsequently formed in the second through hole 119 and the second electrode 141, so as to reduce the contact resistance between the two. In actual applications, the second through hole 119 can also only penetrate a portion of the thickness of the initial fourth sub-isolation layer, and the second electrode 141 is not etched.

[0144] Combined with reference Figure 18 and Figure 19 , forming a second gate 122, the second gate 122 fills the second through hole 119, and the second gate 122 is also located on the top surface of the fourth sub-isolation layer 116 away from the substrate 100, and the second gate 122 corresponds to the second through hole 119 one by one.

[0145] Continue to refer Figure 19 , forming a fifth sub-isolating layer 126 covering the top surface of the substrate 100 which is formed by the second gate 122 and the fourth sub-isolating layer 116 .

[0146] Continue to refer Figure 19A second semiconductor layer 112, a third electrode 142, and a fourth electrode 152 that are in contact with the second semiconductor layer 112 are formed on the top surface of the fifth sub-isolating layer 126 away from the substrate 100. The second semiconductor layer 112 is directly opposite the second gate electrode 122, that is, the orthographic projection of the second semiconductor layer 112 on the substrate 100 is located within the orthographic projection of the second gate electrode 122 on the substrate 100.

[0147] In some embodiments, the material of the third electrode 142 and the material of the fourth electrode 152 are the same, and the third electrode 142 and the fourth electrode 152 can be formed in the same step.

[0148] It should be noted that the manufacturing method provided in another embodiment of the present disclosure does not limit the order of forming the second semiconductor layer 112 , the third electrode 142 and the fourth electrode 152 .

[0149] Combined with reference Figure 19 and Figure 20 , forming a sixth sub-isolating layer 136. The sixth sub-isolating layer 136 completely fills the space between the adjacent third electrodes 142 and fourth electrodes 152, and completely fills the space between the adjacent second semiconductor layers 112. The fourth sub-isolating layer 116, the fifth sub-isolating layer 126, and the sixth sub-isolating layer 136 together constitute the third isolation layer 106.

[0150] Continue to refer Figure 20 A third gate 132 is formed on the top surface of the sixth sub-isolation layer 136, away from the substrate 100. The third gate 132 is directly opposite the second semiconductor layer 112. That is, the orthographic projection of the second semiconductor layer 112 on the substrate 100 is located within the orthographic projection of the third gate 132 on the substrate 100. The second gate 122, the third electrode 142, the second semiconductor layer 112, the fourth electrode 152, and the third gate 132 collectively constitute the second transistor 102.

[0151] In summary, the manufacturing method of the storage array structure provided in another embodiment of the present disclosure is conducive to forming the second transistor 102 as a dual-gate transistor, that is, the threshold voltage of the second transistor 102 is jointly controlled by the second gate 122 and the third gate 132, which is conducive to flexible control of the conduction or shutdown of the second transistor 102 to improve the electrical performance of the storage array structure; on the other hand, the formed storage cell structure does not require a capacitor device, which is conducive to reducing the size of the storage cell structure itself, thereby improving the integration density of the storage cell structure, and improving the storage density of the storage array structure.

[0152] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage array structure, characterized in that: include: substrate; a plurality of first transistors and a plurality of second transistors located on the surface of the substrate, wherein the plurality of first transistors are arranged in a square pattern, the plurality of second transistors are closely packed in a hexagonal pattern, the second transistors and two adjacent first transistors are connected to form a triangle, and the first transistors and the second transistors constitute a memory cell structure; The first transistor includes a first semiconductor layer, a first gate, and a first electrode and a second electrode electrically connected to different regions of the first semiconductor layer, the first electrode is located on the surface of the substrate, the second electrode is located on a side of the first electrode away from the substrate, and the first gate, the first electrode, and the second electrode are insulated from each other, and adjacent second electrodes are insulated from each other; The second transistor includes a second semiconductor layer, a second gate and a third gate located on opposite sides of the second semiconductor layer, and a third electrode and a fourth electrode electrically connected to different regions of the second semiconductor layer. The second gate, the third gate, the third electrode and the fourth electrode are insulated from each other in pairs, and the second electrode is also electrically connected to the second gate.

2. The storage array structure according to claim 1, wherein: The plurality of first transistors are arranged at intervals along a first direction and a second direction, the first direction and the second direction are both parallel to the surface of the substrate, and the first direction and the second direction intersect; The storage array structure further includes: a first word line extending along the first direction, the first word line being in electrical contact with a plurality of first gates spaced apart and arranged along the first direction, and the first word line being insulated from the second gates; A bit line extending along the second direction includes a plurality of first electrodes arranged at intervals along the second direction.

3. The storage array structure according to claim 2, wherein: Also includes: The first isolation layer is located between the bit lines adjacent to each other along the first direction. The first isolation layer has a gap therein. The gap penetrates the first isolation layer along a direction perpendicular to the surface of the substrate.

4. The storage array structure according to claim 3, wherein: Also includes: The second isolation layer is located between the first isolation layer and the second electrode, between the first electrode and the second electrode, and between adjacent first semiconductor layers. The second isolation layer has a stacked structure.

5. The storage array structure according to claim 4, wherein: Along a direction perpendicular to the surface of the substrate, the second isolation layer includes a first sub-isolation layer, a second sub-isolation layer and a third sub-isolation layer stacked in sequence, wherein the material of the first sub-isolation layer and the material of the third sub-isolation layer both include silicon nitride, and the material of the second sub-isolation layer includes silicon oxide.

6. The storage array structure according to claim 1, wherein: The first semiconductor layer encloses a first chamber, wherein the first chamber is a chamber having a first opening, or the first chamber is a chamber having two first openings arranged opposite to each other; The first semiconductor layer has a first inner side and a first outer side opposite to each other, and the first gate is directly opposite to a portion of the first inner side; The first transistor further includes a first gate dielectric layer located between the first gate and the first semiconductor layer.

7. The storage array structure according to claim 6, wherein: Along a direction perpendicular to the surface of the substrate, the first semiconductor layer includes a first portion, a second portion and a third portion; The second electrode is located on at least a portion of the first outer side of the third portion; In a direction perpendicular to the surface of the substrate, the first electrode surrounds at least a portion of the first outer side of the first portion, and / or the first electrode is in contact with and connected to a first bottom surface of the first semiconductor layer close to the substrate.

8. The storage array structure according to claim 2, wherein: The second semiconductor layer has a first surface and a second surface opposite to each other along a direction perpendicular to the surface of the substrate, and has a third surface and a fourth surface opposite to each other along the first direction; The second gate is directly opposite to the first surface, the third gate is directly opposite to the second surface, the third electrode is in contact with the third surface, and the fourth electrode is in contact with the fourth surface; The storage array structure further includes: The third isolation layer is located between the second gate and the first surface, between the third gate and the second surface, and between adjacent second transistors.

9. The storage array structure according to claim 1, wherein: The second semiconductor layer encloses a second chamber, and the second chamber is a chamber having a second opening, or the second chamber is a chamber having two second openings arranged opposite to each other; The second semiconductor layer has a second inner side and a second outer side opposite to each other, the third gate is opposite to at least a portion of the second inner side, and the second gate is opposite to at least a portion of the second outer side; The second transistor further includes: a second gate dielectric layer located between the second gate and the second semiconductor layer; The third gate dielectric layer is located between the third gate and the second semiconductor layer.

10. The storage array structure according to any one of claims 1 to 9, wherein: The potential at the third gate is adjusted according to the usage time of the memory cell structure.

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