A FLASH control circuit based on 8051 core

Abstract

The invention relates to the field of FLASH control technology, and discloses a FLASH control circuit based on an 8051 core, comprising a D flip-flop DFF1, an XOR gate XOR1, a jump instruction pulse generating unit, a jump instruction pulse controlling unit, an AND gate AND1 and an OR gate OR1. In actual use, the invention generates a low-level filtering signal pause_1 by judging whether the instruction executed by the 8051 core is a jump instruction, and when the currently executed instruction is a jump instruction, the filtering signal pause_1 is processed with a signal output from a Q output terminal of the D flip-flop DFF1, thereby changing the waveform of the address latch signal outputted last, so that the 8051 core avoids invalid reading when executing the jump instruction, thereby reducing power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of FLASH control, and in particular to a FLASH control circuit based on an 8051 core. Background Art

[0002] With the rapid development of electronic technology and the continuous expansion of the consumer electronics market, the performance requirements for 8-bit MCUs are getting higher and higher. The main frequencies of the commonly used 8-bit MCUs (Micro Control Units) are generally 16MHz and 24MHz, and the main frequency of the MCU is mainly limited by the reading speed of FLASH (flash memory), among which the commonly used main frequencies of FLASH are 25MHz and 32MHz. In actual use, no matter what the frequency of FLASH and MCU is, the design of the FLASH control circuit is particularly critical.

[0003] For the FLASH control circuit, the design of the address latch signal AE is critical. The address latch signal AE needs to meet the FLASH read setup time, that is, the address latch signal AE cannot be established too early, and secondly, it must exist at the time of FLASH reading. Based on the above two considerations, a pulse signal generated based on address changes is currently commonly used as the address latch signal AE. The structure for generating the address latch signal AE is as follows: Figure 1 and Figure 2 shown.

[0004] exist Figure 1 The entire address latch signal AE generation circuit includes the 8051 CPU core, FLASH control circuit, 64KB FLASH and data selection circuit, among which memaddr[15:0] is the address bus; memdatai[7:0] is the data bus; fae is the FLASH address latch signal; faddr[13:0] is the FLASH address signal. Figure 2 In the example, addr_pulse is the pulse signal generated by the address change; fcpu is the system clock; rst is the system reset. Figure 2 The timing diagram of the actual use of the circuit shown is as follows Figure 3 shown.

[0005] Combination Figure 3 ,right Figure 2 The circuit shown is analyzed. Figure 2 The essence of the circuit shown is to synchronize the address bus by one beat at the falling edge of the system clock and then perform XOR logic to obtain a pulse signal, which serves as the address latch signal AE of the FLASH.

[0006] for Figure 1 and Figure 2In the structure shown, when the system executes a jump instruction such as a JNB instruction, the instruction opcode is 30, and an invalid read occurs. Although it has no effect on the system's functionality, it will cause unnecessary FLASH read power consumption.

[0007] This invalid read situation does not necessarily occur during the execution of the instruction, but is related to the lower two bits of the address bus and the number of bytes of the current instruction. For the JNB instruction, which is a 3-byte instruction, when the lower two bits of the address bus are 2'b01, where 2'b01 represents two binary data of 01, an invalid read situation will occur. For a single-byte jump instruction, an invalid read situation will also occur when the lower two bits of the address bus are 2'b11. For a 2-byte jump instruction, an invalid read situation will also occur when the lower two bits of the address bus are 2'b01. Summary of the invention

[0008] In view of the shortcomings of the background technology, the present invention provides a FLASH control circuit based on the 8051 core. The technical problem to be solved is how to eliminate the invalid FLASH reading caused by the jump instructions of different bytes of the 8051 core when the address bus changes, and reduce the FLASH reading power consumption.

[0009] To solve the above technical problems, the present invention provides the following technical solutions: a FLASH control circuit based on an 8051 core, comprising a D flip-flop DFF1 and an XOR gate XOR1; the D input terminal of the D flip-flop DFF1 is electrically connected to the address bus of the 8051 core, the clock input terminal of the D flip-flop is used to input a system clock signal, and the clear terminal of the D flip-flop is used to input a system reset signal; the two input terminals of the XOR gate XOR1 are electrically connected to the Q output terminal of the D flip-flop DFF1 and the D input terminal of the D flip-flop DFF1 respectively; and further comprising:

[0010] A jump instruction pulse generating unit, a jump instruction pulse controlling unit, an AND gate AND1 and an OR gate OR1;

[0011] The jump instruction pulse generating unit is electrically connected to the 8051 core, and is used to generate a status flag signal jmp_ins when the instruction currently executed by the 8051 core is a jump instruction, and to generate a pulse signal fetch_ael in the last cycle of the jump instruction;

[0012] The jump instruction pulse control unit is electrically connected to the jump instruction pulse generating unit and the 8051 core respectively, and determines whether the instruction currently executed by the 8051 core is a jump instruction based on the status flag signal jmp_ins, and outputs a low-level filtering signal pause_1 of one cycle when the instruction currently executed by the 8051 core is a jump instruction;

[0013] The pulse signal addr_pulse and the filter signal pause_1 outputted from the output end of the XOR gate XOR1 are respectively inputted into the two input ends of the AND gate AND1, the pulse signal fetch_ael and the signal outputted from the AND gate AND1 are respectively inputted into the two input ends of the OR gate OR1, and the output end of the OR gate OR1 is used to output the address latch signal of the FLASH.

[0014] In a certain embodiment, the jump instruction pulse generating unit includes a driving unit and five pulse generating branches, each pulse generating branch includes a NOR gate NOR10, an AND gate AND10-AND gate AND14, a D flip-flop DFF10, a D flip-flop DFF11, a selector MUX1, a selector MUX2 and a logic control unit;

[0015] The first bit of the address bus is input to one input end of the NOR gate NOR10, the second bit of the address bus is input to the other input end of the NOR gate NOR10 after inversion processing, the output end of the NOR gate NOR10 is electrically connected to one input end of the AND gate AND10, the other input end of the AND gate AND10 is used to input a control signal codefetch, the control signal codefetch is generated by the 8051 core, the output end of the AND gate AND10 is electrically connected to one input end of the AND gate AND11;

[0016] The logic control unit is used to determine whether the content of the input data bus is a jump instruction, and input a high-level determination signal to the other input end of the AND gate AND11 when the content of the input data bus is a jump instruction, and vice versa, input a low-level determination signal to the other input end of the AND gate AND11; the output end of the AND gate AND11 is electrically connected to an input end of the AND gate AND12;

[0017] The two input terminals of the selector MUX1 are respectively used to input a low-level signal and a high-level signal, and the output signal of the selector MUX1 is input to the other input terminal of the AND gate AND12 after being inverted; the output terminal of the AND gate AND12 is electrically connected to the D input terminal of the D flip-flop DFF10, the clock input terminal of the D flip-flop DFF10 is used to input the system clock signal, and the Q output terminal of the D flip-flop DFF10 is electrically connected to an input terminal of the AND gate AND13;

[0018] The two input terminals of the selector MUX2 are respectively used to input a low-level signal and a high-level signal, the output terminal of the selector MUX2 is electrically connected to the other input terminal of the AND gate AND13, the output terminal of the AND gate AND13 is electrically connected to the D input terminal of the D flip-flop DFF11, the Q output terminal of the D flip-flop DFF11 is electrically connected to an input terminal of the AND gate AND14, and the other input terminal of the AND gate AND14 and the clock input terminal of the D flip-flop DFF11 are respectively used to input the system clock signal;

[0019] The driving unit controls the conduction of channels of the selector MUX1 and the selector MUX2 based on the content of the instruction cycle counter of the 8051 core.

[0020] In a certain embodiment, the five pulse generating branches are respectively the first pulse generating branch to the fifth pulse generating branch; the Q output ends of the D flip-flops DFF10 of the first pulse generating branch to the third pulse generating branch are electrically connected to each other for outputting the state flag signal jmp_ins1; the Q output end of the D flip-flop DFF10 of the fourth pulse generating branch is electrically connected to the Q output end of the D flip-flop DFF10 of the fifth pulse generating branch for outputting the state flag signal jmp_ins2;

[0021] The driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the first pulse generating branch as follows:

[0022] The driving unit drives the selector MUX1 of the first pulse generating branch to output a high level signal when the content of the instruction cycle counter is three, and drives the selector MUX1 of the first pulse generating branch to output a low level signal otherwise;

[0023] The driving unit drives the selector MUX2 of the first pulse generating branch to output a high level signal when the content of the instruction cycle counter is two, and otherwise drives the selector MUX2 of the first pulse generating branch to output a low level signal.

[0024] In a certain embodiment, the driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the second pulse generating branch as follows:

[0025] The driving unit drives the selector MUX1 of the second pulse generating branch to output a high level signal when the content of the instruction cycle counter is five, and drives the selector MUX1 of the second pulse generating branch to output a low level signal otherwise;

[0026] The driving unit drives the selector MUX2 of the second pulse generating branch to output a high level signal when the content of the instruction cycle counter is four, and otherwise drives the selector MUX2 of the second pulse generating branch to output a low level signal.

[0027] In a certain embodiment, the driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the third pulse generating branch as follows:

[0028] The driving unit drives the selector MUX1 of the third pulse generating branch to output a high level signal when the content of the instruction cycle counter is six, and drives the selector MUX1 of the third pulse generating branch to output a low level signal otherwise;

[0029] The driving unit drives the selector MUX2 of the third pulse generating branch to output a high level signal when the content of the instruction cycle counter is five, and otherwise drives the selector MUX2 of the third pulse generating branch to output a low level signal.

[0030] In a certain embodiment, the driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the fourth pulse generating branch as follows:

[0031] The driving unit drives the selector MUX1 of the fourth pulse generating branch to output a high level signal when the content of the instruction cycle counter is four, and drives the selector MUX1 of the fourth pulse generating branch to output a low level signal otherwise;

[0032] The driving unit drives the selector MUX2 of the fourth pulse generating branch to output a high level signal when the content of the instruction cycle counter is three, and otherwise drives the selector MUX2 of the fourth pulse generating branch to output a low level signal.

[0033] In a certain embodiment, the driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the fifth pulse generating branch as follows:

[0034] The driving unit drives the selector MUX1 of the fifth pulse generating branch to output a high level signal when the content of the instruction cycle counter is six, and drives the selector MUX1 of the fifth pulse generating branch to output a low level signal otherwise;

[0035] The driving unit drives the selector MUX2 of the fifth pulse generating branch to output a high level signal when the content of the instruction cycle counter is five, and otherwise drives the selector MUX2 of the fifth pulse generating branch to output a low level signal.

[0036] In a certain embodiment, the jump instruction pulse control unit includes a single-byte logic processing unit, a double-byte logic processing unit, a three-byte logic processing unit, an AND gate AND20, an AND gate AND21, a NAND gate NAND20, a NAND gate NAND21, a NAND gate NAND22, a selector MUX3, a selector MUX4, a D flip-flop DFF20, and a second driving unit;

[0037] The single-byte logic processing unit determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input data bus content and the control signal codefetch, and inputs a high-level signal to an input end of the NAND gate NAND20 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to an input end of the NAND gate NAND20; the AND gate AND20 is used to perform AND processing on the first bit data and the second bit data of the address bus, and the output end of the AND gate AND20 is electrically connected to the other input end of the NAND gate NAND20;

[0038] The double-byte logic processing unit determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input system instruction content and the status flag signal jmp_ins1, and inputs a high-level signal to one input end of the NAND gate NAND21 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to one input end of the NAND gate NAND21; the two input ends of the selector MUX3 input a high-level signal and a low-level signal respectively, and the output end of the selector MUX3 is electrically connected to the other input end of the NAND gate NAND21;

[0039] The three-byte logic processing unit determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input system instruction content and the status flag signal jmp_ins2, and inputs a high-level signal to one input end of the NAND gate NAND22 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to one input end of the NAND gate NAND22; the two input ends of the selector MUX4 input a high-level signal and a low-level signal respectively, and the output end of the selector MUX4 is electrically connected to the other input end of the NAND gate NAND21;

[0040] The output end of the NAND gate NAND20, the output end of the NAND gate NAND21 and the output end of the NAND gate NAND22 are electrically connected to the three input ends of the AND gate AND21, the output end of the AND gate AND21 is electrically connected to the D input end of the D flip-flop DFF20, the clock input end of the D flip-flop DFF20 is used to input the system clock signal, and the Q output end of the D flip-flop DFF20 is used to output the filter signal pause_1;

[0041] The second driving unit and the content of the instruction cycle counter based on the 8051 core control the channels of the selectors MUX3 and MUX4 to be turned on.

[0042] In a certain implementation manner, the second driving unit and the content of the instruction cycle counter based on the 8051 core control the channel conduction of the selector MUX3 and the selector MUX4 as follows:

[0043] The second driving unit controls the selector MUX3 to output a high level signal when the content of the instruction cycle counter is one or two, and otherwise controls the selector MUX3 to output a low level signal;

[0044] The second driving unit controls the selector MUX4 to output a high level signal when the content of the instruction cycle counter is one, two or three, and otherwise controls the selector MUX4 to output a low level signal.

[0045] In a certain embodiment, the single-byte logic processing unit performs OR processing on the data bus content when the control signal codefetch is at a high level to determine whether the instruction currently executed by the 8051 core is an adjustment instruction;

[0046] The double-byte logic processing unit performs OR processing on the system instruction content when the status flag signal jmp_ins1 is at a high level, and determines whether the instruction currently executed by the 8051 core is an adjustment instruction;

[0047] The three-byte logic processing unit performs OR processing on the system instruction content when the status flag signal jmp_ins2 is at a high level, and determines whether the instruction currently executed by the 8051 core is an adjustment instruction.

[0048] Compared with the prior art, the present invention has the following beneficial effects: the present invention determines whether the instruction executed by the 8051 core is a jump instruction, and generates a low-level filter signal pause_1 when the currently executed instruction is a jump instruction. The filter signal pause_1 and the signal output from the Q output end of the D flip-flop DFF1 are processed, thereby changing the waveform of the address latch signal outputted last, so that the 8051 core avoids invalid reading when executing the jump instruction, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of the structure of the existing address latch signal AE for generating FLASH;

[0050] Figure 2 for Figure 1 A schematic diagram of the structure of the pulse generating circuit in FIG.

[0051] Figure 3 for Figure 2Timing diagram of the circuit;

[0052] Figure 4 It is a schematic diagram of the structure of the present invention in the embodiment;

[0053] Figure 5 A circuit diagram of a pulse generating branch in an embodiment;

[0054] Figure 6 for Figure 5 Waveform diagram when in use;

[0055] Figure 7 Schematic diagram of the structure of the jump instruction pulse control unit in the embodiment;

[0056] Figure 8 for Figure 7 Waveform diagram when the circuit is in use. DETAILED DESCRIPTION

[0057] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0058] For the existing 8051 core, the single-byte jump instructions are: JMP_A_DPTR, RET and RETI; the double-byte jump instructions are: JNZ, JZ, JNC, JC, AJMP, SJMP, ACALL and DJNZ; the three-byte jump instructions are: JNB, JB, JBC, LCALL, DJNZ_ADDR, LJMP and CJNE. In actual use, each jump instruction will cause invalid reading of FLASH under certain conditions, thereby increasing power consumption.

[0059] In order to avoid invalid reads caused by the 8051 core when executing jump instructions, such as Figure 4 As shown, this embodiment provides a FLASH control circuit based on the 8051 core, including a D flip-flop DFF1 and an XOR gate XOR1; the D input terminal of the D flip-flop DFF1 is electrically connected to the address bus memaddr[15:0] of the 8051 core, the clock input terminal of the D flip-flop is used to input the system clock signal fcpu of the 8051 core, and the clear terminal of the D flip-flop DFF1 is used to input the system reset signal rst of the 8051 core; the two input terminals of the XOR gate XOR1 are electrically connected to the Q output terminal of the D flip-flop DFF1 and the D input terminal of the D flip-flop DFF1 respectively; and further includes:

[0060] Jump instruction pulse generating unit 1, jump instruction pulse controlling unit 2, AND gate AND1 and OR gate OR1;

[0061] The jump instruction pulse generating unit 1 is electrically connected to the 8051 core, and is used to generate a status flag signal jmp_ins when the instruction currently executed by the 8051 core is a jump instruction, and to generate a pulse signal fetch_ael in the last cycle of the jump instruction;

[0062] The jump instruction pulse control unit 2 is electrically connected to the jump instruction pulse generating unit 1 and the 8051 core respectively, and determines whether the instruction currently executed by the 8051 core is a jump instruction based on the state flag signal jmp_ins, and outputs a low-level filtering signal pause_1 of one cycle when the instruction currently executed by the 8051 core is a jump instruction; wherein the cycle is one cycle of the pulse signal addr_pulse output by the XOR gate XOR1;

[0063] The pulse signal addr_pulse and the filter signal pause_1 outputted from the output end of the XOR gate XOR1 are respectively inputted into the two input ends of the AND gate AND1, the pulse signal fetch_ael and the signal outputted from the AND gate AND1 are respectively inputted into the two input ends of the OR gate OR1, and the output end of the OR gate OR1 is used to output the address latch signal of the FLASH.

[0064] In actual use, the present invention determines whether the instruction executed by the 8051 core is a jump instruction, and generates a low-level filter signal pause_1 when the currently executed instruction is a jump instruction. The filter signal pause_1 and the signal output from the Q output end of the D flip-flop DFF1 are processed, thereby changing the waveform of the address latch signal output last, so that the 8051 core avoids invalid reading when executing the jump instruction, thereby reducing power consumption.

[0065] Specifically, in this embodiment, the jump instruction pulse generating unit includes a driving unit and five pulse generating branches, such as Figure 5 As shown, each pulse generating branch includes a NOR gate NOR10, an AND gate AND10-AND gate AND14, a D flip-flop DFF10, a D flip-flop DFF11, a selector MUX1, a selector MUX2 and a logic control unit 10;

[0066] The first bit data memaddr[0] of the address bus is input to one input end of the NOR gate NOR10, and the second bit data memaddr[1] of the address bus is input to the other input end of the NOR gate NOR10 after inversion processing. The output end of the NOR gate NOR10 is electrically connected to one input end of the AND gate AND10. The other input end of the AND gate AND10 is used to input a control signal codefetch. The control signal codefetch is generated by the 8051 core. The output end of the AND gate AND10 is electrically connected to one input end of the AND gate AND11.

[0067] The logic control unit 10 is used to determine whether the content of the input data bus memdatai[7:0] is a jump instruction, and input a high-level determination signal to the other input terminal of the AND gate AND11 when the content of the input data bus memdatai[7:0] is a jump instruction, otherwise, input a low-level determination signal to the other input terminal of the AND gate AND11; the output terminal of the AND gate AND11 is electrically connected to an input terminal of the AND gate AND12;

[0068] The two input terminals of the selector MUX1 are respectively used to input a low-level signal and a high-level signal, and the output signal of the selector MUX1 is input to the other input terminal of the AND gate AND12 after being inverted; the output terminal of the AND gate AND12 is electrically connected to the D input terminal of the D flip-flop DFF10, the clock input terminal of the D flip-flop DFF10 is used to input the system clock signal fcpu, and the Q output terminal of the D flip-flop DFF10 is electrically connected to an input terminal of the AND gate AND13;

[0069] The two input terminals of the selector MUX2 are respectively used to input a low level signal and a high level signal, the output terminal of the selector MUX2 is electrically connected to the other input terminal of the AND gate AND13, the output terminal of the AND gate AND13 is electrically connected to the D input terminal of the D flip-flop DFF11, the Q output terminal of the D flip-flop DFF11 is electrically connected to an input terminal of the AND gate AND14, and the other input terminal of the AND gate AND14 and the clock input terminal of the D flip-flop DFF11 are respectively used to input a system clock signal fcpu;

[0070] The driving unit controls the channel conduction of the selector MUX1 and the selector MUX2 based on the content of the instruction cycle counter cycle[3:0] of the 8051 core.

[0071] Specifically, in this embodiment, the five pulse generating branches are respectively the first pulse generating branch to the fifth pulse generating branch; the Q output ends of the D flip-flops DFF10 of the first pulse generating branch to the third pulse generating branch are electrically connected to each other, and are used to output the state flag signal jmp_ins1; the Q output end of the D flip-flop DFF10 of the fourth pulse generating branch is electrically connected to the Q output end of the D flip-flop DFF10 of the fifth pulse generating branch, and are used to output the state flag signal jmp_ins2;

[0072] The driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the first pulse generating branch as follows:

[0073] The driving unit drives the selector MUX1 of the first pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is three, otherwise, the driving unit drives the selector MUX1 of the first pulse generating branch to output a low level signal;

[0074] The driving unit drives the selector MUX2 of the first pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is 2, and otherwise drives the selector MUX2 of the first pulse generating branch to output a low level signal.

[0075] In actual use, the first pulse generation branch is used to judge and process the two-byte and three-cycle jump instructions, where Figure 5 This is a schematic diagram for judging and processing two-byte and three-cycle jump instructions. Figure 5 The actual waveform used in the circuit is as follows Figure 6 shown.

[0076] Specifically, in this embodiment, the driving unit controls the conduction of the channels of the selector MUX1 and the selector MUX2 of the second pulse generating branch as follows:

[0077] The driving unit drives the selector MUX1 of the second pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is five, otherwise, the driving unit drives the selector MUX1 of the second pulse generating branch to output a low level signal;

[0078] The driving unit drives the selector MUX2 of the second pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is four, and otherwise drives the selector MUX2 of the second pulse generating branch to output a low level signal.

[0079] In actual use, the second pulse generation branch is used to judge and process the two-byte and five-cycle jump instructions.

[0080] Specifically, in this embodiment, the driving unit controls the conduction of the channels of the selector MUX1 and the selector MUX2 of the third pulse generating branch as follows:

[0081] The driving unit drives the selector MUX1 of the third pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is six, otherwise, the driving unit drives the selector MUX1 of the third pulse generating branch to output a low level signal;

[0082] The driving unit drives the selector MUX2 of the third pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is five, and otherwise drives the selector MUX2 of the third pulse generating branch to output a low level signal.

[0083] In actual use, the third pulse generation branch is used to judge and process the two-byte and six-cycle jump instructions.

[0084] Specifically, in this embodiment, the driving unit controls the conduction of the channels of the selector MUX1 and the selector MUX2 of the fourth pulse generating branch as follows:

[0085] The driving unit drives the selector MUX1 of the fourth pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is four, and drives the selector MUX1 of the fourth pulse generating branch to output a low level signal otherwise;

[0086] The driving unit drives the selector MUX2 of the fourth pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is three, otherwise, the driving unit drives the selector MUX2 of the fourth pulse generating branch to output a low level signal.

[0087] In actual use, the fourth pulse generates a branch in order to judge and process the three-byte and four-cycle jump instructions.

[0088] Specifically, in this embodiment, the driving unit controls the conduction of the channels of the selector MUX1 and the selector MUX2 of the fifth pulse generating branch as follows:

[0089] The driving unit drives the selector MUX1 of the fifth pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is six, otherwise, the driving unit drives the selector MUX1 of the fifth pulse generating branch to output a low level signal;

[0090] The driving unit drives the selector MUX2 of the fifth pulse generating branch to output a high level signal when the content of the instruction cycle counter cycle[3:0] is five, and otherwise drives the selector MUX2 of the fifth pulse generating branch to output a low level signal.

[0091] In actual use, the fifth pulse generates a branch in order to judge and process the three-byte and six-cycle jump instructions.

[0092] In this embodiment, Figure 7 As shown, the jump instruction pulse control unit 2 includes a single-byte logic processing unit 20, a double-byte logic processing unit 21, a three-byte logic processing unit 22, an AND gate AND20, an AND gate AND21, a NAND gate NAND20, a NAND gate NAND21, a NAND gate NAND22, a selector MUX3, a selector MUX4, a D flip-flop DFF20 and a second driving unit;

[0093] The single-byte logic processing unit 20 determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input data bus content memdatai[7:0] and the control signal codefetch, and inputs a high-level signal to one input end of the NAND gate NAND20 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to one input end of the NAND gate NAND20; the AND gate AND20 is used to perform AND processing on the first bit data memaddr[0] and the second bit data memaddr[0] of the address bus, and the output end of the AND gate AND20 is electrically connected to the other input end of the NAND gate NAND20;

[0094] The double-byte logic processing unit 21 determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input system instruction content instr[7:0] and the status flag signal jmp_ins1, and inputs a high-level signal to one input end of the NAND gate NAND21 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to one input end of the NAND gate NAND21, wherein the system instruction content instr[7:0] is provided by the 8051 core; the two input ends of the selector MUX3 respectively input a high-level signal and a low-level signal, and the output end of the selector MUX3 is electrically connected to the other input end of the NAND gate NAND21;

[0095] The three-byte logic processing unit 22 determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input system instruction content instr[7:0] and the status flag signal jmp_ins2, and inputs a high-level signal to one input end of the NAND gate NAND22 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to one input end of the NAND gate NAND22; the two input ends of the selector MUX4 input a high-level signal and a low-level signal respectively, and the output end of the selector MUX4 is electrically connected to the other input end of the NAND gate NAND21;

[0096] The output end of the NAND gate NAND20, the output end of the NAND gate NAND21 and the output end of the NAND gate NAND22 are electrically connected to the three input ends of the AND gate AND21, the output end of the AND gate AND21 is electrically connected to the D input end of the D flip-flop DFF20, the clock input end of the D flip-flop DFF20 is used to input the system clock signal fcpu, and the Q output end of the D flip-flop DFF20 is used to output the filter signal pause_1;

[0097] The second driving unit and the content of the instruction cycle counter cycle[3:0] based on the 8051 core control the channel conduction of the selector MUX3 and the selector MUX4.

[0098] More specifically, the second driving unit and the content of the instruction cycle counter cycle[3:0] based on the 8051 core control the channel conduction of the selector MUX3 and the selector MUX4 as follows:

[0099] The second driving unit controls the selector MUX3 to output a high level signal when the content of the instruction cycle counter cycle[3:0] is one or two, otherwise controls the selector MUX3 to output a low level signal;

[0100] The second driving unit controls the selector MUX4 to output a high level signal when the content of the instruction cycle counter cycle[3:0] is one, two or three, and otherwise controls the selector MUX4 to output a low level signal.

[0101] More specifically, in this embodiment, the single-byte logic processing unit 20 performs OR processing on the data bus content memdatai[7:0] when the control signal codefetch is at a high level to determine whether the instruction currently executed by the 8051 core is an adjustment instruction;

[0102] The double-byte logic processing unit 21 performs OR processing on the system instruction content instr[7:0] when the status flag signal jmp_ins1 is at a high level, and determines whether the instruction currently executed by the 8051 core is an adjustment instruction;

[0103] The three-byte logic processing unit 22 performs OR processing on the system instruction content instr[7:0] when the status flag signal jmp_ins2 is at a high level, and determines whether the instruction currently executed by the 8051 core is an adjustment instruction.

[0104] Take the JNB instruction opcode 30 as an example, it is a 3-byte 4-cycle instruction. The specific timing diagram is as follows Figure 8 As shown, when the instruction is executed, the instruction cycle counter cycle[3:0] will start to increment from 1, and return to the initial value 1 when it reaches 4. The filter signal pause_l will be generated when the cycle is 3 to eliminate the pulse signal addr_pulse output by the XOR gate XOR1. At the same time, for the jump instruction, a pulse signal fetch_ae will be generated at the end of the instruction cycle, that is, in the last instruction cycle, to prepare for the pre-fetch of the next instruction.

[0105] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A FLASH control circuit based on an 8051 core, comprising a D flip-flop DFF1 and an XOR gate XOR1; the D input terminal of the D flip-flop DFF1 is electrically connected to the address bus of the 8051 core, the clock input terminal of the D flip-flop is used to input a system clock signal, and the clear terminal of the D flip-flop is used to input a system reset signal; the two input terminals of the XOR gate XOR1 are electrically connected to the Q output terminal of the D flip-flop DFF1 and the D input terminal of the D flip-flop DFF1 respectively; characterized in that, Also includes: A jump instruction pulse generating unit, a jump instruction pulse controlling unit, an AND gate AND1 and an OR gate OR1; The jump instruction pulse generating unit is electrically connected to the 8051 core, and is used to generate a status flag signal jmp_ins when the instruction currently executed by the 8051 core is a jump instruction, and to generate a pulse signal fetch_ael in the last cycle of the jump instruction; The jump instruction pulse control unit is electrically connected to the jump instruction pulse generating unit and the 8051 core respectively, and determines whether the instruction currently executed by the 8051 core is a jump instruction based on the status flag signal jmp_ins, and outputs a low-level filtering signal pause_1 of one cycle when the instruction currently executed by the 8051 core is a jump instruction; The pulse signal addr_pulse and the filter signal pause_1 outputted from the output end of the XOR gate XOR1 are respectively inputted into the two input ends of the AND gate AND1, the pulse signal fetch_ael and the signal outputted from the AND gate AND1 are respectively inputted into the two input ends of the OR gate OR1, and the output end of the OR gate OR1 is used to output the address latch signal of FLASH; The jump instruction pulse generating unit includes a driving unit and five pulse generating branches, each of which includes a NOR gate NOR10, an AND gate AND10-AND gate AND14, a D flip-flop DFF10, a D flip-flop DFF11, a selector MUX1, a selector MUX2 and a logic control unit; The first bit of the address bus is input to one input end of the NOR gate NOR10, the second bit of the address bus is input to the other input end of the NOR gate NOR10 after inversion processing, the output end of the NOR gate NOR10 is electrically connected to one input end of the AND gate AND10, the other input end of the AND gate AND10 is used to input a control signal codefetch, the control signal codefetch is generated by the 8051 core, the output end of the AND gate AND10 is electrically connected to one input end of the AND gate AND11; The logic control unit is used to determine whether the content of the input data bus is a jump instruction, and input a high-level determination signal to the other input end of the AND gate AND11 when the content of the input data bus is a jump instruction, and vice versa, input a low-level determination signal to the other input end of the AND gate AND11; the output end of the AND gate AND11 is electrically connected to an input end of the AND gate AND12; The two input terminals of the selector MUX1 are respectively used to input a low-level signal and a high-level signal, and the output signal of the selector MUX1 is input to the other input terminal of the AND gate AND12 after being inverted; the output terminal of the AND gate AND12 is electrically connected to the D input terminal of the D flip-flop DFF10, the clock input terminal of the D flip-flop DFF10 is used to input the system clock signal, and the Q output terminal of the D flip-flop DFF10 is electrically connected to an input terminal of the AND gate AND13; The two input terminals of the selector MUX2 are respectively used to input a low-level signal and a high-level signal, the output terminal of the selector MUX2 is electrically connected to the other input terminal of the AND gate AND13, the output terminal of the AND gate AND13 is electrically connected to the D input terminal of the D flip-flop DFF11, the Q output terminal of the D flip-flop DFF11 is electrically connected to an input terminal of the AND gate AND14, and the other input terminal of the AND gate AND14 and the clock input terminal of the D flip-flop DFF11 are respectively used to input the system clock signal; The driving unit controls the conduction of channels of the selector MUX1 and the selector MUX2 based on the content of the instruction cycle counter of the 8051 core.

2. The FLASH control circuit based on 8051 core according to claim 1, characterized in that: The five pulse generating branches are respectively the first pulse generating branch to the fifth pulse generating branch; the Q output ends of the D flip-flops DFF10 of the first pulse generating branch to the third pulse generating branch are electrically connected to each other, and are used to output the state flag signal jmp_ins1; the Q output end of the D flip-flop DFF10 of the fourth pulse generating branch is electrically connected to the Q output end of the D flip-flop DFF10 of the fifth pulse generating branch, and are used to output the state flag signal jmp_ins2; The driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the first pulse generating branch as follows: The driving unit drives the selector MUX1 of the first pulse generating branch to output a high level signal when the content of the instruction cycle counter is three, and drives the selector MUX1 of the first pulse generating branch to output a low level signal otherwise; The driving unit drives the selector MUX2 of the first pulse generating branch to output a high level signal when the content of the instruction cycle counter is two, and otherwise drives the selector MUX2 of the first pulse generating branch to output a low level signal.

3. The FLASH control circuit based on 8051 core according to claim 2, characterized in that: The driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the second pulse generating branch as follows: The driving unit drives the selector MUX1 of the second pulse generating branch to output a high level signal when the content of the instruction cycle counter is five, and drives the selector MUX1 of the second pulse generating branch to output a low level signal otherwise; The driving unit drives the selector MUX2 of the second pulse generating branch to output a high level signal when the content of the instruction cycle counter is four, and otherwise drives the selector MUX2 of the second pulse generating branch to output a low level signal.

4. The FLASH control circuit based on 8051 core according to claim 3, characterized in that: The driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the third pulse generating branch as follows: The driving unit drives the selector MUX1 of the third pulse generating branch to output a high level signal when the content of the instruction cycle counter is six, and drives the selector MUX1 of the third pulse generating branch to output a low level signal otherwise; The driving unit drives the selector MUX2 of the third pulse generating branch to output a high level signal when the content of the instruction cycle counter is five, and otherwise drives the selector MUX2 of the third pulse generating branch to output a low level signal.

5. The FLASH control circuit based on 8051 core according to claim 4, characterized in that: The driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the fourth pulse generating branch as follows: The driving unit drives the selector MUX1 of the fourth pulse generating branch to output a high level signal when the content of the instruction cycle counter is four, and drives the selector MUX1 of the fourth pulse generating branch to output a low level signal otherwise; The driving unit drives the selector MUX2 of the fourth pulse generating branch to output a high level signal when the content of the instruction cycle counter is three, and otherwise drives the selector MUX2 of the fourth pulse generating branch to output a low level signal.

6. The FLASH control circuit based on 8051 core according to claim 5, characterized in that: The driving unit controls the conduction of the channels of the selectors MUX1 and MUX2 of the fifth pulse generating branch as follows: The driving unit drives the selector MUX1 of the fifth pulse generating branch to output a high level signal when the content of the instruction cycle counter is six, and drives the selector MUX1 of the fifth pulse generating branch to output a low level signal otherwise; The driving unit drives the selector MUX2 of the fifth pulse generating branch to output a high level signal when the content of the instruction cycle counter is five, and otherwise drives the selector MUX2 of the fifth pulse generating branch to output a low level signal.

7. The FLASH control circuit based on 8051 core according to claim 6, characterized in that: The jump instruction pulse control unit includes a single-byte logic processing unit, a double-byte logic processing unit, a three-byte logic processing unit, an AND gate AND20, an AND gate AND21, a NAND gate NAND20, a NAND gate NAND21, a NAND gate NAND22, a selector MUX3, a selector MUX4, a D flip-flop DFF20 and a second driving unit; The single-byte logic processing unit determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input data bus content and the control signal codefetch, and inputs a high-level signal to an input end of the NAND gate NAND20 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to an input end of the NAND gate NAND20; the AND gate AND20 is used to perform AND processing on the first bit data and the second bit data of the address bus, and the output end of the AND gate AND20 is electrically connected to the other input end of the NAND gate NAND20; The double-byte logic processing unit determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input system instruction content and the status flag signal jmp_ins1, and inputs a high-level signal to one input end of the NAND gate NAND21 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to one input end of the NAND gate NAND21; the two input ends of the selector MUX3 input a high-level signal and a low-level signal respectively, and the output end of the selector MUX3 is electrically connected to the other input end of the NAND gate NAND21; The three-byte logic processing unit determines whether the instruction currently executed by the 8051 core is a jump instruction based on the input system instruction content and the status flag signal jmp_ins2, and inputs a high-level signal to one input end of the NAND gate NAND22 when the instruction currently executed by the 8051 core is a jump instruction, otherwise, a low-level signal is input to one input end of the NAND gate NAND22; the two input ends of the selector MUX4 input a high-level signal and a low-level signal respectively, and the output end of the selector MUX4 is electrically connected to the other input end of the NAND gate NAND21; The output end of the NAND gate NAND20, the output end of the NAND gate NAND21 and the output end of the NAND gate NAND22 are electrically connected to the three input ends of the AND gate AND21, the output end of the AND gate AND21 is electrically connected to the D input end of the D flip-flop DFF20, the clock input end of the D flip-flop DFF20 is used to input the system clock signal, and the Q output end of the D flip-flop DFF20 is used to output the filter signal pause_1; The second driving unit and the content of the instruction cycle counter based on the 8051 core control the channels of the selectors MUX3 and MUX4 to be turned on.

8. The FLASH control circuit based on 8051 core according to claim 7, characterized in that: The second driving unit and the content of the instruction cycle counter based on the 8051 core control the channel conduction of the selector MUX3 and the selector MUX4 as follows: The second driving unit controls the selector MUX3 to output a high level signal when the content of the instruction cycle counter is one or two, and otherwise controls the selector MUX3 to output a low level signal; The second driving unit controls the selector MUX4 to output a high level signal when the content of the instruction cycle counter is one, two or three, and otherwise controls the selector MUX4 to output a low level signal.

9. The FLASH control circuit based on 8051 core according to claim 7, characterized in that: The single-byte logic processing unit performs OR processing on the data bus content when the control signal codefetch is at a high level to determine whether the instruction currently executed by the 8051 core is an adjustment instruction; The double-byte logic processing unit performs OR processing on the system instruction content when the status flag signal jmp_ins1 is at a high level, and determines whether the instruction currently executed by the 8051 core is an adjustment instruction; The three-byte logic processing unit performs OR processing on the system instruction content when the status flag signal jmp_ins2 is at a high level, and determines whether the instruction currently executed by the 8051 core is an adjustment instruction.

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